[meta-intel] gpio sus configuration as interrupt

[Kumar Nagaraj]

Hai,
                Can some please clarify my queries below?


1.      In  E3845 Bay Trail-I SOC data sheet I see only 2 register banks South Core & SUS.However in the patch 0002-gpio-add-support-for-Intel-Baytrail-GPIO-controller an additional register bank North Core is also listed. I am thinking that this patch refers to some other version of Bay Trail SOC.Can someone confirm?

2.      This query is regarding configuring the gpios as interrupts .I have a use case in which EVQ-Q1E06K provides the steering wheel switches ( HOME,PREV,NEXT,VOL+,VOL-) are connected to gpios GPIO_S5[00], GPIO_S5[01]... GPIO_S5[04] as inputs for a Bay Trail-I SOC.It is expected to trigger interrupt on these gpios when any switch is pressed.

Iam thinking that I will have to configure the SUS pins 0 to 4 as gpios to irqs.Can someone  provide inputs on how I achieve this?I referred existing gpio_keys.c sample code & found that it can be achieved by configuring  device tree. Am not sure how I can do this.Please correct me & also provide your ideas.



Thanks & Regards,

Kumar


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