[meta-freescale] [meta-fsl-arm][PATCH 2/2] linux-imx (3.0.35): Add fix pll4 set_rate callback

[Fabio Estevam]

On Fri, Jun 28, 2013 at 9:54 AM, Daiane Angolini
<daiane.angolini at freescale.com> wrote:
> This patch has been send by Alexander Smirnov to meta-freescale
> mailing list and is still not applied in Freescale GIT server.
>
> Apply it here as a interim solution.
>
> Change-Id: I44cf01f8461e91ec13ed3b9d045f8ea484988876
> Signed-off-by: Daiane Angolini <daiane.angolini at freescale.com>
> ---
>  ...x_arm_mach-mx6_fix_pll4_set_rate_callback.patch |   34 ++++++++++++++++++++
>  recipes-kernel/linux/linux-imx_3.0.35.bb           |    1 +
>  2 files changed, 35 insertions(+)
>  create mode 100644 recipes-kernel/linux/linux-imx/linux-imx_arm_mach-mx6_fix_pll4_set_rate_callback.patch
>
> diff --git a/recipes-kernel/linux/linux-imx/linux-imx_arm_mach-mx6_fix_pll4_set_rate_callback.patch b/recipes-kernel/linux/linux-imx/linux-imx_arm_mach-mx6_fix_pll4_set_rate_callback.patch
> new file mode 100644
> index 0000000..754d958
> --- /dev/null
> +++ b/recipes-kernel/linux/linux-imx/linux-imx_arm_mach-mx6_fix_pll4_set_rate_callback.patch
> @@ -0,0 +1,34 @@


>From field missing?

> +There is single method to set clock-rate for both audio and video pll-s
> +in i.MX6q clock system implementation. That's possible due to they have
> +similar set of registers with a different bases. But there is also one
> +common register: CCM_ANALOG_MISC2, which contains post-dividers.
> +
> +In current implementation, independently of whether audio or video clock
> +is going to be set, the mask 0xc0000000 is applied to MISC2 register.
> +This means, that if the audio clock rate is changed, the video clock
> +post-dividers possibly will be corrupted.
> +
> +This patch fixes the issue described above.
> +
> +Signed-off-by: Alexander Smirnov <alex.bluesman.smirnov at gmail.com>