[meta-freescale] [meta-fsl-arm][PATCH 2/2] linux-imx (3.0.35): Add fix pll4 set_rate callback

[Daiane Angolini]

This patch has been send by Alexander Smirnov to meta-freescale
mailing list and is still not applied in Freescale GIT server.

Apply it here as a interim solution.

Change-Id: I44cf01f8461e91ec13ed3b9d045f8ea484988876
Signed-off-by: Daiane Angolini <daiane.angolini at freescale.com>
---
 ...x_arm_mach-mx6_fix_pll4_set_rate_callback.patch |   34 ++++++++++++++++++++
 recipes-kernel/linux/linux-imx_3.0.35.bb           |    1 +
 2 files changed, 35 insertions(+)
 create mode 100644 recipes-kernel/linux/linux-imx/linux-imx_arm_mach-mx6_fix_pll4_set_rate_callback.patch

diff --git a/recipes-kernel/linux/linux-imx/linux-imx_arm_mach-mx6_fix_pll4_set_rate_callback.patch b/recipes-kernel/linux/linux-imx/linux-imx_arm_mach-mx6_fix_pll4_set_rate_callback.patch
new file mode 100644
index 0000000..754d958
--- /dev/null
+++ b/recipes-kernel/linux/linux-imx/linux-imx_arm_mach-mx6_fix_pll4_set_rate_callback.patch
@@ -0,0 +1,34 @@
+There is single method to set clock-rate for both audio and video pll-s
+in i.MX6q clock system implementation. That's possible due to they have
+similar set of registers with a different bases. But there is also one
+common register: CCM_ANALOG_MISC2, which contains post-dividers.
+
+In current implementation, independently of whether audio or video clock
+is going to be set, the mask 0xc0000000 is applied to MISC2 register.
+This means, that if the audio clock rate is changed, the video clock
+post-dividers possibly will be corrupted.
+
+This patch fixes the issue described above.
+
+Signed-off-by: Alexander Smirnov <alex.bluesman.smirnov at gmail.com>
+---
+ arch/arm/mach-mx6/clock.c |    3 ++-
+ 1 files changed, 2 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/mach-mx6/clock.c b/arch/arm/mach-mx6/clock.c
+index 8c590b7..8706c32 100644
+--- a/arch/arm/mach-mx6/clock.c
++++ b/arch/arm/mach-mx6/clock.c
+@@ -1023,7 +1023,8 @@ static int _clk_audio_video_set_rate(struct clk *clk, unsigned long rate)
+ 	__raw_writel(mfn, pllbase + PLL_NUM_DIV_OFFSET);
+ 	__raw_writel(mfd, pllbase + PLL_DENOM_DIV_OFFSET);
+ 
+-	if (rev >= IMX_CHIP_REVISION_1_1) {
++	if ((rev >= IMX_CHIP_REVISION_1_1) &&
++	    (pllbase == PLL5_VIDEO_BASE_ADDR)) {
+ 		reg = __raw_readl(ANA_MISC2_BASE_ADDR)
+ 			& ~ANADIG_ANA_MISC2_CONTROL3_MASK;
+ 		reg |= control3 << ANADIG_ANA_MISC2_CONTROL3_OFFSET;
+-- 
+1.7.2.5
+
diff --git a/recipes-kernel/linux/linux-imx_3.0.35.bb b/recipes-kernel/linux/linux-imx_3.0.35.bb
index ce4bac3..3de908b 100644
--- a/recipes-kernel/linux/linux-imx_3.0.35.bb
+++ b/recipes-kernel/linux/linux-imx_3.0.35.bb
@@ -10,3 +10,4 @@ COMPATIBLE_MACHINE = "(mx6)"
 # Revision of 4.0.0 branch
 SRCREV = "572fd62b7e2d70ef83e2ca8fe9895fe6f1531f8a"
 LOCALVERSION = "-4.0.0+yocto"
+SRC_URI += "file://linux-imx_arm_mach-mx6_fix_pll4_set_rate_callback.patch"
-- 
1.7.10.4