[meta-intel] gpio sus configuration as interrupt

[Darren Hart]

Kumar,

On Intel there is an upcoming modification to the ACPI specification that
will enable you to describe in ACPI via named method (_PRP) what you can do
in Device Tree for the other architectures. In the meantime, board files are
the most expedient option. For more detail on both the _PRP and board files,
see my "How not to write an x86 platform driver" presentation at the 2013
Embedded Linux Europe Conference:

http://events.linuxfoundation.org/sites/events/files/slides/x86-platform.pdf

And I think there is video..... but I can't seem to find it. Perhaps your
google foo will prove superior ;-)



-- 
Darren Hart
Yocto Project - Linux Kernel
Intel Open Source Technology Center

From:  "chiau.ee.chew" <chiau.ee.chew at intel.com>
Date:  Monday, March 17, 2014 at 22:37
To:  Darren Hart <dvhart at linux.intel.com>, Kumar Nagaraj <kumarn at hcl.com>,
"meta-intel at yoctoproject.org" <meta-intel at yoctoproject.org>
Cc:  "nvijaykumar.engineer at gmail.com" <nvijaykumar.engineer at gmail.com>
Subject:  RE: [meta-intel] gpio sus configuration as interrupt

> The same GPIO IP is being used across different variants of BayTrail. The
> patch that you pointed out is the correct GPIO driver to be used for BYT-I .
>  
> 
> From: Darren Hart [mailto:dvhart at linux.intel.com]
> Sent: Tuesday, March 18, 2014 6:56 AM
> To: Kumar Nagaraj; meta-intel at yoctoproject.org
> Cc: nvijaykumar.engineer at gmail.com; Chew, Chiau Ee
> Subject: Re: [meta-intel] gpio sus configuration as interrupt
>  
> 
> Adding Chiau Ee.
> 
> -- 
> 
> Darren Hart
> 
> Yocto Project - Linux Kernel
> 
> Intel Open Source Technology Center
> 
>  
> 
> From: Kumar Nagaraj <kumarn at hcl.com>
> Date: Wednesday, March 12, 2014 at 9:23
> To: "meta-intel at yoctoproject.org" <meta-intel at yoctoproject.org>
> Cc: "nvijaykumar.engineer at gmail.com" <nvijaykumar.engineer at gmail.com>
> Subject: [meta-intel] gpio sus configuration as interrupt
> 
>  
>> 
>> Hai,
>>                 Can some please clarify my queries below?
>>  
>> 1.     In  E3845 Bay Trail-I SOC data sheet I see only 2 register banks South
>> Core & SUS.However in the patch
>> 0002-gpio-add-support-for-Intel-Baytrail-GPIO-controller an additional
>> register bank North Core is also listed. I am thinking that this patch refers
>> to some other version of Bay Trail SOC.Can someone confirm?
>> 
>> 2.     This query is regarding configuring the gpios as interrupts .I have a
>> use case in which EVQ-Q1E06K provides the steering wheel switches (
>> HOME,PREV,NEXT,VOL+,VOL-) are connected to gpios GPIO_S5[00], GPIO_S5[01]Š
>> GPIO_S5[04] as inputs for a Bay Trail-I SOC.It is expected to trigger
>> interrupt on these gpios when any switch is pressed.
>> 
>> Iam thinking that I will have to configure the SUS pins 0 to 4 as gpios to
>> irqs.Can someone  provide inputs on how I achieve this?I referred existing
>> gpio_keys.c sample code & found that it can be achieved by configuring
>> device tree. Am not sure how I can do this.Please correct me & also provide
>> your ideas. 
>> 
>>  
>> 
>> Thanks & Regards,
>> 
>> Kumar
>> 
>> 
>> 
>> ::DISCLAIMER::
>> -----------------------------------------------------------------------------
>> -----------------------------------------------------------------------
>> The contents of this e-mail and any attachment(s) are confidential and
>> intended for the named recipient(s) only.
>> E-mail transmission is not guaranteed to be secure or error-free as
>> information could be intercepted, corrupted,
>> lost, destroyed, arrive late or incomplete, or may contain viruses in
>> transmission. The e mail and its contents
>> (with or without referred errors) shall therefore not attach any liability on
>> the originator or HCL or its affiliates.
>> Views or opinions, if any, presented in this email are solely those of the
>> author and may not necessarily reflect the
>> views or opinions of HCL or its affiliates. Any form of reproduction,
>> dissemination, copying, disclosure, modification,
>> distribution and / or publication of this message without the prior written
>> consent of authorized representative of
>> HCL is strictly prohibited. If you have received this email in error please
>> delete it and notify the sender immediately.
>> Before opening any email and/or attachments, please check them for viruses
>> and other defects.
>> -----------------------------------------------------------------------------
>> -----------------------------------------------------------------------
>> -- _______________________________________________ meta-intel mailing list
>> meta-intel at yoctoproject.org
>> https://lists.yoctoproject.org/listinfo/meta-intel


-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.yoctoproject.org/pipermail/meta-intel/attachments/20140318/c295d966/attachment.html>