[meta-freescale] [3rdparty][PATCH] linux-fslc: ccimx6ulsbcexpress: Adapt to v4.19
Alex Gonzalez
alex.gonzalez at digi.com
Thu Jan 3 02:43:46 PST 2019
The ConnectCore 6UL SOM and SBC Express are already included in upstream
v4.19.
Signed-off-by: Alex Gonzalez <alex.gonzalez at digi.com>
---
...-mtd-gpmi-change-the-BCH-layout-setting-f.patch | 51 +++--
...6q-read-OCOTP-through-nvmem-for-imx6ul-im.patch | 18 +-
...6ul-use-nvmem-cells-for-cpu-speed-grading.patch | 9 +-
...6ul-Add-DTS-for-ConnectCore-6UL-System-On.patch | 236 --------------------
...6ul-Add-DTS-for-ConnectCore-6UL-SBC-Expre.patch | 244 ---------------------
recipes-kernel/linux/linux-fslc_%.bbappend | 2 -
6 files changed, 37 insertions(+), 523 deletions(-)
delete mode 100644 recipes-kernel/linux/linux-fslc/ccimx6ul/0004-ARM-dts-imx6ul-Add-DTS-for-ConnectCore-6UL-System-On.patch
delete mode 100644 recipes-kernel/linux/linux-fslc/ccimx6ul/0005-ARM-dts-imx6ul-Add-DTS-for-ConnectCore-6UL-SBC-Expre.patch
diff --git a/recipes-kernel/linux/linux-fslc/ccimx6ul/0001-MLK-11719-4-mtd-gpmi-change-the-BCH-layout-setting-f.patch b/recipes-kernel/linux/linux-fslc/ccimx6ul/0001-MLK-11719-4-mtd-gpmi-change-the-BCH-layout-setting-f.patch
index 82d15a2538d2..c2b81030a34d 100644
--- a/recipes-kernel/linux/linux-fslc/ccimx6ul/0001-MLK-11719-4-mtd-gpmi-change-the-BCH-layout-setting-f.patch
+++ b/recipes-kernel/linux/linux-fslc/ccimx6ul/0001-MLK-11719-4-mtd-gpmi-change-the-BCH-layout-setting-f.patch
@@ -1,7 +1,6 @@
-From a736d243e0b552e2b1ae80fe6d9026a2754752e3 Mon Sep 17 00:00:00 2001
From: Alex Gonzalez <alex.gonzalez at digi.com>
Date: Fri, 24 Aug 2018 18:53:40 +0200
-Subject: [PATCH 1/5] MLK-11719-4: mtd: gpmi: change the BCH layout setting for
+Subject: [PATCH] MLK-11719-4: mtd: gpmi: change the BCH layout setting for
large oob NAND
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
@@ -59,10 +58,10 @@ Signed-off-by: Alex Gonzalez <alex.gonzalez at digi.com>
3 files changed, 248 insertions(+), 49 deletions(-)
diff --git a/drivers/mtd/nand/raw/gpmi-nand/gpmi-lib.c b/drivers/mtd/nand/raw/gpmi-nand/gpmi-lib.c
-index 83697b8df871..921af1824590 100644
+index 88ea2203e263..a4cd9523e220 100644
--- a/drivers/mtd/nand/raw/gpmi-nand/gpmi-lib.c
+++ b/drivers/mtd/nand/raw/gpmi-nand/gpmi-lib.c
-@@ -225,7 +225,8 @@ void gpmi_dump_info(struct gpmi_nand_data *this)
+@@ -212,7 +212,8 @@ void gpmi_dump_info(struct gpmi_nand_data *this)
"ECC Strength : %u\n"
"Page Size in Bytes : %u\n"
"Metadata Size in Bytes : %u\n"
@@ -72,7 +71,7 @@ index 83697b8df871..921af1824590 100644
"ECC Chunk Count : %u\n"
"Payload Size in Bytes : %u\n"
"Auxiliary Size in Bytes: %u\n"
-@@ -236,7 +237,8 @@ void gpmi_dump_info(struct gpmi_nand_data *this)
+@@ -223,7 +224,8 @@ void gpmi_dump_info(struct gpmi_nand_data *this)
geo->ecc_strength,
geo->page_size,
geo->metadata_size,
@@ -82,7 +81,7 @@ index 83697b8df871..921af1824590 100644
geo->ecc_chunk_count,
geo->payload_size,
geo->auxiliary_size,
-@@ -251,7 +253,8 @@ int bch_set_geometry(struct gpmi_nand_data *this)
+@@ -238,7 +240,8 @@ int bch_set_geometry(struct gpmi_nand_data *this)
struct resources *r = &this->resources;
struct bch_geometry *bch_geo = &this->bch_geometry;
unsigned int block_count;
@@ -92,7 +91,7 @@ index 83697b8df871..921af1824590 100644
unsigned int metadata_size;
unsigned int ecc_strength;
unsigned int page_size;
-@@ -263,7 +266,8 @@ int bch_set_geometry(struct gpmi_nand_data *this)
+@@ -250,7 +253,8 @@ int bch_set_geometry(struct gpmi_nand_data *this)
return ret;
block_count = bch_geo->ecc_chunk_count - 1;
@@ -102,7 +101,7 @@ index 83697b8df871..921af1824590 100644
metadata_size = bch_geo->metadata_size;
ecc_strength = bch_geo->ecc_strength >> 1;
page_size = bch_geo->page_size;
-@@ -290,13 +294,13 @@ int bch_set_geometry(struct gpmi_nand_data *this)
+@@ -277,13 +281,13 @@ int bch_set_geometry(struct gpmi_nand_data *this)
| BF_BCH_FLASH0LAYOUT0_META_SIZE(metadata_size)
| BF_BCH_FLASH0LAYOUT0_ECC0(ecc_strength, this)
| BF_BCH_FLASH0LAYOUT0_GF(gf_len, this)
@@ -119,10 +118,10 @@ index 83697b8df871..921af1824590 100644
/* Set *all* chip selects to use layout 0. */
diff --git a/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c b/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
-index f6aa358a3452..8c0f2a83e2a3 100644
+index 1c1ebbc82824..bc4a364e5696 100644
--- a/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
+++ b/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
-@@ -192,6 +192,36 @@ static inline bool gpmi_check_ecc(struct gpmi_nand_data *this)
+@@ -179,6 +179,36 @@ static inline bool gpmi_check_ecc(struct gpmi_nand_data *this)
return geo->ecc_strength <= this->devdata->bch_max_ecc_strength;
}
@@ -159,7 +158,7 @@ index f6aa358a3452..8c0f2a83e2a3 100644
/*
* If we can get the ECC information from the nand chip, we do not
* need to calculate them ourselves.
-@@ -220,13 +250,14 @@ static int set_geometry_by_ecc_info(struct gpmi_nand_data *this,
+@@ -207,13 +237,14 @@ static int set_geometry_by_ecc_info(struct gpmi_nand_data *this,
chip->ecc_strength_ds, chip->ecc_step_ds);
return -EINVAL;
}
@@ -177,7 +176,7 @@ index f6aa358a3452..8c0f2a83e2a3 100644
dev_err(this->dev,
"unsupported nand chip. ecc size: %d, oob size : %d\n",
ecc_step, mtd->oobsize);
-@@ -236,7 +267,7 @@ static int set_geometry_by_ecc_info(struct gpmi_nand_data *this,
+@@ -223,7 +254,7 @@ static int set_geometry_by_ecc_info(struct gpmi_nand_data *this,
/* The default value, see comment in the legacy_set_geometry(). */
geo->metadata_size = 10;
@@ -186,7 +185,7 @@ index f6aa358a3452..8c0f2a83e2a3 100644
/*
* Now, the NAND chip with 2K page(data chunk is 512byte) shows below:
-@@ -308,6 +339,129 @@ static int set_geometry_by_ecc_info(struct gpmi_nand_data *this,
+@@ -295,6 +326,129 @@ static int set_geometry_by_ecc_info(struct gpmi_nand_data *this,
return 0;
}
@@ -316,7 +315,7 @@ index f6aa358a3452..8c0f2a83e2a3 100644
static int legacy_set_geometry(struct gpmi_nand_data *this)
{
struct bch_geometry *geo = &this->bch_geometry;
-@@ -327,13 +481,15 @@ static int legacy_set_geometry(struct gpmi_nand_data *this)
+@@ -314,13 +468,15 @@ static int legacy_set_geometry(struct gpmi_nand_data *this)
geo->gf_len = 13;
/* The default for chunk size. */
@@ -336,7 +335,7 @@ index f6aa358a3452..8c0f2a83e2a3 100644
/* We use the same ECC strength for all chunks. */
geo->ecc_strength = get_ecc_strength(this);
-@@ -422,22 +578,25 @@ static int legacy_set_geometry(struct gpmi_nand_data *this)
+@@ -409,22 +565,25 @@ static int legacy_set_geometry(struct gpmi_nand_data *this)
int common_nfc_set_geometry(struct gpmi_nand_data *this)
{
@@ -374,7 +373,7 @@ index f6aa358a3452..8c0f2a83e2a3 100644
}
struct dma_chan *get_dma_chan(struct gpmi_nand_data *this)
-@@ -1013,7 +1172,8 @@ static int gpmi_ecc_read_page_data(struct nand_chip *chip,
+@@ -997,7 +1156,8 @@ static int gpmi_ecc_read_page_data(struct nand_chip *chip,
/* Read ECC bytes into our internal raw_buffer */
offset = nfc_geo->metadata_size * 8;
@@ -384,7 +383,7 @@ index f6aa358a3452..8c0f2a83e2a3 100644
offset -= eccbits;
bitoffset = offset % 8;
eccbytes = DIV_ROUND_UP(offset + eccbits, 8);
-@@ -1050,19 +1210,19 @@ static int gpmi_ecc_read_page_data(struct nand_chip *chip,
+@@ -1034,19 +1194,19 @@ static int gpmi_ecc_read_page_data(struct nand_chip *chip,
if (i == 0) {
/* The first block includes metadata */
flips = nand_check_erased_ecc_chunk(
@@ -397,7 +396,7 @@ index f6aa358a3452..8c0f2a83e2a3 100644
+ buf + i * nfc_geo->ecc_chunkn_size,
+ nfc_geo->ecc_chunkn_size,
+ eccbuf, eccbytes,
-+ payload_virt,
++ this->payload_virt,
+ nfc_geo->metadata_size,
+ nfc_geo->ecc_strength);
} else {
@@ -415,7 +414,7 @@ index f6aa358a3452..8c0f2a83e2a3 100644
}
if (flips > 0) {
-@@ -1150,9 +1310,24 @@ static int gpmi_ecc_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
+@@ -1134,9 +1294,24 @@ static int gpmi_ecc_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
}
}
@@ -441,7 +440,7 @@ index f6aa358a3452..8c0f2a83e2a3 100644
meta = 0;
buf = buf + first * size;
}
-@@ -1165,21 +1340,37 @@ static int gpmi_ecc_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
+@@ -1149,21 +1324,37 @@ static int gpmi_ecc_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
/* change the BCH registers and bch_geometry{} */
n = last - first + 1;
@@ -482,7 +481,7 @@ index f6aa358a3452..8c0f2a83e2a3 100644
geo->auxiliary_status_offset = ALIGN(meta, 4);
dev_dbg(this->dev, "page:%d(%d:%d)%d, chunk:(%d:%d), BCH PG size:%d\n",
-@@ -1402,7 +1593,7 @@ static int gpmi_ecc_read_page_raw(struct mtd_info *mtd,
+@@ -1386,7 +1577,7 @@ static int gpmi_ecc_read_page_raw(struct mtd_info *mtd,
{
struct gpmi_nand_data *this = nand_get_controller_data(chip);
struct bch_geometry *nfc_geo = &this->bch_geometry;
@@ -491,7 +490,7 @@ index f6aa358a3452..8c0f2a83e2a3 100644
int eccbits = nfc_geo->ecc_strength * nfc_geo->gf_len;
u8 *tmp_buf = this->raw_buffer;
size_t src_bit_off;
-@@ -1487,7 +1678,7 @@ static int gpmi_ecc_write_page_raw(struct mtd_info *mtd,
+@@ -1471,7 +1662,7 @@ static int gpmi_ecc_write_page_raw(struct mtd_info *mtd,
{
struct gpmi_nand_data *this = nand_get_controller_data(chip);
struct bch_geometry *nfc_geo = &this->bch_geometry;
@@ -500,7 +499,7 @@ index f6aa358a3452..8c0f2a83e2a3 100644
int eccbits = nfc_geo->ecc_strength * nfc_geo->gf_len;
u8 *tmp_buf = this->raw_buffer;
uint8_t *oob = chip->oob_poi;
-@@ -1863,7 +2054,7 @@ static int gpmi_init_last(struct gpmi_nand_data *this)
+@@ -1847,7 +2038,7 @@ static int gpmi_init_last(struct gpmi_nand_data *this)
ecc->read_oob_raw = gpmi_ecc_read_oob_raw;
ecc->write_oob_raw = gpmi_ecc_write_oob_raw;
ecc->mode = NAND_ECC_HW;
@@ -510,10 +509,10 @@ index f6aa358a3452..8c0f2a83e2a3 100644
mtd_set_ooblayout(mtd, &gpmi_ooblayout_ops);
diff --git a/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.h b/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.h
-index 6aa10d6962d6..fb50520608ac 100644
+index 69cd0cbde4f2..ef4e57256d30 100644
--- a/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.h
+++ b/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.h
-@@ -39,9 +39,9 @@ struct resources {
+@@ -30,9 +30,9 @@ struct resources {
* @page_size: The size, in bytes, of a physical page, including
* both data and OOB.
* @metadata_size: The size, in bytes, of the metadata.
@@ -526,7 +525,7 @@ index 6aa10d6962d6..fb50520608ac 100644
* @ecc_chunk_count: The number of ECC chunks in the page,
* @payload_size: The size, in bytes, of the payload buffer.
* @auxiliary_size: The size, in bytes, of the auxiliary buffer.
-@@ -51,19 +51,23 @@ struct resources {
+@@ -42,19 +42,23 @@ struct resources {
* which the underlying physical block mark appears.
* @block_mark_bit_offset: The bit offset into the ECC-based page view at
* which the underlying physical block mark appears.
diff --git a/recipes-kernel/linux/linux-fslc/ccimx6ul/0002-cpufreq-imx6q-read-OCOTP-through-nvmem-for-imx6ul-im.patch b/recipes-kernel/linux/linux-fslc/ccimx6ul/0002-cpufreq-imx6q-read-OCOTP-through-nvmem-for-imx6ul-im.patch
index bcd42bb8f2a1..26f6ba89fa2c 100644
--- a/recipes-kernel/linux/linux-fslc/ccimx6ul/0002-cpufreq-imx6q-read-OCOTP-through-nvmem-for-imx6ul-im.patch
+++ b/recipes-kernel/linux/linux-fslc/ccimx6ul/0002-cpufreq-imx6q-read-OCOTP-through-nvmem-for-imx6ul-im.patch
@@ -1,8 +1,6 @@
-From d29d8485ed649d45aa11b4a6081fb121f65fb41a Mon Sep 17 00:00:00 2001
From: Anson Huang <Anson.Huang at nxp.com>
Date: Mon, 8 Oct 2018 14:07:34 +0800
-Subject: [PATCH 2/5] cpufreq: imx6q: read OCOTP through nvmem for
- imx6ul/imx6ull
+Subject: [PATCH] cpufreq: imx6q: read OCOTP through nvmem for imx6ul/imx6ull
On i.MX6UL/i.MX6ULL, accessing OCOTP directly is wrong because
the ocotp clock needs to be enabled first. Add support for reading
@@ -18,18 +16,18 @@ Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki at intel.com>
1 file changed, 35 insertions(+), 17 deletions(-)
diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c
-index 8b3c2a79ad6c..564bc23f709b 100644
+index b2ff423ad7f8..8cfee0ab804b 100644
--- a/drivers/cpufreq/imx6q-cpufreq.c
+++ b/drivers/cpufreq/imx6q-cpufreq.c
-@@ -11,6 +11,7 @@
- #include <linux/cpufreq.h>
+@@ -12,6 +12,7 @@
+ #include <linux/cpu_cooling.h>
#include <linux/err.h>
#include <linux/module.h>
+#include <linux/nvmem-consumer.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/pm_opp.h>
-@@ -269,20 +270,32 @@ static void imx6q_opp_check_speed_grading(struct device *dev)
+@@ -290,20 +291,32 @@ static void imx6q_opp_check_speed_grading(struct device *dev)
#define OCOTP_CFG3_6ULL_SPEED_792MHZ 0x2
#define OCOTP_CFG3_6ULL_SPEED_900MHZ 0x3
@@ -72,7 +70,7 @@ index 8b3c2a79ad6c..564bc23f709b 100644
}
/*
-@@ -293,7 +306,6 @@ static void imx6ul_opp_check_speed_grading(struct device *dev)
+@@ -314,7 +327,6 @@ static void imx6ul_opp_check_speed_grading(struct device *dev)
* 2b'11: 900000000Hz on i.MX6ULL only;
* We need to set the max speed of ARM according to fuse map.
*/
@@ -80,7 +78,7 @@ index 8b3c2a79ad6c..564bc23f709b 100644
val >>= OCOTP_CFG3_SPEED_SHIFT;
val &= 0x3;
-@@ -313,9 +325,7 @@ static void imx6ul_opp_check_speed_grading(struct device *dev)
+@@ -334,9 +346,7 @@ static void imx6ul_opp_check_speed_grading(struct device *dev)
dev_warn(dev, "failed to disable 900MHz OPP\n");
}
@@ -91,7 +89,7 @@ index 8b3c2a79ad6c..564bc23f709b 100644
}
static int imx6q_cpufreq_probe(struct platform_device *pdev)
-@@ -373,10 +383,18 @@ static int imx6q_cpufreq_probe(struct platform_device *pdev)
+@@ -394,10 +404,18 @@ static int imx6q_cpufreq_probe(struct platform_device *pdev)
}
if (of_machine_is_compatible("fsl,imx6ul") ||
diff --git a/recipes-kernel/linux/linux-fslc/ccimx6ul/0003-ARM-dts-imx6ul-use-nvmem-cells-for-cpu-speed-grading.patch b/recipes-kernel/linux/linux-fslc/ccimx6ul/0003-ARM-dts-imx6ul-use-nvmem-cells-for-cpu-speed-grading.patch
index 27f4666d513b..e8c6d16a3acd 100644
--- a/recipes-kernel/linux/linux-fslc/ccimx6ul/0003-ARM-dts-imx6ul-use-nvmem-cells-for-cpu-speed-grading.patch
+++ b/recipes-kernel/linux/linux-fslc/ccimx6ul/0003-ARM-dts-imx6ul-use-nvmem-cells-for-cpu-speed-grading.patch
@@ -1,7 +1,6 @@
-From 6e7242f21f0d9461e1ad3b13a4118c44e17cfa38 Mon Sep 17 00:00:00 2001
From: Anson Huang <Anson.Huang at nxp.com>
Date: Fri, 14 Sep 2018 10:59:21 +0800
-Subject: [PATCH 3/5] ARM: dts: imx6ul: use nvmem-cells for cpu speed grading
+Subject: [PATCH] ARM: dts: imx6ul: use nvmem-cells for cpu speed grading
On i.MX6UL, accessing OCOTP directly is wrong because the ocotp clock
needs to be enabled first, so use the nvmem-cells binding instead.
@@ -14,10 +13,10 @@ Signed-off-by: Shawn Guo <shawnguo at kernel.org>
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
-index 47a3453a4211..9670f15bcb31 100644
+index 6dc0b569acdf..c670d8e4e0a9 100644
--- a/arch/arm/boot/dts/imx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul.dtsi
-@@ -88,6 +88,8 @@
+@@ -89,6 +89,8 @@
"pll1_sys";
arm-supply = <®_arm>;
soc-supply = <®_soc>;
@@ -26,7 +25,7 @@ index 47a3453a4211..9670f15bcb31 100644
};
};
-@@ -926,6 +928,10 @@
+@@ -932,6 +934,10 @@
tempmon_temp_grade: temp-grade at 20 {
reg = <0x20 4>;
};
diff --git a/recipes-kernel/linux/linux-fslc/ccimx6ul/0004-ARM-dts-imx6ul-Add-DTS-for-ConnectCore-6UL-System-On.patch b/recipes-kernel/linux/linux-fslc/ccimx6ul/0004-ARM-dts-imx6ul-Add-DTS-for-ConnectCore-6UL-System-On.patch
deleted file mode 100644
index 6658df5895af..000000000000
--- a/recipes-kernel/linux/linux-fslc/ccimx6ul/0004-ARM-dts-imx6ul-Add-DTS-for-ConnectCore-6UL-System-On.patch
+++ /dev/null
@@ -1,236 +0,0 @@
-From f41c981a8a997b50077943ce21659ad7e73e8365 Mon Sep 17 00:00:00 2001
-From: Alex Gonzalez <alex.gonzalez at digi.com>
-Date: Thu, 12 Jul 2018 10:20:35 +0200
-Subject: [PATCH 4/5] ARM: dts: imx6ul: Add DTS for ConnectCore 6UL
- System-On-Module (SOM)
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The ConnectCore 6UL System-On-Module has the following hardware
-specification:
-
-* Based on a NXP i.MX6UL SoC
-* Industrial temperature ranges (-40ºC to +85ºC)
-* Up to 1GB DDR3 memory
-* Up to 2GB NAND flash
-* Dual Ethernet
-* On module 802.11 WiFi and Bluetooth 4.2 (QCA6564)
-* On module NXP Kinetis KL03
-* On module Microchip ATECC508A crypto element
-
-Signed-off-by: Alex Gonzalez <alex.gonzalez at digi.com>
-Signed-off-by: Shawn Guo <shawnguo at kernel.org>
-(cherry picked from commit 0b9c89e213d227d3649a1cb77bb6b912fbd532f9)
----
- arch/arm/boot/dts/imx6ul-ccimx6ulsom.dtsi | 201 ++++++++++++++++++++++++++++++
- 1 file changed, 201 insertions(+)
- create mode 100644 arch/arm/boot/dts/imx6ul-ccimx6ulsom.dtsi
-
-diff --git a/arch/arm/boot/dts/imx6ul-ccimx6ulsom.dtsi b/arch/arm/boot/dts/imx6ul-ccimx6ulsom.dtsi
-new file mode 100644
-index 000000000000..c71a84da1af0
---- /dev/null
-+++ b/arch/arm/boot/dts/imx6ul-ccimx6ulsom.dtsi
-@@ -0,0 +1,201 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Digi International's ConnectCore 6UL System-On-Module device tree source
-+ *
-+ * Copyright 2018 Digi International, Inc.
-+ *
-+ */
-+
-+/ {
-+ reserved-memory {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ ranges;
-+
-+ linux,cma {
-+ compatible = "shared-dma-pool";
-+ reusable;
-+ size = <0x4000000>;
-+ linux,cma-default;
-+ };
-+ };
-+};
-+
-+&adc1 {
-+ vref-supply = <&vdda_adc_3v3>;
-+};
-+
-+&gpmi {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_gpmi_nand>;
-+ status = "okay";
-+};
-+
-+&i2c1 {
-+ clock-frequency = <100000>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_i2c1>;
-+ status = "okay";
-+
-+ pfuze3000: pmic at 8 {
-+ compatible = "fsl,pfuze3000";
-+ reg = <0x08>;
-+
-+ regulators {
-+ int_3v3: sw1a {
-+ regulator-min-microvolt = <700000>;
-+ regulator-max-microvolt = <3300000>;
-+ regulator-ramp-delay = <6250>;
-+ regulator-boot-on;
-+ regulator-always-on;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdd_arm_soc_in: sw1b {
-+ regulator-min-microvolt = <700000>;
-+ regulator-max-microvolt = <1475000>;
-+ regulator-ramp-delay = <6250>;
-+ regulator-boot-on;
-+ regulator-always-on;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <925000>;
-+ };
-+ };
-+
-+ ext_3v3: sw2 {
-+ regulator-min-microvolt = <2500000>;
-+ regulator-max-microvolt = <3300000>;
-+ regulator-ramp-delay = <6250>;
-+ regulator-always-on;
-+ regulator-boot-on;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc_ddr3: sw3 {
-+ regulator-min-microvolt = <900000>;
-+ regulator-max-microvolt = <1650000>;
-+ regulator-always-on;
-+ regulator-boot-on;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <1300000>;
-+ };
-+ };
-+
-+ swbst_reg: swbst {
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5150000>;
-+ };
-+
-+ vdd_snvs_3v3: vsnvs {
-+ regulator-min-microvolt = <1000000>;
-+ regulator-max-microvolt = <3000000>;
-+ regulator-boot-on;
-+ regulator-always-on;
-+ };
-+
-+ vrefddr: vrefddr {
-+ regulator-boot-on;
-+ regulator-always-on;
-+ };
-+
-+ vdda_adc_3v3: vldo1 {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vref-adc-3v3";
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ regulator-always-on;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ ldo2_ext: vldo2 {
-+ regulator-min-microvolt = <800000>;
-+ regulator-max-microvolt = <1550000>;
-+ };
-+
-+ vdda_wlan: vccsd {
-+ regulator-min-microvolt = <2850000>;
-+ regulator-max-microvolt = <3300000>;
-+ regulator-always-on;
-+ regulator-boot-on;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdd_high_in: v33 {
-+ regulator-min-microvolt = <2850000>;
-+ regulator-max-microvolt = <3300000>;
-+ regulator-boot-on;
-+ regulator-always-on;
-+ };
-+
-+ ldo3_int: vldo3 {
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <3300000>;
-+ };
-+
-+ ldo4_ext: vldo4 {
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <3300000>;
-+ };
-+
-+ vcoin_chg: vcoin {
-+ regulator-min-microvolt = <2500000>;
-+ regulator-max-microvolt = <3300000>;
-+ };
-+ };
-+ };
-+};
-+
-+&iomuxc {
-+ pinctrl_gpmi_nand: gpmigrp {
-+ fsl,pins = <
-+ MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1
-+ MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1
-+ MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1
-+ MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1
-+ MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1
-+ MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1
-+ MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1
-+ MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1
-+ MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1
-+ MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1
-+ MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1
-+ MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1
-+ MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1
-+ MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1
-+ MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb0b1
-+ >;
-+ };
-+
-+ pinctrl_i2c1: i2c1grp {
-+ fsl,pins = <
-+ MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
-+ MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
-+ >;
-+ };
-+};
-+
-+®_arm {
-+ vin-supply = <&vdd_arm_soc_in>;
-+ regulator-allow-bypass;
-+};
-+
-+®_soc {
-+ vin-supply = <&vdd_arm_soc_in>;
-+ regulator-allow-bypass;
-+};
diff --git a/recipes-kernel/linux/linux-fslc/ccimx6ul/0005-ARM-dts-imx6ul-Add-DTS-for-ConnectCore-6UL-SBC-Expre.patch b/recipes-kernel/linux/linux-fslc/ccimx6ul/0005-ARM-dts-imx6ul-Add-DTS-for-ConnectCore-6UL-SBC-Expre.patch
deleted file mode 100644
index 2cdc4d8af26d..000000000000
--- a/recipes-kernel/linux/linux-fslc/ccimx6ul/0005-ARM-dts-imx6ul-Add-DTS-for-ConnectCore-6UL-SBC-Expre.patch
+++ /dev/null
@@ -1,244 +0,0 @@
-From 9ca4211642dc7d6521594b58600ecab8088039e2 Mon Sep 17 00:00:00 2001
-From: Alex Gonzalez <alex.gonzalez at digi.com>
-Date: Thu, 12 Jul 2018 10:20:36 +0200
-Subject: [PATCH 5/5] ARM: dts: imx6ul: Add DTS for ConnectCore 6UL SBC Express
-
-The ConnectCore 6UL Single Board Computer (SBC) Express contains the
-ConnectCore 6UL System-On-Module.
-
-Its hardware specifications are:
-
-* 256MB DDR3 memory
-* 256MB NAND flash
-* Single Ethernet
-* USB Host and USB-OTG
-* MicroSD external storage
-* Groove connectors and Raspberry Pi Hat compatible expansion header
-
-Signed-off-by: Alex Gonzalez <alex.gonzalez at digi.com>
-Signed-off-by: Shawn Guo <shawnguo at kernel.org>
-(cherry picked from commit 8c7725829989d2711875f60356d22bc5af981ac0)
----
- arch/arm/boot/dts/Makefile | 1 +
- arch/arm/boot/dts/imx6ul-ccimx6ulsbcexpress.dts | 200 ++++++++++++++++++++++++
- 2 files changed, 201 insertions(+)
- create mode 100644 arch/arm/boot/dts/imx6ul-ccimx6ulsbcexpress.dts
-
-diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
-index 37a3de760d40..6135d3dc381c 100644
---- a/arch/arm/boot/dts/Makefile
-+++ b/arch/arm/boot/dts/Makefile
-@@ -533,6 +533,7 @@ dtb-$(CONFIG_SOC_IMX6SX) += \
- imx6sx-udoo-neo-full.dtb
- dtb-$(CONFIG_SOC_IMX6UL) += \
- imx6ul-14x14-evk.dtb \
-+ imx6ul-ccimx6ulsbcexpress.dtb \
- imx6ul-geam.dtb \
- imx6ul-isiot-emmc.dtb \
- imx6ul-isiot-nand.dtb \
-diff --git a/arch/arm/boot/dts/imx6ul-ccimx6ulsbcexpress.dts b/arch/arm/boot/dts/imx6ul-ccimx6ulsbcexpress.dts
-new file mode 100644
-index 000000000000..3792679c0c90
---- /dev/null
-+++ b/arch/arm/boot/dts/imx6ul-ccimx6ulsbcexpress.dts
-@@ -0,0 +1,200 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Digi International's ConnectCore6UL SBC Express board device tree source
-+ *
-+ * Copyright 2018 Digi International, Inc.
-+ *
-+ */
-+
-+/dts-v1/;
-+#include <dt-bindings/input/input.h>
-+#include <dt-bindings/interrupt-controller/irq.h>
-+#include "imx6ul.dtsi"
-+#include "imx6ul-ccimx6ulsom.dtsi"
-+
-+/ {
-+ model = "Digi International ConnectCore 6UL SBC Express.";
-+ compatible = "digi,ccimx6ulsbcexpress", "digi,ccimx6ulsom",
-+ "fsl,imx6ul";
-+};
-+
-+&adc1 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_adc1>;
-+ status = "okay";
-+};
-+
-+&can1 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_flexcan1>;
-+ xceiver-supply = <&ext_3v3>;
-+ status = "okay";
-+};
-+
-+&ecspi3 {
-+ cs-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_ecspi3_master>;
-+ status = "okay";
-+};
-+
-+&fec1 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_enet1>;
-+ phy-mode = "rmii";
-+ phy-handle = <ðphy0>;
-+ status = "okay";
-+
-+ mdio {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ ethphy0: ethernet-phy at 0 {
-+ compatible = "ethernet-phy-ieee802.3-c22";
-+ smsc,disable-energy-detect;
-+ reg = <0>;
-+ };
-+ };
-+};
-+
-+&i2c2 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_i2c2>;
-+ status = "okay";
-+};
-+
-+&pwm1 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_pwm1>;
-+ status = "okay";
-+};
-+
-+&uart4 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_uart4>;
-+ status = "okay";
-+};
-+
-+&uart5 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_uart5>;
-+ status = "okay";
-+};
-+
-+&usbotg1 {
-+ dr_mode = "host";
-+ disable-over-current;
-+ status = "okay";
-+};
-+
-+&usbotg2 {
-+ dr_mode = "host";
-+ disable-over-current;
-+ status = "okay";
-+};
-+
-+&usdhc2 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_usdhc2>;
-+ broken-cd; /* no carrier detect line (use polling) */
-+ no-1-8-v;
-+ status = "okay";
-+};
-+
-+&iomuxc {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_hog>;
-+
-+ pinctrl_adc1: adc1grp {
-+ fsl,pins = <
-+ /* GPIO1_4/ADC1_IN4 (pin 7 of the expansion header) */
-+ MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
-+ >;
-+ };
-+
-+ pinctrl_ecspi3_master: ecspi3grp1 {
-+ fsl,pins = <
-+ MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x10b0
-+ MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x10b0
-+ MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x10b0
-+ MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x10b0 /* Chip Select */
-+ >;
-+ };
-+
-+ pinctrl_ecspi3_slave: ecspi3grp2 {
-+ fsl,pins = <
-+ MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x10b0
-+ MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x10b0
-+ MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x10b0
-+ MX6UL_PAD_UART2_TX_DATA__ECSPI3_SS0 0x10b0 /* Chip Select */
-+ >;
-+ };
-+
-+ pinctrl_enet1: enet1grp {
-+ fsl,pins = <
-+ MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
-+ MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
-+ MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
-+ MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
-+ MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
-+ MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
-+ MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
-+ MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
-+ MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
-+ MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x40017051
-+ >;
-+ };
-+
-+ pinctrl_flexcan1: flexcan1grp{
-+ fsl,pins = <
-+ MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX 0x1b020
-+ MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX 0x1b020
-+ >;
-+ };
-+
-+ pinctrl_i2c2: i2c2grp {
-+ fsl,pins = <
-+ MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x4001b8b0
-+ MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x4001b8b0
-+ >;
-+ };
-+
-+ pinctrl_pwm1: pwm1grp {
-+ fsl,pins = <
-+ MX6UL_PAD_LCD_DATA00__PWM1_OUT 0x10b0
-+ >;
-+ };
-+
-+ pinctrl_uart4: uart4grp {
-+ fsl,pins = <
-+ MX6UL_PAD_LCD_CLK__UART4_DCE_TX 0x1b0b1
-+ MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX 0x1b0b1
-+ >;
-+ };
-+
-+ pinctrl_uart5: uart5grp {
-+ fsl,pins = <
-+ MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1
-+ MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1
-+ >;
-+ };
-+
-+ pinctrl_usdhc2: usdhc2grp {
-+ fsl,pins = <
-+ MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059
-+ MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10071
-+ MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17059
-+ MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17059
-+ MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17059
-+ MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17059
-+ >;
-+ };
-+
-+ /* General purpose pinctrl */
-+ pinctrl_hog: hoggrp {
-+ fsl,pins = <
-+ /* GPIOs BANK 3 */
-+ MX6UL_PAD_LCD_RESET__GPIO3_IO04 0xf030
-+ >;
-+ };
-+};
diff --git a/recipes-kernel/linux/linux-fslc_%.bbappend b/recipes-kernel/linux/linux-fslc_%.bbappend
index 15af9917f6a2..5621c4999765 100644
--- a/recipes-kernel/linux/linux-fslc_%.bbappend
+++ b/recipes-kernel/linux/linux-fslc_%.bbappend
@@ -12,8 +12,6 @@ SRC_URI_append_ccimx6ul = " \
file://0001-MLK-11719-4-mtd-gpmi-change-the-BCH-layout-setting-f.patch \
file://0002-cpufreq-imx6q-read-OCOTP-through-nvmem-for-imx6ul-im.patch \
file://0003-ARM-dts-imx6ul-use-nvmem-cells-for-cpu-speed-grading.patch \
- file://0004-ARM-dts-imx6ul-Add-DTS-for-ConnectCore-6UL-System-On.patch \
- file://0005-ARM-dts-imx6ul-Add-DTS-for-ConnectCore-6UL-SBC-Expre.patch \
"
do_configure_prepend_imx6qdl-variscite-som() {
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