[meta-freescale] cannot configure divider when PLL is powered on

[Vishnu Motghare]

Hi,

I'm using i.MX6 board which has dw-hdmi Synopsys DesignWare HDMI
Controller. I 'm using linux-3.10 kernel version which doesn't have DRM
support for Synopsys.  So, I back ported drm driver from linux-4.8.

Driver probed happend successfully. Following is dmesg

[    1.642015] imx-drm display-subsystem: bound 120000.hdmi (ops
dw_hdmi_imx_ops)
[    1.649845] imx-drm display-subsystem: bound
2000000.aips-bus:ldb at 020e0008 (ops imx_ldb_ops)


I got following error,

imx-ldb ldb.15: unable to set di1 parent clock to original parent

So' I ported following patch from mainline kernel,

https://patchwork.kernel.org/patch/9336099/

After this I'm getting following error,

clk_pllv3_set_rate: cannot configure divider when PLL is powered on


I'm not getting any clue to fix this error. Doen any other patch is
required to fix this issue?
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.yoctoproject.org/pipermail/meta-freescale/attachments/20180201/52a93298/attachment.html>