[meta-freescale] [PATCH][linux-fslc][4.1-1.0.x-imx] net: fec: support RRACC_SHIFT16 to align IP header

[Eric Nelson]

Hi Andy,

On 09/23/2016 10:00 PM, Andy Duan wrote:
> From: Eric Nelson <eric at nelint.com> Sent: Saturday, September 24, 2016 9:44 AM
>> To: meta-freescale at yoctoproject.org
>> Cc: linux at arm.linux.org.uk; andrew at lunn.ch; Andy Duan
>> <fugang.duan at nxp.com>; otavio at ossystems.com.br; Eric Nelson
>> <eric at nelint.com>
>> Subject: [PATCH][linux-fslc][4.1-1.0.x-imx] net: fec: support RRACC_SHIFT16
>> to align IP header
>>
>> The i.MX6 UL and DQLS variants all support shifting the data payload of
>> received packets by 16-bits, which aligns the IP header on a longword
>> boundary, which is, if not required, at least strongly suggested by the Linux
>> networking layer.
>>
>> Without this patch, a huge number of alignment faults will be taken by the IP
>> stack, as seen in /proc/cpu/alignment:
>>
>> 	~/$ cat /proc/cpu/alignment
>> 	User:		0
>> 	System:		72645 (inet_gro_receive+0x104/0x27c)
>> 	Skipped:	0
>> 	Half:		0
>> 	Word:		0
>> 	DWord:		0
>> 	Multi:		72645
>> 	User faults:	3 (fixup+warn)
>>
>> With this patch, I am still seeing some alignment faults, but on the order of 10
>> after a 100MiB transfer instead of the 72k shown above.
>>
>> This patch was suggested by Andrew Lunn in this message to linux-netdev:
>> 	http://marc.info/?l=linux-arm-kernel&m=147465452108384&w=2
>>
>> and adapted from a patch by Russell King from 2014:
>> 	http://git.arm.linux.org.uk/cgit/linux-arm.git/commit/?h=fec-
>> testing&id=70d8a8a
>>
>> Signed-off-by: Eric Nelson <eric at nelint.com>
>> ---
>> I've only tested this patch on i.MX6UL at the moment, an encourage others
>> using 4.1.x to try it out.
>>
>> I did look at the RM for the i.MX6SX and updates will be needed for that
>> machine because the bit appears to be in a different location.
>>
>> Note that there are lots of other patches in Russell's tree that deserve some
>> effort in bringing up-stream and I encourage others to make use of his work.
>>
>>  drivers/net/ethernet/freescale/fec.h      |  4 ++++
>>  drivers/net/ethernet/freescale/fec_main.c | 36
> 
> Test pass the patch on i.MX6UL.
> But still have some comments as below.
> 
>> +++++++++++++++++++++++++------
>>  2 files changed, 34 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/net/ethernet/freescale/fec.h
>> b/drivers/net/ethernet/freescale/fec.h
>> index 65a3cd3..5ed0a5c 100644
>> --- a/drivers/net/ethernet/freescale/fec.h
>> +++ b/drivers/net/ethernet/freescale/fec.h
>> @@ -436,6 +436,7 @@ struct bufdesc_ex {
>>  #define FEC_QUIRK_SINGLE_MDIO		(1 << 11)
>>  /* Controller supports RACC register */
>>  #define FEC_QUIRK_HAS_RACC		(1 << 12)
>> +
>>  /*
>>   * i.MX6Q/DL ENET cannot wake up system in wait mode because ENET tx &
>> rx
>>   * interrupt signal don't connect to GPC. So use pm qos to avoid cpu enter
>> @@ -443,6 +444,9 @@ struct bufdesc_ex {
>>   */
>>  #define FEC_QUIRK_BUG_WAITMODE         (1 << 13)
>>
>> +/* Controller has ability to offset rx packets */
>> +#define FEC_QUIRK_RX_SHIFT16            (1 << 14)
>> + 
> 
> It is not necessary to define the quirk flag. 
> All SOCs with RACC register has the bit.   
> 

I just checked, and I was wrong in my comment about the SoloX
using a different bit. I think I was looking at the bitfield in the
ENETx_TACC register.

Okay. I'll re-work this for a V3 on linux-fslc.