[meta-freescale] [meta-fsl-arm-extra][PATCH v2 2/2] imx6q-elo: Rename board to imx6q-dms-ba16
Akshay Bhat
akshay.bhat at timesys.com
Mon Aug 8 08:35:37 PDT 2016
elo is a internal name used by GE for Advantech dms-ba16 board. The
board is a generic Advantech board, hence change the vendor to Advantech
and rename the board from elo to dms-ba16.
Signed-off-by: Akshay Bhat <akshay.bhat at timesys.com>
---
conf/machine/imx6q-dms-ba16.conf | 21 +
conf/machine/imx6q-elo.conf | 23 -
...-arm-imx-Add-support-for-GE-Bx50v3-boards.patch | 1245 --------------------
...0002-board-ge-bx50v3-Update-display-setup.patch | 293 -----
...dd-support-for-FSL-Community-Yocto-images.patch | 128 --
...board-ge-bx50v3-Add-support-for-ELO-board.patch | 222 ----
...oard-ge-bx50v3-Fix-bootargs-for-ELO-board.patch | 37 -
.../0006-mx6q_ba16-Add-1G-DDR-support.patch | 343 ------
...board-ge-bx50v3-Add-correct-SATA-settings.patch | 59 -
recipes-bsp/u-boot/u-boot-ge_2015.10.bb | 22 -
.../0001-rtc-rx8010-Add-driver-to-kernel.patch | 1020 ----------------
...Add-support-for-production-silicon-varian.patch | 101 --
...Upgrade-of-register-definitions-to-suppor.patch | 257 ----
.../linux-ge-3.14/0004-rtc-da9063-RTC-driver.patch | 399 -------
...da9063-Add-support-for-AD-silicon-variant.patch | 582 ---------
...Get-irq-base-dynamically-before-registeri.patch | 42 -
...7-mfd-da9063-Add-support-for-OnKey-driver.patch | 114 --
...i_imx-Make-receive-DPLL-mode-configurable.patch | 51 -
...d-DT-bindings-to-configure-PHY-Tx-driver-.patch | 112 --
...-dts-imx-Add-support-for-Advantech-GE-ELO.patch | 817 -------------
recipes-kernel/linux/linux-ge-3.14/defconfig | 453 -------
recipes-kernel/linux/linux-ge_3.14.bb | 25 -
22 files changed, 21 insertions(+), 6345 deletions(-)
create mode 100644 conf/machine/imx6q-dms-ba16.conf
delete mode 100644 conf/machine/imx6q-elo.conf
delete mode 100644 recipes-bsp/u-boot/u-boot-ge-2015.10/0001-arm-imx-Add-support-for-GE-Bx50v3-boards.patch
delete mode 100644 recipes-bsp/u-boot/u-boot-ge-2015.10/0002-board-ge-bx50v3-Update-display-setup.patch
delete mode 100644 recipes-bsp/u-boot/u-boot-ge-2015.10/0003-ge_bx50v3-Add-support-for-FSL-Community-Yocto-images.patch
delete mode 100644 recipes-bsp/u-boot/u-boot-ge-2015.10/0004-board-ge-bx50v3-Add-support-for-ELO-board.patch
delete mode 100644 recipes-bsp/u-boot/u-boot-ge-2015.10/0005-board-ge-bx50v3-Fix-bootargs-for-ELO-board.patch
delete mode 100644 recipes-bsp/u-boot/u-boot-ge-2015.10/0006-mx6q_ba16-Add-1G-DDR-support.patch
delete mode 100644 recipes-bsp/u-boot/u-boot-ge-2015.10/0007-board-ge-bx50v3-Add-correct-SATA-settings.patch
delete mode 100644 recipes-bsp/u-boot/u-boot-ge_2015.10.bb
delete mode 100644 recipes-kernel/linux/linux-ge-3.14/0001-rtc-rx8010-Add-driver-to-kernel.patch
delete mode 100644 recipes-kernel/linux/linux-ge-3.14/0002-mfd-da9063-Add-support-for-production-silicon-varian.patch
delete mode 100644 recipes-kernel/linux/linux-ge-3.14/0003-mfd-da9063-Upgrade-of-register-definitions-to-suppor.patch
delete mode 100644 recipes-kernel/linux/linux-ge-3.14/0004-rtc-da9063-RTC-driver.patch
delete mode 100644 recipes-kernel/linux/linux-ge-3.14/0005-mfd-da9063-Add-support-for-AD-silicon-variant.patch
delete mode 100644 recipes-kernel/linux/linux-ge-3.14/0006-mfd-da9063-Get-irq-base-dynamically-before-registeri.patch
delete mode 100644 recipes-kernel/linux/linux-ge-3.14/0007-mfd-da9063-Add-support-for-OnKey-driver.patch
delete mode 100644 recipes-kernel/linux/linux-ge-3.14/0008-ahci_imx-Make-receive-DPLL-mode-configurable.patch
delete mode 100644 recipes-kernel/linux/linux-ge-3.14/0009-PCI-imx6-Add-DT-bindings-to-configure-PHY-Tx-driver-.patch
delete mode 100644 recipes-kernel/linux/linux-ge-3.14/0010-ARM-dts-imx-Add-support-for-Advantech-GE-ELO.patch
delete mode 100644 recipes-kernel/linux/linux-ge-3.14/defconfig
delete mode 100644 recipes-kernel/linux/linux-ge_3.14.bb
diff --git a/conf/machine/imx6q-dms-ba16.conf b/conf/machine/imx6q-dms-ba16.conf
new file mode 100644
index 0000000..2b06499
--- /dev/null
+++ b/conf/machine/imx6q-dms-ba16.conf
@@ -0,0 +1,21 @@
+#@TYPE: Machine
+#@NAME: Advantech DMS BA16
+#@SOC: i.MX6Q
+#@DESCRIPTION: Machine configuration for Advantech DMS BA16 board
+#@MAINTAINER: Akshay Bhat <akshay.bhat at timesys.com>
+
+include conf/machine/include/imx-base.inc
+include conf/machine/include/tune-cortexa9.inc
+
+SOC_FAMILY = "mx6:mx6q"
+
+UBOOT_MACHINE = "dms-ba16_defconfig"
+
+PREFERRED_PROVIDER_virtual/kernel = "linux-advantech"
+PREFERRED_PROVIDER_kernel = "linux-advantech"
+KERNEL_DEVICETREE = "imx6q-dms-ba16.dtb"
+KERNEL_IMAGETYPE = "uImage"
+
+MACHINE_FEATURES += "pci"
+
+SERIAL_CONSOLE = "115200 ttymxc3"
diff --git a/conf/machine/imx6q-elo.conf b/conf/machine/imx6q-elo.conf
deleted file mode 100644
index 88c4c9f..0000000
--- a/conf/machine/imx6q-elo.conf
+++ /dev/null
@@ -1,23 +0,0 @@
-#@TYPE: Machine
-#@NAME: General Electric ELO
-#@SOC: i.MX6Q
-#@DESCRIPTION: Machine configuration for Advantech/GE ELO system
-#@MAINTAINER: Justin Waters <justin.waters at timesys.com>
-
-include conf/machine/include/imx-base.inc
-include conf/machine/include/tune-cortexa9.inc
-
-SOC_FAMILY = "mx6:mx6q"
-
-PREFERRED_PROVIDER_virtual/bootloader = "u-boot-ge"
-PREFERRED_PROVIDER_u-boot = "u-boot-ge"
-UBOOT_MACHINE = "ge_elo_yocto_defconfig"
-
-PREFERRED_PROVIDER_virtual/kernel = "linux-ge"
-PREFERRED_PROVIDER_kernel = "linux-ge"
-KERNEL_DEVICETREE = "imx6q-elo.dtb"
-KERNEL_IMAGETYPE = "uImage"
-
-MACHINE_FEATURES += "pci"
-
-SERIAL_CONSOLE = "115200 ttymxc3"
diff --git a/recipes-bsp/u-boot/u-boot-ge-2015.10/0001-arm-imx-Add-support-for-GE-Bx50v3-boards.patch b/recipes-bsp/u-boot/u-boot-ge-2015.10/0001-arm-imx-Add-support-for-GE-Bx50v3-boards.patch
deleted file mode 100644
index 9696a4a..0000000
--- a/recipes-bsp/u-boot/u-boot-ge-2015.10/0001-arm-imx-Add-support-for-GE-Bx50v3-boards.patch
+++ /dev/null
@@ -1,1245 +0,0 @@
-From b887466cde24f9bedd11af567e9dae02112f55ae Mon Sep 17 00:00:00 2001
-From: Akshay Bhat <akshay.bhat at timesys.com>
-Date: Wed, 9 Dec 2015 17:43:17 -0500
-Subject: [PATCH 1/7] arm: imx: Add support for GE Bx50v3 boards
-
-Add support for GE B450v3, B650v3 and B850v3 boards. The boards
-are based on Advantech BA16 module which has a i.MX6D processor.
-The boards support:
- - FEC Ethernet
- - USB Ports
- - SDHC and MMC boot
- - SPI NOR
- - LVDS and HDMI display
-
-Basic information about the module:
- - Module manufacturer: Advantech
- - CPU: Freescale ARM Cortex-A9 i.MX6D
- - SPECS:
- Up to 2GB Onboard DDR3 Memory;
- Up to 16GB Onboard eMMC NAND Flash
- Supports OpenGL ES 2.0 and OpenVG 1.1
- HDMI, 24-bit LVDS
- 1x UART, 2x I2C, 8x GPIO,
- 4x Host USB 2.0 port, 1x USB OTG port,
- 1x micro SD (SDHC),1x SDIO, 1x SATA II,
- 1x 10/100/1000 Mbps Ethernet, 1x PCIe X1 Gen2
-
-Signed-off-by: Akshay Bhat <akshay.bhat at timesys.com>
-Series-to: u-boot at lists.denx.de
-Series-cc: justin.waters at timesys.com
-Series-cc: sbabic at denx.de
-Series-cc: van.freenix at gmail.com
-Series-version: 2
-Series-changes: 2
-- Address comments from Peng Fan:
-- Use static for iomux definitions and imx6_rgmii_rework()
-- Use IS_ENABLED instead of ifdef in detect_baseboard()
-- Remove unused BMODE cmd
-- Get rid of CONFIG_SYS_EXTRA_OPTIONS and use Kconfig
-- Get rid of unused CONFIG_SYS_RECOVERY and CONFIG_ENV_IS_IN_MMC
-- Cleanup incorrect comments
-- Move gpio and display setup from board_early_init_f to board_init
-
-Upstream-Status: Submitted [u-boot at lists.denx.de]
----
- arch/arm/cpu/armv7/mx6/Kconfig | 13 +
- board/ge/bx50v3/Kconfig | 18 ++
- board/ge/bx50v3/MAINTAINERS | 8 +
- board/ge/bx50v3/Makefile | 8 +
- board/ge/bx50v3/bx50v3.c | 533 +++++++++++++++++++++++++++++++++++++++++
- board/ge/bx50v3/bx50v3.cfg | 151 ++++++++++++
- configs/ge_b450v3_defconfig | 8 +
- configs/ge_b650v3_defconfig | 8 +
- configs/ge_b850v3_defconfig | 8 +
- include/configs/ge_bx50v3.h | 349 +++++++++++++++++++++++++++
- 10 files changed, 1104 insertions(+)
- create mode 100644 board/ge/bx50v3/Kconfig
- create mode 100644 board/ge/bx50v3/MAINTAINERS
- create mode 100644 board/ge/bx50v3/Makefile
- create mode 100644 board/ge/bx50v3/bx50v3.c
- create mode 100644 board/ge/bx50v3/bx50v3.cfg
- create mode 100644 configs/ge_b450v3_defconfig
- create mode 100644 configs/ge_b650v3_defconfig
- create mode 100644 configs/ge_b850v3_defconfig
- create mode 100644 include/configs/ge_bx50v3.h
-
-diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
-index 8489182..722e0d0 100644
---- a/arch/arm/cpu/armv7/mx6/Kconfig
-+++ b/arch/arm/cpu/armv7/mx6/Kconfig
-@@ -60,6 +60,18 @@ config TARGET_CM_FX6
- config TARGET_EMBESTMX6BOARDS
- bool "embestmx6boards"
-
-+config TARGET_GE_B450V3
-+ bool "General Electric B450v3"
-+ select MX6Q
-+
-+config TARGET_GE_B650V3
-+ bool "General Electric B650v3"
-+ select MX6Q
-+
-+config TARGET_GE_B850V3
-+ bool "General Electric B850v3"
-+ select MX6Q
-+
- config TARGET_GW_VENTANA
- bool "gw_ventana"
- select SUPPORT_SPL
-@@ -153,6 +165,7 @@ endchoice
- config SYS_SOC
- default "mx6"
-
-+source "board/ge/bx50v3/Kconfig"
- source "board/aristainetos/Kconfig"
- source "board/bachmann/ot1200/Kconfig"
- source "board/barco/platinum/Kconfig"
-diff --git a/board/ge/bx50v3/Kconfig b/board/ge/bx50v3/Kconfig
-new file mode 100644
-index 0000000..d50dece
---- /dev/null
-+++ b/board/ge/bx50v3/Kconfig
-@@ -0,0 +1,18 @@
-+if TARGET_GE_B450V3 || TARGET_GE_B650V3 || TARGET_GE_B850V3
-+
-+config IMX_CONFIG
-+ default "board/ge/bx50v3/bx50v3.cfg"
-+
-+config SYS_BOARD
-+ default "bx50v3"
-+
-+config SYS_VENDOR
-+ default "ge"
-+
-+config SYS_SOC
-+ default "mx6"
-+
-+config SYS_CONFIG_NAME
-+ default "ge_bx50v3"
-+
-+endif
-diff --git a/board/ge/bx50v3/MAINTAINERS b/board/ge/bx50v3/MAINTAINERS
-new file mode 100644
-index 0000000..8e60791
---- /dev/null
-+++ b/board/ge/bx50v3/MAINTAINERS
-@@ -0,0 +1,8 @@
-+GE_BX50V3 BOARD
-+M: Martin Donnelly <martin.donnelly at ge.com>
-+S: Maintained
-+F: board/ge/bx50v3/
-+F: include/configs/ge_bx50v3.h
-+F: configs/ge_b450v3_defconfig
-+F: configs/ge_b650v3_defconfig
-+F: configs/ge_b850v3_defconfig
-diff --git a/board/ge/bx50v3/Makefile b/board/ge/bx50v3/Makefile
-new file mode 100644
-index 0000000..bcd149f
---- /dev/null
-+++ b/board/ge/bx50v3/Makefile
-@@ -0,0 +1,8 @@
-+#
-+# Copyright 2015 Timesys Corporation
-+# Copyright 2015 General Electric Company
-+#
-+# SPDX-License-Identifier: GPL-2.0+
-+#
-+
-+obj-y := bx50v3.o
-diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c
-new file mode 100644
-index 0000000..70c298d
---- /dev/null
-+++ b/board/ge/bx50v3/bx50v3.c
-@@ -0,0 +1,533 @@
-+/*
-+ * Copyright 2015 Timesys Corporation
-+ * Copyright 2015 General Electric Company
-+ * Copyright 2012 Freescale Semiconductor, Inc.
-+ *
-+ * SPDX-License-Identifier: GPL-2.0+
-+ */
-+
-+#include <asm/arch/clock.h>
-+#include <asm/arch/imx-regs.h>
-+#include <asm/arch/iomux.h>
-+#include <asm/arch/mx6-pins.h>
-+#include <asm/errno.h>
-+#include <asm/gpio.h>
-+#include <asm/imx-common/mxc_i2c.h>
-+#include <asm/imx-common/iomux-v3.h>
-+#include <asm/imx-common/boot_mode.h>
-+#include <asm/imx-common/video.h>
-+#include <mmc.h>
-+#include <fsl_esdhc.h>
-+#include <miiphy.h>
-+#include <netdev.h>
-+#include <asm/arch/mxc_hdmi.h>
-+#include <asm/arch/crm_regs.h>
-+#include <asm/io.h>
-+#include <asm/arch/sys_proto.h>
-+#include <i2c.h>
-+DECLARE_GLOBAL_DATA_PTR;
-+
-+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
-+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
-+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-+
-+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
-+ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
-+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-+
-+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
-+ PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
-+
-+#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
-+ PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
-+
-+#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
-+ PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
-+
-+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
-+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
-+
-+#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
-+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
-+ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
-+
-+#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
-+
-+int dram_init(void)
-+{
-+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
-+
-+ return 0;
-+}
-+
-+static iomux_v3_cfg_t const uart3_pads[] = {
-+ MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
-+ MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
-+ MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-+ MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-+};
-+
-+static iomux_v3_cfg_t const uart4_pads[] = {
-+ MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-+ MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-+};
-+
-+static iomux_v3_cfg_t const enet_pads[] = {
-+ MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
-+ MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
-+ MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
-+ MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-+ MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-+ MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-+ MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-+ MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
-+ MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
-+ MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-+ MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-+ MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-+ MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-+ MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-+ MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-+ /* AR8033 PHY Reset */
-+ MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
-+};
-+
-+static void setup_iomux_enet(void)
-+{
-+ imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
-+
-+ /* Reset AR8033 PHY */
-+ gpio_direction_output(IMX_GPIO_NR(1, 28), 0);
-+ udelay(500);
-+ gpio_set_value(IMX_GPIO_NR(1, 28), 1);
-+}
-+
-+static iomux_v3_cfg_t const usdhc2_pads[] = {
-+ MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-+ MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-+ MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-+ MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-+ MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-+ MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-+ MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
-+};
-+
-+static iomux_v3_cfg_t const usdhc3_pads[] = {
-+ MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-+ MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-+ MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-+ MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-+ MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-+ MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-+ MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-+ MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-+ MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-+ MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-+ MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-+};
-+
-+static iomux_v3_cfg_t const usdhc4_pads[] = {
-+ MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-+ MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-+ MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-+ MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-+ MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-+ MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-+ MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-+ MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-+ MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-+ MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-+ MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
-+ MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
-+};
-+
-+static iomux_v3_cfg_t const ecspi1_pads[] = {
-+ MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
-+ MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
-+ MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
-+ MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
-+};
-+
-+static struct i2c_pads_info i2c_pad_info1 = {
-+ .scl = {
-+ .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD,
-+ .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD,
-+ .gp = IMX_GPIO_NR(5, 27)
-+ },
-+ .sda = {
-+ .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD,
-+ .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD,
-+ .gp = IMX_GPIO_NR(5, 26)
-+ }
-+};
-+
-+static struct i2c_pads_info i2c_pad_info2 = {
-+ .scl = {
-+ .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
-+ .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
-+ .gp = IMX_GPIO_NR(4, 12)
-+ },
-+ .sda = {
-+ .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
-+ .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
-+ .gp = IMX_GPIO_NR(4, 13)
-+ }
-+};
-+
-+static struct i2c_pads_info i2c_pad_info3 = {
-+ .scl = {
-+ .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD,
-+ .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD,
-+ .gp = IMX_GPIO_NR(1, 3)
-+ },
-+ .sda = {
-+ .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD,
-+ .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD,
-+ .gp = IMX_GPIO_NR(1, 6)
-+ }
-+};
-+
-+#ifdef CONFIG_MXC_SPI
-+int board_spi_cs_gpio(unsigned bus, unsigned cs)
-+{
-+ return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1;
-+}
-+
-+static void setup_spi(void)
-+{
-+ imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
-+}
-+#endif
-+
-+static iomux_v3_cfg_t const pcie_pads[] = {
-+ MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
-+ MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
-+};
-+
-+static void setup_pcie(void)
-+{
-+ imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
-+}
-+
-+static void setup_iomux_uart(void)
-+{
-+ imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
-+ imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
-+}
-+
-+#ifdef CONFIG_FSL_ESDHC
-+struct fsl_esdhc_cfg usdhc_cfg[3] = {
-+ {USDHC2_BASE_ADDR},
-+ {USDHC3_BASE_ADDR},
-+ {USDHC4_BASE_ADDR},
-+};
-+
-+#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
-+#define USDHC4_CD_GPIO IMX_GPIO_NR(6, 11)
-+
-+int board_mmc_getcd(struct mmc *mmc)
-+{
-+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
-+ int ret = 0;
-+
-+ switch (cfg->esdhc_base) {
-+ case USDHC2_BASE_ADDR:
-+ ret = !gpio_get_value(USDHC2_CD_GPIO);
-+ break;
-+ case USDHC3_BASE_ADDR:
-+ ret = 1; /* eMMC is always present */
-+ break;
-+ case USDHC4_BASE_ADDR:
-+ ret = !gpio_get_value(USDHC4_CD_GPIO);
-+ break;
-+ }
-+
-+ return ret;
-+}
-+
-+int board_mmc_init(bd_t *bis)
-+{
-+ int ret;
-+ int i;
-+
-+ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
-+ switch (i) {
-+ case 0:
-+ imx_iomux_v3_setup_multiple_pads(
-+ usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
-+ gpio_direction_input(USDHC2_CD_GPIO);
-+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
-+ break;
-+ case 1:
-+ imx_iomux_v3_setup_multiple_pads(
-+ usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
-+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-+ break;
-+ case 2:
-+ imx_iomux_v3_setup_multiple_pads(
-+ usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
-+ gpio_direction_input(USDHC4_CD_GPIO);
-+ usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
-+ break;
-+ default:
-+ printf("Warning: you configured more USDHC controllers\n"
-+ "(%d) then supported by the board (%d)\n",
-+ i + 1, CONFIG_SYS_FSL_USDHC_NUM);
-+ return -EINVAL;
-+ }
-+
-+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
-+ if (ret)
-+ return ret;
-+ }
-+
-+ return 0;
-+}
-+#endif
-+
-+static int mx6_rgmii_rework(struct phy_device *phydev)
-+{
-+ /* Configure AR8033 to ouput a 125MHz clk from CLK_25M */
-+ /* set device address 0x7 */
-+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
-+ /* offset 0x8016: CLK_25M Clock Select */
-+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
-+ /* enable register write, no post increment, address 0x7 */
-+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
-+ /* set to 125 MHz from local PLL source */
-+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18);
-+
-+ /* rgmii tx clock delay enable */
-+ /* set debug port address: SerDes Test and System Mode Control */
-+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
-+ /* enable rgmii tx clock delay */
-+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
-+
-+ return 0;
-+}
-+
-+int board_phy_config(struct phy_device *phydev)
-+{
-+ mx6_rgmii_rework(phydev);
-+
-+ if (phydev->drv->config)
-+ phydev->drv->config(phydev);
-+
-+ return 0;
-+}
-+
-+#if defined(CONFIG_VIDEO_IPUV3)
-+static iomux_v3_cfg_t const backlight_pads[] = {
-+ /* Power for LVDS Display */
-+ MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
-+#define LVDS_POWER_GP IMX_GPIO_NR(3, 22)
-+ /* Backlight enable for LVDS display */
-+ MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
-+#define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 0)
-+};
-+
-+static void do_enable_hdmi(struct display_info_t const *dev)
-+{
-+ imx_enable_hdmi_phy();
-+}
-+
-+int board_cfb_skip(void)
-+{
-+ gpio_direction_output(LVDS_POWER_GP, 1);
-+
-+ return 0;
-+}
-+
-+static int detect_baseboard(struct display_info_t const *dev)
-+{
-+ if (IS_ENABLED(CONFIG_TARGET_GE_B450V3) ||
-+ IS_ENABLED(CONFIG_TARGET_GE_B650V3))
-+ return 1;
-+
-+ return 0;
-+}
-+
-+struct display_info_t const displays[] = {{
-+ .bus = -1,
-+ .addr = -1,
-+ .pixfmt = IPU_PIX_FMT_RGB24,
-+ .detect = detect_baseboard,
-+ .enable = NULL,
-+ .mode = {
-+ .name = "G121X1-L03",
-+ .refresh = 60,
-+ .xres = 1024,
-+ .yres = 768,
-+ .pixclock = 15385,
-+ .left_margin = 20,
-+ .right_margin = 300,
-+ .upper_margin = 30,
-+ .lower_margin = 8,
-+ .hsync_len = 1,
-+ .vsync_len = 1,
-+ .sync = FB_SYNC_EXT,
-+ .vmode = FB_VMODE_NONINTERLACED
-+} }, {
-+ .bus = -1,
-+ .addr = 3,
-+ .pixfmt = IPU_PIX_FMT_RGB24,
-+ .detect = detect_hdmi,
-+ .enable = do_enable_hdmi,
-+ .mode = {
-+ .name = "HDMI",
-+ .refresh = 60,
-+ .xres = 1024,
-+ .yres = 768,
-+ .pixclock = 15385,
-+ .left_margin = 220,
-+ .right_margin = 40,
-+ .upper_margin = 21,
-+ .lower_margin = 7,
-+ .hsync_len = 60,
-+ .vsync_len = 10,
-+ .sync = FB_SYNC_EXT,
-+ .vmode = FB_VMODE_NONINTERLACED
-+} } };
-+size_t display_count = ARRAY_SIZE(displays);
-+
-+static void setup_display(void)
-+{
-+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
-+ int reg;
-+
-+ enable_ipu_clock();
-+ imx_setup_hdmi();
-+
-+ reg = readl(&mxc_ccm->CCGR3);
-+ reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
-+ writel(reg, &mxc_ccm->CCGR3);
-+
-+ reg = readl(&mxc_ccm->cs2cdr);
-+ reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
-+ MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
-+ reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
-+ (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
-+ writel(reg, &mxc_ccm->cs2cdr);
-+
-+ reg = readl(&mxc_ccm->cscmr2);
-+ reg |= (MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
-+ writel(reg, &mxc_ccm->cscmr2);
-+
-+ reg = readl(&mxc_ccm->chsccdr);
-+ reg |= (CHSCCDR_CLK_SEL_LDB_DI0
-+ << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
-+ writel(reg, &mxc_ccm->chsccdr);
-+
-+ reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
-+ | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
-+ | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
-+ | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
-+ | IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT
-+ | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
-+ | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
-+ | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0
-+ | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
-+ writel(reg, &iomux->gpr[2]);
-+
-+ reg = readl(&iomux->gpr[3]);
-+ reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
-+ IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
-+ IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
-+ | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
-+ << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET)
-+ | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
-+ << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
-+ writel(reg, &iomux->gpr[3]);
-+
-+ /* backlights off until needed */
-+ imx_iomux_v3_setup_multiple_pads(backlight_pads,
-+ ARRAY_SIZE(backlight_pads));
-+ gpio_direction_input(LVDS_POWER_GP);
-+ gpio_direction_input(LVDS_BACKLIGHT_GP);
-+}
-+#endif /* CONFIG_VIDEO_IPUV3 */
-+
-+/*
-+ * Do not overwrite the console
-+ * Use always serial for U-Boot console
-+ */
-+int overwrite_console(void)
-+{
-+ return 1;
-+}
-+
-+int board_eth_init(bd_t *bis)
-+{
-+ setup_iomux_enet();
-+ setup_pcie();
-+
-+ return cpu_eth_init(bis);
-+}
-+
-+static iomux_v3_cfg_t const misc_pads[] = {
-+ MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
-+};
-+#define SUS_S3_OUT IMX_GPIO_NR(4, 11)
-+#define WIFI_EN IMX_GPIO_NR(6, 14)
-+
-+int board_early_init_f(void)
-+{
-+ imx_iomux_v3_setup_multiple_pads(misc_pads,
-+ ARRAY_SIZE(misc_pads));
-+
-+ setup_iomux_uart();
-+
-+
-+ return 0;
-+}
-+
-+int board_init(void)
-+{
-+ gpio_direction_output(SUS_S3_OUT, 1);
-+ gpio_direction_output(WIFI_EN, 1);
-+#if defined(CONFIG_VIDEO_IPUV3)
-+ setup_display();
-+#endif
-+ /* address of boot parameters */
-+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
-+
-+#ifdef CONFIG_MXC_SPI
-+ setup_spi();
-+#endif
-+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
-+ setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
-+ setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
-+
-+ return 0;
-+}
-+
-+#ifdef CONFIG_CMD_BMODE
-+static const struct boot_mode board_boot_modes[] = {
-+ /* 4 bit bus width */
-+ {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
-+ {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
-+ {NULL, 0},
-+};
-+#endif
-+
-+int board_late_init(void)
-+{
-+#ifdef CONFIG_CMD_BMODE
-+ add_board_boot_modes(board_boot_modes);
-+#endif
-+ /* We need at least 200ms between power on and backlight on
-+ * as per specifications from CHI MEI */
-+ mdelay(250);
-+
-+ /* Backlight Power */
-+ gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
-+
-+ return 0;
-+}
-+
-+int checkboard(void)
-+{
-+ printf("BOARD: %s\n", CONFIG_BOARD_NAME);
-+ return 0;
-+}
-diff --git a/board/ge/bx50v3/bx50v3.cfg b/board/ge/bx50v3/bx50v3.cfg
-new file mode 100644
-index 0000000..de88769
---- /dev/null
-+++ b/board/ge/bx50v3/bx50v3.cfg
-@@ -0,0 +1,151 @@
-+/*
-+ *
-+ * Copyright 2015 Timesys Corporation.
-+ * Copyright 2015 General Electric Company
-+ *
-+ * SPDX-License-Identifier: GPL-2.0+
-+ *
-+ * Refer doc/README.imximage for more details about how-to configure
-+ * and create imximage boot image
-+ *
-+ * The syntax is taken as close as possible with the kwbimage
-+ */
-+
-+IMAGE_VERSION 2
-+BOOT_FROM sd
-+
-+#define __ASSEMBLY__
-+#include <config.h>
-+#include "asm/arch/mx6-ddr.h"
-+#include "asm/arch/iomux.h"
-+#include "asm/arch/crm_regs.h"
-+
-+/* DDR IO */
-+DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000c0000
-+DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
-+DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000030
-+DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000030
-+DATA 4, MX6_IOM_DRAM_CAS, 0x00000030
-+DATA 4, MX6_IOM_DRAM_RAS, 0x00000030
-+DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
-+DATA 4, MX6_IOM_DRAM_RESET, 0x00000030
-+DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
-+DATA 4, MX6_IOM_DRAM_SDODT0, 0x00000030
-+DATA 4, MX6_IOM_DRAM_SDODT1, 0x00000030
-+DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
-+DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
-+DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
-+DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
-+DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
-+DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
-+DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
-+DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
-+DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
-+DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
-+DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
-+DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
-+DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
-+DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
-+DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
-+DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
-+DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
-+DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
-+DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
-+DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030
-+DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030
-+DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030
-+DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030
-+DATA 4, MX6_IOM_DRAM_DQM4, 0x00000030
-+DATA 4, MX6_IOM_DRAM_DQM5, 0x00000030
-+DATA 4, MX6_IOM_DRAM_DQM6, 0x00000030
-+DATA 4, MX6_IOM_DRAM_DQM7, 0x00000030
-+
-+/* Calibrations */
-+/* ZQ */
-+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003
-+/* write leveling */
-+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F
-+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
-+DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F001F
-+DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F
-+/* Read DQS Gating calibration */
-+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x45380544
-+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x05280530
-+DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x4530053C
-+DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x0530050C
-+/* Read calibration */
-+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x36303032
-+DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x38363042
-+/* Write calibration */
-+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3A3A423E
-+DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4A38483E
-+/* read data bit delay */
-+DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
-+DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
-+DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
-+DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
-+DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
-+DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
-+DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
-+DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
-+
-+/* Complete calibration by forced measurment */
-+DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
-+DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
-+
-+/* MMDC init */
-+DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036
-+DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
-+DATA 4, MX6_MMDC_P0_MDCFG0, 0x8A8F79A4
-+DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538E64
-+DATA 4, MX6_MMDC_P0_MDCFG2, 0x01ff00db
-+DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740
-+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
-+DATA 4, MX6_MMDC_P0_MDRWD, 0x000026d2
-+DATA 4, MX6_MMDC_P0_MDOR, 0x008F1023
-+DATA 4, MX6_MMDC_P0_MDASP, 0x00000047
-+DATA 4, MX6_MMDC_P0_MDCTL, 0x841a0000
-+
-+/* Initialize Micron MT41J128M */
-+DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032
-+DATA 4, MX6_MMDC_P0_MDSCR, 0x0408803a
-+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
-+DATA 4, MX6_MMDC_P0_MDSCR, 0x0000803b
-+DATA 4, MX6_MMDC_P0_MDSCR, 0x00408031
-+DATA 4, MX6_MMDC_P0_MDSCR, 0x00408039
-+DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030
-+DATA 4, MX6_MMDC_P0_MDSCR, 0x09408038
-+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
-+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008048
-+DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
-+DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00011117
-+DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00011117
-+DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
-+DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
-+DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
-+
-+/* set the default clock gate to save power */
-+DATA 4, CCM_CCGR0, 0x00C03F3F
-+DATA 4, CCM_CCGR1, 0x0030FC03
-+DATA 4, CCM_CCGR2, 0x0FFFC000
-+DATA 4, CCM_CCGR3, 0x3FF00000
-+DATA 4, CCM_CCGR4, 0x00FFF300
-+DATA 4, CCM_CCGR5, 0x0F0000C3
-+DATA 4, CCM_CCGR6, 0x000003FF
-+
-+/* enable AXI cache for VDOA/VPU/IPU */
-+DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
-+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-+DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
-+DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
-+
-+/*
-+ * Setup CCM_CCOSR register as follows:
-+ *
-+ * cko1_en 1 --> CKO1 enabled
-+ * cko1_div 111 --> divide by 8
-+ * cko1_sel 1011 --> ahb_clk_root
-+ *
-+ * This sets CKO1 at ahb_clk_root/8 132/8 16.5 MHz
-+ */
-+DATA 4, CCM_CCOSR, 0x000000fb
-diff --git a/configs/ge_b450v3_defconfig b/configs/ge_b450v3_defconfig
-new file mode 100644
-index 0000000..02873ce
---- /dev/null
-+++ b/configs/ge_b450v3_defconfig
-@@ -0,0 +1,8 @@
-+CONFIG_ARM=y
-+CONFIG_ARCH_MX6=y
-+CONFIG_TARGET_GE_B450V3=y
-+# CONFIG_CMD_IMLS is not set
-+# CONFIG_CMD_FLASH is not set
-+CONFIG_CMD_GPIO=y
-+CONFIG_SPI_FLASH=y
-+CONFIG_SPI_FLASH_STMICRO=y
-diff --git a/configs/ge_b650v3_defconfig b/configs/ge_b650v3_defconfig
-new file mode 100644
-index 0000000..3d10b35
---- /dev/null
-+++ b/configs/ge_b650v3_defconfig
-@@ -0,0 +1,8 @@
-+CONFIG_ARM=y
-+CONFIG_ARCH_MX6=y
-+CONFIG_TARGET_GE_B650V3=y
-+# CONFIG_CMD_IMLS is not set
-+# CONFIG_CMD_FLASH is not set
-+CONFIG_CMD_GPIO=y
-+CONFIG_SPI_FLASH=y
-+CONFIG_SPI_FLASH_STMICRO=y
-diff --git a/configs/ge_b850v3_defconfig b/configs/ge_b850v3_defconfig
-new file mode 100644
-index 0000000..e3f4a0a
---- /dev/null
-+++ b/configs/ge_b850v3_defconfig
-@@ -0,0 +1,8 @@
-+CONFIG_ARM=y
-+CONFIG_ARCH_MX6=y
-+CONFIG_TARGET_GE_B850V3=y
-+# CONFIG_CMD_IMLS is not set
-+# CONFIG_CMD_FLASH is not set
-+CONFIG_CMD_GPIO=y
-+CONFIG_SPI_FLASH=y
-+CONFIG_SPI_FLASH_STMICRO=y
-diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h
-new file mode 100644
-index 0000000..6fa4a9a
---- /dev/null
-+++ b/include/configs/ge_bx50v3.h
-@@ -0,0 +1,349 @@
-+/*
-+ * Copyright (C) 2015 Timesys Corporation
-+ * Copyright (C) 2015 General Electric Company
-+ * Copyright (C) 2014 Advantech
-+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
-+ *
-+ * Configuration settings for the GE MX6Q Bx50v3 boards.
-+ *
-+ * SPDX-License-Identifier: GPL-2.0+
-+ */
-+
-+#ifndef __GE_BX50V3_CONFIG_H
-+#define __GE_BX50V3_CONFIG_H
-+
-+#include <asm/arch/imx-regs.h>
-+#include <asm/imx-common/gpio.h>
-+
-+#if defined(CONFIG_TARGET_GE_B450V3)
-+#define CONFIG_BOARD_NAME "General Electric B450v3"
-+#define CONFIG_DEFAULT_FDT_FILE "/boot/imx6q-b450v3.dtb"
-+#elif defined(CONFIG_TARGET_GE_B650V3)
-+#define CONFIG_BOARD_NAME "General Electric B650v3"
-+#define CONFIG_DEFAULT_FDT_FILE "/boot/imx6q-b650v3.dtb"
-+#elif defined(CONFIG_TARGET_GE_B850V3)
-+#define CONFIG_BOARD_NAME "General Electric B850v3"
-+#define CONFIG_DEFAULT_FDT_FILE "/boot/imx6q-b850v3.dtb"
-+#else
-+#define CONFIG_BOARD_NAME "General Electric BA16 Generic"
-+#define CONFIG_DEFAULT_FDT_FILE "/boot/imx6q-ba16.dtb"
-+#endif
-+
-+#define CONFIG_MXC_UART_BASE UART3_BASE
-+#define CONFIG_CONSOLE_DEV "ttymxc2"
-+
-+#define PHYS_SDRAM_SIZE (2u * 1024 * 1024 * 1024)
-+
-+#define CONFIG_SUPPORT_EMMC_BOOT
-+
-+#define CONFIG_BOOTDELAY 1
-+
-+#include "mx6_common.h"
-+#include <linux/sizes.h>
-+
-+#define CONFIG_DISPLAY_CPUINFO
-+#define CONFIG_DISPLAY_BOARDINFO
-+
-+#define CONFIG_CMDLINE_TAG
-+#define CONFIG_SETUP_MEMORY_TAGS
-+#define CONFIG_INITRD_TAG
-+#define CONFIG_REVISION_TAG
-+#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
-+
-+#define CONFIG_BOARD_EARLY_INIT_F
-+#define CONFIG_BOARD_LATE_INIT
-+
-+#define CONFIG_MXC_GPIO
-+#define CONFIG_MXC_UART
-+
-+#define CONFIG_CMD_FUSE
-+#define CONFIG_MXC_OCOTP
-+
-+/* SATA Configs */
-+#define CONFIG_CMD_SATA
-+#define CONFIG_DWC_AHSATA
-+#define CONFIG_SYS_SATA_MAX_DEVICE 1
-+#define CONFIG_DWC_AHSATA_PORT_ID 0
-+#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
-+#define CONFIG_LBA48
-+#define CONFIG_LIBATA
-+
-+/* MMC Configs */
-+#define CONFIG_FSL_ESDHC
-+#define CONFIG_FSL_USDHC
-+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-+#define CONFIG_MMC
-+#define CONFIG_CMD_MMC
-+#define CONFIG_GENERIC_MMC
-+#define CONFIG_BOUNCE_BUFFER
-+#define CONFIG_CMD_EXT2
-+#define CONFIG_CMD_FAT
-+#define CONFIG_DOS_PARTITION
-+
-+/* USB Configs */
-+#define CONFIG_CMD_USB
-+#define CONFIG_CMD_FAT
-+#define CONFIG_USB_EHCI
-+#define CONFIG_USB_EHCI_MX6
-+#define CONFIG_USB_STORAGE
-+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-+#define CONFIG_MXC_USB_FLAGS 0
-+#define CONFIG_USB_KEYBOARD
-+#define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP
-+
-+#define CONFIG_CI_UDC
-+#define CONFIG_USBD_HS
-+#define CONFIG_USB_GADGET_DUALSPEED
-+#define CONFIG_USB_GADGET
-+#define CONFIG_USB_GADGET_DOWNLOAD
-+#define CONFIG_CMD_USB_MASS_STORAGE
-+#define CONFIG_USB_GADGET_MASS_STORAGE
-+#define CONFIG_USB_FUNCTION_MASS_STORAGE
-+#define CONFIG_USB_GADGET_VBUS_DRAW 2
-+#define CONFIG_G_DNL_VENDOR_NUM 0x0525
-+#define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5
-+#define CONFIG_G_DNL_MANUFACTURER "Advantech"
-+
-+/* Networking Configs */
-+#define CONFIG_CMD_PING
-+#define CONFIG_CMD_DHCP
-+#define CONFIG_CMD_MII
-+#define CONFIG_FEC_MXC
-+#define CONFIG_MII
-+#define IMX_FEC_BASE ENET_BASE_ADDR
-+#define CONFIG_FEC_XCV_TYPE RGMII
-+#define CONFIG_ETHPRIME "FEC"
-+#define CONFIG_FEC_MXC_PHYADDR 4
-+#define CONFIG_PHYLIB
-+#define CONFIG_PHY_ATHEROS
-+
-+/* Serial Flash */
-+#define CONFIG_CMD_SF
-+#ifdef CONFIG_CMD_SF
-+#define CONFIG_MXC_SPI
-+#define CONFIG_SF_DEFAULT_BUS 0
-+#define CONFIG_SF_DEFAULT_CS 0
-+#define CONFIG_SF_DEFAULT_SPEED 20000000
-+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
-+#endif
-+
-+/* allow to overwrite serial and ethaddr */
-+#define CONFIG_ENV_OVERWRITE
-+#define CONFIG_CONS_INDEX 1
-+#define CONFIG_BAUDRATE 115200
-+
-+/* Command definition */
-+#define CONFIG_CMD_BMODE
-+#define CONFIG_CMD_BOOTZ
-+#undef CONFIG_CMD_IMLS
-+
-+#define CONFIG_LOADADDR 0x12000000
-+#define CONFIG_SYS_TEXT_BASE 0x17800000
-+
-+#define CONFIG_EXTRA_ENV_SETTINGS \
-+ "script=boot.scr\0" \
-+ "image=/boot/uImage\0" \
-+ "uboot=u-boot.imx\0" \
-+ "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
-+ "fdt_addr=0x18000000\0" \
-+ "boot_fdt=yes\0" \
-+ "ip_dyn=yes\0" \
-+ "console=" CONFIG_CONSOLE_DEV "\0" \
-+ "fdt_high=0xffffffff\0" \
-+ "initrd_high=0xffffffff\0" \
-+ "sddev=0\0" \
-+ "emmcdev=1\0" \
-+ "partnum=1\0" \
-+ "update_sd_firmware=" \
-+ "if test ${ip_dyn} = yes; then " \
-+ "setenv get_cmd dhcp; " \
-+ "else " \
-+ "setenv get_cmd tftp; " \
-+ "fi; " \
-+ "if mmc dev ${mmcdev}; then " \
-+ "if ${get_cmd} ${update_sd_firmware_filename}; then " \
-+ "setexpr fw_sz ${filesize} / 0x200; " \
-+ "setexpr fw_sz ${fw_sz} + 1; " \
-+ "mmc write ${loadaddr} 0x2 ${fw_sz}; " \
-+ "fi; " \
-+ "fi\0" \
-+ "update_sf_uboot=" \
-+ "if tftp $loadaddr $uboot; then " \
-+ "sf probe; " \
-+ "sf erase 0 0xC0000; " \
-+ "sf write $loadaddr 0x400 $filesize; " \
-+ "echo 'U-Boot upgraded. Please reset'; " \
-+ "fi\0" \
-+ "setargs=setenv bootargs console=${console},${baudrate} " \
-+ "root=/dev/${rootdev} rw rootwait cma=128M\0" \
-+ "loadbootscript=" \
-+ "ext2load ${dev} ${devnum}:${partnum} ${loadaddr} ${script};\0" \
-+ "bootscript=echo Running bootscript from ${dev}:${devnum}:${partnum};" \
-+ " source\0" \
-+ "loadimage=" \
-+ "ext2load ${dev} ${devnum}:${partnum} ${loadaddr} ${image}\0" \
-+ "loadfdt=ext2load ${dev} ${devnum}:${partnum} ${fdt_addr} ${fdt_file}\0" \
-+ "tryboot=" \
-+ "if run loadbootscript; then " \
-+ "run bootscript; " \
-+ "else " \
-+ "if run loadimage; then " \
-+ "run doboot; " \
-+ "fi; " \
-+ "fi;\0" \
-+ "doboot=echo Booting from ${dev}:${devnum}:${partnum} ...; " \
-+ "run setargs; " \
-+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
-+ "if run loadfdt; then " \
-+ "bootm ${loadaddr} - ${fdt_addr}; " \
-+ "else " \
-+ "if test ${boot_fdt} = try; then " \
-+ "bootm; " \
-+ "else " \
-+ "echo WARN: Cannot load the DT; " \
-+ "fi; " \
-+ "fi; " \
-+ "else " \
-+ "bootm; " \
-+ "fi;\0" \
-+ "netargs=setenv bootargs console=${console},${baudrate} " \
-+ "root=/dev/nfs " \
-+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
-+ "netboot=echo Booting from net ...; " \
-+ "run netargs; " \
-+ "if test ${ip_dyn} = yes; then " \
-+ "setenv get_cmd dhcp; " \
-+ "else " \
-+ "setenv get_cmd tftp; " \
-+ "fi; " \
-+ "${get_cmd} ${image}; " \
-+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
-+ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
-+ "bootm ${loadaddr} - ${fdt_addr}; " \
-+ "else " \
-+ "if test ${boot_fdt} = try; then " \
-+ "bootm; " \
-+ "else " \
-+ "echo WARN: Cannot load the DT; " \
-+ "fi; " \
-+ "fi; " \
-+ "else " \
-+ "bootm; " \
-+ "fi;\0" \
-+
-+#define CONFIG_BOOTCOMMAND \
-+ "usb start; " \
-+ "setenv dev usb; " \
-+ "setenv devnum 0; " \
-+ "setenv rootdev sda1; " \
-+ "run tryboot; " \
-+ \
-+ "setenv dev mmc; " \
-+ "setenv rootdev mmcblk0p1; " \
-+ \
-+ "setenv devnum ${sddev}; " \
-+ "if mmc dev ${devnum}; then " \
-+ "run tryboot; " \
-+ "setenv rootdev mmcblk1p1; " \
-+ "fi; " \
-+ \
-+ "setenv devnum ${emmcdev}; " \
-+ "if mmc dev ${devnum}; then " \
-+ "run tryboot; " \
-+ "fi; " \
-+ \
-+ "bmode usb; " \
-+
-+#define CONFIG_ARP_TIMEOUT 200UL
-+
-+/* Miscellaneous configurable options */
-+#define CONFIG_SYS_LONGHELP
-+#define CONFIG_SYS_HUSH_PARSER
-+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-+#define CONFIG_AUTO_COMPLETE
-+
-+/* Print Buffer Size */
-+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-+
-+#define CONFIG_SYS_MEMTEST_START 0x10000000
-+#define CONFIG_SYS_MEMTEST_END 0x10010000
-+#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
-+
-+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-+
-+#define CONFIG_CMDLINE_EDITING
-+#define CONFIG_STACKSIZE (128 * 1024)
-+
-+/* Physical Memory Map */
-+#define CONFIG_NR_DRAM_BANKS 1
-+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-+
-+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
-+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
-+
-+#define CONFIG_SYS_INIT_SP_OFFSET \
-+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-+#define CONFIG_SYS_INIT_SP_ADDR \
-+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-+
-+/* FLASH and environment organization */
-+#define CONFIG_SYS_NO_FLASH
-+
-+#define CONFIG_ENV_IS_IN_SPI_FLASH
-+#define CONFIG_ENV_SIZE (8 * 1024)
-+#define CONFIG_ENV_OFFSET (768 * 1024)
-+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
-+#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
-+#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
-+#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
-+#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
-+
-+#define CONFIG_OF_LIBFDT
-+
-+#ifndef CONFIG_SYS_DCACHE_OFF
-+#define CONFIG_CMD_CACHE
-+#endif
-+
-+#define CONFIG_SYS_FSL_USDHC_NUM 3
-+
-+/* Framebuffer */
-+#define CONFIG_VIDEO
-+#define CONFIG_VIDEO_IPUV3
-+#define CONFIG_CFB_CONSOLE
-+#define CONFIG_VGA_AS_SINGLE_DEVICE
-+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
-+#define CONFIG_VIDEO_BMP_RLE8
-+#define CONFIG_SPLASH_SCREEN
-+#define CONFIG_SPLASH_SCREEN_ALIGN
-+#define CONFIG_BMP_16BPP
-+#define CONFIG_VIDEO_LOGO
-+#define CONFIG_VIDEO_BMP_LOGO
-+#define CONFIG_IPUV3_CLK 260000000
-+#define CONFIG_IMX_HDMI
-+#define CONFIG_IMX_VIDEO_SKIP
-+
-+#undef CONFIG_CMD_PCI
-+#ifdef CONFIG_CMD_PCI
-+#define CONFIG_PCI
-+#define CONFIG_PCI_PNP
-+#define CONFIG_PCI_SCAN_SHOW
-+#define CONFIG_PCIE_IMX
-+#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12)
-+#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(1, 5)
-+#endif
-+
-+/* I2C Configs */
-+#define CONFIG_CMD_I2C
-+#define CONFIG_SYS_I2C
-+#define CONFIG_SYS_I2C_MXC
-+#define CONFIG_SYS_I2C_SPEED 100000
-+#define CONFIG_SYS_I2C_MXC_I2C1
-+#define CONFIG_SYS_I2C_MXC_I2C2
-+#define CONFIG_SYS_I2C_MXC_I2C3
-+
-+#endif /* __GE_BX50V3_CONFIG_H */
---
-2.5.0
-
diff --git a/recipes-bsp/u-boot/u-boot-ge-2015.10/0002-board-ge-bx50v3-Update-display-setup.patch b/recipes-bsp/u-boot/u-boot-ge-2015.10/0002-board-ge-bx50v3-Update-display-setup.patch
deleted file mode 100644
index 2ee2b31..0000000
--- a/recipes-bsp/u-boot/u-boot-ge-2015.10/0002-board-ge-bx50v3-Update-display-setup.patch
+++ /dev/null
@@ -1,293 +0,0 @@
-From 047844511f92e9e9ea089f019318280cb4c3a75a Mon Sep 17 00:00:00 2001
-From: Akshay Bhat <akshay.bhat at timesys.com>
-Date: Thu, 4 Feb 2016 12:22:52 -0500
-Subject: [PATCH 2/7] board: ge: bx50v3: Update display setup
-
-- Disable LVDS1 on B450v3/B650v3 boards since they no longer have
-connectors for it.
-- Implement imx6 MLK-10782-3 or ERR009219 errata for LVDS clock switch.
-This patch was ported from Freescale 3.10.17_1.0.0_ga kernel to u-boot.
-- Split the display setup into 2 different functions. One for B850v3 that
-does a setup of LVDS and HDMI with clock source for LVDS/IPU_DI set to
-video PLL. The other for B450v3/B650v3 that does a setup of LVDS only with
-clock source for LVDS/IPU_DI set to USB PLL.
-
-Upstream-Status: Pending
-
-Waiting on v2 patch to get accepted.
-http://lists.denx.de/pipermail/u-boot/2016-January/243985.html
-
-Signed-off-by: Akshay Bhat <akshay.bhat at timesys.com>
----
- board/ge/bx50v3/bx50v3.c | 240 ++++++++++++++++++++++++++++++++++++++---------
- 1 file changed, 198 insertions(+), 42 deletions(-)
-
-diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c
-index 70c298d..cf2cd1a 100644
---- a/board/ge/bx50v3/bx50v3.c
-+++ b/board/ge/bx50v3/bx50v3.c
-@@ -390,55 +390,208 @@ struct display_info_t const displays[] = {{
- } } };
- size_t display_count = ARRAY_SIZE(displays);
-
--static void setup_display(void)
-+static void enable_videopll(void)
-+{
-+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-+ s32 timeout = 100000;
-+
-+ setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
-+
-+ /* set video pll to 910MHz (24MHz * (37+11/12))
-+ * video pll post div to 910/4 = 227.5MHz
-+ */
-+ clrsetbits_le32(&ccm->analog_pll_video,
-+ BM_ANADIG_PLL_VIDEO_DIV_SELECT |
-+ BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
-+ BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) |
-+ BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0));
-+
-+ writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
-+ writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
-+
-+ clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
-+
-+ while (timeout--)
-+ if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
-+ break;
-+ if (timeout < 0)
-+ printf("Warning: video pll lock timeout!\n");
-+
-+ clrsetbits_le32(&ccm->analog_pll_video,
-+ BM_ANADIG_PLL_VIDEO_BYPASS,
-+ BM_ANADIG_PLL_VIDEO_ENABLE);
-+}
-+
-+static void set_ldb_clock_source(u8 source)
- {
- struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-- struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
- int reg;
-+ /*
-+ * Need to follow a strict procedure when changing the LDB
-+ * clock, else we can introduce a glitch. Things to keep in
-+ * mind:
-+ * 1. The current and new parent clocks must be disabled.
-+ * 2. The default clock for ldb_dio_clk is mmdc_ch1 which has
-+ * no CG bit.
-+ * 3. In the RTL implementation of the LDB_DI_CLK_SEL mux
-+ * the top four options are in one mux and the PLL3 option along
-+ * with another option is in the second mux. There is third mux
-+ * used to decide between the first and second mux.
-+ * The code below switches the parent to the bottom mux first
-+ * and then manipulates the top mux. This ensures that no glitch
-+ * will enter the divider.
-+ *
-+ * Need to disable MMDC_CH1 clock manually as there is no CG bit
-+ * for this clock. The only way to disable this clock is to move
-+ * it to pll3_sw_clk and then to disable pll3_sw_clk
-+ * Make sure periph2_clk2_sel is set to pll3_sw_clk
-+ */
-+ /* Set MMDC_CH1 mask bit */
-+ reg = readl(&mxc_ccm->ccdr);
-+ reg |= MXC_CCM_CCDR_MMDC_CH1_HS_MASK;
-+ writel(reg, &mxc_ccm->ccdr);
-+
-+ /* Set periph2_clk2_sel to be sourced from PLL3_sw_clk */
-+ reg = readl(&mxc_ccm->cbcmr);
-+ reg &= ~MXC_CCM_CBCMR_PERIPH2_CLK2_SEL;
-+ writel(reg, &mxc_ccm->cbcmr);
-+
-+ /*
-+ * Set the periph2_clk_sel to the top mux so that
-+ * mmdc_ch1 is from pll3_sw_clk.
-+ */
-+ reg = readl(&mxc_ccm->cbcdr);
-+ reg |= MXC_CCM_CBCDR_PERIPH2_CLK_SEL;
-+ writel(reg, &mxc_ccm->cbcdr);
-+
-+ /* Wait for the clock switch */
-+ while (readl(&mxc_ccm->cdhipr))
-+ ;
-+ /* Disable pll3_sw_clk by selecting bypass clock source */
-+ reg = readl(&mxc_ccm->ccsr);
-+ reg |= MXC_CCM_CCSR_PLL3_SW_CLK_SEL;
-+ writel(reg, &mxc_ccm->ccsr);
-+
-+ /* Set the ldb_di0_clk and ldb_di1_clk to 111b */
-+ reg = readl(&mxc_ccm->cs2cdr);
-+ reg |= ((7 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
-+ | (7 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
-+ writel(reg, &mxc_ccm->cs2cdr);
-
-- enable_ipu_clock();
-- imx_setup_hdmi();
--
-- reg = readl(&mxc_ccm->CCGR3);
-- reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
-- writel(reg, &mxc_ccm->CCGR3);
-+ /* Set the ldb_di0_clk and ldb_di1_clk to 100b */
-+ reg = readl(&mxc_ccm->cs2cdr);
-+ reg &= ~(MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK
-+ | MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK);
-+ reg |= ((4 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
-+ | (4 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
-+ writel(reg, &mxc_ccm->cs2cdr);
-
-+ /* Set the ldb_di0_clk and ldb_di1_clk to desired source */
- reg = readl(&mxc_ccm->cs2cdr);
-- reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
-- MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
-- reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
-- (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
-+ reg &= ~(MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK
-+ | MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK);
-+ reg |= ((source << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
-+ | (source << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
- writel(reg, &mxc_ccm->cs2cdr);
-
-- reg = readl(&mxc_ccm->cscmr2);
-- reg |= (MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
-- writel(reg, &mxc_ccm->cscmr2);
--
-- reg = readl(&mxc_ccm->chsccdr);
-- reg |= (CHSCCDR_CLK_SEL_LDB_DI0
-- << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
-- writel(reg, &mxc_ccm->chsccdr);
--
-- reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
-- | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
-- | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
-- | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
-- | IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT
-- | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
-- | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
-- | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0
-- | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
-- writel(reg, &iomux->gpr[2]);
--
-- reg = readl(&iomux->gpr[3]);
-- reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
-- IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
-- IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
-- | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
-- << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET)
-- | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
-- << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
-- writel(reg, &iomux->gpr[3]);
-+ /* Unbypass pll3_sw_clk */
-+ reg = readl(&mxc_ccm->ccsr);
-+ reg &= ~MXC_CCM_CCSR_PLL3_SW_CLK_SEL;
-+ writel(reg, &mxc_ccm->ccsr);
-+
-+ /*
-+ * Set the periph2_clk_sel back to the bottom mux so that
-+ * mmdc_ch1 is from its original parent.
-+ */
-+ reg = readl(&mxc_ccm->cbcdr);
-+ reg &= ~MXC_CCM_CBCDR_PERIPH2_CLK_SEL;
-+ writel(reg, &mxc_ccm->cbcdr);
-+
-+ /* Wait for the clock switch */
-+ while (readl(&mxc_ccm->cdhipr))
-+ ;
-+ /* Clear MMDC_CH1 mask bit */
-+ reg = readl(&mxc_ccm->ccdr);
-+ reg &= ~MXC_CCM_CCDR_MMDC_CH1_HS_MASK;
-+ writel(reg, &mxc_ccm->ccdr);
-+}
-+
-+static void setup_display_b850v3(void)
-+{
-+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
-+
-+ /* Set LDB clock to Video PLL */
-+ set_ldb_clock_source(0);
-+ enable_videopll();
-+
-+ /* IPU1 D0 clock is 227.5 / 3.5 = 65MHz */
-+ clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
-+
-+ imx_setup_hdmi();
-+
-+ /* Set LDB_DI0 as clock source for IPU_DI0 */
-+ clrsetbits_le32(&mxc_ccm->chsccdr,
-+ MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
-+ (CHSCCDR_CLK_SEL_LDB_DI0 <<
-+ MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
-+
-+ /* Turn on IPU LDB DI0 clocks */
-+ setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
-+
-+ enable_ipu_clock();
-+
-+ writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
-+ IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
-+ IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
-+ IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
-+ IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
-+ IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
-+ IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
-+ IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
-+ IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
-+ IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0,
-+ &iomux->gpr[2]);
-+
-+ clrbits_le32(&iomux->gpr[3],
-+ IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
-+ IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
-+ IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
-+}
-+
-+static void setup_display_bx50v3(void)
-+{
-+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
-+
-+ /* Set LDB clock to USB PLL */
-+ set_ldb_clock_source(4);
-+
-+ /* IPU1 DI0 clock is 480/7 = 68.5 MHz */
-+ setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
-+
-+ /* Set LDB_DI0 as clock source for IPU_DI0 */
-+ clrsetbits_le32(&mxc_ccm->chsccdr,
-+ MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
-+ (CHSCCDR_CLK_SEL_LDB_DI0 <<
-+ MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
-+
-+ /* Turn on IPU LDB DI0 clocks */
-+ setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
-+
-+ enable_ipu_clock();
-+
-+ writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
-+ IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
-+ IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
-+ IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
-+ IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
-+ &iomux->gpr[2]);
-+
-+ clrsetbits_le32(&iomux->gpr[3],
-+ IOMUXC_GPR3_LVDS0_MUX_CTL_MASK,
-+ (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
-+ IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET));
-
- /* backlights off until needed */
- imx_iomux_v3_setup_multiple_pads(backlight_pads,
-@@ -487,7 +640,10 @@ int board_init(void)
- gpio_direction_output(SUS_S3_OUT, 1);
- gpio_direction_output(WIFI_EN, 1);
- #if defined(CONFIG_VIDEO_IPUV3)
-- setup_display();
-+ if (IS_ENABLED(CONFIG_TARGET_GE_B850V3))
-+ setup_display_b850v3();
-+ else
-+ setup_display_bx50v3();
- #endif
- /* address of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
---
-2.5.0
-
diff --git a/recipes-bsp/u-boot/u-boot-ge-2015.10/0003-ge_bx50v3-Add-support-for-FSL-Community-Yocto-images.patch b/recipes-bsp/u-boot/u-boot-ge-2015.10/0003-ge_bx50v3-Add-support-for-FSL-Community-Yocto-images.patch
deleted file mode 100644
index b5e3a52..0000000
--- a/recipes-bsp/u-boot/u-boot-ge-2015.10/0003-ge_bx50v3-Add-support-for-FSL-Community-Yocto-images.patch
+++ /dev/null
@@ -1,128 +0,0 @@
-From 6b0a4665c760d25362752cc57ee239bb19e4f87d Mon Sep 17 00:00:00 2001
-From: Justin Waters <justin.waters at timesys.com>
-Date: Wed, 9 Mar 2016 13:16:39 -0500
-Subject: [PATCH 3/7] ge_bx50v3: Add support for FSL Community Yocto images
-
-The Freescale community images use two partitions: one for
-boot files, the other for the RFS. This option makes the default
-configurable at build time.
-
-Signed-off-by: Justin Waters <justin.waters at timesys.com>
----
- board/ge/bx50v3/Kconfig | 4 ++++
- include/configs/ge_bx50v3.h | 36 ++++++++++++++++++++++++------------
- 2 files changed, 28 insertions(+), 12 deletions(-)
-
-diff --git a/board/ge/bx50v3/Kconfig b/board/ge/bx50v3/Kconfig
-index d50dece..320b3b8 100644
---- a/board/ge/bx50v3/Kconfig
-+++ b/board/ge/bx50v3/Kconfig
-@@ -15,4 +15,8 @@ config SYS_SOC
- config SYS_CONFIG_NAME
- default "ge_bx50v3"
-
-+config YOCTO_IMAGE
-+ bool "Use yocto image layout"
-+ default n
-+
- endif
-diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h
-index 6fa4a9a..4b3c25e 100644
---- a/include/configs/ge_bx50v3.h
-+++ b/include/configs/ge_bx50v3.h
-@@ -17,21 +17,31 @@
-
- #if defined(CONFIG_TARGET_GE_B450V3)
- #define CONFIG_BOARD_NAME "General Electric B450v3"
--#define CONFIG_DEFAULT_FDT_FILE "/boot/imx6q-b450v3.dtb"
-+#define CONFIG_DEFAULT_FDT_FILE "imx6q-b450v3.dtb"
- #elif defined(CONFIG_TARGET_GE_B650V3)
- #define CONFIG_BOARD_NAME "General Electric B650v3"
--#define CONFIG_DEFAULT_FDT_FILE "/boot/imx6q-b650v3.dtb"
-+#define CONFIG_DEFAULT_FDT_FILE "imx6q-b650v3.dtb"
- #elif defined(CONFIG_TARGET_GE_B850V3)
- #define CONFIG_BOARD_NAME "General Electric B850v3"
--#define CONFIG_DEFAULT_FDT_FILE "/boot/imx6q-b850v3.dtb"
-+#define CONFIG_DEFAULT_FDT_FILE "mx6q-b850v3.dtb"
- #else
- #define CONFIG_BOARD_NAME "General Electric BA16 Generic"
--#define CONFIG_DEFAULT_FDT_FILE "/boot/imx6q-ba16.dtb"
-+#define CONFIG_DEFAULT_FDT_FILE "imx6q-ba16.dtb"
- #endif
-
- #define CONFIG_MXC_UART_BASE UART3_BASE
- #define CONFIG_CONSOLE_DEV "ttymxc2"
-
-+#ifdef CONFIG_YOCTO_IMAGE
-+#define CONFIG_BOOT_DIR ""
-+#define CONFIG_LOADCMD "fatload"
-+#define CONFIG_RFSPART "2"
-+#else
-+#define CONFIG_BOOT_DIR "/boot"
-+#define CONFIG_LOADCMD "ext2load"
-+#define CONFIG_RFSPART "1"
-+#endif
-+
- #define PHYS_SDRAM_SIZE (2u * 1024 * 1024 * 1024)
-
- #define CONFIG_SUPPORT_EMMC_BOOT
-@@ -144,9 +154,9 @@
-
- #define CONFIG_EXTRA_ENV_SETTINGS \
- "script=boot.scr\0" \
-- "image=/boot/uImage\0" \
-+ "image=" CONFIG_BOOT_DIR "/uImage\0" \
- "uboot=u-boot.imx\0" \
-- "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
-+ "fdt_file=" CONFIG_BOOT_DIR "/" CONFIG_DEFAULT_FDT_FILE "\0" \
- "fdt_addr=0x18000000\0" \
- "boot_fdt=yes\0" \
- "ip_dyn=yes\0" \
-@@ -156,6 +166,8 @@
- "sddev=0\0" \
- "emmcdev=1\0" \
- "partnum=1\0" \
-+ "loadcmd=" CONFIG_LOADCMD "\0" \
-+ "rfspart=" CONFIG_RFSPART "\0" \
- "update_sd_firmware=" \
- "if test ${ip_dyn} = yes; then " \
- "setenv get_cmd dhcp; " \
-@@ -179,12 +191,12 @@
- "setargs=setenv bootargs console=${console},${baudrate} " \
- "root=/dev/${rootdev} rw rootwait cma=128M\0" \
- "loadbootscript=" \
-- "ext2load ${dev} ${devnum}:${partnum} ${loadaddr} ${script};\0" \
-+ "${loadcmd} ${dev} ${devnum}:${partnum} ${loadaddr} ${script};\0" \
- "bootscript=echo Running bootscript from ${dev}:${devnum}:${partnum};" \
- " source\0" \
- "loadimage=" \
-- "ext2load ${dev} ${devnum}:${partnum} ${loadaddr} ${image}\0" \
-- "loadfdt=ext2load ${dev} ${devnum}:${partnum} ${fdt_addr} ${fdt_file}\0" \
-+ "${loadcmd} ${dev} ${devnum}:${partnum} ${loadaddr} ${image}\0" \
-+ "loadfdt=${loadcmd} ${dev} ${devnum}:${partnum} ${fdt_addr} ${fdt_file}\0" \
- "tryboot=" \
- "if run loadbootscript; then " \
- "run bootscript; " \
-@@ -237,16 +249,16 @@
- "usb start; " \
- "setenv dev usb; " \
- "setenv devnum 0; " \
-- "setenv rootdev sda1; " \
-+ "setenv rootdev sda${rfspart}; " \
- "run tryboot; " \
- \
- "setenv dev mmc; " \
-- "setenv rootdev mmcblk0p1; " \
-+ "setenv rootdev mmcblk0p${rfspart}; " \
- \
- "setenv devnum ${sddev}; " \
- "if mmc dev ${devnum}; then " \
- "run tryboot; " \
-- "setenv rootdev mmcblk1p1; " \
-+ "setenv rootdev mmcblk1p${rfspart}; " \
- "fi; " \
- \
- "setenv devnum ${emmcdev}; " \
---
-2.5.0
-
diff --git a/recipes-bsp/u-boot/u-boot-ge-2015.10/0004-board-ge-bx50v3-Add-support-for-ELO-board.patch b/recipes-bsp/u-boot/u-boot-ge-2015.10/0004-board-ge-bx50v3-Add-support-for-ELO-board.patch
deleted file mode 100644
index cabe809..0000000
--- a/recipes-bsp/u-boot/u-boot-ge-2015.10/0004-board-ge-bx50v3-Add-support-for-ELO-board.patch
+++ /dev/null
@@ -1,222 +0,0 @@
-From 51606911d456bbcbdb85337a87dd35ce059bed4f Mon Sep 17 00:00:00 2001
-From: Justin Waters <justin.waters at timesys.com>
-Date: Wed, 9 Mar 2016 13:19:14 -0500
-Subject: [PATCH 4/7] board: ge: bx50v3: Add support for ELO board
-
-The ELO board uses the same Q7 module as the bx50v3 boards, but with
-a different baseboard. However, there are only two main differences
-that affect U-boot:
-
-1) Dual channel LVDS display
-2) Serial console
-
-Signed-off-by: Justin Waters <justin.waters at timesys.com>
----
- arch/arm/cpu/armv7/mx6/Kconfig | 4 +++
- board/ge/bx50v3/Kconfig | 2 +-
- board/ge/bx50v3/bx50v3.c | 76 ++++++++++++++++++++++++++++++++++++++++++
- configs/ge_elo_defconfig | 8 +++++
- configs/ge_elo_yocto_defconfig | 9 +++++
- include/configs/ge_bx50v3.h | 8 +++++
- 6 files changed, 106 insertions(+), 1 deletion(-)
- create mode 100644 configs/ge_elo_defconfig
- create mode 100644 configs/ge_elo_yocto_defconfig
-
-diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
-index 722e0d0..b93c661 100644
---- a/arch/arm/cpu/armv7/mx6/Kconfig
-+++ b/arch/arm/cpu/armv7/mx6/Kconfig
-@@ -60,6 +60,10 @@ config TARGET_CM_FX6
- config TARGET_EMBESTMX6BOARDS
- bool "embestmx6boards"
-
-+config TARGET_GE_ELO
-+ bool "General Electric ELO"
-+ select MX6Q
-+
- config TARGET_GE_B450V3
- bool "General Electric B450v3"
- select MX6Q
-diff --git a/board/ge/bx50v3/Kconfig b/board/ge/bx50v3/Kconfig
-index 320b3b8..c88058b 100644
---- a/board/ge/bx50v3/Kconfig
-+++ b/board/ge/bx50v3/Kconfig
-@@ -1,4 +1,4 @@
--if TARGET_GE_B450V3 || TARGET_GE_B650V3 || TARGET_GE_B850V3
-+if TARGET_GE_ELO || TARGET_GE_B450V3 || TARGET_GE_B650V3 || TARGET_GE_B850V3
-
- config IMX_CONFIG
- default "board/ge/bx50v3/bx50v3.cfg"
-diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c
-index cf2cd1a..8d3e47a 100644
---- a/board/ge/bx50v3/bx50v3.c
-+++ b/board/ge/bx50v3/bx50v3.c
-@@ -324,6 +324,8 @@ static iomux_v3_cfg_t const backlight_pads[] = {
- /* Backlight enable for LVDS display */
- MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
- #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 0)
-+ /* Set PWM to GPIO so backlight is full strength */
-+ MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
- };
-
- static void do_enable_hdmi(struct display_info_t const *dev)
-@@ -344,6 +346,9 @@ static int detect_baseboard(struct display_info_t const *dev)
- IS_ENABLED(CONFIG_TARGET_GE_B650V3))
- return 1;
-
-+ if (IS_ENABLED(CONFIG_TARGET_GE_ELO))
-+ return (0 == dev->addr);
-+
- return 0;
- }
-
-@@ -369,6 +374,26 @@ struct display_info_t const displays[] = {{
- .vmode = FB_VMODE_NONINTERLACED
- } }, {
- .bus = -1,
-+ .addr = 0,
-+ .pixfmt = IPU_PIX_FMT_RGB24,
-+ .detect = detect_baseboard,
-+ .enable = NULL,
-+ .mode = {
-+ .name = "SHARP-LQ156M1LG21",
-+ .refresh = 60,
-+ .xres = 1920,
-+ .yres = 1080,
-+ .pixclock = 7851,
-+ .left_margin = 100,
-+ .right_margin = 40,
-+ .upper_margin = 30,
-+ .lower_margin = 3,
-+ .hsync_len = 10,
-+ .vsync_len = 2,
-+ .sync = FB_SYNC_EXT,
-+ .vmode = FB_VMODE_NONINTERLACED
-+} }, {
-+ .bus = -1,
- .addr = 3,
- .pixfmt = IPU_PIX_FMT_RGB24,
- .detect = detect_hdmi,
-@@ -559,6 +584,55 @@ static void setup_display_b850v3(void)
- IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
- }
-
-+static void setup_display_elo(void)
-+{
-+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
-+
-+ set_ldb_clock_source(1);
-+
-+ clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
-+
-+ imx_setup_hdmi();
-+
-+ /* Set LDB_DI0 as clock source for IPU_DI0 */
-+ clrsetbits_le32(&mxc_ccm->chsccdr,
-+ MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
-+ (CHSCCDR_CLK_SEL_LDB_DI0 <<
-+ MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
-+
-+ /* Turn on IPU LDB DI0 clocks */
-+ setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
-+
-+ enable_ipu_clock();
-+
-+ writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
-+ IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH |
-+ IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
-+ IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
-+ IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
-+ IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
-+ IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
-+ IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
-+ IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
-+ IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0,
-+ &iomux->gpr[2]);
-+
-+ clrsetbits_le32(&iomux->gpr[3],
-+ IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
-+ IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
-+ IOMUXC_GPR3_HDMI_MUX_CTL_MASK,
-+ (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
-+ IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET));
-+
-+ /* backlights off until needed */
-+ imx_iomux_v3_setup_multiple_pads(backlight_pads,
-+ ARRAY_SIZE(backlight_pads));
-+
-+ gpio_direction_input(LVDS_POWER_GP);
-+ gpio_direction_input(LVDS_BACKLIGHT_GP);
-+}
-+
- static void setup_display_bx50v3(void)
- {
- struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-@@ -642,6 +716,8 @@ int board_init(void)
- #if defined(CONFIG_VIDEO_IPUV3)
- if (IS_ENABLED(CONFIG_TARGET_GE_B850V3))
- setup_display_b850v3();
-+ else if (IS_ENABLED(CONFIG_TARGET_GE_ELO))
-+ setup_display_elo();
- else
- setup_display_bx50v3();
- #endif
-diff --git a/configs/ge_elo_defconfig b/configs/ge_elo_defconfig
-new file mode 100644
-index 0000000..51835ce
---- /dev/null
-+++ b/configs/ge_elo_defconfig
-@@ -0,0 +1,8 @@
-+CONFIG_ARM=y
-+CONFIG_ARCH_MX6=y
-+CONFIG_TARGET_GE_ELO=y
-+# CONFIG_CMD_IMLS is not set
-+# CONFIG_CMD_FLASH is not set
-+CONFIG_CMD_GPIO=y
-+CONFIG_SPI_FLASH=y
-+CONFIG_SPI_FLASH_STMICRO=y
-diff --git a/configs/ge_elo_yocto_defconfig b/configs/ge_elo_yocto_defconfig
-new file mode 100644
-index 0000000..1cd475c
---- /dev/null
-+++ b/configs/ge_elo_yocto_defconfig
-@@ -0,0 +1,9 @@
-+CONFIG_ARM=y
-+CONFIG_ARCH_MX6=y
-+CONFIG_TARGET_GE_ELO=y
-+# CONFIG_CMD_IMLS is not set
-+# CONFIG_CMD_FLASH is not set
-+CONFIG_CMD_GPIO=y
-+CONFIG_SPI_FLASH=y
-+CONFIG_SPI_FLASH_STMICRO=y
-+CONFIG_YOCTO_IMAGE=y
-diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h
-index 4b3c25e..8be4350 100644
---- a/include/configs/ge_bx50v3.h
-+++ b/include/configs/ge_bx50v3.h
-@@ -24,13 +24,21 @@
- #elif defined(CONFIG_TARGET_GE_B850V3)
- #define CONFIG_BOARD_NAME "General Electric B850v3"
- #define CONFIG_DEFAULT_FDT_FILE "mx6q-b850v3.dtb"
-+#elif defined(CONFIG_TARGET_GE_ELO)
-+#define CONFIG_BOARD_NAME "General Electric ELO"
-+#define CONFIG_DEFAULT_FDT_FILE "imx6q-elo.dtb"
- #else
- #define CONFIG_BOARD_NAME "General Electric BA16 Generic"
- #define CONFIG_DEFAULT_FDT_FILE "imx6q-ba16.dtb"
- #endif
-
-+#if defined(CONFIG_TARGET_GE_ELO)
-+#define CONFIG_MXC_UART_BASE UART4_BASE
-+#define CONFIG_CONSOLE_DEV "ttymxc3"
-+#else
- #define CONFIG_MXC_UART_BASE UART3_BASE
- #define CONFIG_CONSOLE_DEV "ttymxc2"
-+#endif
-
- #ifdef CONFIG_YOCTO_IMAGE
- #define CONFIG_BOOT_DIR ""
---
-2.5.0
-
diff --git a/recipes-bsp/u-boot/u-boot-ge-2015.10/0005-board-ge-bx50v3-Fix-bootargs-for-ELO-board.patch b/recipes-bsp/u-boot/u-boot-ge-2015.10/0005-board-ge-bx50v3-Fix-bootargs-for-ELO-board.patch
deleted file mode 100644
index bf6d5c0..0000000
--- a/recipes-bsp/u-boot/u-boot-ge-2015.10/0005-board-ge-bx50v3-Fix-bootargs-for-ELO-board.patch
+++ /dev/null
@@ -1,37 +0,0 @@
-From 17d0da9815466516a8daae8e6d5c6d797caa75fc Mon Sep 17 00:00:00 2001
-From: Justin Waters <justin.waters at timesys.com>
-Date: Thu, 10 Mar 2016 15:26:30 -0500
-Subject: [PATCH 5/7] board: ge: bx50v3: Fix bootargs for ELO board
-
----
- include/configs/ge_bx50v3.h | 4 +++-
- 1 file changed, 3 insertions(+), 1 deletion(-)
-
-diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h
-index 8be4350..5219746 100644
---- a/include/configs/ge_bx50v3.h
-+++ b/include/configs/ge_bx50v3.h
-@@ -35,9 +35,11 @@
- #if defined(CONFIG_TARGET_GE_ELO)
- #define CONFIG_MXC_UART_BASE UART4_BASE
- #define CONFIG_CONSOLE_DEV "ttymxc3"
-+#define CONFIG_EXTRA_BOOTARGS "panic=10"
- #else
- #define CONFIG_MXC_UART_BASE UART3_BASE
- #define CONFIG_CONSOLE_DEV "ttymxc2"
-+#define CONFIG_EXTRA_BOOTARGS "cma=128M"
- #endif
-
- #ifdef CONFIG_YOCTO_IMAGE
-@@ -197,7 +199,7 @@
- "echo 'U-Boot upgraded. Please reset'; " \
- "fi\0" \
- "setargs=setenv bootargs console=${console},${baudrate} " \
-- "root=/dev/${rootdev} rw rootwait cma=128M\0" \
-+ "root=/dev/${rootdev} rw rootwait " CONFIG_EXTRA_BOOTARGS "\0" \
- "loadbootscript=" \
- "${loadcmd} ${dev} ${devnum}:${partnum} ${loadaddr} ${script};\0" \
- "bootscript=echo Running bootscript from ${dev}:${devnum}:${partnum};" \
---
-2.5.0
-
diff --git a/recipes-bsp/u-boot/u-boot-ge-2015.10/0006-mx6q_ba16-Add-1G-DDR-support.patch b/recipes-bsp/u-boot/u-boot-ge-2015.10/0006-mx6q_ba16-Add-1G-DDR-support.patch
deleted file mode 100644
index 55853e1..0000000
--- a/recipes-bsp/u-boot/u-boot-ge-2015.10/0006-mx6q_ba16-Add-1G-DDR-support.patch
+++ /dev/null
@@ -1,343 +0,0 @@
-From 4fe4dc9cab80b3d61df30cb883081a3189b6660a Mon Sep 17 00:00:00 2001
-From: Ken Lin <ken.lin at advantech.com.tw>
-Date: Thu, 31 Mar 2016 12:45:11 +0800
-Subject: [PATCH 6/7] mx6q_ba16: Add 1G DDR support
-
----
- board/ge/bx50v3/Kconfig | 15 ++-
- board/ge/bx50v3/ddr_1g.cfg | 262 ++++++++++++++++++++++++++++++++++++++
- configs/ge_elo_yocto_1g_defconfig | 10 ++
- include/configs/ge_bx50v3.h | 4 +
- 4 files changed, 290 insertions(+), 1 deletion(-)
- create mode 100644 board/ge/bx50v3/ddr_1g.cfg
- create mode 100644 configs/ge_elo_yocto_1g_defconfig
-
-diff --git a/board/ge/bx50v3/Kconfig b/board/ge/bx50v3/Kconfig
-index c88058b..05cc07a 100644
---- a/board/ge/bx50v3/Kconfig
-+++ b/board/ge/bx50v3/Kconfig
-@@ -1,7 +1,20 @@
- if TARGET_GE_ELO || TARGET_GE_B450V3 || TARGET_GE_B650V3 || TARGET_GE_B850V3
-
-+choice
-+ prompt "DDR Size"
-+ default SYS_DDR_2G
-+
-+config SYS_DDR_1G
-+ bool "1GiB"
-+
-+config SYS_DDR_2G
-+ bool "2GiB"
-+
-+endchoice
-+
- config IMX_CONFIG
-- default "board/ge/bx50v3/bx50v3.cfg"
-+ default "board/ge/bx50v3/bx50v3.cfg" if SYS_DDR_2G
-+ default "board/ge/bx50v3/ddr_1g.cfg" if SYS_DDR_1G
-
- config SYS_BOARD
- default "bx50v3"
-diff --git a/board/ge/bx50v3/ddr_1g.cfg b/board/ge/bx50v3/ddr_1g.cfg
-new file mode 100644
-index 0000000..967082d
---- /dev/null
-+++ b/board/ge/bx50v3/ddr_1g.cfg
-@@ -0,0 +1,262 @@
-+/*
-+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
-+ * Jason Liu <r64343 at freescale.com>
-+ *
-+ * SPDX-License-Identifier: GPL-2.0+
-+ *
-+ * Refer doc/README.imximage for more details about how-to configure
-+ * and create imximage boot image
-+ *
-+ * The syntax is taken as close as possible with the kwbimage
-+ */
-+
-+
-+IMAGE_VERSION 2
-+BOOT_FROM sd
-+
-+//*================================================================================================
-+// Disable WDOG
-+//*================================================================================================
-+//setmem /16 0x020bc000 = 0x30
-+
-+
-+//*================================================================================================
-+// Enable all clocks (they are disabled by ROM code)
-+//*================================================================================================
-+DATA 4 0x020c4068 0xffffffff
-+DATA 4 0x020c406c 0xffffffff
-+DATA 4 0x020c4070 0xffffffff
-+DATA 4 0x020c4074 0xffffffff
-+DATA 4 0x020c4078 0xffffffff
-+DATA 4 0x020c407c 0xffffffff
-+DATA 4 0x020c4080 0xffffffff
-+DATA 4 0x020c4084 0xffffffff
-+
-+
-+//*
-+// Initialize 64-bit DDR3
-+//*
-+
-+//######################################################
-+// IOMUX
-+//######################################################
-+
-+//DDR IO TYPE:
-+DATA 4 0x020e0798 0x000c0000 // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE - DDR_SEL11
-+DATA 4 0x020e0758 0x00000000 // IOMUXC_SW_PAD_CTL_GRP_DDRPKE - PKE0 , Pull disabled for all, except DQS.
-+
-+//CLOCK:
-+DATA 4 0x020e0588 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 - DSE101, DDR_INPUT0, HYS0
-+DATA 4 0x020e0594 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 - DSE101, DDR_INPUT0, HYS0
-+
-+//ADDRESS:
-+DATA 4 0x020e056c 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS - DSE110, DDR_INPUT1, HYS0
-+DATA 4 0x020e0578 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS - DSE110, DDR_INPUT1, HYS0
-+DATA 4 0x020e074c 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_ADDDS - DSE110
-+
-+//CONTROL:
-+DATA 4 0x020e057c 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET - DSE110, DDR_INPUT1, HYS0, DDR_SEL00
-+
-+DATA 4 0x020e058c 0x00000000 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2
-+DATA 4 0x020e059c 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0
-+DATA 4 0x020e05a0 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1
-+DATA 4 0x020e078c 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_CTLDS - DSE110
-+
-+
-+//DATA STROBE:
-+DATA 4 0x020e0750 0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL - DDR_INPUT1
-+
-+DATA 4 0x020e05a8 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 - DSE110
-+DATA 4 0x020e05b0 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 - DSE110
-+DATA 4 0x020e0524 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 - DSE110
-+DATA 4 0x020e051c 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 - DSE110
-+DATA 4 0x020e0518 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4 - DSE110
-+DATA 4 0x020e050c 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5 - DSE110
-+DATA 4 0x020e05b8 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6 - DSE110
-+DATA 4 0x020e05c0 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7 - DSE110
-+
-+//DATA:
-+DATA 4 0x020e0774 0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE- DDR_INPUT 1,diff
-+
-+DATA 4 0x020e0784 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B0DS - DSE110
-+DATA 4 0x020e0788 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B1DS - DSE110
-+DATA 4 0x020e0794 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B2DS - DSE110
-+DATA 4 0x020e079c 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B3DS - DSE110
-+DATA 4 0x020e07a0 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B4DS - DSE110
-+DATA 4 0x020e07a4 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B5DS - DSE110
-+DATA 4 0x020e07a8 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B6DS - DSE110
-+DATA 4 0x020e0748 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B7DS - DSE110
-+
-+DATA 4 0x020e05ac 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 - DSE110, DDR_INPUT1, HYS0
-+DATA 4 0x020e05b4 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 - DSE110, DDR_INPUT1, HYS0
-+DATA 4 0x020e0528 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 - DSE110, DDR_INPUT1, HYS0
-+DATA 4 0x020e0520 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 - DSE110, DDR_INPUT1, HYS0
-+DATA 4 0x020e0514 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 - DSE110, DDR_INPUT1, HYS0
-+DATA 4 0x020e0510 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 - DSE110, DDR_INPUT1, HYS0
-+DATA 4 0x020e05bc 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 - DSE110, DDR_INPUT1, HYS0
-+DATA 4 0x020e05c4 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 - DSE110, DDR_INPUT1, HYS0
-+
-+
-+
-+//######################################################
-+//Calibrations:
-+//######################################################
-+// ZQ:
-+DATA 4 0x021b0800 0xa1390003 // DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic HW ZQ calibration.
-+
-+// write leveling
-+DATA 4 0x021b080c 0x001F001F
-+DATA 4 0x021b0810 0x001F001F
-+
-+DATA 4 0x021b480c 0x001F001F
-+DATA 4 0x021b4810 0x001F001F
-+
-+//DQS gating, read delay, write delay calibration values based on calibration compare of 0x00ffff00:
-+// It is highly recommended for the user to run calibration code on her/his specific board
-+//and replace following delay values accordingly:
-+
-+
-+
-+//Read DQS Gating calibration
-+DATA 4 0x021b083c 0x43480350
-+DATA 4 0x021b0840 0x033C0340
-+DATA 4 0x021b483c 0x43480350
-+DATA 4 0x021b4840 0x03340314
-+
-+//Read calibration
-+DATA 4 0x021b0848 0x382E2C32
-+DATA 4 0x021b4848 0x38363044
-+
-+//Write calibration
-+DATA 4 0x021b0850 0x3A38403A
-+DATA 4 0x021b4850 0x4432483E
-+
-+
-+
-+//read data bit delay: (3 is the reccommended default value, although out of reset value is 0):
-+DATA 4 0x021b081c 0x33333333 // DDR_PHY_P0_MPREDQBY0DL3
-+DATA 4 0x021b0820 0x33333333 // DDR_PHY_P0_MPREDQBY1DL3
-+DATA 4 0x021b0824 0x33333333 // DDR_PHY_P0_MPREDQBY2DL3
-+DATA 4 0x021b0828 0x33333333 // DDR_PHY_P0_MPREDQBY3DL3
-+DATA 4 0x021b481c 0x33333333 // DDR_PHY_P1_MPREDQBY0DL3
-+DATA 4 0x021b4820 0x33333333 // DDR_PHY_P1_MPREDQBY1DL3
-+DATA 4 0x021b4824 0x33333333 // DDR_PHY_P1_MPREDQBY2DL3
-+DATA 4 0x021b4828 0x33333333 // DDR_PHY_P1_MPREDQBY3DL3
-+
-+
-+//DATA 4 0x021b082c 0xf3333333 // wr bit delay, byte 0
-+//DATA 4 0x021b0830 0xf3333333 // wr bit delay, byte 1
-+//DATA 4 0x021b0834 0xf3333333 // wr bit delay, byte 2
-+//DATA 4 0x021b0838 0xf3333333 // wr bit delay, byte 3
-+//DATA 4 0x021b482c 0xf3333333 // wr bit delay, byte 4
-+//DATA 4 0x021b4830 0xf3333333 // wr bit delay, byte 5
-+//DATA 4 0x021b4834 0xf3333333 // wr bit delay, byte 6
-+//DATA 4 0x021b4838 0xf3333333 // wr bit delay, byte 7
-+
-+
-+//For i.mx6qd parts of versions A & B (v1.0, v1.1), uncomment the following lines. For version C (v1.2), keep commented
-+//DATA 4 0x021b08c0 0x24911492 // fine tune SDCLK duty cyc to low - seen to improve measured duty cycle of i.mx6
-+//DATA 4 0x021b48c0 0x24911492
-+
-+//######################################################
-+// Complete calibration by forced measurment:
-+//######################################################
-+DATA 4 0x021b08b8 0x00000800 // DDR_PHY_P0_MPMUR0, frc_msr
-+DATA 4 0x021b48b8 0x00000800 // DDR_PHY_P0_MPMUR0, frc_msr
-+
-+//######################################################
-+//MMDC init:
-+
-+
-+//528MHz
-+//in DDR3, 64-bit mode, only MMDC0 is initiated:
-+DATA 4 0x021b0004 0x00020036 // MMDC0_MDPDC see spread sheet for timings
-+DATA 4 0x021b0008 0x09444040 // MMDC0_MDOTC see spread sheet for timings
-+DATA 4 0x021b000c 0x555A79A5 // MMDC0_MDCFG0 see spread sheet for timings. CL8
-+DATA 4 0x021b0010 0xDB538E64 // MMDC0_MDCFG1 see spread sheet for timings
-+DATA 4 0x021b0014 0x01ff00db // MMDC0_MDCFG2 - tRRD - 4ck; tWTR - 4ck; tRTP - 4ck; tDLLK - 512ck
-+DATA 4 0x021b0018 0x00001740 // MMDC0_MDMISC, RALAT0x5
-+//MDMISC: RALAT kept to the high level of 5.
-+//MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits:
-+//a. better operation at low frequency
-+//b. Small performence improvment
-+
-+DATA 4 0x021b001c 0x00008000 // MMDC0_MDSCR
-+
-+DATA 4 0x021b002c 0x000026d2 // MMDC0_MDRWD
-+DATA 4 0x021b0030 0x005a1023 // MMDC0_MDOR - tXPR - 91ck; SDE_to_RST - 13ck; RST_to_CKE - 32ck //jimmy
-+DATA 4 0x021b0040 0x00000027 // CS0_END - 0x4fffffff
-+
-+
-+
-+
-+DATA 4 0x021b0000 0x831a0000 // MMDC0_MDCTL - row - 14bits; col 10bits; burst length 8; 64-bit data bus
-+
-+
-+
-+//######################################################
-+// Initialize 2GB DDR3 - Micron MT41J128M , but fit wide range of other DDR3 devices
-+//MR2:
-+DATA 4 0x021b001c 0x04088032 // MMDC0_MDSCR
-+DATA 4 0x021b001c 0x0408803a // MMDC0_MDSCR
-+
-+
-+//MR3:
-+DATA 4 0x021b001c 0x00008033 // MMDC0_MDSCR
-+DATA 4 0x021b001c 0x0000803b // MMDC0_MDSCR
-+//MR1:
-+DATA 4 0x021b001c 0x00048031 // MMDC0_MDSCR
-+DATA 4 0x021b001c 0x00048039 // MMDC0_MDSCR
-+//MR0:
-+
-+DATA 4 0x021b001c 0x09408030 // MMDC0_MDSCR,
-+DATA 4 0x021b001c 0x09408038 // MMDC0_MDSCR,
-+
-+//DDR device ZQ calibration:
-+DATA 4 0x021b001c 0x04008040 // MMDC0_MDSCR,
-+DATA 4 0x021b001c 0x04008048 // MMDC0_MDSCR
-+//######################################################
-+//final DDR setup, before operation start:
-+
-+DATA 4 0x021b0020 0x00005800 // MMDC0_MDREF, enable auto refresh, set refresh rate.
-+
-+//Following ODT setup (0x11117) represents(along with obove DDR device configs) : i.mx_ODTDDR_device_ODT120OHm.
-+//User might to also interested in trying the value of 0x00000007,which represents: i.mx_ODT disabled, DDR_device_ODT120Ohm.
-+//0x00000007 saves more power, and seen to run very well with Freescale RDKs. Still, running with no ODT has it's implications
-+// of signal integrity and should be carefully simulated during board design.
-+
-+DATA 4 0x021b0818 0x00033337 // DDR_PHY_P0_MPODTCTRL, ODT enable
-+DATA 4 0x021b4818 0x00033337 // DDR_PHY_P1_MPODTCTRL
-+
-+DATA 4 0x021b0004 0x00025576 // MMDC0_MDPDC see spread sheet for timings, SDCTL power down enabled
-+
-+DATA 4 0x021b0404 0x00011006 //MMDC0_MAPSR ADOPT power down enabled
-+
-+DATA 4 0x021b001c 0x00000000 // MMDC0_MDSCR
-+
-+
-+/* set the default clock gate to save power */
-+DATA 4 0x020c4068 0x00C03F3F
-+DATA 4 0x020c406c 0x0030FC03
-+DATA 4 0x020c4070 0x0FFFC000
-+DATA 4 0x020c4074 0x3FF00000
-+DATA 4 0x020c4078 0x00FFF300
-+DATA 4 0x020c407c 0x0F0000C3
-+DATA 4 0x020c4080 0x000003FF
-+
-+/* enable AXI cache for VDOA/VPU/IPU */
-+DATA 4 0x020e0010 0xF00000CF
-+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-+DATA 4 0x020e0018 0x007F007F
-+DATA 4 0x020e001c 0x007F007F
-+
-+/*
-+ * Setup CCM_CCOSR register as follows:
-+ *
-+ * cko1_en 1 --> CKO1 enabled
-+ * cko1_div 111 --> divide by 8
-+ * cko1_sel 1011 --> ahb_clk_root
-+ *
-+ * This sets CKO1 at ahb_clk_root/8 132/8 16.5 MHz
-+ */
-+DATA 4 0x020c4060 0x000000fb
-diff --git a/configs/ge_elo_yocto_1g_defconfig b/configs/ge_elo_yocto_1g_defconfig
-new file mode 100644
-index 0000000..978b336
---- /dev/null
-+++ b/configs/ge_elo_yocto_1g_defconfig
-@@ -0,0 +1,10 @@
-+CONFIG_ARM=y
-+CONFIG_ARCH_MX6=y
-+CONFIG_TARGET_GE_ELO=y
-+CONFIG_SYS_DDR_1G=y
-+# CONFIG_CMD_IMLS is not set
-+# CONFIG_CMD_FLASH is not set
-+CONFIG_CMD_GPIO=y
-+CONFIG_SPI_FLASH=y
-+CONFIG_SPI_FLASH_STMICRO=y
-+CONFIG_YOCTO_IMAGE=y
-diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h
-index 5219746..4aaccaa 100644
---- a/include/configs/ge_bx50v3.h
-+++ b/include/configs/ge_bx50v3.h
-@@ -52,7 +52,11 @@
- #define CONFIG_RFSPART "1"
- #endif
-
-+#ifdef CONFIG_SYS_DDR_1G
-+#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
-+#else
- #define PHYS_SDRAM_SIZE (2u * 1024 * 1024 * 1024)
-+#endif
-
- #define CONFIG_SUPPORT_EMMC_BOOT
-
---
-2.5.0
-
diff --git a/recipes-bsp/u-boot/u-boot-ge-2015.10/0007-board-ge-bx50v3-Add-correct-SATA-settings.patch b/recipes-bsp/u-boot/u-boot-ge-2015.10/0007-board-ge-bx50v3-Add-correct-SATA-settings.patch
deleted file mode 100644
index 5d2b01d..0000000
--- a/recipes-bsp/u-boot/u-boot-ge-2015.10/0007-board-ge-bx50v3-Add-correct-SATA-settings.patch
+++ /dev/null
@@ -1,59 +0,0 @@
-From 660d9fe934bd3dcb0dde077d6f51adf8fc4fc779 Mon Sep 17 00:00:00 2001
-From: Justin Waters <justin.waters at timesys.com>
-Date: Tue, 19 Apr 2016 14:36:16 -0400
-Subject: [PATCH 7/7] board: ge: bx50v3: Add correct SATA settings
-
-Signed-off-by: Justin Waters <justin.waters at timesys.com>
----
- board/ge/bx50v3/bx50v3.c | 28 ++++++++++++++++++++++++++++
- 1 file changed, 28 insertions(+)
-
-diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c
-index 8d3e47a..18cac38 100644
---- a/board/ge/bx50v3/bx50v3.c
-+++ b/board/ge/bx50v3/bx50v3.c
-@@ -698,6 +698,30 @@ static iomux_v3_cfg_t const misc_pads[] = {
- #define SUS_S3_OUT IMX_GPIO_NR(4, 11)
- #define WIFI_EN IMX_GPIO_NR(6, 14)
-
-+int setup_ba16_sata(void)
-+{
-+ struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
-+ int ret;
-+
-+ ret = enable_sata_clock();
-+ if (ret)
-+ return ret;
-+
-+ clrsetbits_le32(&iomuxc_regs->gpr[13],
-+ IOMUXC_GPR13_SATA_MASK,
-+ IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
-+ |IOMUXC_GPR13_SATA_PHY_7_SATA2M
-+ |IOMUXC_GPR13_SATA_SPEED_3G
-+ |(1<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
-+ |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
-+ |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_12_16
-+ |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P33_DB
-+ |IOMUXC_GPR13_SATA_PHY_2_TX_1P133V
-+ |IOMUXC_GPR13_SATA_PHY_1_SLOW);
-+
-+ return 0;
-+}
-+
- int board_early_init_f(void)
- {
- imx_iomux_v3_setup_multiple_pads(misc_pads,
-@@ -755,6 +779,10 @@ int board_late_init(void)
- /* Backlight Power */
- gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
-
-+#ifdef CONFIG_CMD_SATA
-+ setup_ba16_sata();
-+#endif
-+
- return 0;
- }
-
---
-2.5.0
-
diff --git a/recipes-bsp/u-boot/u-boot-ge_2015.10.bb b/recipes-bsp/u-boot/u-boot-ge_2015.10.bb
deleted file mode 100644
index 901744b..0000000
--- a/recipes-bsp/u-boot/u-boot-ge_2015.10.bb
+++ /dev/null
@@ -1,22 +0,0 @@
-require recipes-bsp/u-boot/u-boot.inc
-
-DESCRIPTION = "U-Boot for GE i.MX6 BA16 based platforms"
-LICENSE = "GPLv2+"
-LIC_FILES_CHKSUM = "file://Licenses/README;md5=0507cd7da8e7ad6d6701926ec9b84c95"
-DEPENDS = "u-boot-mkimage-native"
-
-PROVIDES = "u-boot"
-
-SRCREV = "1b6aee73e60023ae4ba16b11ce7bc23e0e8552f7"
-SRC_URI = "git://github.com/Freescale/u-boot-fslc.git;branch=2015.10+fslc \
- file://0001-arm-imx-Add-support-for-GE-Bx50v3-boards.patch \
- file://0002-board-ge-bx50v3-Update-display-setup.patch \
- file://0003-ge_bx50v3-Add-support-for-FSL-Community-Yocto-images.patch \
- file://0004-board-ge-bx50v3-Add-support-for-ELO-board.patch \
- file://0005-board-ge-bx50v3-Fix-bootargs-for-ELO-board.patch \
- file://0006-mx6q_ba16-Add-1G-DDR-support.patch \
- file://0007-board-ge-bx50v3-Add-correct-SATA-settings.patch \
-"
-
-PACKAGE_ARCH = "${MACHINE_ARCH}"
-COMPATIBLE_MACHINE = "(imx6q-elo)"
diff --git a/recipes-kernel/linux/linux-ge-3.14/0001-rtc-rx8010-Add-driver-to-kernel.patch b/recipes-kernel/linux/linux-ge-3.14/0001-rtc-rx8010-Add-driver-to-kernel.patch
deleted file mode 100644
index e88b71b..0000000
--- a/recipes-kernel/linux/linux-ge-3.14/0001-rtc-rx8010-Add-driver-to-kernel.patch
+++ /dev/null
@@ -1,1020 +0,0 @@
-From fc70b949055cfcf19914e9ab1a6ab21d9e7e9634 Mon Sep 17 00:00:00 2001
-From: Justin Waters <justin.waters at timesys.com>
-Date: Mon, 22 Dec 2014 11:35:24 -0500
-Subject: [PATCH 01/10] rtc-rx8010: Add driver to kernel
-
-This is the rx810_k3.8-v1.3 version from the Epson support site:
-
-http://www5.epsondevice.com/en/quartz/tech/linux_for_rtc/software/rx8010_k3.8-v1.3.zip
----
- drivers/rtc/Kconfig | 8 +
- drivers/rtc/Makefile | 1 +
- drivers/rtc/rtc-rx8010.c | 965 +++++++++++++++++++++++++++++++++++++++++++++++
- 3 files changed, 974 insertions(+)
- create mode 100644 drivers/rtc/rtc-rx8010.c
-
-diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
-index db933de..87ed3a3 100644
---- a/drivers/rtc/Kconfig
-+++ b/drivers/rtc/Kconfig
-@@ -494,6 +494,14 @@ config RTC_DRV_FM3130
- This driver can also be built as a module. If so the module
- will be called rtc-fm3130.
-
-+config RTC_DRV_RX8010
-+ tristate "Epson RX-8010SJ"
-+ help
-+ If you say yes here you will get support for the Epson RX-8010SJ.
-+
-+ This driver can also be built as a module. If so the module
-+ will be called rtc-rx8010.
-+
- config RTC_DRV_RX8581
- tristate "Epson RX-8581"
- help
-diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
-index b427bf7..1512f48 100644
---- a/drivers/rtc/Makefile
-+++ b/drivers/rtc/Makefile
-@@ -106,6 +106,7 @@ obj-$(CONFIG_RTC_DRV_RS5C348) += rtc-rs5c348.o
- obj-$(CONFIG_RTC_DRV_RS5C372) += rtc-rs5c372.o
- obj-$(CONFIG_RTC_DRV_RV3029C2) += rtc-rv3029c2.o
- obj-$(CONFIG_RTC_DRV_RX4581) += rtc-rx4581.o
-+obj-$(CONFIG_RTC_DRV_RX8010) += rtc-rx8010.o
- obj-$(CONFIG_RTC_DRV_RX8025) += rtc-rx8025.o
- obj-$(CONFIG_RTC_DRV_RX8581) += rtc-rx8581.o
- obj-$(CONFIG_RTC_DRV_S35390A) += rtc-s35390a.o
-diff --git a/drivers/rtc/rtc-rx8010.c b/drivers/rtc/rtc-rx8010.c
-new file mode 100644
-index 0000000..80f7506
---- /dev/null
-+++ b/drivers/rtc/rtc-rx8010.c
-@@ -0,0 +1,965 @@
-+//======================================================================
-+// Driver for the Epson RTC module RX-8010 SJ
-+//
-+// Copyright(C) SEIKO EPSON CORPORATION 2013. All rights reserved.
-+//
-+// Derived from RX-8025 driver:
-+// Copyright (C) 2009 Wolfgang Grandegger <wg at grandegger.com>
-+//
-+// Copyright (C) 2005 by Digi International Inc.
-+// All rights reserved.
-+//
-+// Modified by fengjh at rising.com.cn
-+// <http://lists.lm-sensors.org/mailman/listinfo/lm-sensors>
-+// 2006.11
-+//
-+// Code cleanup by Sergei Poselenov, <sposelenov at emcraft.com>
-+// Converted to new style by Wolfgang Grandegger <wg at grandegger.com>
-+// Alarm and periodic interrupt added by Dmitry Rakhchev <rda at emcraft.com>
-+//
-+//
-+// This driver software is distributed as is, without any warranty of any kind,
-+// either express or implied as further specified in the GNU Public License. This
-+// software may be used and distributed according to the terms of the GNU Public
-+// License, version 2 as published by the Free Software Foundation.
-+// See the file COPYING in the main directory of this archive for more details.
-+//
-+// You should have received a copy of the GNU General Public License along with
-+// this program. If not, see <http://www.gnu.org/licenses/>.
-+//======================================================================
-+
-+#if 0
-+#define DEBUG
-+#include <linux/device.h>
-+#undef DEBUG
-+#endif
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/slab.h>
-+#include <linux/init.h>
-+#include <linux/bcd.h>
-+#include <linux/i2c.h>
-+#include <linux/list.h>
-+#include <linux/rtc.h>
-+#include <linux/of_gpio.h>
-+
-+#include <linux/of.h>
-+#include <linux/of_device.h>
-+#include <linux/of_irq.h>
-+#include <linux/interrupt.h>
-+#include <linux/input.h>
-+
-+
-+// RX-8010 Register definitions
-+#define RX8010_REG_SEC 0x10
-+#define RX8010_REG_MIN 0x11
-+#define RX8010_REG_HOUR 0x12
-+#define RX8010_REG_WDAY 0x13
-+#define RX8010_REG_MDAY 0x14
-+#define RX8010_REG_MONTH 0x15
-+#define RX8010_REG_YEAR 0x16
-+// 0x17 is reserved
-+#define RX8010_REG_ALMIN 0x18
-+#define RX8010_REG_ALHOUR 0x19
-+#define RX8010_REG_ALWDAY 0x1A
-+#define RX8010_REG_TCOUNT0 0x1B
-+#define RX8010_REG_TCOUNT1 0x1C
-+#define RX8010_REG_EXT 0x1D
-+#define RX8010_REG_FLAG 0x1E
-+#define RX8010_REG_CTRL 0x1F
-+#define RX8010_REG_USER0 0x20
-+#define RX8010_REG_USER1 0x21
-+#define RX8010_REG_USER2 0x22
-+#define RX8010_REG_USER3 0x23
-+#define RX8010_REG_USER4 0x24
-+#define RX8010_REG_USER5 0x25
-+#define RX8010_REG_USER6 0x26
-+#define RX8010_REG_USER7 0x27
-+#define RX8010_REG_USER8 0x28
-+#define RX8010_REG_USER9 0x29
-+#define RX8010_REG_USERA 0x2A
-+#define RX8010_REG_USERB 0x2B
-+#define RX8010_REG_USERC 0x2C
-+#define RX8010_REG_USERD 0x2D
-+#define RX8010_REG_USERE 0x2E
-+#define RX8010_REG_USERF 0x2F
-+// 0x30 is reserved
-+// 0x31 is reserved
-+#define RX8010_REG_IRQ 0x32
-+
-+// Extension Register (1Dh) bit positions
-+#define RX8010_BIT_EXT_TSEL (7 << 0)
-+#define RX8010_BIT_EXT_WADA (1 << 3)
-+#define RX8010_BIT_EXT_TE (1 << 4)
-+#define RX8010_BIT_EXT_USEL (1 << 5)
-+#define RX8010_BIT_EXT_FSEL (3 << 6)
-+
-+// Flag Register (1Eh) bit positions
-+#define RX8010_BIT_FLAG_VLF (1 << 1)
-+#define RX8010_BIT_FLAG_AF (1 << 3)
-+#define RX8010_BIT_FLAG_TF (1 << 4)
-+#define RX8010_BIT_FLAG_UF (1 << 5)
-+
-+// Control Register (1Fh) bit positions
-+#define RX8010_BIT_CTRL_TSTP (1 << 2)
-+#define RX8010_BIT_CTRL_AIE (1 << 3)
-+#define RX8010_BIT_CTRL_TIE (1 << 4)
-+#define RX8010_BIT_CTRL_UIE (1 << 5)
-+#define RX8010_BIT_CTRL_STOP (1 << 6)
-+#define RX8010_BIT_CTRL_TEST (1 << 7)
-+
-+
-+static const struct i2c_device_id rx8010_id[] = {
-+ { "rx8010", 0 },
-+ { }
-+};
-+MODULE_DEVICE_TABLE(i2c, rx8010_id);
-+
-+struct rx8010_data {
-+ struct i2c_client *client;
-+ struct rtc_device *rtc;
-+ struct work_struct work_1;
-+ struct work_struct work_2;
-+ u8 ctrlreg;
-+ int irq_1;
-+ int irq_2;
-+ unsigned exiting:1;
-+};
-+
-+typedef struct {
-+ u8 number;
-+ u8 value;
-+}reg_data;
-+
-+#define SE_RTC_REG_READ _IOWR('p', 0x20, reg_data)
-+#define SE_RTC_REG_WRITE _IOW('p', 0x21, reg_data)
-+
-+//----------------------------------------------------------------------
-+// rx8010_read_reg()
-+// reads a rx8010 register (see Register defines)
-+// See also rx8010_read_regs() to read multiple registers.
-+//
-+//----------------------------------------------------------------------
-+static int rx8010_read_reg(struct i2c_client *client, int number, u8 *value)
-+{
-+ int ret = i2c_smbus_read_byte_data(client, number) ;
-+
-+ //check for error
-+ if (ret < 0) {
-+ dev_err(&client->dev, "Unable to read register #%d\n", number);
-+ return ret;
-+ }
-+
-+ *value = ret;
-+ return 0;
-+}
-+
-+//----------------------------------------------------------------------
-+// rx8010_read_regs()
-+// reads a specified number of rx8010 registers (see Register defines)
-+// See also rx8010_read_reg() to read single register.
-+//
-+//----------------------------------------------------------------------
-+static int rx8010_read_regs(struct i2c_client *client, int number, u8 length, u8 *values)
-+{
-+ int ret = i2c_smbus_read_i2c_block_data(client, number, length, values);
-+
-+ //check for length error
-+ if (ret != length) {
-+ dev_err(&client->dev, "Unable to read registers #%d..#%d\n", number, number + length - 1);
-+ return ret < 0 ? ret : -EIO;
-+ }
-+
-+ return 0;
-+}
-+
-+//----------------------------------------------------------------------
-+// rx8010_write_reg()
-+// writes a rx8010 register (see Register defines)
-+// See also rx8010_write_regs() to write multiple registers.
-+//
-+//----------------------------------------------------------------------
-+static int rx8010_write_reg(struct i2c_client *client, int number, u8 value)
-+{
-+ int ret = i2c_smbus_write_byte_data(client, number, value);
-+
-+ //check for error
-+ if (ret)
-+ dev_err(&client->dev, "Unable to write register #%d\n", number);
-+
-+ return ret;
-+}
-+
-+//----------------------------------------------------------------------
-+// rx8010_write_regs()
-+// writes a specified number of rx8010 registers (see Register defines)
-+// See also rx8010_write_reg() to write a single register.
-+//
-+//----------------------------------------------------------------------
-+static int rx8010_write_regs(struct i2c_client *client, int number, u8 length, u8 *values)
-+{
-+ int ret = i2c_smbus_write_i2c_block_data(client, number, length, values);
-+
-+ //check for error
-+ if (ret)
-+ dev_err(&client->dev, "Unable to write registers #%d..#%d\n", number, number + length - 1);
-+
-+ return ret;
-+}
-+
-+//----------------------------------------------------------------------
-+// rx8010_irq_1()
-+// irq handler
-+//
-+//----------------------------------------------------------------------
-+static irqreturn_t rx8010_irq_1(int irq, void *dev_id)
-+{
-+ struct i2c_client *client = dev_id;
-+ struct rx8010_data *rx8010 = i2c_get_clientdata(client);
-+
-+ disable_irq_nosync(irq);
-+ schedule_work(&rx8010->work_1);
-+
-+
-+ return IRQ_HANDLED;
-+}
-+
-+//----------------------------------------------------------------------
-+// rx8010_work_1()
-+//
-+//----------------------------------------------------------------------
-+static void rx8010_work_1(struct work_struct *work)
-+{
-+ struct rx8010_data *rx8010 = container_of(work, struct rx8010_data, work_1);
-+ struct i2c_client *client = rx8010->client;
-+ struct mutex *lock = &rx8010->rtc->ops_lock;
-+ u8 status;
-+
-+ mutex_lock(lock);
-+
-+ if (rx8010_read_reg(client, RX8010_REG_FLAG, &status))
-+ goto out;
-+
-+ // check VLF
-+ if ((status & RX8010_BIT_FLAG_VLF))
-+ dev_warn(&client->dev, "Frequency stop was detected, probably due to a supply voltage drop\n");
-+
-+ dev_dbg(&client->dev, "%s: RX8010_REG_FLAG: %xh\n", __func__, status);
-+
-+ // periodic "fixed-cycle" timer
-+ if (status & RX8010_BIT_FLAG_TF) {
-+ status &= ~RX8010_BIT_FLAG_TF;
-+ local_irq_disable();
-+ rtc_update_irq(rx8010->rtc, 1, RTC_PF | RTC_IRQF);
-+ local_irq_enable();
-+ }
-+
-+ // alarm function
-+ if (status & RX8010_BIT_FLAG_AF) {
-+ status &= ~RX8010_BIT_FLAG_AF;
-+ local_irq_disable();
-+ rtc_update_irq(rx8010->rtc, 1, RTC_AF | RTC_IRQF);
-+ local_irq_enable();
-+ }
-+
-+ // time update function
-+ if (status & RX8010_BIT_FLAG_UF) {
-+ status &= ~RX8010_BIT_FLAG_UF;
-+ local_irq_disable();
-+ rtc_update_irq(rx8010->rtc, 1, RTC_UF | RTC_IRQF);
-+ local_irq_enable();
-+ }
-+
-+ // acknowledge IRQ (clear flags)
-+ rx8010_write_reg(client, RX8010_REG_FLAG, status);
-+
-+out:
-+ if (!rx8010->exiting)
-+ {
-+ if (rx8010->irq_1 > 0)
-+ enable_irq(rx8010->irq_1);
-+ else
-+ enable_irq(client->irq);
-+ }
-+
-+ mutex_unlock(lock);
-+}
-+
-+//----------------------------------------------------------------------
-+// rx8010_irq_2()
-+// irq handler
-+//
-+//----------------------------------------------------------------------
-+static irqreturn_t rx8010_irq_2(int irq, void *dev_id)
-+{
-+ struct i2c_client *client = dev_id;
-+ struct rx8010_data *rx8010 = i2c_get_clientdata(client);
-+
-+ disable_irq_nosync(irq);
-+ schedule_work(&rx8010->work_2);
-+
-+
-+ return IRQ_HANDLED;
-+}
-+
-+//----------------------------------------------------------------------
-+// rx8010_work_2()
-+//
-+//----------------------------------------------------------------------
-+static void rx8010_work_2(struct work_struct *work)
-+{
-+ struct rx8010_data *rx8010 = container_of(work, struct rx8010_data, work_2);
-+ struct i2c_client *client = rx8010->client;
-+ struct mutex *lock = &rx8010->rtc->ops_lock;
-+ u8 status;
-+
-+ mutex_lock(lock);
-+
-+ if (rx8010_read_reg(client, RX8010_REG_FLAG, &status))
-+ goto out;
-+
-+ // check VLF
-+ if ((status & RX8010_BIT_FLAG_VLF))
-+ dev_warn(&client->dev, "Frequency stop was detected, \
-+ probably due to a supply voltage drop\n");
-+
-+ dev_dbg(&client->dev, "%s: RX8010_REG_FLAG: %xh\n", __func__, status);
-+
-+ // periodic "fixed-cycle" timer
-+ if (status & RX8010_BIT_FLAG_TF) {
-+ status &= ~RX8010_BIT_FLAG_TF;
-+ local_irq_disable();
-+ rtc_update_irq(rx8010->rtc, 1, RTC_PF | RTC_IRQF);
-+ local_irq_enable();
-+ }
-+
-+ // acknowledge IRQ (clear flags)
-+ rx8010_write_reg(client, RX8010_REG_FLAG, status);
-+
-+out:
-+ if (!rx8010->exiting)
-+ {
-+ if (rx8010->irq_2 > 0)
-+ enable_irq(rx8010->irq_2);
-+ else
-+ enable_irq(client->irq);
-+ }
-+
-+ mutex_unlock(lock);
-+}
-+
-+//----------------------------------------------------------------------
-+// rx8010_get_time()
-+// gets the current time from the rx8010 registers
-+//
-+//----------------------------------------------------------------------
-+static int rx8010_get_time(struct device *dev, struct rtc_time *dt)
-+{
-+ struct rx8010_data *rx8010 = dev_get_drvdata(dev);
-+ u8 date[7];
-+ int err;
-+
-+ err = rx8010_read_regs(rx8010->client, RX8010_REG_SEC, 7, date);
-+ if (err)
-+ return err;
-+
-+ dev_dbg(dev, "%s: read 0x%02x 0x%02x "
-+ "0x%02x 0x%02x 0x%02x 0x%02x 0x%02x\n", __func__,
-+ date[0], date[1], date[2], date[3], date[4], date[5], date[6]);
-+
-+ //Note: need to subtract 0x10 for index as register offset starts at 0x10
-+ dt->tm_sec = bcd2bin(date[RX8010_REG_SEC-0x10] & 0x7f);
-+ dt->tm_min = bcd2bin(date[RX8010_REG_MIN-0x10] & 0x7f);
-+ dt->tm_hour = bcd2bin(date[RX8010_REG_HOUR-0x10] & 0x3f); //only 24-hour clock
-+ dt->tm_mday = bcd2bin(date[RX8010_REG_MDAY-0x10] & 0x3f);
-+ dt->tm_mon = bcd2bin(date[RX8010_REG_MONTH-0x10] & 0x1f) - 1;
-+ dt->tm_year = bcd2bin(date[RX8010_REG_YEAR-0x10]);
-+ dt->tm_wday = bcd2bin(date[RX8010_REG_WDAY-0x10] & 0x7f);
-+
-+ if (dt->tm_year < 70)
-+ dt->tm_year += 100;
-+
-+ dev_dbg(dev, "%s: date %ds %dm %dh %dmd %dm %dy\n", __func__,
-+ dt->tm_sec, dt->tm_min, dt->tm_hour,
-+ dt->tm_mday, dt->tm_mon, dt->tm_year);
-+
-+ return rtc_valid_tm(dt);
-+}
-+
-+//----------------------------------------------------------------------
-+// rx8010_set_time()
-+// Sets the current time in the rx8010 registers
-+//
-+// BUG: The HW assumes every year that is a multiple of 4 to be a leap
-+// year. Next time this is wrong is 2100, which will not be a leap year
-+//
-+// Note: If STOP is not set/cleared, the clock will start when the seconds
-+// register is written
-+//
-+//----------------------------------------------------------------------
-+static int rx8010_set_time(struct device *dev, struct rtc_time *dt)
-+{
-+ struct rx8010_data *rx8010 = dev_get_drvdata(dev);
-+ u8 date[7];
-+ u8 ctrl;
-+ int ret;
-+
-+ //set STOP bit before changing clock/calendar
-+ rx8010_read_reg(rx8010->client, RX8010_REG_CTRL, &ctrl);
-+ rx8010->ctrlreg = ctrl | RX8010_BIT_CTRL_STOP;
-+ rx8010_write_reg(rx8010->client, RX8010_REG_CTRL, rx8010->ctrlreg);
-+
-+ //Note: need to subtract 0x10 for index as register offset starts at 0x10
-+ date[RX8010_REG_SEC-0x10] = bin2bcd(dt->tm_sec);
-+ date[RX8010_REG_MIN-0x10] = bin2bcd(dt->tm_min);
-+ date[RX8010_REG_HOUR-0x10] = bin2bcd(dt->tm_hour); //only 24hr time
-+
-+ date[RX8010_REG_MDAY-0x10] = bin2bcd(dt->tm_mday);
-+ date[RX8010_REG_MONTH-0x10] = bin2bcd(dt->tm_mon + 1);
-+ date[RX8010_REG_YEAR-0x10] = bin2bcd(dt->tm_year % 100);
-+ date[RX8010_REG_WDAY-0x10] = bin2bcd(dt->tm_wday);
-+
-+ dev_dbg(dev, "%s: write 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x\n",
-+ __func__, date[0], date[1], date[2], date[3], date[4], date[5], date[6]);
-+
-+ ret = rx8010_write_regs(rx8010->client, RX8010_REG_SEC, 7, date);
-+
-+ //clear STOP bit after changing clock/calendar
-+ rx8010_read_reg(rx8010->client, RX8010_REG_CTRL, &ctrl);
-+ rx8010->ctrlreg = ctrl & ~RX8010_BIT_CTRL_STOP;
-+ rx8010_write_reg(rx8010->client, RX8010_REG_CTRL, rx8010->ctrlreg);
-+
-+ return ret;
-+}
-+
-+//----------------------------------------------------------------------
-+// rx8010_init_client()
-+// initializes the rx8010
-+//
-+//----------------------------------------------------------------------
-+static int rx8010_init_client(struct i2c_client *client, int *need_reset)
-+{
-+ struct rx8010_data *rx8010 = i2c_get_clientdata(client);
-+ u8 ctrl[3];
-+ int need_clear = 0;
-+ int err;
-+
-+ //set reserved register 0x17 with specified value of 0xD8
-+ err = rx8010_write_reg(client, 0x17, 0xD8);
-+ if (err)
-+ goto out;
-+
-+ //set reserved register 0x30 with specified value of 0x00
-+ err = rx8010_write_reg(client, 0x30, 0x00);
-+ if (err)
-+ goto out;
-+
-+ //set reserved register 0x31 with specified value of 0x08
-+ err = rx8010_write_reg(client, 0x31, 0x08);
-+ if (err)
-+ goto out;
-+
-+ //set reserved register 0x32 with default value
-+ err = rx8010_write_reg(client, RX8010_REG_IRQ, 0x00);
-+ if (err)
-+ goto out;
-+
-+
-+ //get current extension, flag, control register values
-+ err = rx8010_read_regs(rx8010->client, RX8010_REG_EXT, 3, ctrl);
-+ if (err)
-+ goto out;
-+
-+ //check for VLF Flag (set at power-on)
-+ if ((ctrl[1] & RX8010_BIT_FLAG_VLF)) {
-+ dev_warn(&client->dev, "Frequency stop was detected, probably due to a supply voltage drop\n");
-+ *need_reset = 1;
-+ }
-+
-+ //check for Alarm Flag
-+ if (ctrl[1] & RX8010_BIT_FLAG_AF) {
-+ dev_warn(&client->dev, "Alarm was detected\n");
-+ need_clear = 1;
-+ }
-+
-+ //check for Periodic Timer Flag
-+ if (ctrl[1] & RX8010_BIT_FLAG_TF) {
-+ dev_warn(&client->dev, "Periodic timer was detected\n");
-+ need_clear = 1;
-+ }
-+
-+ //check for Update Timer Flag
-+ if (ctrl[1] & RX8010_BIT_FLAG_UF) {
-+ dev_warn(&client->dev, "Update timer was detected\n");
-+ need_clear = 1;
-+ }
-+
-+ //reset or clear needed?
-+ if (*need_reset) {
-+ //clear 1d, 1e, 1f registers
-+ ctrl[0] = ctrl[1] = ctrl[2] = 0;
-+ err = rx8010_write_regs(client, RX8010_REG_EXT, 3, ctrl);
-+ if (err)
-+ goto out;
-+ }
-+ else if(need_clear){
-+ //clear flag register
-+ err = rx8010_write_reg(client, RX8010_REG_FLAG, 0x00);
-+ if (err)
-+ goto out;
-+ }
-+
-+ //set "test bit" and reserved bits of control register zero
-+ rx8010->ctrlreg = (ctrl[2] & ~RX8010_BIT_CTRL_TEST);
-+out:
-+ return err;
-+}
-+
-+//----------------------------------------------------------------------
-+// rx8010_read_alarm()
-+// reads current Alarm
-+//
-+// Notes: - currently filters the AE bits (bit 7)
-+// - assumes WADA setting is week (week/day)
-+//----------------------------------------------------------------------
-+static int rx8010_read_alarm(struct device *dev, struct rtc_wkalrm *t)
-+{
-+ struct rx8010_data *rx8010 = dev_get_drvdata(dev);
-+ struct i2c_client *client = rx8010->client;
-+ u8 alarmvals[3]; //minute, hour, week/day values
-+ u8 ctrl[3]; //extension, flag, control values
-+ int err;
-+
-+ if (client->irq <= 0)
-+ return -EINVAL;
-+
-+ //get current minute, hour, week/day alarm values
-+ err = rx8010_read_regs(client, RX8010_REG_ALMIN, 3, alarmvals);
-+ if (err)
-+ return err;
-+ dev_dbg(dev, "%s: minutes:0x%02x hours:0x%02x week/day:0x%02x\n",
-+ __func__, alarmvals[0], alarmvals[1], alarmvals[2]);
-+
-+
-+ //get current extension, flag, control register values
-+ err = rx8010_read_regs(client, RX8010_REG_EXT, 3, ctrl);
-+ if (err)
-+ return err;
-+ dev_dbg(dev, "%s: extension:0x%02x flag:0x%02x control:0x%02x \n",
-+ __func__, ctrl[0], ctrl[1], ctrl[2]);
-+
-+ // Hardware alarm precision is 1 minute
-+ t->time.tm_sec = 0;
-+ t->time.tm_min = bcd2bin(alarmvals[0] & 0x7f); //0x7f filters AE bit currently
-+ t->time.tm_hour = bcd2bin(alarmvals[1] & 0x3f); //0x3f filters AE bit currently, also 24hr only
-+
-+ t->time.tm_wday = -1;
-+ t->time.tm_mday = -1;
-+ t->time.tm_mon = -1;
-+ t->time.tm_year = -1;
-+
-+ dev_dbg(dev, "%s: date: %ds %dm %dh %dmd %dm %dy\n",
-+ __func__,
-+ t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
-+ t->time.tm_mday, t->time.tm_mon, t->time.tm_year);
-+
-+ t->enabled = !!(rx8010->ctrlreg & RX8010_BIT_CTRL_AIE); //check if interrupt is enabled
-+ t->pending = (ctrl[1] & RX8010_BIT_FLAG_AF) && t->enabled; //check if flag is triggered
-+
-+ return err;
-+}
-+
-+//----------------------------------------------------------------------
-+// rx8010_set_alarm()
-+// sets Alarm
-+//
-+// Notes: - currently filters the AE bits (bit 7)
-+// - assumes WADA setting is week (week/day)
-+//----------------------------------------------------------------------
-+static int rx8010_set_alarm(struct device *dev, struct rtc_wkalrm *t)
-+{
-+ struct i2c_client *client = to_i2c_client(dev);
-+ struct rx8010_data *rx8010 = dev_get_drvdata(dev);
-+ u8 alarmvals[3]; //minute, hour, day
-+ u8 extreg; //extension register
-+ u8 flagreg; //flag register
-+ int err;
-+
-+ if (client->irq <= 0)
-+ return -EINVAL;
-+
-+ //get current extension register
-+ err = rx8010_read_reg(client, RX8010_REG_EXT, &extreg);
-+ if (err <0)
-+ return err;
-+
-+ //get current flag register
-+ err = rx8010_read_reg(client, RX8010_REG_FLAG, &flagreg);
-+ if (err <0)
-+ return err;
-+
-+ // Hardware alarm precision is 1 minute
-+ alarmvals[0] = bin2bcd(t->time.tm_min);
-+ alarmvals[1] = bin2bcd(t->time.tm_hour);
-+ alarmvals[2] = bin2bcd(t->time.tm_mday);
-+ dev_dbg(dev, "%s: write 0x%02x 0x%02x 0x%02x\n", __func__, alarmvals[0], alarmvals[1], alarmvals[2]);
-+
-+ //check interrupt enable and disable
-+ if (rx8010->ctrlreg & RX8010_BIT_CTRL_AIE) {
-+ rx8010->ctrlreg &= ~RX8010_BIT_CTRL_AIE;
-+ err = rx8010_write_reg(rx8010->client, RX8010_REG_CTRL, rx8010->ctrlreg);
-+ if (err)
-+ return err;
-+ }
-+
-+ //write the new minute and hour values
-+ //Note:assume minute and hour values will be enabled. Bit 7 of each of the
-+ // minute, hour, week/day register can be set which will "disable" the
-+ // register from triggering an alarm. See the RX8010 spec for more information
-+ err = rx8010_write_regs(rx8010->client, RX8010_REG_ALMIN, 2, alarmvals);
-+ if (err)
-+ return err;
-+
-+ //set Week/Day bit
-+ // Week setting is typically not used, so we will assume "day" setting
-+ extreg |= RX8010_BIT_EXT_WADA; //set to "day of month"
-+ err = rx8010_write_reg(rx8010->client, RX8010_REG_EXT, extreg);
-+ if (err)
-+ return err;
-+
-+ //set Day of Month register
-+ if (alarmvals[2] == 0) {
-+ alarmvals[2] |= 0x80; //turn on AE bit to ignore day of month (no zero day)
-+ err = rx8010_write_reg(rx8010->client, RX8010_REG_ALWDAY, alarmvals[2]);
-+ }
-+ else {
-+ err = rx8010_write_reg(rx8010->client, RX8010_REG_ALWDAY, alarmvals[2]);
-+ }
-+ if (err)
-+ return err;
-+
-+ //clear Alarm Flag
-+ flagreg &= ~RX8010_BIT_FLAG_AF;
-+ err = rx8010_write_reg(rx8010->client, RX8010_REG_FLAG, flagreg);
-+ if (err)
-+ return err;
-+
-+ //re-enable interrupt if required
-+ if (t->enabled) {
-+
-+ if ( rx8010->rtc->uie_rtctimer.enabled )
-+ rx8010->ctrlreg |= RX8010_BIT_CTRL_UIE; //set update interrupt enable
-+ if ( rx8010->rtc->aie_timer.enabled )
-+ rx8010->ctrlreg |= (RX8010_BIT_CTRL_AIE | RX8010_BIT_CTRL_UIE); //set alarm interrupt enable
-+
-+ err = rx8010_write_reg(rx8010->client, RX8010_REG_CTRL, rx8010->ctrlreg);
-+ if (err)
-+ return err;
-+ }
-+
-+ return 0;
-+}
-+
-+//----------------------------------------------------------------------
-+// rx8010_alarm_irq_enable()
-+// sets enables Alarm IRQ
-+//
-+// Todo: -
-+//
-+//----------------------------------------------------------------------
-+static int rx8010_alarm_irq_enable(struct device *dev, unsigned int enabled)
-+{
-+ struct i2c_client *client = to_i2c_client(dev);
-+ struct rx8010_data *rx8010 = dev_get_drvdata(dev);
-+ u8 flagreg;
-+ u8 ctrl;
-+ int err;
-+
-+ //get the current ctrl settings
-+ ctrl = rx8010->ctrlreg;
-+
-+ if (enabled)
-+ {
-+ if ( rx8010->rtc->uie_rtctimer.enabled )
-+ ctrl |= RX8010_BIT_CTRL_UIE; //set update interrupt enable
-+ if ( rx8010->rtc->aie_timer.enabled )
-+ ctrl |= (RX8010_BIT_CTRL_AIE | RX8010_BIT_CTRL_UIE); //set alarm interrupt enable
-+ }
-+ else
-+ {
-+ if ( ! rx8010->rtc->uie_rtctimer.enabled )
-+ ctrl &= ~RX8010_BIT_CTRL_UIE; //clear update interrupt enable
-+ if ( ! rx8010->rtc->aie_timer.enabled )
-+ {
-+ if ( rx8010->rtc->uie_rtctimer.enabled )
-+ ctrl &= ~RX8010_BIT_CTRL_AIE;
-+ else
-+ ctrl &= ~(RX8010_BIT_CTRL_AIE | RX8010_BIT_CTRL_UIE); //clear alarm interrupt enable
-+ }
-+ }
-+
-+ //clear alarm flag
-+ err = rx8010_read_reg(client, RX8010_REG_FLAG, &flagreg);
-+ if (err <0)
-+ return err;
-+ flagreg &= ~RX8010_BIT_FLAG_AF;
-+ err = rx8010_write_reg(rx8010->client, RX8010_REG_FLAG, flagreg);
-+ if (err)
-+ return err;
-+
-+ //update the Control register if the setting changed
-+ if (ctrl != rx8010->ctrlreg) {
-+ rx8010->ctrlreg = ctrl;
-+ err = rx8010_write_reg(rx8010->client, RX8010_REG_CTRL, rx8010->ctrlreg);
-+ if (err)
-+ return err;
-+ }
-+
-+ return 0;
-+}
-+
-+//---------------------------------------------------------------------------
-+// rx8010_ioctl()
-+//
-+//---------------------------------------------------------------------------
-+static int rx8010_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
-+{
-+ struct i2c_client *client = to_i2c_client(dev);
-+ //struct rx8010_data *rx8010 = dev_get_drvdata(dev);
-+ //struct mutex *lock = &rx8010->rtc->ops_lock;
-+ int ret = 0;
-+ int tmp;
-+ void __user *argp = (void __user *)arg;
-+ reg_data reg;
-+
-+ dev_dbg(dev, "%s: cmd=%x\n", __func__, cmd);
-+
-+ switch (cmd) {
-+ case SE_RTC_REG_READ:
-+ if (copy_from_user(®, argp, sizeof(reg)))
-+ return -EFAULT;
-+ if ( reg.number < RX8010_REG_SEC || reg.number > RX8010_REG_IRQ )
-+ return -EFAULT;
-+ //mutex_lock(lock);
-+ ret = rx8010_read_reg(client, reg.number, ®.value);
-+ //mutex_unlock(lock);
-+ if (! ret )
-+ return copy_to_user(argp, ®, sizeof(reg)) ? -EFAULT : 0;
-+ break;
-+
-+ case SE_RTC_REG_WRITE:
-+ if (copy_from_user(®, argp, sizeof(reg)))
-+ return -EFAULT;
-+ if ( reg.number < RX8010_REG_SEC || reg.number > RX8010_REG_IRQ )
-+ return -EFAULT;
-+ //mutex_lock(lock);
-+ ret = rx8010_write_reg(client, reg.number, reg.value);
-+ //mutex_unlock(lock);
-+ break;
-+
-+ case RTC_VL_READ:
-+ //mutex_lock(lock);
-+ ret = rx8010_read_reg(client, RX8010_REG_FLAG, ®.value);
-+ //mutex_unlock(lock);
-+ if (! ret)
-+ {
-+ tmp = !!(reg.value & RX8010_BIT_FLAG_VLF);
-+ return copy_to_user(argp, &tmp, sizeof(tmp)) ? -EFAULT : 0;
-+ }
-+ break;
-+
-+ case RTC_VL_CLR:
-+ //mutex_lock(lock);
-+ ret = rx8010_read_reg(client, RX8010_REG_FLAG, ®.value);
-+ if (! ret)
-+ {
-+ reg.value &= ~RX8010_BIT_FLAG_VLF;
-+ ret = rx8010_write_reg(client, RX8010_REG_FLAG, reg.value);
-+ }
-+ //mutex_unlock(lock);
-+ break;
-+
-+ default:
-+ return -ENOIOCTLCMD;
-+ }
-+
-+ return ret;
-+}
-+
-+static struct rtc_class_ops rx8010_rtc_ops = {
-+ .read_time = rx8010_get_time,
-+ .set_time = rx8010_set_time,
-+ .read_alarm = rx8010_read_alarm,
-+ .set_alarm = rx8010_set_alarm,
-+ .alarm_irq_enable = rx8010_alarm_irq_enable,
-+ .ioctl = rx8010_ioctl,
-+};
-+
-+//----------------------------------------------------------------------
-+// rx8010_probe()
-+// probe routine for the rx8010 driver
-+//
-+//----------------------------------------------------------------------
-+static int rx8010_probe(struct i2c_client *client, const struct i2c_device_id *id)
-+{
-+ struct device_node *np = client->dev.of_node;
-+ struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
-+ struct rx8010_data *rx8010;
-+ int err, gpio, i, irqs_success = 0, need_reset = 0;
-+ const char * irq_name[2] = {"rx8010-irq_1", "rx8010-irq_2"};
-+
-+ if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_I2C_BLOCK)) {
-+ dev_err(&adapter->dev, "doesn't support required functionality\n");
-+ err = -EIO;
-+ goto errout;
-+ }
-+
-+ rx8010 = devm_kzalloc(&client->dev, sizeof(struct rx8010_data), GFP_KERNEL);
-+ if (!rx8010) {
-+ dev_err(&adapter->dev, "failed to alloc memory\n");
-+ err = -ENOMEM;
-+ goto errout;
-+ }
-+
-+ rx8010->client = client;
-+ i2c_set_clientdata(client, rx8010);
-+
-+ err = rx8010_init_client(client, &need_reset);
-+ if (err)
-+ goto errout;
-+
-+
-+ if (need_reset) {
-+ struct rtc_time tm;
-+ rtc_time_to_tm(0, &tm); // set to 1970/1/1
-+ rx8010_set_time(&client->dev, &tm);
-+ dev_warn(&client->dev, " - time reset to 1970/1/1\n");
-+ }
-+
-+ rx8010->rtc = rtc_device_register(client->name, &client->dev, &rx8010_rtc_ops, THIS_MODULE);
-+
-+ if (IS_ERR(rx8010->rtc)) {
-+ err = PTR_ERR(rx8010->rtc);
-+ dev_err(&client->dev, "unable to register the class device\n");
-+ goto errout;
-+ }
-+
-+ // get interrupts
-+ rx8010->irq_1 = rx8010->irq_2 = -1;
-+ for ( i=0; i < 2; i++ )
-+ {
-+ gpio = of_get_named_gpio(np, irq_name[i], 0);
-+ if (gpio_is_valid(gpio)) {
-+ int irq;
-+ err = devm_gpio_request_one(&client->dev, gpio, GPIOF_DIR_IN,
-+ irq_name[i]);
-+ if (err) {
-+ dev_err(&client->dev, "cannot request %s\n", irq_name[i]);
-+ goto errout_reg;
-+ }
-+ irq = gpio_to_irq(gpio);
-+ dev_dbg(&client->dev, "%s %d\n", irq_name[i], irq);
-+ if (irq <= 0) {
-+ dev_warn(&client->dev, "Failed to "
-+ "convert gpio #%d to %s\n",
-+ gpio, irq_name[i]);
-+ goto errout_reg;
-+ }
-+ err = devm_request_threaded_irq(&client->dev,irq, NULL,
-+ i==0 ? rx8010_irq_1 : rx8010_irq_2,
-+ IRQF_TRIGGER_LOW | IRQF_ONESHOT,
-+ irq_name[i],
-+ client);
-+ if (err) {
-+ dev_err(&client->dev, "unable to request %s\n", irq_name[i]);
-+ goto errout_reg;
-+ }
-+ if (i == 0)
-+ {
-+ rx8010->irq_1 = irq;
-+ INIT_WORK(&rx8010->work_1, rx8010_work_1);
-+ }
-+ else
-+ {
-+ rx8010->irq_2 = irq;
-+ INIT_WORK(&rx8010->work_2, rx8010_work_2);
-+ }
-+ irqs_success++;
-+ } else {
-+ dev_warn(&client->dev, "%s missing or invalid\n",
-+ irq_name[i]);
-+ }
-+ }
-+
-+ // another irq request try if one failed above
-+ if ( ! irqs_success && client->irq > 0 ){
-+ dev_info(&client->dev, "IRQ %d supplied\n", client->irq);
-+ err = devm_request_threaded_irq(&client->dev,client->irq, NULL,
-+ rx8010_irq_1,
-+ IRQF_TRIGGER_LOW | IRQF_ONESHOT,
-+ "rx8010", client);
-+
-+ if (err) {
-+ dev_err(&client->dev, "unable to request IRQ\n");
-+ goto errout_reg;
-+ }
-+ INIT_WORK(&rx8010->work_1, rx8010_work_1);
-+ }
-+
-+
-+ rx8010->rtc->irq_freq = 1;
-+ rx8010->rtc->max_user_freq = 1;
-+
-+ return 0;
-+
-+errout_reg:
-+ rtc_device_unregister(rx8010->rtc);
-+
-+errout:
-+ dev_err(&adapter->dev, "probing for rx8010 failed\n");
-+ return err;
-+}
-+
-+//----------------------------------------------------------------------
-+// rx8010_remove()
-+// remove routine for the rx8010 driver
-+//
-+//----------------------------------------------------------------------
-+static int rx8010_remove(struct i2c_client *client)
-+{
-+ struct rx8010_data *rx8010 = i2c_get_clientdata(client);
-+ struct mutex *lock = &rx8010->rtc->ops_lock;
-+
-+ if (client->irq > 0 || rx8010->irq_1 > 0 || rx8010->irq_2 > 0) {
-+ mutex_lock(lock);
-+ rx8010->exiting = 1;
-+ mutex_unlock(lock);
-+
-+ //cancel_work
-+ if (rx8010->irq_1 > 0 || client->irq > 0)
-+ cancel_work_sync(&rx8010->work_1);
-+ if (rx8010->irq_2 > 0)
-+ cancel_work_sync(&rx8010->work_2);
-+ }
-+
-+ rtc_device_unregister(rx8010->rtc);
-+
-+ return 0;
-+}
-+
-+static struct i2c_driver rx8010_driver = {
-+ .driver = {
-+ .name = "rtc-rx8010",
-+ .owner = THIS_MODULE,
-+ },
-+ .probe = rx8010_probe,
-+ .remove = rx8010_remove,
-+ .id_table = rx8010_id,
-+};
-+
-+module_i2c_driver(rx8010_driver);
-+
-+MODULE_AUTHOR("Dennis Henderson <henderson.dennis at erd.epson.com>");
-+MODULE_DESCRIPTION("RX-8010 SJ RTC driver");
-+MODULE_LICENSE("GPL");
---
-2.5.0
-
diff --git a/recipes-kernel/linux/linux-ge-3.14/0002-mfd-da9063-Add-support-for-production-silicon-varian.patch b/recipes-kernel/linux/linux-ge-3.14/0002-mfd-da9063-Add-support-for-production-silicon-varian.patch
deleted file mode 100644
index 1866b02..0000000
--- a/recipes-kernel/linux/linux-ge-3.14/0002-mfd-da9063-Add-support-for-production-silicon-varian.patch
+++ /dev/null
@@ -1,101 +0,0 @@
-From 19c444fc1fcc26077437e3fd5acef9fcf6044b9c Mon Sep 17 00:00:00 2001
-From: "Opensource [Steve Twiss]" <stwiss.opensource at diasemi.com>
-Date: Fri, 14 Feb 2014 14:08:11 +0000
-Subject: [PATCH 02/10] mfd: da9063: Add support for production silicon variant
- code
-
-Add the correct silicon variant code ID (0x5) to the driver. This
-new code is the 'production' variant code ID for DA9063.
-
-This patch will remove the older variant code ID which matches the
-pre-production silicon ID (0x3) for the DA9063 chip.
-
-There is also some small amount of correction done in this patch:
-it splits the revision code and correctly names it according to
-the hardware specification and moves the dev_info() call before
-the variant ID test.
-
-Signed-off-by: Opensource [Steve Twiss] <stwiss.opensource at diasemi.com>
-Signed-off-by: Lee Jones <lee.jones at linaro.org>
----
- drivers/mfd/da9063-core.c | 25 ++++++++++++++-----------
- include/linux/mfd/da9063/core.h | 6 +++++-
- 2 files changed, 19 insertions(+), 12 deletions(-)
-
-diff --git a/drivers/mfd/da9063-core.c b/drivers/mfd/da9063-core.c
-index 26937cd..e70ae31 100644
---- a/drivers/mfd/da9063-core.c
-+++ b/drivers/mfd/da9063-core.c
-@@ -110,7 +110,7 @@ static const struct mfd_cell da9063_devs[] = {
- int da9063_device_init(struct da9063 *da9063, unsigned int irq)
- {
- struct da9063_pdata *pdata = da9063->dev->platform_data;
-- int model, revision;
-+ int model, variant_id, variant_code;
- int ret;
-
- if (pdata) {
-@@ -141,23 +141,26 @@ int da9063_device_init(struct da9063 *da9063, unsigned int irq)
- return -ENODEV;
- }
-
-- ret = regmap_read(da9063->regmap, DA9063_REG_CHIP_VARIANT, &revision);
-+ ret = regmap_read(da9063->regmap, DA9063_REG_CHIP_VARIANT, &variant_id);
- if (ret < 0) {
-- dev_err(da9063->dev, "Cannot read chip revision id.\n");
-+ dev_err(da9063->dev, "Cannot read chip variant id.\n");
- return -EIO;
- }
-- revision >>= DA9063_CHIP_VARIANT_SHIFT;
-- if (revision != 3) {
-- dev_err(da9063->dev, "Unknown chip revision: %d\n", revision);
-+
-+ variant_code = variant_id >> DA9063_CHIP_VARIANT_SHIFT;
-+
-+ dev_info(da9063->dev,
-+ "Device detected (chip-ID: 0x%02X, var-ID: 0x%02X)\n",
-+ model, variant_id);
-+
-+ if (variant_code != PMIC_DA9063_BB) {
-+ dev_err(da9063->dev, "Unknown chip variant code: 0x%02X\n",
-+ variant_code);
- return -ENODEV;
- }
-
- da9063->model = model;
-- da9063->revision = revision;
--
-- dev_info(da9063->dev,
-- "Device detected (model-ID: 0x%02X rev-ID: 0x%02X)\n",
-- model, revision);
-+ da9063->variant_code = variant_code;
-
- ret = da9063_irq_init(da9063);
- if (ret) {
-diff --git a/include/linux/mfd/da9063/core.h b/include/linux/mfd/da9063/core.h
-index 2d2a0af..00a9aac 100644
---- a/include/linux/mfd/da9063/core.h
-+++ b/include/linux/mfd/da9063/core.h
-@@ -33,6 +33,10 @@ enum da9063_models {
- PMIC_DA9063 = 0x61,
- };
-
-+enum da9063_variant_codes {
-+ PMIC_DA9063_BB = 0x5
-+};
-+
- /* Interrupts */
- enum da9063_irqs {
- DA9063_IRQ_ONKEY = 0,
-@@ -72,7 +76,7 @@ struct da9063 {
- /* Device */
- struct device *dev;
- unsigned short model;
-- unsigned short revision;
-+ unsigned char variant_code;
- unsigned int flags;
-
- /* Control interface */
---
-2.5.0
-
diff --git a/recipes-kernel/linux/linux-ge-3.14/0003-mfd-da9063-Upgrade-of-register-definitions-to-suppor.patch b/recipes-kernel/linux/linux-ge-3.14/0003-mfd-da9063-Upgrade-of-register-definitions-to-suppor.patch
deleted file mode 100644
index 0e22385..0000000
--- a/recipes-kernel/linux/linux-ge-3.14/0003-mfd-da9063-Upgrade-of-register-definitions-to-suppor.patch
+++ /dev/null
@@ -1,257 +0,0 @@
-From b7085a60a9784fce6e0a01c333f875cc7ee9826d Mon Sep 17 00:00:00 2001
-From: "Opensource [Steve Twiss]" <stwiss.opensource at diasemi.com>
-Date: Thu, 6 Mar 2014 16:40:02 +0000
-Subject: [PATCH 03/10] mfd: da9063: Upgrade of register definitions to support
- production silicon
-
-This patch updates the register definitions for DA9063 to support the
-production silicon variant code ID (0x5). These changes are not backwards
-compatible with the previous register definitions and can only be used
-with the production variant of DA9063.
-
-Signed-off-by: Opensource [Steve Twiss] <stwiss.opensource at diasemi.com>
-Signed-off-by: Lee Jones <lee.jones at linaro.org>
----
- include/linux/mfd/da9063/registers.h | 120 ++++++++++++++++++-----------------
- 1 file changed, 62 insertions(+), 58 deletions(-)
-
-diff --git a/include/linux/mfd/da9063/registers.h b/include/linux/mfd/da9063/registers.h
-index 5834813..09a85c6 100644
---- a/include/linux/mfd/da9063/registers.h
-+++ b/include/linux/mfd/da9063/registers.h
-@@ -17,11 +17,7 @@
- #define _DA9063_REG_H
-
- #define DA9063_I2C_PAGE_SEL_SHIFT 1
--
- #define DA9063_EVENT_REG_NUM 4
--#define DA9210_EVENT_REG_NUM 2
--#define DA9063_EXT_EVENT_REG_NUM (DA9063_EVENT_REG_NUM + \
-- DA9210_EVENT_REG_NUM)
-
- /* Page selection I2C or SPI always in the begining of any page. */
- /* Page 0 : I2C access 0x000 - 0x0FF SPI access 0x000 - 0x07F */
-@@ -61,9 +57,9 @@
- #define DA9063_REG_GPIO_10_11 0x1A
- #define DA9063_REG_GPIO_12_13 0x1B
- #define DA9063_REG_GPIO_14_15 0x1C
--#define DA9063_REG_GPIO_MODE_0_7 0x1D
--#define DA9063_REG_GPIO_MODE_8_15 0x1E
--#define DA9063_REG_GPIO_SWITCH_CONT 0x1F
-+#define DA9063_REG_GPIO_MODE0_7 0x1D
-+#define DA9063_REG_GPIO_MODE8_15 0x1E
-+#define DA9063_REG_SWITCH_CONT 0x1F
-
- /* Regulator Control Registers */
- #define DA9063_REG_BCORE2_CONT 0x20
-@@ -83,7 +79,7 @@
- #define DA9063_REG_LDO9_CONT 0x2E
- #define DA9063_REG_LDO10_CONT 0x2F
- #define DA9063_REG_LDO11_CONT 0x30
--#define DA9063_REG_VIB 0x31
-+#define DA9063_REG_SUPPLIES 0x31
- #define DA9063_REG_DVC_1 0x32
- #define DA9063_REG_DVC_2 0x33
-
-@@ -97,9 +93,9 @@
- #define DA9063_REG_ADCIN1_RES 0x3A
- #define DA9063_REG_ADCIN2_RES 0x3B
- #define DA9063_REG_ADCIN3_RES 0x3C
--#define DA9063_REG_MON1_RES 0x3D
--#define DA9063_REG_MON2_RES 0x3E
--#define DA9063_REG_MON3_RES 0x3F
-+#define DA9063_REG_MON_A8_RES 0x3D
-+#define DA9063_REG_MON_A9_RES 0x3E
-+#define DA9063_REG_MON_A10_RES 0x3F
-
- /* RTC Calendar and Alarm Registers */
- #define DA9063_REG_COUNT_S 0x40
-@@ -108,15 +104,16 @@
- #define DA9063_REG_COUNT_D 0x43
- #define DA9063_REG_COUNT_MO 0x44
- #define DA9063_REG_COUNT_Y 0x45
--#define DA9063_REG_ALARM_MI 0x46
--#define DA9063_REG_ALARM_H 0x47
--#define DA9063_REG_ALARM_D 0x48
--#define DA9063_REG_ALARM_MO 0x49
--#define DA9063_REG_ALARM_Y 0x4A
--#define DA9063_REG_SECOND_A 0x4B
--#define DA9063_REG_SECOND_B 0x4C
--#define DA9063_REG_SECOND_C 0x4D
--#define DA9063_REG_SECOND_D 0x4E
-+#define DA9063_REG_ALARM_S 0x46
-+#define DA9063_REG_ALARM_MI 0x47
-+#define DA9063_REG_ALARM_H 0x48
-+#define DA9063_REG_ALARM_D 0x49
-+#define DA9063_REG_ALARM_MO 0x4A
-+#define DA9063_REG_ALARM_Y 0x4B
-+#define DA9063_REG_SECOND_A 0x4C
-+#define DA9063_REG_SECOND_B 0x4D
-+#define DA9063_REG_SECOND_C 0x4E
-+#define DA9063_REG_SECOND_D 0x4F
-
- /* Sequencer Control Registers */
- #define DA9063_REG_SEQ 0x81
-@@ -226,35 +223,37 @@
- #define DA9063_REG_CONFIG_J 0x10F
- #define DA9063_REG_CONFIG_K 0x110
- #define DA9063_REG_CONFIG_L 0x111
--#define DA9063_REG_MON_REG_1 0x112
--#define DA9063_REG_MON_REG_2 0x113
--#define DA9063_REG_MON_REG_3 0x114
--#define DA9063_REG_MON_REG_4 0x115
--#define DA9063_REG_MON_REG_5 0x116
--#define DA9063_REG_MON_REG_6 0x117
--#define DA9063_REG_TRIM_CLDR 0x118
--
-+#define DA9063_REG_CONFIG_M 0x112
-+#define DA9063_REG_CONFIG_N 0x113
-+
-+#define DA9063_REG_MON_REG_1 0x114
-+#define DA9063_REG_MON_REG_2 0x115
-+#define DA9063_REG_MON_REG_3 0x116
-+#define DA9063_REG_MON_REG_4 0x117
-+#define DA9063_REG_MON_REG_5 0x11E
-+#define DA9063_REG_MON_REG_6 0x11F
-+#define DA9063_REG_TRIM_CLDR 0x120
- /* General Purpose Registers */
--#define DA9063_REG_GP_ID_0 0x119
--#define DA9063_REG_GP_ID_1 0x11A
--#define DA9063_REG_GP_ID_2 0x11B
--#define DA9063_REG_GP_ID_3 0x11C
--#define DA9063_REG_GP_ID_4 0x11D
--#define DA9063_REG_GP_ID_5 0x11E
--#define DA9063_REG_GP_ID_6 0x11F
--#define DA9063_REG_GP_ID_7 0x120
--#define DA9063_REG_GP_ID_8 0x121
--#define DA9063_REG_GP_ID_9 0x122
--#define DA9063_REG_GP_ID_10 0x123
--#define DA9063_REG_GP_ID_11 0x124
--#define DA9063_REG_GP_ID_12 0x125
--#define DA9063_REG_GP_ID_13 0x126
--#define DA9063_REG_GP_ID_14 0x127
--#define DA9063_REG_GP_ID_15 0x128
--#define DA9063_REG_GP_ID_16 0x129
--#define DA9063_REG_GP_ID_17 0x12A
--#define DA9063_REG_GP_ID_18 0x12B
--#define DA9063_REG_GP_ID_19 0x12C
-+#define DA9063_REG_GP_ID_0 0x121
-+#define DA9063_REG_GP_ID_1 0x122
-+#define DA9063_REG_GP_ID_2 0x123
-+#define DA9063_REG_GP_ID_3 0x124
-+#define DA9063_REG_GP_ID_4 0x125
-+#define DA9063_REG_GP_ID_5 0x126
-+#define DA9063_REG_GP_ID_6 0x127
-+#define DA9063_REG_GP_ID_7 0x128
-+#define DA9063_REG_GP_ID_8 0x129
-+#define DA9063_REG_GP_ID_9 0x12A
-+#define DA9063_REG_GP_ID_10 0x12B
-+#define DA9063_REG_GP_ID_11 0x12C
-+#define DA9063_REG_GP_ID_12 0x12D
-+#define DA9063_REG_GP_ID_13 0x12E
-+#define DA9063_REG_GP_ID_14 0x12F
-+#define DA9063_REG_GP_ID_15 0x130
-+#define DA9063_REG_GP_ID_16 0x131
-+#define DA9063_REG_GP_ID_17 0x132
-+#define DA9063_REG_GP_ID_18 0x133
-+#define DA9063_REG_GP_ID_19 0x134
-
- /* Chip ID and variant */
- #define DA9063_REG_CHIP_ID 0x181
-@@ -405,8 +404,10 @@
- /* DA9063_REG_CONTROL_B (addr=0x0F) */
- #define DA9063_CHG_SEL 0x01
- #define DA9063_WATCHDOG_PD 0x02
-+#define DA9063_RESET_BLINKING 0x04
- #define DA9063_NRES_MODE 0x08
- #define DA9063_NONKEY_LOCK 0x10
-+#define DA9063_BUCK_SLOWSTART 0x80
-
- /* DA9063_REG_CONTROL_C (addr=0x10) */
- #define DA9063_DEBOUNCING_MASK 0x07
-@@ -466,6 +467,7 @@
- #define DA9063_GPADC_PAUSE 0x02
- #define DA9063_PMIF_DIS 0x04
- #define DA9063_HS2WIRE_DIS 0x08
-+#define DA9063_CLDR_PAUSE 0x10
- #define DA9063_BBAT_DIS 0x20
- #define DA9063_OUT_32K_PAUSE 0x40
- #define DA9063_PMCONT_DIS 0x80
-@@ -660,7 +662,7 @@
- #define DA9063_GPIO15_TYPE_GPO 0x04
- #define DA9063_GPIO15_NO_WAKEUP 0x80
-
--/* DA9063_REG_GPIO_MODE_0_7 (addr=0x1D) */
-+/* DA9063_REG_GPIO_MODE0_7 (addr=0x1D) */
- #define DA9063_GPIO0_MODE 0x01
- #define DA9063_GPIO1_MODE 0x02
- #define DA9063_GPIO2_MODE 0x04
-@@ -670,7 +672,7 @@
- #define DA9063_GPIO6_MODE 0x40
- #define DA9063_GPIO7_MODE 0x80
-
--/* DA9063_REG_GPIO_MODE_8_15 (addr=0x1E) */
-+/* DA9063_REG_GPIO_MODE8_15 (addr=0x1E) */
- #define DA9063_GPIO8_MODE 0x01
- #define DA9063_GPIO9_MODE 0x02
- #define DA9063_GPIO10_MODE 0x04
-@@ -702,12 +704,12 @@
- #define DA9063_SWITCH_SR_5MV 0x10
- #define DA9063_SWITCH_SR_10MV 0x20
- #define DA9063_SWITCH_SR_50MV 0x30
--#define DA9063_SWITCH_SR_DIS 0x40
-+#define DA9063_CORE_SW_INTERNAL 0x40
- #define DA9063_CP_EN_MODE 0x80
-
- /* DA9063_REGL_Bxxxx_CONT common bits (addr=0x20-0x25) */
- #define DA9063_BUCK_EN 0x01
--#define DA9063_BUCK_GPI_MASK 0x06
-+#define DA9063_BUCK_GPI_MASK 0x06
- #define DA9063_BUCK_GPI_OFF 0x00
- #define DA9063_BUCK_GPI_GPIO1 0x02
- #define DA9063_BUCK_GPI_GPIO2 0x04
-@@ -841,25 +843,27 @@
- #define DA9063_COUNT_YEAR_MASK 0x3F
- #define DA9063_MONITOR 0x40
-
--/* DA9063_REG_ALARM_MI (addr=0x46) */
-+/* DA9063_REG_ALARM_S (addr=0x46) */
-+#define DA9063_ALARM_S_MASK 0x3F
- #define DA9063_ALARM_STATUS_ALARM 0x80
- #define DA9063_ALARM_STATUS_TICK 0x40
-+/* DA9063_REG_ALARM_MI (addr=0x47) */
- #define DA9063_ALARM_MIN_MASK 0x3F
-
--/* DA9063_REG_ALARM_H (addr=0x47) */
-+/* DA9063_REG_ALARM_H (addr=0x48) */
- #define DA9063_ALARM_HOUR_MASK 0x1F
-
--/* DA9063_REG_ALARM_D (addr=0x48) */
-+/* DA9063_REG_ALARM_D (addr=0x49) */
- #define DA9063_ALARM_DAY_MASK 0x1F
-
--/* DA9063_REG_ALARM_MO (addr=0x49) */
-+/* DA9063_REG_ALARM_MO (addr=0x4A) */
- #define DA9063_TICK_WAKE 0x20
- #define DA9063_TICK_TYPE 0x10
- #define DA9063_TICK_TYPE_SEC 0x00
- #define DA9063_TICK_TYPE_MIN 0x10
- #define DA9063_ALARM_MONTH_MASK 0x0F
-
--/* DA9063_REG_ALARM_Y (addr=0x4A) */
-+/* DA9063_REG_ALARM_Y (addr=0x4B) */
- #define DA9063_TICK_ON 0x80
- #define DA9063_ALARM_ON 0x40
- #define DA9063_ALARM_YEAR_MASK 0x3F
-@@ -906,7 +910,7 @@
-
- /* DA9063_REG_Bxxxx_CFG common bits (addr=0x9D-0xA2) */
- #define DA9063_BUCK_FB_MASK 0x07
--#define DA9063_BUCK_PD_DIS_SHIFT 5
-+#define DA9063_BUCK_PD_DIS_MASK 0x20
- #define DA9063_BUCK_MODE_MASK 0xC0
- #define DA9063_BUCK_MODE_MANUAL 0x00
- #define DA9063_BUCK_MODE_SLEEP 0x40
---
-2.5.0
-
diff --git a/recipes-kernel/linux/linux-ge-3.14/0004-rtc-da9063-RTC-driver.patch b/recipes-kernel/linux/linux-ge-3.14/0004-rtc-da9063-RTC-driver.patch
deleted file mode 100644
index aadc66d..0000000
--- a/recipes-kernel/linux/linux-ge-3.14/0004-rtc-da9063-RTC-driver.patch
+++ /dev/null
@@ -1,399 +0,0 @@
-From 8115b46c6de0f3afb6e3cb8746a8729cf59cbf56 Mon Sep 17 00:00:00 2001
-From: "Opensource [Steve Twiss]" <stwiss.opensource at diasemi.com>
-Date: Fri, 6 Jun 2014 14:36:03 -0700
-Subject: [PATCH 04/10] rtc: da9063: RTC driver
-
-Add the RTC driver for DA9063.
-
-[akpm at linux-foundation.org: coding-style tweaks]
-Signed-off-by: Opensource [Steve Twiss] <stwiss.opensource at diasemi.com>
-Cc: Alessandro Zummo <a.zummo at towertech.it>
-Cc: Lee Jones <lee.jones at linaro.org>
-Cc: Mark Brown <broonie at linaro.org>
-Cc: Philipp Zabel <p.zabel at pengutronix.de>
-Cc: Samuel Ortiz <sameo at linux.intel.com>
-Cc: David Dajun Chen <david.chen at diasemi.com>
-Signed-off-by: Andrew Morton <akpm at linux-foundation.org>
-Signed-off-by: Linus Torvalds <torvalds at linux-foundation.org>
----
- drivers/rtc/Kconfig | 10 ++
- drivers/rtc/Makefile | 1 +
- drivers/rtc/rtc-da9063.c | 333 +++++++++++++++++++++++++++++++++++++++++++++++
- 3 files changed, 344 insertions(+)
- create mode 100644 drivers/rtc/rtc-da9063.c
-
-diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
-index 87ed3a3..dbafefe 100644
---- a/drivers/rtc/Kconfig
-+++ b/drivers/rtc/Kconfig
-@@ -754,6 +754,16 @@ config RTC_DRV_DA9055
- This driver can also be built as a module. If so, the module
- will be called rtc-da9055
-
-+config RTC_DRV_DA9063
-+ tristate "Dialog Semiconductor DA9063 RTC"
-+ depends on MFD_DA9063
-+ help
-+ If you say yes here you will get support for the RTC subsystem
-+ of the Dialog Semiconductor DA9063.
-+
-+ This driver can also be built as a module. If so, the module
-+ will be called "rtc-da9063".
-+
- config RTC_DRV_EFI
- tristate "EFI RTC"
- depends on IA64
-diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
-index 1512f48..715be64 100644
---- a/drivers/rtc/Makefile
-+++ b/drivers/rtc/Makefile
-@@ -32,6 +32,7 @@ obj-$(CONFIG_RTC_DRV_CMOS) += rtc-cmos.o
- obj-$(CONFIG_RTC_DRV_COH901331) += rtc-coh901331.o
- obj-$(CONFIG_RTC_DRV_DA9052) += rtc-da9052.o
- obj-$(CONFIG_RTC_DRV_DA9055) += rtc-da9055.o
-+obj-$(CONFIG_RTC_DRV_DA9063) += rtc-da9063.o
- obj-$(CONFIG_RTC_DRV_DAVINCI) += rtc-davinci.o
- obj-$(CONFIG_RTC_DRV_DM355EVM) += rtc-dm355evm.o
- obj-$(CONFIG_RTC_DRV_VRTC) += rtc-mrst.o
-diff --git a/drivers/rtc/rtc-da9063.c b/drivers/rtc/rtc-da9063.c
-new file mode 100644
-index 0000000..5953930
---- /dev/null
-+++ b/drivers/rtc/rtc-da9063.c
-@@ -0,0 +1,333 @@
-+/* rtc-da9063.c - Real time clock device driver for DA9063
-+ * Copyright (C) 2013-14 Dialog Semiconductor Ltd.
-+ *
-+ * This library is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU Library General Public
-+ * License as published by the Free Software Foundation; either
-+ * version 2 of the License, or (at your option) any later version.
-+ *
-+ * This library is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-+ * Library General Public License for more details.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/init.h>
-+#include <linux/platform_device.h>
-+#include <linux/interrupt.h>
-+#include <linux/rtc.h>
-+#include <linux/slab.h>
-+#include <linux/delay.h>
-+#include <linux/regmap.h>
-+#include <linux/mfd/da9063/registers.h>
-+#include <linux/mfd/da9063/core.h>
-+
-+#define YEARS_TO_DA9063(year) ((year) - 100)
-+#define MONTHS_TO_DA9063(month) ((month) + 1)
-+#define YEARS_FROM_DA9063(year) ((year) + 100)
-+#define MONTHS_FROM_DA9063(month) ((month) - 1)
-+
-+#define RTC_DATA_LEN (DA9063_REG_COUNT_Y - DA9063_REG_COUNT_S + 1)
-+#define RTC_SEC 0
-+#define RTC_MIN 1
-+#define RTC_HOUR 2
-+#define RTC_DAY 3
-+#define RTC_MONTH 4
-+#define RTC_YEAR 5
-+
-+struct da9063_rtc {
-+ struct rtc_device *rtc_dev;
-+ struct da9063 *hw;
-+ struct rtc_time alarm_time;
-+ bool rtc_sync;
-+};
-+
-+static void da9063_data_to_tm(u8 *data, struct rtc_time *tm)
-+{
-+ tm->tm_sec = data[RTC_SEC] & DA9063_COUNT_SEC_MASK;
-+ tm->tm_min = data[RTC_MIN] & DA9063_COUNT_MIN_MASK;
-+ tm->tm_hour = data[RTC_HOUR] & DA9063_COUNT_HOUR_MASK;
-+ tm->tm_mday = data[RTC_DAY] & DA9063_COUNT_DAY_MASK;
-+ tm->tm_mon = MONTHS_FROM_DA9063(data[RTC_MONTH] &
-+ DA9063_COUNT_MONTH_MASK);
-+ tm->tm_year = YEARS_FROM_DA9063(data[RTC_YEAR] &
-+ DA9063_COUNT_YEAR_MASK);
-+}
-+
-+static void da9063_tm_to_data(struct rtc_time *tm, u8 *data)
-+{
-+ data[RTC_SEC] &= ~DA9063_COUNT_SEC_MASK;
-+ data[RTC_SEC] |= tm->tm_sec & DA9063_COUNT_SEC_MASK;
-+
-+ data[RTC_MIN] &= ~DA9063_COUNT_MIN_MASK;
-+ data[RTC_MIN] |= tm->tm_min & DA9063_COUNT_MIN_MASK;
-+
-+ data[RTC_HOUR] &= ~DA9063_COUNT_HOUR_MASK;
-+ data[RTC_HOUR] |= tm->tm_hour & DA9063_COUNT_HOUR_MASK;
-+
-+ data[RTC_DAY] &= ~DA9063_COUNT_DAY_MASK;
-+ data[RTC_DAY] |= tm->tm_mday & DA9063_COUNT_DAY_MASK;
-+
-+ data[RTC_MONTH] &= ~DA9063_COUNT_MONTH_MASK;
-+ data[RTC_MONTH] |= MONTHS_TO_DA9063(tm->tm_mon) &
-+ DA9063_COUNT_MONTH_MASK;
-+
-+ data[RTC_YEAR] &= ~DA9063_COUNT_YEAR_MASK;
-+ data[RTC_YEAR] |= YEARS_TO_DA9063(tm->tm_year) &
-+ DA9063_COUNT_YEAR_MASK;
-+}
-+
-+static int da9063_rtc_stop_alarm(struct device *dev)
-+{
-+ struct da9063_rtc *rtc = dev_get_drvdata(dev);
-+
-+ return regmap_update_bits(rtc->hw->regmap, DA9063_REG_ALARM_Y,
-+ DA9063_ALARM_ON, 0);
-+}
-+
-+static int da9063_rtc_start_alarm(struct device *dev)
-+{
-+ struct da9063_rtc *rtc = dev_get_drvdata(dev);
-+
-+ return regmap_update_bits(rtc->hw->regmap, DA9063_REG_ALARM_Y,
-+ DA9063_ALARM_ON, DA9063_ALARM_ON);
-+}
-+
-+static int da9063_rtc_read_time(struct device *dev, struct rtc_time *tm)
-+{
-+ struct da9063_rtc *rtc = dev_get_drvdata(dev);
-+ unsigned long tm_secs;
-+ unsigned long al_secs;
-+ u8 data[RTC_DATA_LEN];
-+ int ret;
-+
-+ ret = regmap_bulk_read(rtc->hw->regmap, DA9063_REG_COUNT_S,
-+ data, RTC_DATA_LEN);
-+ if (ret < 0) {
-+ dev_err(dev, "Failed to read RTC time data: %d\n", ret);
-+ return ret;
-+ }
-+
-+ if (!(data[RTC_SEC] & DA9063_RTC_READ)) {
-+ dev_dbg(dev, "RTC not yet ready to be read by the host\n");
-+ return -EINVAL;
-+ }
-+
-+ da9063_data_to_tm(data, tm);
-+
-+ rtc_tm_to_time(tm, &tm_secs);
-+ rtc_tm_to_time(&rtc->alarm_time, &al_secs);
-+
-+ /* handle the rtc synchronisation delay */
-+ if (rtc->rtc_sync == true && al_secs - tm_secs == 1)
-+ memcpy(tm, &rtc->alarm_time, sizeof(struct rtc_time));
-+ else
-+ rtc->rtc_sync = false;
-+
-+ return rtc_valid_tm(tm);
-+}
-+
-+static int da9063_rtc_set_time(struct device *dev, struct rtc_time *tm)
-+{
-+ struct da9063_rtc *rtc = dev_get_drvdata(dev);
-+ u8 data[RTC_DATA_LEN];
-+ int ret;
-+
-+ da9063_tm_to_data(tm, data);
-+ ret = regmap_bulk_write(rtc->hw->regmap, DA9063_REG_COUNT_S,
-+ data, RTC_DATA_LEN);
-+ if (ret < 0)
-+ dev_err(dev, "Failed to set RTC time data: %d\n", ret);
-+
-+ return ret;
-+}
-+
-+static int da9063_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
-+{
-+ struct da9063_rtc *rtc = dev_get_drvdata(dev);
-+ u8 data[RTC_DATA_LEN];
-+ int ret;
-+ unsigned int val;
-+
-+ ret = regmap_bulk_read(rtc->hw->regmap, DA9063_REG_ALARM_S,
-+ &data[RTC_SEC], RTC_DATA_LEN);
-+ if (ret < 0)
-+ return ret;
-+
-+ da9063_data_to_tm(data, &alrm->time);
-+
-+ alrm->enabled = !!(data[RTC_YEAR] & DA9063_ALARM_ON);
-+
-+ ret = regmap_read(rtc->hw->regmap, DA9063_REG_EVENT_A, &val);
-+ if (ret < 0)
-+ return ret;
-+
-+ if (val & (DA9063_E_ALARM))
-+ alrm->pending = 1;
-+ else
-+ alrm->pending = 0;
-+
-+ return 0;
-+}
-+
-+static int da9063_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
-+{
-+ struct da9063_rtc *rtc = dev_get_drvdata(dev);
-+ u8 data[RTC_DATA_LEN];
-+ int ret;
-+
-+ da9063_tm_to_data(&alrm->time, data);
-+
-+ ret = da9063_rtc_stop_alarm(dev);
-+ if (ret < 0) {
-+ dev_err(dev, "Failed to stop alarm: %d\n", ret);
-+ return ret;
-+ }
-+
-+ ret = regmap_bulk_write(rtc->hw->regmap, DA9063_REG_ALARM_S,
-+ data, RTC_DATA_LEN);
-+ if (ret < 0) {
-+ dev_err(dev, "Failed to write alarm: %d\n", ret);
-+ return ret;
-+ }
-+
-+ rtc->alarm_time = alrm->time;
-+
-+ if (alrm->enabled) {
-+ ret = da9063_rtc_start_alarm(dev);
-+ if (ret < 0) {
-+ dev_err(dev, "Failed to start alarm: %d\n", ret);
-+ return ret;
-+ }
-+ }
-+
-+ return ret;
-+}
-+
-+static int da9063_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
-+{
-+ if (enabled)
-+ return da9063_rtc_start_alarm(dev);
-+ else
-+ return da9063_rtc_stop_alarm(dev);
-+}
-+
-+static irqreturn_t da9063_alarm_event(int irq, void *data)
-+{
-+ struct da9063_rtc *rtc = data;
-+
-+ regmap_update_bits(rtc->hw->regmap, DA9063_REG_ALARM_Y,
-+ DA9063_ALARM_ON, 0);
-+
-+ rtc->rtc_sync = true;
-+ rtc_update_irq(rtc->rtc_dev, 1, RTC_IRQF | RTC_AF);
-+
-+ return IRQ_HANDLED;
-+}
-+
-+static const struct rtc_class_ops da9063_rtc_ops = {
-+ .read_time = da9063_rtc_read_time,
-+ .set_time = da9063_rtc_set_time,
-+ .read_alarm = da9063_rtc_read_alarm,
-+ .set_alarm = da9063_rtc_set_alarm,
-+ .alarm_irq_enable = da9063_rtc_alarm_irq_enable,
-+};
-+
-+static int da9063_rtc_probe(struct platform_device *pdev)
-+{
-+ struct da9063 *da9063 = dev_get_drvdata(pdev->dev.parent);
-+ struct da9063_rtc *rtc;
-+ int irq_alarm;
-+ u8 data[RTC_DATA_LEN];
-+ int ret;
-+
-+ ret = regmap_update_bits(da9063->regmap, DA9063_REG_CONTROL_E,
-+ DA9063_RTC_EN, DA9063_RTC_EN);
-+ if (ret < 0) {
-+ dev_err(&pdev->dev, "Failed to enable RTC\n");
-+ goto err;
-+ }
-+
-+ ret = regmap_update_bits(da9063->regmap, DA9063_REG_EN_32K,
-+ DA9063_CRYSTAL, DA9063_CRYSTAL);
-+ if (ret < 0) {
-+ dev_err(&pdev->dev, "Failed to run 32kHz oscillator\n");
-+ goto err;
-+ }
-+
-+ ret = regmap_update_bits(da9063->regmap, DA9063_REG_ALARM_S,
-+ DA9063_ALARM_STATUS_TICK | DA9063_ALARM_STATUS_ALARM,
-+ 0);
-+ if (ret < 0) {
-+ dev_err(&pdev->dev, "Failed to access RTC alarm register\n");
-+ goto err;
-+ }
-+
-+ ret = regmap_update_bits(da9063->regmap, DA9063_REG_ALARM_S,
-+ DA9063_ALARM_STATUS_ALARM,
-+ DA9063_ALARM_STATUS_ALARM);
-+ if (ret < 0) {
-+ dev_err(&pdev->dev, "Failed to access RTC alarm register\n");
-+ goto err;
-+ }
-+
-+ ret = regmap_update_bits(da9063->regmap, DA9063_REG_ALARM_Y,
-+ DA9063_TICK_ON, 0);
-+ if (ret < 0) {
-+ dev_err(&pdev->dev, "Failed to disable TICKs\n");
-+ goto err;
-+ }
-+
-+ ret = regmap_bulk_read(da9063->regmap, DA9063_REG_ALARM_S,
-+ data, RTC_DATA_LEN);
-+ if (ret < 0) {
-+ dev_err(&pdev->dev, "Failed to read initial alarm data: %d\n",
-+ ret);
-+ goto err;
-+ }
-+
-+ rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
-+ if (!rtc)
-+ return -ENOMEM;
-+
-+ platform_set_drvdata(pdev, rtc);
-+
-+ irq_alarm = platform_get_irq_byname(pdev, "ALARM");
-+ ret = devm_request_threaded_irq(&pdev->dev, irq_alarm, NULL,
-+ da9063_alarm_event,
-+ IRQF_TRIGGER_LOW | IRQF_ONESHOT,
-+ "ALARM", rtc);
-+ if (ret) {
-+ dev_err(&pdev->dev, "Failed to request ALARM IRQ %d: %d\n",
-+ irq_alarm, ret);
-+ goto err;
-+ }
-+
-+ rtc->hw = da9063;
-+ rtc->rtc_dev = devm_rtc_device_register(&pdev->dev, DA9063_DRVNAME_RTC,
-+ &da9063_rtc_ops, THIS_MODULE);
-+ if (IS_ERR(rtc->rtc_dev))
-+ return PTR_ERR(rtc->rtc_dev);
-+
-+ da9063_data_to_tm(data, &rtc->alarm_time);
-+ rtc->rtc_sync = false;
-+err:
-+ return ret;
-+}
-+
-+static struct platform_driver da9063_rtc_driver = {
-+ .probe = da9063_rtc_probe,
-+ .driver = {
-+ .name = DA9063_DRVNAME_RTC,
-+ .owner = THIS_MODULE,
-+ },
-+};
-+
-+module_platform_driver(da9063_rtc_driver);
-+
-+MODULE_AUTHOR("S Twiss <stwiss.opensource at diasemi.com>");
-+MODULE_DESCRIPTION("Real time clock device driver for Dialog DA9063");
-+MODULE_LICENSE("GPL v2");
-+MODULE_ALIAS("platform:" DA9063_DRVNAME_RTC);
---
-2.5.0
-
diff --git a/recipes-kernel/linux/linux-ge-3.14/0005-mfd-da9063-Add-support-for-AD-silicon-variant.patch b/recipes-kernel/linux/linux-ge-3.14/0005-mfd-da9063-Add-support-for-AD-silicon-variant.patch
deleted file mode 100644
index 0a7e161..0000000
--- a/recipes-kernel/linux/linux-ge-3.14/0005-mfd-da9063-Add-support-for-AD-silicon-variant.patch
+++ /dev/null
@@ -1,582 +0,0 @@
-From bdc0b750279f006abb80a60b288761e9674c51a3 Mon Sep 17 00:00:00 2001
-From: "Opensource [Steve Twiss]" <stwiss.opensource at diasemi.com>
-Date: Mon, 21 Jul 2014 11:39:33 +0100
-Subject: [PATCH 05/10] mfd: da9063: Add support for AD silicon variant
-
-Add register definitions for DA9063 AD (0x3) silicon variant ID
-the ability to choose the silicon variant at run-time using regmap
-configuration. This patch also adds RTC support for the AD silicon
-changes.
-
-It adds both BB and AD support as regmap ranges and then makes the
-distinction between the two tables at run-time. This allows both AD
-and BB silicon variants to be supported at the same time.
-
-Suggested-by: Philipp Zabel <p.zabel at pengutronix.de>
-Signed-off-by: Opensource [Steve Twiss] <stwiss.opensource at diasemi.com>
-Signed-off-by: Lee Jones <lee.jones at linaro.org>
----
- drivers/mfd/da9063-core.c | 6 +-
- drivers/mfd/da9063-i2c.c | 134 ++++++++++++++++++++++++++++-------
- drivers/rtc/rtc-da9063.c | 54 +++++++++-----
- include/linux/mfd/da9063/core.h | 3 +-
- include/linux/mfd/da9063/registers.h | 129 +++++++++++++++++++++------------
- 5 files changed, 236 insertions(+), 90 deletions(-)
-
-diff --git a/drivers/mfd/da9063-core.c b/drivers/mfd/da9063-core.c
-index e70ae31..93db8bb 100644
---- a/drivers/mfd/da9063-core.c
-+++ b/drivers/mfd/da9063-core.c
-@@ -153,9 +153,9 @@ int da9063_device_init(struct da9063 *da9063, unsigned int irq)
- "Device detected (chip-ID: 0x%02X, var-ID: 0x%02X)\n",
- model, variant_id);
-
-- if (variant_code != PMIC_DA9063_BB) {
-- dev_err(da9063->dev, "Unknown chip variant code: 0x%02X\n",
-- variant_code);
-+ if (variant_code < PMIC_DA9063_BB && variant_code != PMIC_DA9063_AD) {
-+ dev_err(da9063->dev,
-+ "Cannot support variant code: 0x%02X\n", variant_code);
- return -ENODEV;
- }
-
-diff --git a/drivers/mfd/da9063-i2c.c b/drivers/mfd/da9063-i2c.c
-index 8db5c805..21fd8d9 100644
---- a/drivers/mfd/da9063-i2c.c
-+++ b/drivers/mfd/da9063-i2c.c
-@@ -25,10 +25,10 @@
- #include <linux/mfd/da9063/pdata.h>
- #include <linux/mfd/da9063/registers.h>
-
--static const struct regmap_range da9063_readable_ranges[] = {
-+static const struct regmap_range da9063_ad_readable_ranges[] = {
- {
- .range_min = DA9063_REG_PAGE_CON,
-- .range_max = DA9063_REG_SECOND_D,
-+ .range_max = DA9063_AD_REG_SECOND_D,
- }, {
- .range_min = DA9063_REG_SEQ,
- .range_max = DA9063_REG_ID_32_31,
-@@ -37,14 +37,14 @@ static const struct regmap_range da9063_readable_ranges[] = {
- .range_max = DA9063_REG_AUTO3_LOW,
- }, {
- .range_min = DA9063_REG_T_OFFSET,
-- .range_max = DA9063_REG_GP_ID_19,
-+ .range_max = DA9063_AD_REG_GP_ID_19,
- }, {
- .range_min = DA9063_REG_CHIP_ID,
- .range_max = DA9063_REG_CHIP_VARIANT,
- },
- };
-
--static const struct regmap_range da9063_writeable_ranges[] = {
-+static const struct regmap_range da9063_ad_writeable_ranges[] = {
- {
- .range_min = DA9063_REG_PAGE_CON,
- .range_max = DA9063_REG_PAGE_CON,
-@@ -53,7 +53,7 @@ static const struct regmap_range da9063_writeable_ranges[] = {
- .range_max = DA9063_REG_VSYS_MON,
- }, {
- .range_min = DA9063_REG_COUNT_S,
-- .range_max = DA9063_REG_ALARM_Y,
-+ .range_max = DA9063_AD_REG_ALARM_Y,
- }, {
- .range_min = DA9063_REG_SEQ,
- .range_max = DA9063_REG_ID_32_31,
-@@ -62,14 +62,14 @@ static const struct regmap_range da9063_writeable_ranges[] = {
- .range_max = DA9063_REG_AUTO3_LOW,
- }, {
- .range_min = DA9063_REG_CONFIG_I,
-- .range_max = DA9063_REG_MON_REG_4,
-+ .range_max = DA9063_AD_REG_MON_REG_4,
- }, {
-- .range_min = DA9063_REG_GP_ID_0,
-- .range_max = DA9063_REG_GP_ID_19,
-+ .range_min = DA9063_AD_REG_GP_ID_0,
-+ .range_max = DA9063_AD_REG_GP_ID_19,
- },
- };
-
--static const struct regmap_range da9063_volatile_ranges[] = {
-+static const struct regmap_range da9063_ad_volatile_ranges[] = {
- {
- .range_min = DA9063_REG_STATUS_A,
- .range_max = DA9063_REG_EVENT_D,
-@@ -81,26 +81,104 @@ static const struct regmap_range da9063_volatile_ranges[] = {
- .range_max = DA9063_REG_ADC_MAN,
- }, {
- .range_min = DA9063_REG_ADC_RES_L,
-- .range_max = DA9063_REG_SECOND_D,
-+ .range_max = DA9063_AD_REG_SECOND_D,
- }, {
-- .range_min = DA9063_REG_MON_REG_5,
-- .range_max = DA9063_REG_MON_REG_6,
-+ .range_min = DA9063_AD_REG_MON_REG_5,
-+ .range_max = DA9063_AD_REG_MON_REG_6,
- },
- };
-
--static const struct regmap_access_table da9063_readable_table = {
-- .yes_ranges = da9063_readable_ranges,
-- .n_yes_ranges = ARRAY_SIZE(da9063_readable_ranges),
-+static const struct regmap_access_table da9063_ad_readable_table = {
-+ .yes_ranges = da9063_ad_readable_ranges,
-+ .n_yes_ranges = ARRAY_SIZE(da9063_ad_readable_ranges),
- };
-
--static const struct regmap_access_table da9063_writeable_table = {
-- .yes_ranges = da9063_writeable_ranges,
-- .n_yes_ranges = ARRAY_SIZE(da9063_writeable_ranges),
-+static const struct regmap_access_table da9063_ad_writeable_table = {
-+ .yes_ranges = da9063_ad_writeable_ranges,
-+ .n_yes_ranges = ARRAY_SIZE(da9063_ad_writeable_ranges),
- };
-
--static const struct regmap_access_table da9063_volatile_table = {
-- .yes_ranges = da9063_volatile_ranges,
-- .n_yes_ranges = ARRAY_SIZE(da9063_volatile_ranges),
-+static const struct regmap_access_table da9063_ad_volatile_table = {
-+ .yes_ranges = da9063_ad_volatile_ranges,
-+ .n_yes_ranges = ARRAY_SIZE(da9063_ad_volatile_ranges),
-+};
-+
-+static const struct regmap_range da9063_bb_readable_ranges[] = {
-+ {
-+ .range_min = DA9063_REG_PAGE_CON,
-+ .range_max = DA9063_BB_REG_SECOND_D,
-+ }, {
-+ .range_min = DA9063_REG_SEQ,
-+ .range_max = DA9063_REG_ID_32_31,
-+ }, {
-+ .range_min = DA9063_REG_SEQ_A,
-+ .range_max = DA9063_REG_AUTO3_LOW,
-+ }, {
-+ .range_min = DA9063_REG_T_OFFSET,
-+ .range_max = DA9063_BB_REG_GP_ID_19,
-+ }, {
-+ .range_min = DA9063_REG_CHIP_ID,
-+ .range_max = DA9063_REG_CHIP_VARIANT,
-+ },
-+};
-+
-+static const struct regmap_range da9063_bb_writeable_ranges[] = {
-+ {
-+ .range_min = DA9063_REG_PAGE_CON,
-+ .range_max = DA9063_REG_PAGE_CON,
-+ }, {
-+ .range_min = DA9063_REG_FAULT_LOG,
-+ .range_max = DA9063_REG_VSYS_MON,
-+ }, {
-+ .range_min = DA9063_REG_COUNT_S,
-+ .range_max = DA9063_BB_REG_ALARM_Y,
-+ }, {
-+ .range_min = DA9063_REG_SEQ,
-+ .range_max = DA9063_REG_ID_32_31,
-+ }, {
-+ .range_min = DA9063_REG_SEQ_A,
-+ .range_max = DA9063_REG_AUTO3_LOW,
-+ }, {
-+ .range_min = DA9063_REG_CONFIG_I,
-+ .range_max = DA9063_BB_REG_MON_REG_4,
-+ }, {
-+ .range_min = DA9063_BB_REG_GP_ID_0,
-+ .range_max = DA9063_BB_REG_GP_ID_19,
-+ },
-+};
-+
-+static const struct regmap_range da9063_bb_volatile_ranges[] = {
-+ {
-+ .range_min = DA9063_REG_STATUS_A,
-+ .range_max = DA9063_REG_EVENT_D,
-+ }, {
-+ .range_min = DA9063_REG_CONTROL_F,
-+ .range_max = DA9063_REG_CONTROL_F,
-+ }, {
-+ .range_min = DA9063_REG_ADC_MAN,
-+ .range_max = DA9063_REG_ADC_MAN,
-+ }, {
-+ .range_min = DA9063_REG_ADC_RES_L,
-+ .range_max = DA9063_BB_REG_SECOND_D,
-+ }, {
-+ .range_min = DA9063_BB_REG_MON_REG_5,
-+ .range_max = DA9063_BB_REG_MON_REG_6,
-+ },
-+};
-+
-+static const struct regmap_access_table da9063_bb_readable_table = {
-+ .yes_ranges = da9063_bb_readable_ranges,
-+ .n_yes_ranges = ARRAY_SIZE(da9063_bb_readable_ranges),
-+};
-+
-+static const struct regmap_access_table da9063_bb_writeable_table = {
-+ .yes_ranges = da9063_bb_writeable_ranges,
-+ .n_yes_ranges = ARRAY_SIZE(da9063_bb_writeable_ranges),
-+};
-+
-+static const struct regmap_access_table da9063_bb_volatile_table = {
-+ .yes_ranges = da9063_bb_volatile_ranges,
-+ .n_yes_ranges = ARRAY_SIZE(da9063_bb_volatile_ranges),
- };
-
- static const struct regmap_range_cfg da9063_range_cfg[] = {
-@@ -123,10 +201,6 @@ static struct regmap_config da9063_regmap_config = {
- .max_register = DA9063_REG_CHIP_VARIANT,
-
- .cache_type = REGCACHE_RBTREE,
--
-- .rd_table = &da9063_readable_table,
-- .wr_table = &da9063_writeable_table,
-- .volatile_table = &da9063_volatile_table,
- };
-
- static int da9063_i2c_probe(struct i2c_client *i2c,
-@@ -143,6 +217,16 @@ static int da9063_i2c_probe(struct i2c_client *i2c,
- da9063->dev = &i2c->dev;
- da9063->chip_irq = i2c->irq;
-
-+ if (da9063->variant_code == PMIC_DA9063_AD) {
-+ da9063_regmap_config.rd_table = &da9063_ad_readable_table;
-+ da9063_regmap_config.wr_table = &da9063_ad_writeable_table;
-+ da9063_regmap_config.volatile_table = &da9063_ad_volatile_table;
-+ } else {
-+ da9063_regmap_config.rd_table = &da9063_bb_readable_table;
-+ da9063_regmap_config.wr_table = &da9063_bb_writeable_table;
-+ da9063_regmap_config.volatile_table = &da9063_bb_volatile_table;
-+ }
-+
- da9063->regmap = devm_regmap_init_i2c(i2c, &da9063_regmap_config);
- if (IS_ERR(da9063->regmap)) {
- ret = PTR_ERR(da9063->regmap);
-diff --git a/drivers/rtc/rtc-da9063.c b/drivers/rtc/rtc-da9063.c
-index 5953930..731ed1a 100644
---- a/drivers/rtc/rtc-da9063.c
-+++ b/drivers/rtc/rtc-da9063.c
-@@ -29,6 +29,8 @@
- #define YEARS_FROM_DA9063(year) ((year) + 100)
- #define MONTHS_FROM_DA9063(month) ((month) - 1)
-
-+#define RTC_ALARM_DATA_LEN (DA9063_AD_REG_ALARM_Y - DA9063_AD_REG_ALARM_MI + 1)
-+
- #define RTC_DATA_LEN (DA9063_REG_COUNT_Y - DA9063_REG_COUNT_S + 1)
- #define RTC_SEC 0
- #define RTC_MIN 1
-@@ -42,6 +44,10 @@ struct da9063_rtc {
- struct da9063 *hw;
- struct rtc_time alarm_time;
- bool rtc_sync;
-+ int alarm_year;
-+ int alarm_start;
-+ int alarm_len;
-+ int data_start;
- };
-
- static void da9063_data_to_tm(u8 *data, struct rtc_time *tm)
-@@ -83,7 +89,7 @@ static int da9063_rtc_stop_alarm(struct device *dev)
- {
- struct da9063_rtc *rtc = dev_get_drvdata(dev);
-
-- return regmap_update_bits(rtc->hw->regmap, DA9063_REG_ALARM_Y,
-+ return regmap_update_bits(rtc->hw->regmap, rtc->alarm_year,
- DA9063_ALARM_ON, 0);
- }
-
-@@ -91,7 +97,7 @@ static int da9063_rtc_start_alarm(struct device *dev)
- {
- struct da9063_rtc *rtc = dev_get_drvdata(dev);
-
-- return regmap_update_bits(rtc->hw->regmap, DA9063_REG_ALARM_Y,
-+ return regmap_update_bits(rtc->hw->regmap, rtc->alarm_year,
- DA9063_ALARM_ON, DA9063_ALARM_ON);
- }
-
-@@ -151,8 +157,9 @@ static int da9063_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
- int ret;
- unsigned int val;
-
-- ret = regmap_bulk_read(rtc->hw->regmap, DA9063_REG_ALARM_S,
-- &data[RTC_SEC], RTC_DATA_LEN);
-+ data[RTC_SEC] = 0;
-+ ret = regmap_bulk_read(rtc->hw->regmap, rtc->alarm_start,
-+ &data[rtc->data_start], rtc->alarm_len);
- if (ret < 0)
- return ret;
-
-@@ -186,14 +193,14 @@ static int da9063_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
- return ret;
- }
-
-- ret = regmap_bulk_write(rtc->hw->regmap, DA9063_REG_ALARM_S,
-- data, RTC_DATA_LEN);
-+ ret = regmap_bulk_write(rtc->hw->regmap, rtc->alarm_start,
-+ &data[rtc->data_start], rtc->alarm_len);
- if (ret < 0) {
- dev_err(dev, "Failed to write alarm: %d\n", ret);
- return ret;
- }
-
-- rtc->alarm_time = alrm->time;
-+ da9063_data_to_tm(data, &rtc->alarm_time);
-
- if (alrm->enabled) {
- ret = da9063_rtc_start_alarm(dev);
-@@ -218,7 +225,7 @@ static irqreturn_t da9063_alarm_event(int irq, void *data)
- {
- struct da9063_rtc *rtc = data;
-
-- regmap_update_bits(rtc->hw->regmap, DA9063_REG_ALARM_Y,
-+ regmap_update_bits(rtc->hw->regmap, rtc->alarm_year,
- DA9063_ALARM_ON, 0);
-
- rtc->rtc_sync = true;
-@@ -257,7 +264,23 @@ static int da9063_rtc_probe(struct platform_device *pdev)
- goto err;
- }
-
-- ret = regmap_update_bits(da9063->regmap, DA9063_REG_ALARM_S,
-+ rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
-+ if (!rtc)
-+ return -ENOMEM;
-+
-+ if (da9063->variant_code == PMIC_DA9063_AD) {
-+ rtc->alarm_year = DA9063_AD_REG_ALARM_Y;
-+ rtc->alarm_start = DA9063_AD_REG_ALARM_MI;
-+ rtc->alarm_len = RTC_ALARM_DATA_LEN;
-+ rtc->data_start = RTC_MIN;
-+ } else {
-+ rtc->alarm_year = DA9063_BB_REG_ALARM_Y;
-+ rtc->alarm_start = DA9063_BB_REG_ALARM_S;
-+ rtc->alarm_len = RTC_DATA_LEN;
-+ rtc->data_start = RTC_SEC;
-+ }
-+
-+ ret = regmap_update_bits(da9063->regmap, rtc->alarm_start,
- DA9063_ALARM_STATUS_TICK | DA9063_ALARM_STATUS_ALARM,
- 0);
- if (ret < 0) {
-@@ -265,7 +288,7 @@ static int da9063_rtc_probe(struct platform_device *pdev)
- goto err;
- }
-
-- ret = regmap_update_bits(da9063->regmap, DA9063_REG_ALARM_S,
-+ ret = regmap_update_bits(da9063->regmap, rtc->alarm_start,
- DA9063_ALARM_STATUS_ALARM,
- DA9063_ALARM_STATUS_ALARM);
- if (ret < 0) {
-@@ -273,25 +296,22 @@ static int da9063_rtc_probe(struct platform_device *pdev)
- goto err;
- }
-
-- ret = regmap_update_bits(da9063->regmap, DA9063_REG_ALARM_Y,
-+ ret = regmap_update_bits(da9063->regmap, rtc->alarm_year,
- DA9063_TICK_ON, 0);
- if (ret < 0) {
- dev_err(&pdev->dev, "Failed to disable TICKs\n");
- goto err;
- }
-
-- ret = regmap_bulk_read(da9063->regmap, DA9063_REG_ALARM_S,
-- data, RTC_DATA_LEN);
-+ data[RTC_SEC] = 0;
-+ ret = regmap_bulk_read(da9063->regmap, rtc->alarm_start,
-+ &data[rtc->data_start], rtc->alarm_len);
- if (ret < 0) {
- dev_err(&pdev->dev, "Failed to read initial alarm data: %d\n",
- ret);
- goto err;
- }
-
-- rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
-- if (!rtc)
-- return -ENOMEM;
--
- platform_set_drvdata(pdev, rtc);
-
- irq_alarm = platform_get_irq_byname(pdev, "ALARM");
-diff --git a/include/linux/mfd/da9063/core.h b/include/linux/mfd/da9063/core.h
-index 00a9aac..b92a326 100644
---- a/include/linux/mfd/da9063/core.h
-+++ b/include/linux/mfd/da9063/core.h
-@@ -34,7 +34,8 @@ enum da9063_models {
- };
-
- enum da9063_variant_codes {
-- PMIC_DA9063_BB = 0x5
-+ PMIC_DA9063_AD = 0x3,
-+ PMIC_DA9063_BB = 0x5,
- };
-
- /* Interrupts */
-diff --git a/include/linux/mfd/da9063/registers.h b/include/linux/mfd/da9063/registers.h
-index 09a85c6..2e0ba6d5 100644
---- a/include/linux/mfd/da9063/registers.h
-+++ b/include/linux/mfd/da9063/registers.h
-@@ -104,16 +104,27 @@
- #define DA9063_REG_COUNT_D 0x43
- #define DA9063_REG_COUNT_MO 0x44
- #define DA9063_REG_COUNT_Y 0x45
--#define DA9063_REG_ALARM_S 0x46
--#define DA9063_REG_ALARM_MI 0x47
--#define DA9063_REG_ALARM_H 0x48
--#define DA9063_REG_ALARM_D 0x49
--#define DA9063_REG_ALARM_MO 0x4A
--#define DA9063_REG_ALARM_Y 0x4B
--#define DA9063_REG_SECOND_A 0x4C
--#define DA9063_REG_SECOND_B 0x4D
--#define DA9063_REG_SECOND_C 0x4E
--#define DA9063_REG_SECOND_D 0x4F
-+
-+#define DA9063_AD_REG_ALARM_MI 0x46
-+#define DA9063_AD_REG_ALARM_H 0x47
-+#define DA9063_AD_REG_ALARM_D 0x48
-+#define DA9063_AD_REG_ALARM_MO 0x49
-+#define DA9063_AD_REG_ALARM_Y 0x4A
-+#define DA9063_AD_REG_SECOND_A 0x4B
-+#define DA9063_AD_REG_SECOND_B 0x4C
-+#define DA9063_AD_REG_SECOND_C 0x4D
-+#define DA9063_AD_REG_SECOND_D 0x4E
-+
-+#define DA9063_BB_REG_ALARM_S 0x46
-+#define DA9063_BB_REG_ALARM_MI 0x47
-+#define DA9063_BB_REG_ALARM_H 0x48
-+#define DA9063_BB_REG_ALARM_D 0x49
-+#define DA9063_BB_REG_ALARM_MO 0x4A
-+#define DA9063_BB_REG_ALARM_Y 0x4B
-+#define DA9063_BB_REG_SECOND_A 0x4C
-+#define DA9063_BB_REG_SECOND_B 0x4D
-+#define DA9063_BB_REG_SECOND_C 0x4E
-+#define DA9063_BB_REG_SECOND_D 0x4F
-
- /* Sequencer Control Registers */
- #define DA9063_REG_SEQ 0x81
-@@ -223,37 +234,67 @@
- #define DA9063_REG_CONFIG_J 0x10F
- #define DA9063_REG_CONFIG_K 0x110
- #define DA9063_REG_CONFIG_L 0x111
--#define DA9063_REG_CONFIG_M 0x112
--#define DA9063_REG_CONFIG_N 0x113
--
--#define DA9063_REG_MON_REG_1 0x114
--#define DA9063_REG_MON_REG_2 0x115
--#define DA9063_REG_MON_REG_3 0x116
--#define DA9063_REG_MON_REG_4 0x117
--#define DA9063_REG_MON_REG_5 0x11E
--#define DA9063_REG_MON_REG_6 0x11F
--#define DA9063_REG_TRIM_CLDR 0x120
-+
-+#define DA9063_AD_REG_MON_REG_1 0x112
-+#define DA9063_AD_REG_MON_REG_2 0x113
-+#define DA9063_AD_REG_MON_REG_3 0x114
-+#define DA9063_AD_REG_MON_REG_4 0x115
-+#define DA9063_AD_REG_MON_REG_5 0x116
-+#define DA9063_AD_REG_MON_REG_6 0x117
-+#define DA9063_AD_REG_TRIM_CLDR 0x118
-+
-+#define DA9063_AD_REG_GP_ID_0 0x119
-+#define DA9063_AD_REG_GP_ID_1 0x11A
-+#define DA9063_AD_REG_GP_ID_2 0x11B
-+#define DA9063_AD_REG_GP_ID_3 0x11C
-+#define DA9063_AD_REG_GP_ID_4 0x11D
-+#define DA9063_AD_REG_GP_ID_5 0x11E
-+#define DA9063_AD_REG_GP_ID_6 0x11F
-+#define DA9063_AD_REG_GP_ID_7 0x120
-+#define DA9063_AD_REG_GP_ID_8 0x121
-+#define DA9063_AD_REG_GP_ID_9 0x122
-+#define DA9063_AD_REG_GP_ID_10 0x123
-+#define DA9063_AD_REG_GP_ID_11 0x124
-+#define DA9063_AD_REG_GP_ID_12 0x125
-+#define DA9063_AD_REG_GP_ID_13 0x126
-+#define DA9063_AD_REG_GP_ID_14 0x127
-+#define DA9063_AD_REG_GP_ID_15 0x128
-+#define DA9063_AD_REG_GP_ID_16 0x129
-+#define DA9063_AD_REG_GP_ID_17 0x12A
-+#define DA9063_AD_REG_GP_ID_18 0x12B
-+#define DA9063_AD_REG_GP_ID_19 0x12C
-+
-+#define DA9063_BB_REG_CONFIG_M 0x112
-+#define DA9063_BB_REG_CONFIG_N 0x113
-+
-+#define DA9063_BB_REG_MON_REG_1 0x114
-+#define DA9063_BB_REG_MON_REG_2 0x115
-+#define DA9063_BB_REG_MON_REG_3 0x116
-+#define DA9063_BB_REG_MON_REG_4 0x117
-+#define DA9063_BB_REG_MON_REG_5 0x11E
-+#define DA9063_BB_REG_MON_REG_6 0x11F
-+#define DA9063_BB_REG_TRIM_CLDR 0x120
- /* General Purpose Registers */
--#define DA9063_REG_GP_ID_0 0x121
--#define DA9063_REG_GP_ID_1 0x122
--#define DA9063_REG_GP_ID_2 0x123
--#define DA9063_REG_GP_ID_3 0x124
--#define DA9063_REG_GP_ID_4 0x125
--#define DA9063_REG_GP_ID_5 0x126
--#define DA9063_REG_GP_ID_6 0x127
--#define DA9063_REG_GP_ID_7 0x128
--#define DA9063_REG_GP_ID_8 0x129
--#define DA9063_REG_GP_ID_9 0x12A
--#define DA9063_REG_GP_ID_10 0x12B
--#define DA9063_REG_GP_ID_11 0x12C
--#define DA9063_REG_GP_ID_12 0x12D
--#define DA9063_REG_GP_ID_13 0x12E
--#define DA9063_REG_GP_ID_14 0x12F
--#define DA9063_REG_GP_ID_15 0x130
--#define DA9063_REG_GP_ID_16 0x131
--#define DA9063_REG_GP_ID_17 0x132
--#define DA9063_REG_GP_ID_18 0x133
--#define DA9063_REG_GP_ID_19 0x134
-+#define DA9063_BB_REG_GP_ID_0 0x121
-+#define DA9063_BB_REG_GP_ID_1 0x122
-+#define DA9063_BB_REG_GP_ID_2 0x123
-+#define DA9063_BB_REG_GP_ID_3 0x124
-+#define DA9063_BB_REG_GP_ID_4 0x125
-+#define DA9063_BB_REG_GP_ID_5 0x126
-+#define DA9063_BB_REG_GP_ID_6 0x127
-+#define DA9063_BB_REG_GP_ID_7 0x128
-+#define DA9063_BB_REG_GP_ID_8 0x129
-+#define DA9063_BB_REG_GP_ID_9 0x12A
-+#define DA9063_BB_REG_GP_ID_10 0x12B
-+#define DA9063_BB_REG_GP_ID_11 0x12C
-+#define DA9063_BB_REG_GP_ID_12 0x12D
-+#define DA9063_BB_REG_GP_ID_13 0x12E
-+#define DA9063_BB_REG_GP_ID_14 0x12F
-+#define DA9063_BB_REG_GP_ID_15 0x130
-+#define DA9063_BB_REG_GP_ID_16 0x131
-+#define DA9063_BB_REG_GP_ID_17 0x132
-+#define DA9063_BB_REG_GP_ID_18 0x133
-+#define DA9063_BB_REG_GP_ID_19 0x134
-
- /* Chip ID and variant */
- #define DA9063_REG_CHIP_ID 0x181
-@@ -404,10 +445,10 @@
- /* DA9063_REG_CONTROL_B (addr=0x0F) */
- #define DA9063_CHG_SEL 0x01
- #define DA9063_WATCHDOG_PD 0x02
--#define DA9063_RESET_BLINKING 0x04
-+#define DA9063_BB_RESET_BLINKING 0x04
- #define DA9063_NRES_MODE 0x08
- #define DA9063_NONKEY_LOCK 0x10
--#define DA9063_BUCK_SLOWSTART 0x80
-+#define DA9063_BB_BUCK_SLOWSTART 0x80
-
- /* DA9063_REG_CONTROL_C (addr=0x10) */
- #define DA9063_DEBOUNCING_MASK 0x07
-@@ -467,7 +508,7 @@
- #define DA9063_GPADC_PAUSE 0x02
- #define DA9063_PMIF_DIS 0x04
- #define DA9063_HS2WIRE_DIS 0x08
--#define DA9063_CLDR_PAUSE 0x10
-+#define DA9063_BB_CLDR_PAUSE 0x10
- #define DA9063_BBAT_DIS 0x20
- #define DA9063_OUT_32K_PAUSE 0x40
- #define DA9063_PMCONT_DIS 0x80
-@@ -844,7 +885,7 @@
- #define DA9063_MONITOR 0x40
-
- /* DA9063_REG_ALARM_S (addr=0x46) */
--#define DA9063_ALARM_S_MASK 0x3F
-+#define DA9063_BB_ALARM_S_MASK 0x3F
- #define DA9063_ALARM_STATUS_ALARM 0x80
- #define DA9063_ALARM_STATUS_TICK 0x40
- /* DA9063_REG_ALARM_MI (addr=0x47) */
---
-2.5.0
-
diff --git a/recipes-kernel/linux/linux-ge-3.14/0006-mfd-da9063-Get-irq-base-dynamically-before-registeri.patch b/recipes-kernel/linux/linux-ge-3.14/0006-mfd-da9063-Get-irq-base-dynamically-before-registeri.patch
deleted file mode 100644
index 4870138..0000000
--- a/recipes-kernel/linux/linux-ge-3.14/0006-mfd-da9063-Get-irq-base-dynamically-before-registeri.patch
+++ /dev/null
@@ -1,42 +0,0 @@
-From f996ed516921512ab7a13db776f66420e07e6b90 Mon Sep 17 00:00:00 2001
-From: Dmitry Lavnikevich <d.lavnikevich at sam-solutions.com>
-Date: Fri, 21 Nov 2014 18:29:07 +0300
-Subject: [PATCH 06/10] mfd: da9063: Get irq base dynamically before
- registering device
-
-After registering mfd device with proper irq_base
-platform_get_irq_byname() calls will return VIRQ instead of local IRQ.
-This fixes da9063 rtc registration issue:
-da9063-rtc da9063-rtc: Failed to request ALARM IRQ 1: -22
-
-Signed-off-by: Dmitry Lavnikevich <d.lavnikevich at sam-solutions.com>
-Signed-off-by: Lee Jones <lee.jones at linaro.org>
----
- drivers/mfd/da9063-core.c | 4 +++-
- 1 file changed, 3 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/mfd/da9063-core.c b/drivers/mfd/da9063-core.c
-index 93db8bb..f38bc98 100644
---- a/drivers/mfd/da9063-core.c
-+++ b/drivers/mfd/da9063-core.c
-@@ -118,7 +118,7 @@ int da9063_device_init(struct da9063 *da9063, unsigned int irq)
- da9063->irq_base = pdata->irq_base;
- } else {
- da9063->flags = 0;
-- da9063->irq_base = 0;
-+ da9063->irq_base = -1;
- }
- da9063->chip_irq = irq;
-
-@@ -168,6 +168,8 @@ int da9063_device_init(struct da9063 *da9063, unsigned int irq)
- return ret;
- }
-
-+ da9063->irq_base = regmap_irq_chip_get_base(da9063->regmap_irq);
-+
- ret = mfd_add_devices(da9063->dev, -1, da9063_devs,
- ARRAY_SIZE(da9063_devs), NULL, da9063->irq_base,
- NULL);
---
-2.5.0
-
diff --git a/recipes-kernel/linux/linux-ge-3.14/0007-mfd-da9063-Add-support-for-OnKey-driver.patch b/recipes-kernel/linux/linux-ge-3.14/0007-mfd-da9063-Add-support-for-OnKey-driver.patch
deleted file mode 100644
index b5b9216..0000000
--- a/recipes-kernel/linux/linux-ge-3.14/0007-mfd-da9063-Add-support-for-OnKey-driver.patch
+++ /dev/null
@@ -1,114 +0,0 @@
-From 9d4ceb72253709f7ae6fe02b65eed40053a94902 Mon Sep 17 00:00:00 2001
-From: Steve Twiss <stwiss.opensource at diasemi.com>
-Date: Tue, 19 May 2015 11:32:45 +0100
-Subject: [PATCH 07/10] mfd: da9063: Add support for OnKey driver
-
-Add MFD support for the DA9063 OnKey driver
-
-The function da9063_clear_fault_log() is added to mitigate the case of a
-hardware power-cut after a long-long OnKey press. Although there is no
-software intervention in this case (by definition) such a shutdown would
-cause persistent information within the DA9063 FAULT_LOG that would be
-available during the next device restart.
-
-Clearance of this persistent register must be completed after such a
-hardware power-cut operation has happened so that the FAULT_LOG does not
-continue with previous values. The clearance function has been added here
-in the kernel driver because wiping the fault-log cannot be counted on
-outside the Linux kernel.
-
-Signed-off-by: Steve Twiss <stwiss.opensource at diasemi.com>
-[Lee: Removed 'key_power' for Dmitry to take through the Input Tree]
-Signed-off-by: Lee Jones <lee.jones at linaro.org>
----
- drivers/mfd/da9063-core.c | 54 +++++++++++++++++++++++++++++++++++++++++++++++
- 1 file changed, 54 insertions(+)
-
-diff --git a/drivers/mfd/da9063-core.c b/drivers/mfd/da9063-core.c
-index f38bc98..141c2df 100644
---- a/drivers/mfd/da9063-core.c
-+++ b/drivers/mfd/da9063-core.c
-@@ -60,6 +60,7 @@ static struct resource da9063_rtc_resources[] = {
-
- static struct resource da9063_onkey_resources[] = {
- {
-+ .name = "ONKEY",
- .start = DA9063_IRQ_ONKEY,
- .end = DA9063_IRQ_ONKEY,
- .flags = IORESOURCE_IRQ,
-@@ -96,6 +97,7 @@ static const struct mfd_cell da9063_devs[] = {
- .name = DA9063_DRVNAME_ONKEY,
- .num_resources = ARRAY_SIZE(da9063_onkey_resources),
- .resources = da9063_onkey_resources,
-+ .of_compatible = "dlg,da9063-onkey",
- },
- {
- .name = DA9063_DRVNAME_RTC,
-@@ -107,12 +109,64 @@ static const struct mfd_cell da9063_devs[] = {
- },
- };
-
-+static int da9063_clear_fault_log(struct da9063 *da9063)
-+{
-+ int ret = 0;
-+ int fault_log = 0;
-+
-+ ret = regmap_read(da9063->regmap, DA9063_REG_FAULT_LOG, &fault_log);
-+ if (ret < 0) {
-+ dev_err(da9063->dev, "Cannot read FAULT_LOG.\n");
-+ return -EIO;
-+ }
-+
-+ if (fault_log) {
-+ if (fault_log & DA9063_TWD_ERROR)
-+ dev_dbg(da9063->dev,
-+ "Fault log entry detected: DA9063_TWD_ERROR\n");
-+ if (fault_log & DA9063_POR)
-+ dev_dbg(da9063->dev,
-+ "Fault log entry detected: DA9063_POR\n");
-+ if (fault_log & DA9063_VDD_FAULT)
-+ dev_dbg(da9063->dev,
-+ "Fault log entry detected: DA9063_VDD_FAULT\n");
-+ if (fault_log & DA9063_VDD_START)
-+ dev_dbg(da9063->dev,
-+ "Fault log entry detected: DA9063_VDD_START\n");
-+ if (fault_log & DA9063_TEMP_CRIT)
-+ dev_dbg(da9063->dev,
-+ "Fault log entry detected: DA9063_TEMP_CRIT\n");
-+ if (fault_log & DA9063_KEY_RESET)
-+ dev_dbg(da9063->dev,
-+ "Fault log entry detected: DA9063_KEY_RESET\n");
-+ if (fault_log & DA9063_NSHUTDOWN)
-+ dev_dbg(da9063->dev,
-+ "Fault log entry detected: DA9063_NSHUTDOWN\n");
-+ if (fault_log & DA9063_WAIT_SHUT)
-+ dev_dbg(da9063->dev,
-+ "Fault log entry detected: DA9063_WAIT_SHUT\n");
-+ }
-+
-+ ret = regmap_write(da9063->regmap,
-+ DA9063_REG_FAULT_LOG,
-+ fault_log);
-+ if (ret < 0)
-+ dev_err(da9063->dev,
-+ "Cannot reset FAULT_LOG values %d\n", ret);
-+
-+ return ret;
-+}
-+
- int da9063_device_init(struct da9063 *da9063, unsigned int irq)
- {
- struct da9063_pdata *pdata = da9063->dev->platform_data;
- int model, variant_id, variant_code;
- int ret;
-
-+ ret = da9063_clear_fault_log(da9063);
-+ if (ret < 0)
-+ dev_err(da9063->dev, "Cannot clear fault log\n");
-+
- if (pdata) {
- da9063->flags = pdata->flags;
- da9063->irq_base = pdata->irq_base;
---
-2.5.0
-
diff --git a/recipes-kernel/linux/linux-ge-3.14/0008-ahci_imx-Make-receive-DPLL-mode-configurable.patch b/recipes-kernel/linux/linux-ge-3.14/0008-ahci_imx-Make-receive-DPLL-mode-configurable.patch
deleted file mode 100644
index 6d39784..0000000
--- a/recipes-kernel/linux/linux-ge-3.14/0008-ahci_imx-Make-receive-DPLL-mode-configurable.patch
+++ /dev/null
@@ -1,51 +0,0 @@
-From 50473c9e2f1db391699e3240a05215ccdb4e81aa Mon Sep 17 00:00:00 2001
-From: Justin Waters <justin.waters at timesys.com>
-Date: Wed, 2 Mar 2016 11:47:13 -0500
-Subject: [PATCH 08/10] ahci_imx: Make receive DPLL mode configurable
-
-Signed-off-by: Justin Waters <justin.waters at timesys.com>
----
- drivers/ata/ahci_imx.c | 13 ++++++++++++-
- 1 file changed, 12 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/ata/ahci_imx.c b/drivers/ata/ahci_imx.c
-index 69422dc..176ca1f 100644
---- a/drivers/ata/ahci_imx.c
-+++ b/drivers/ata/ahci_imx.c
-@@ -475,6 +475,13 @@ static const struct reg_value gpr13_rx_eq[] = {
- { 4000, IMX6Q_GPR13_SATA_RX_EQ_VAL_4_0_DB },
- };
-
-+static const struct reg_value gpr13_rx_dpll[] = {
-+ { 0, IMX6Q_GPR13_SATA_RX_DPLL_MODE_1P_1F },
-+ { 1, IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_2F },
-+ { 2, IMX6Q_GPR13_SATA_RX_DPLL_MODE_1P_4F },
-+ { 3, IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F },
-+};
-+
- static const struct reg_property gpr13_props[] = {
- {
- .name = "fsl,transmit-level-mV",
-@@ -500,6 +507,11 @@ static const struct reg_property gpr13_props[] = {
- .name = "fsl,no-spread-spectrum",
- .def_value = IMX6Q_GPR13_SATA_MPLL_SS_EN,
- .set_value = 0,
-+ }, {
-+ .name = "fsl,receive-dpll-mode",
-+ .values = gpr13_rx_dpll,
-+ .num_values = ARRAY_SIZE(gpr13_rx_dpll),
-+ .def_value = IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F,
- },
- };
-
-@@ -603,7 +615,6 @@ static int imx_ahci_probe(struct platform_device *pdev)
-
- imxpriv->phy_params =
- IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M |
-- IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F |
- IMX6Q_GPR13_SATA_SPD_MODE_3P0G |
- reg_value;
- }
---
-2.5.0
-
diff --git a/recipes-kernel/linux/linux-ge-3.14/0009-PCI-imx6-Add-DT-bindings-to-configure-PHY-Tx-driver-.patch b/recipes-kernel/linux/linux-ge-3.14/0009-PCI-imx6-Add-DT-bindings-to-configure-PHY-Tx-driver-.patch
deleted file mode 100644
index ef12179..0000000
--- a/recipes-kernel/linux/linux-ge-3.14/0009-PCI-imx6-Add-DT-bindings-to-configure-PHY-Tx-driver-.patch
+++ /dev/null
@@ -1,112 +0,0 @@
-From 4227f47441830cf8f639ae7875dc64ced854b068 Mon Sep 17 00:00:00 2001
-From: Justin Waters <justin.waters at timesys.com>
-Date: Fri, 15 Jan 2016 10:24:35 -0500
-Subject: [PATCH 09/10] PCI: imx6: Add DT bindings to configure PHY Tx driver
- settings
-
-The settings in GPR8 are dependent upon the particular layout of the
-hardware platform. As such, they should be configurable via the device
-tree.
-
-Look up PHY Tx driver settings from the device tree. Fall back to the
-original hard-coded values if they are not specified in the device tree.
-
-Signed-off-by: Justin Waters <justin.waters at timesys.com>
-Signed-off-by: Bjorn Helgaas <bhelgaas at google.com>
-Acked-by: Lucas Stach <l.stach at pengutronix.de>
----
- .../devicetree/bindings/pci/fsl,imx6q-pcie.txt | 7 ++++
- drivers/pci/host/pci-imx6.c | 41 +++++++++++++++++++---
- 2 files changed, 43 insertions(+), 5 deletions(-)
-
-diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
-index ad81179..e2f26ff 100644
---- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
-+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
-@@ -19,6 +19,13 @@ Additional required properties for imx6sx-pcie:
- - power supplies:
- - pcie-phy-supply: regulator used to power the PCIe PHY
-
-+Optional properties:
-+- fsl,tx-deemph-gen1: Gen1 De-emphasis value. Default: 20
-+- fsl,tx-deemph-gen2-3p5db: Gen2 (3.5db) De-emphasis value. Default: 20
-+- fsl,tx-deemph-gen2-6db: Gen2 (6db) De-emphasis value. Default: 20
-+- fsl,tx-swing-full: Gen2 TX SWING FULL value. Default: 115
-+- fsl,tx-swing-low: TX launch amplitude swing_low value. Default: 115
-+
- Example:
-
- pcie at 0x01000000 {
-diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c
-index e48091f..cfc51fb 100644
---- a/drivers/pci/host/pci-imx6.c
-+++ b/drivers/pci/host/pci-imx6.c
-@@ -58,6 +58,11 @@ struct imx6_pcie {
- struct regmap *iomuxc_gpr;
- struct regmap *reg_src;
- struct regulator *pcie_phy_regulator;
-+ u32 tx_deemph_gen1;
-+ u32 tx_deemph_gen2_3p5db;
-+ u32 tx_deemph_gen2_6db;
-+ u32 tx_swing_full;
-+ u32 tx_swing_low;
- };
-
- /* PCIe Root Complex registers (memory-mapped) */
-@@ -522,15 +527,20 @@ static int imx6_pcie_init_phy(struct pcie_port *pp)
- IMX6Q_GPR12_LOS_LEVEL, IMX6Q_GPR12_LOS_LEVEL_9);
-
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
-- IMX6Q_GPR8_TX_DEEMPH_GEN1, 20 << 0);
-+ IMX6Q_GPR8_TX_DEEMPH_GEN1,
-+ imx6_pcie->tx_deemph_gen1 << 0);
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
-- IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB, 20 << 6);
-+ IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB,
-+ imx6_pcie->tx_deemph_gen2_3p5db << 6);
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
-- IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB, 20 << 12);
-+ IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB,
-+ imx6_pcie->tx_deemph_gen2_6db << 12);
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
-- IMX6Q_GPR8_TX_SWING_FULL, 115 << 18);
-+ IMX6Q_GPR8_TX_SWING_FULL,
-+ imx6_pcie->tx_swing_full << 18);
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
-- IMX6Q_GPR8_TX_SWING_LOW, 115 << 25);
-+ IMX6Q_GPR8_TX_SWING_LOW,
-+ imx6_pcie->tx_swing_low << 25);
- }
-
- return 0;
-@@ -1320,6 +1330,27 @@ static int __init imx6_pcie_probe(struct platform_device *pdev)
- return PTR_ERR(imx6_pcie->iomuxc_gpr);
- }
-
-+ /* Grab PCIe PHY Tx Settings */
-+ if (of_property_read_u32(np, "fsl,tx-deemph-gen1",
-+ &imx6_pcie->tx_deemph_gen1))
-+ imx6_pcie->tx_deemph_gen1 = 20;
-+
-+ if (of_property_read_u32(np, "fsl,tx-deemph-gen2-3p5db",
-+ &imx6_pcie->tx_deemph_gen2_3p5db))
-+ imx6_pcie->tx_deemph_gen2_3p5db = 20;
-+
-+ if (of_property_read_u32(np, "fsl,tx-deemph-gen2-6db",
-+ &imx6_pcie->tx_deemph_gen2_6db))
-+ imx6_pcie->tx_deemph_gen2_6db = 20;
-+
-+ if (of_property_read_u32(np, "fsl,tx-swing-full",
-+ &imx6_pcie->tx_swing_full))
-+ imx6_pcie->tx_swing_full = 115;
-+
-+ if (of_property_read_u32(np, "fsl,tx-swing-low",
-+ &imx6_pcie->tx_swing_low))
-+ imx6_pcie->tx_swing_low = 115;
-+
- if (IS_ENABLED(CONFIG_EP_MODE_IN_EP_RC_SYS)) {
- int i;
- void *test_reg1, *test_reg2;
---
-2.5.0
-
diff --git a/recipes-kernel/linux/linux-ge-3.14/0010-ARM-dts-imx-Add-support-for-Advantech-GE-ELO.patch b/recipes-kernel/linux/linux-ge-3.14/0010-ARM-dts-imx-Add-support-for-Advantech-GE-ELO.patch
deleted file mode 100644
index d0b56ef..0000000
--- a/recipes-kernel/linux/linux-ge-3.14/0010-ARM-dts-imx-Add-support-for-Advantech-GE-ELO.patch
+++ /dev/null
@@ -1,817 +0,0 @@
-From 382cafd78e69c6e6a51a8908d3fa787779791e64 Mon Sep 17 00:00:00 2001
-From: Justin Waters <justin.waters at timesys.com>
-Date: Fri, 12 Dec 2014 17:12:24 -0500
-Subject: [PATCH 10/10] ARM: dts: imx: Add support for Advantech/GE ELO
-
-Add support for the Advantech/GE ELO Board.
-
-Signed-off-by: Justin Waters <justin.waters at timesys.com>
----
- arch/arm/boot/dts/imx6q-elo.dts | 795 ++++++++++++++++++++++++++++++++++++++++
- 1 file changed, 795 insertions(+)
- create mode 100644 arch/arm/boot/dts/imx6q-elo.dts
-
-diff --git a/arch/arm/boot/dts/imx6q-elo.dts b/arch/arm/boot/dts/imx6q-elo.dts
-new file mode 100644
-index 0000000..7442e2c
---- /dev/null
-+++ b/arch/arm/boot/dts/imx6q-elo.dts
-@@ -0,0 +1,795 @@
-+/*
-+ * Copyright 2016 Timesys Corporation
-+ * Copyright 2016 General Electric Company
-+ *
-+ * The code contained herein is licensed under the GNU General Public
-+ * License. You may obtain a copy of the GNU General Public License
-+ * Version 2 or later at the following locations:
-+ *
-+ * http://www.opensource.org/licenses/gpl-license.html
-+ * http://www.gnu.org/copyleft/gpl.html
-+ */
-+
-+/dts-v1/;
-+
-+#include "imx6q.dtsi"
-+
-+/ {
-+ model = "General Electric ELO";
-+ compatible = "fsl,imx6q-elo", "fsl,imx6q";
-+
-+ aliases {
-+ mxcfb0 = &mxcfb1;
-+ mxcfb1 = &mxcfb2;
-+ mmc0 = &usdhc2;
-+ mmc1 = &usdhc3;
-+ mmc2 = &usdhc4;
-+ };
-+
-+ memory {
-+ reg = <0x10000000 0x40000000>;
-+ };
-+
-+ clocks {
-+ clk24m: clk24m {
-+ compatible = "fixed-clock";
-+ #clock-cells = <0>;
-+ clock-frequency = <24000000>;
-+ };
-+ };
-+
-+ regulators {
-+ compatible = "simple-bus";
-+
-+ reg_usb_otg_vbus: usb_otg_vbus {
-+ compatible = "regulator-fixed";
-+ regulator-name = "usb_otg_vbus";
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ };
-+
-+ reg_usb_h1_vbus: usb_h1_vbus {
-+ compatible = "regulator-fixed";
-+ regulator-name = "usb_h1_vbus";
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ };
-+
-+ reg_1p8v: 1p8v {
-+ compatible = "regulator-fixed";
-+ regulator-name = "1P8V";
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ regulator-always-on;
-+ };
-+
-+ reg_3p3v: 3p3v {
-+ compatible = "regulator-fixed";
-+ regulator-name = "3P3V";
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ regulator-always-on;
-+ };
-+
-+ reg_lvds: regulator-lvds {
-+ compatible = "regulator-fixed";
-+ regulator-name = "lvds_ppen";
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ regulator-boot-on;
-+ gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
-+ enable-active-high;
-+ };
-+ };
-+
-+ sound {
-+ compatible = "fsl,imx6q-ba16-sgtl5000",
-+ "fsl,imx-audio-sgtl5000";
-+ model = "imx6q-ba16-sgtl5000";
-+ cpu-dai = <&ssi1>;
-+ audio-codec = <&codec>;
-+ audio-routing =
-+ "MIC_IN", "Mic Jack",
-+ "Mic Jack", "Mic Bias",
-+ "Headphone Jack", "HP_OUT";
-+ mux-int-port = <1>;
-+ mux-ext-port = <4>;
-+ };
-+
-+ sound-hdmi {
-+ compatible = "fsl,imx6q-audio-hdmi",
-+ "fsl,imx-audio-hdmi"; model = "imx-audio-hdmi";
-+ hdmi-controller = <&hdmi_audio>;
-+ };
-+
-+ mxcfb1: fb at 0 {
-+ compatible = "fsl,mxc_sdc_fb";
-+ disp_dev = "ldb";
-+ interface_pix_fmt = "RGB24";
-+ default_bpp = <32>;
-+ int_clk = <0>;
-+ late_init = <0>;
-+ status = "okay";
-+ };
-+
-+ mxcfb2: fb at 1 {
-+ compatible = "fsl,mxc_sdc_fb";
-+ disp_dev = "hdmi";
-+ interface_pix_fmt = "RGB24";
-+ mode_str ="1920x1080M at 60";
-+ default_bpp = <24>;
-+ int_clk = <0>;
-+ late_init = <0>;
-+ status = "okay";
-+ };
-+
-+ backlight {
-+ compatible = "pwm-backlight";
-+ pwms = <&pwm1 0 5000000>;
-+ brightness-levels = < 0 1 2 3 4 5 6 7 8 9
-+ 10 11 12 13 14 15 16 17 18 19
-+ 20 21 22 23 24 25 26 27 28 29
-+ 30 31 32 33 34 35 36 37 38 39
-+ 40 41 42 43 44 45 46 47 48 49
-+ 50 51 52 53 54 55 56 57 58 59
-+ 60 61 62 63 64 65 66 67 68 69
-+ 70 71 72 73 74 75 76 77 78 79
-+ 80 81 82 83 84 85 86 87 88 89
-+ 90 91 92 93 94 95 96 97 98 99
-+ 100 101 102 103 104 105 106 107 108 109
-+ 110 111 112 113 114 115 116 117 118 119
-+ 120 121 122 123 124 125 126 127 128 129
-+ 130 131 132 133 134 135 136 137 138 139
-+ 140 141 142 143 144 145 146 147 148 149
-+ 150 151 152 153 154 155 156 157 158 159
-+ 160 161 162 163 164 165 166 167 168 169
-+ 170 171 172 173 174 175 176 177 178 179
-+ 180 181 182 183 184 185 186 187 188 189
-+ 190 191 192 193 194 195 196 197 198 199
-+ 200 201 202 203 204 205 206 207 208 209
-+ 210 211 212 213 214 215 216 217 218 219
-+ 220 221 222 223 224 225 226 227 228 229
-+ 230 231 232 233 234 235 236 237 238 239
-+ 240 241 242 243 244 245 246 247 248 249
-+ 250 251 252 253 254 255>;
-+ default-brightness-level = <255>;
-+ power-supply = <®_lvds>;
-+ enable-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
-+ };
-+
-+ v4l2_out {
-+ compatible = "fsl,mxc_v4l2_output";
-+ status = "okay";
-+ };
-+};
-+
-+&audmux {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_audmux>;
-+ status = "okay";
-+};
-+
-+&clks {
-+ fsl,ldb-di0-parent = <&clks IMX6QDL_CLK_PLL2_PFD0_352M>;
-+ fsl,ldb-di1-parent = <&clks IMX6QDL_CLK_PLL2_PFD0_352M>;
-+};
-+
-+&ecspi1 {
-+ fsl,spi-num-chipselects = <1>;
-+ cs-gpios = <&gpio2 30 0>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_ecspi1>;
-+ status = "okay";
-+
-+ flash: n25q032 at 0 {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ compatible = "st,n25q032";
-+ spi-max-frequency = <20000000>;
-+ reg = <0>;
-+ partition at 0 {
-+ label = "U-Boot";
-+ reg = <0x0 0xC0000>;
-+ };
-+ partition at C0000 {
-+ label = "env";
-+ reg = <0xC0000 0x10000>;
-+ };
-+ partition at D0000 {
-+ label = "spare";
-+ reg = <0xD0000 0x130000>;
-+ };
-+ };
-+};
-+
-+&ecspi5 {
-+ fsl,spi-num-chipselects = <1>;
-+ cs-gpios = <&gpio1 17 0>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_ecspi5>;
-+ status = "okay";
-+
-+ m25_eeprom: m25p80 at 0 {
-+ compatible = "atmel,at25";
-+ spi-max-frequency = <20000000>;
-+ size = <0x8000>;
-+ pagesize = <64>;
-+ reg = <0>;
-+ address-width = <16>;
-+ };
-+};
-+
-+&fec {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_enet>;
-+ phy-mode = "rgmii";
-+ status = "okay";
-+};
-+
-+&cpu0 {
-+ arm-supply = <®_arm>;
-+ soc-supply = <®_soc>;
-+ pu-supply = <®_pu>;
-+};
-+
-+&dcic1 {
-+ dcic_id = <0>;
-+ dcic_mux = "dcic-hdmi";
-+ status = "okay";
-+};
-+
-+&dcic2 {
-+ dcic_id = <1>;
-+ dcic_mux = "dcic-lvds1";
-+ status = "okay";
-+};
-+
-+
-+&gpc {
-+ fsl,cpu_pupscr_sw2iso = <0xf>;
-+ fsl,cpu_pupscr_sw = <0xf>;
-+ fsl,cpu_pdnscr_iso2sw = <0x1>;
-+ fsl,cpu_pdnscr_iso = <0x1>;
-+ fsl,ldo-bypass = <0>;
-+ fsl,wdog-reset = <1>; /* watchdog select of reset source */
-+ pu-supply = <®_pu>;
-+};
-+
-+&hdmi_audio {
-+ status = "okay";
-+};
-+
-+&hdmi_cec {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_hdmi_cec>;
-+ status = "okay";
-+};
-+
-+&hdmi_core {
-+ ipu_id = <1>;
-+ disp_id = <0>;
-+ status = "okay";
-+};
-+
-+&hdmi_video {
-+ fsl,phy_reg_vlev = <0x01ad>;
-+ fsl,phy_reg_cksymtx = <0x800d>;
-+ status = "okay";
-+};
-+
-+&i2c1 {
-+ clock-frequency = <100000>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_i2c1>;
-+ status = "okay";
-+
-+ codec: sgtl5000 at 0a {
-+ compatible = "fsl,sgtl5000";
-+ reg = <0x0a>;
-+ clocks = <&clks 201>;
-+ VDDA-supply = <®_1p8v>;
-+ VDDIO-supply = <®_3p3v>;
-+ };
-+};
-+
-+&i2c2 {
-+ clock-frequency = <100000>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_i2c2>;
-+ status = "okay";
-+
-+ hdmi: edid at 50 {
-+ compatible = "fsl,imx6-hdmi-i2c";
-+ reg = <0x50>;
-+ };
-+};
-+
-+&i2c3 {
-+ clock-frequency = <100000>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_i2c3>;
-+ status = "okay";
-+
-+ pmic at 58 {
-+ compatible = "dialog,da9063";
-+ reg = <0x58>;
-+ interrupt-parent = <&gpio7>;
-+ interrupts = <13 0x8>; /* active-low GPIO7_13 */
-+
-+ regulators {
-+ bcore1 {
-+ regulator-min-microvolt = <1420000>;
-+ regulator-max-microvolt = <1420000>;
-+ regulator-always-on;
-+ regulator-boot-on;
-+ };
-+
-+ bcore2 {
-+ regulator-min-microvolt = <1420000>;
-+ regulator-max-microvolt = <1420000>;
-+ regulator-always-on;
-+ regulator-boot-on;
-+ };
-+
-+ bpro {
-+ regulator-min-microvolt = <1500000>;
-+ regulator-max-microvolt = <1500000>;
-+ regulator-always-on;
-+ regulator-boot-on;
-+ };
-+
-+ bmem {
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ regulator-always-on;
-+ regulator-boot-on;
-+ };
-+
-+ bio: bio {
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ regulator-always-on;
-+ regulator-boot-on;
-+ };
-+
-+ bperi: bperi {
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ regulator-always-on;
-+ regulator-boot-on;
-+ };
-+
-+ ldo1 {
-+ regulator-min-microvolt = <600000>;
-+ regulator-max-microvolt = <1860000>;
-+ };
-+
-+ ldo2 {
-+ regulator-min-microvolt = <600000>;
-+ regulator-max-microvolt = <1860000>;
-+ };
-+
-+ ldo3 {
-+ regulator-min-microvolt = <900000>;
-+ regulator-max-microvolt = <3440000>;
-+ };
-+
-+ ldo4 {
-+ regulator-min-microvolt = <900000>;
-+ regulator-max-microvolt = <3440000>;
-+ };
-+
-+ ldo5 {
-+ regulator-min-microvolt = <900000>;
-+ regulator-max-microvolt = <3600000>;
-+ regulator-always-on;
-+ regulator-boot-on;
-+ };
-+
-+ ldo6 {
-+ regulator-min-microvolt = <900000>;
-+ regulator-max-microvolt = <3600000>;
-+ regulator-always-on;
-+ regulator-boot-on;
-+ };
-+
-+ ldo7 {
-+ regulator-min-microvolt = <900000>;
-+ regulator-max-microvolt = <3600000>;
-+ regulator-always-on;
-+ regulator-boot-on;
-+ };
-+
-+ ldo8 {
-+ regulator-min-microvolt = <900000>;
-+ regulator-max-microvolt = <3600000>;
-+ regulator-always-on;
-+ regulator-boot-on;
-+ };
-+
-+ ldo9 {
-+ regulator-min-microvolt = <950000>;
-+ regulator-max-microvolt = <3600000>;
-+ regulator-always-on;
-+ regulator-boot-on;
-+ };
-+
-+ ldo10 {
-+ regulator-min-microvolt = <900000>;
-+ regulator-max-microvolt = <3600000>;
-+ regulator-always-on;
-+ regulator-boot-on;
-+ };
-+
-+ ldo11 {
-+ regulator-min-microvolt = <900000>;
-+ regulator-max-microvolt = <3600000>;
-+ regulator-always-on;
-+ regulator-boot-on;
-+ };
-+ };
-+ };
-+
-+ rtc at 32 {
-+ compatible = "epson,rx8010";
-+ reg = <0x32>;
-+ interrupt-parent = <&gpio4>;
-+ interrupts = <10>;
-+ rx8010-irq_1 = <&gpio4 10 0>;
-+ };
-+};
-+
-+&iomuxc {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_hog>;
-+
-+ hog {
-+ pinctrl_hog: hoggrp-1 {
-+ fsl,pins = <
-+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000 /* uSDHC2 CD */
-+ MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 /* uSDHC4 CD */
-+ MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 /* uSDHC4 SDIO PWR */
-+ MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000 /* uSDHC4 SDIO WP */
-+ MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x80000000 /* uSDHC4 SDIO LED */
-+ MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x80000000 /* SPI1 CS */
-+ MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* FEC Reset */
-+ MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000 /* GPIO0 */
-+ MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000 /* GPIO1 */
-+ MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 /* GPIO2 */
-+ MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000 /* GPIO3 */
-+ MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x80000000 /* GPIO4 */
-+ MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x80000000 /* GPIO5 */
-+ MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000 /* GPIO6 */
-+ MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x80000000 /* GPIO7 */
-+ MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000 /* CAM_PWDN */
-+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* CAM_RST */
-+ MX6QDL_PAD_GPIO_9__WDOG1_B 0x80000000 /* Watchdog out */
-+ MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x80000000 /* HUB_RESET */
-+ MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x80000000 /* PMIC Interrupt */
-+ MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x80000000 /* AR8033 Interrupt */
-+ MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x80000000 /* BLEN_OUT */
-+ MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* LVDS_PPEN_OUT */
-+ MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x80000000 /* RTC_INT */
-+ >;
-+ };
-+ };
-+
-+ usdhc3 {
-+ pinctrl_usdhc3_reset: usdhc3grp-reset {
-+ fsl,pins = <
-+ MX6QDL_PAD_SD3_RST__SD3_RESET 0x170F9
-+ >;
-+ };
-+ };
-+
-+ audmux {
-+ pinctrl_audmux: audmuxgrp {
-+ fsl,pins = <
-+ MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
-+ MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0
-+ MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
-+ MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0
-+ >;
-+ };
-+ };
-+
-+ ecspi1 {
-+ pinctrl_ecspi1: ecspi1grp {
-+ fsl,pins = <
-+ MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
-+ MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
-+ MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
-+ >;
-+ };
-+ };
-+
-+ ecspi5 {
-+ pinctrl_ecspi5: ecspi5grp {
-+ fsl,pins = <
-+ MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x1b0b0
-+ MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0x1b0b0
-+ MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x1b0b0
-+ MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0
-+ >;
-+ };
-+ };
-+
-+ hdmi_cec {
-+ pinctrl_hdmi_cec: hdmicecgrp {
-+ fsl,pins = <
-+ MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
-+ >;
-+ };
-+ };
-+
-+ usbotg {
-+ pinctrl_usbotg: usbotggrp {
-+ fsl,pins = <
-+ MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
-+ >;
-+ };
-+ };
-+
-+ usdhc2 {
-+ pinctrl_usdhc2: usdhc2grp {
-+ fsl,pins = <
-+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
-+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
-+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
-+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
-+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
-+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
-+ >;
-+ };
-+ };
-+
-+ usdhc3 {
-+ pinctrl_usdhc3: usdhc3grp {
-+ fsl,pins = <
-+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
-+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
-+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
-+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
-+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
-+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
-+ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
-+ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
-+ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
-+ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
-+ >;
-+ };
-+ };
-+
-+ usdhc4 {
-+ pinctrl_usdhc4: usdhc4grp {
-+ fsl,pins = <
-+ MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
-+ MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
-+ MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
-+ MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
-+ MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
-+ MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
-+ MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
-+ MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
-+ MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
-+ MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
-+ >;
-+ };
-+ };
-+
-+ i2c1 {
-+ pinctrl_i2c1: i2c1grp {
-+ fsl,pins = <
-+ MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
-+ MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
-+ >;
-+ };
-+ };
-+
-+ i2c2 {
-+ pinctrl_i2c2: i2c2grp {
-+ fsl,pins = <
-+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
-+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
-+ >;
-+ };
-+ };
-+
-+ i2c3 {
-+ pinctrl_i2c3: i2c3grp {
-+ fsl,pins = <
-+ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
-+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
-+ >;
-+ };
-+ };
-+
-+ pwm1 {
-+ pinctrl_pwm1: pwm1grp {
-+ fsl,pins = <
-+ MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
-+ >;
-+ };
-+ };
-+
-+ pwm2 {
-+ pinctrl_pwm2: pwm2grp {
-+ fsl,pins = <
-+ MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
-+ >;
-+ };
-+ };
-+
-+ enet {
-+ pinctrl_enet: enetgrp {
-+ fsl,pins = <
-+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
-+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
-+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0
-+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0
-+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0
-+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0
-+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0
-+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0
-+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
-+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
-+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
-+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
-+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
-+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
-+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
-+ >;
-+ };
-+ };
-+
-+ uart3 {
-+ pinctrl_uart3: uart3grp {
-+ fsl,pins = <
-+ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
-+ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
-+ MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
-+ MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
-+ >;
-+ };
-+ };
-+
-+ uart4 {
-+ pinctrl_uart4: uart4grp {
-+ fsl,pins = <
-+ MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
-+ MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
-+ >;
-+ };
-+ };
-+};
-+
-+&ldb {
-+ split-mode;
-+ status = "okay";
-+
-+ lvds-channel at 0 {
-+ fsl,data-mapping = "spwg";
-+ fsl,data-width = <24>;
-+ crtc = "ipu1-di0";
-+ status = "okay";
-+
-+ display-timings {
-+ native-mode = <&timing0>;
-+ timing0: SHARP-LQ156M1LG21 {
-+ clock-frequency = <65000000>;
-+ hactive = <1920>;
-+ vactive = <1080>;
-+ hback-porch = <100>;
-+ hfront-porch = <40>;
-+ vback-porch = <30>;
-+ vfront-porch = <3>;
-+ hsync-len = <10>;
-+ vsync-len = <2>;
-+ };
-+ };
-+ };
-+
-+ lvds-channel at 1 {
-+ status = "disabled";
-+ };
-+};
-+
-+&pcie {
-+ reset-gpio = <&gpio7 12 0>;
-+ fsl,tx-deemph-gen1 = <0>;
-+ fsl,tx-deemph-gen2-3p5db = <0>;
-+ fsl,tx-deemph-gen2-6db = <20>;
-+ fsl,tx-swing-full = <103>;
-+ fsl,tx-swing-low = <103>;
-+ status = "okay";
-+};
-+
-+
-+&pwm1 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_pwm1>;
-+ status = "okay";
-+};
-+
-+&pwm2 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_pwm2>;
-+ status = "okay";
-+};
-+
-+&ssi1 {
-+ fsl,mode = "i2s-master";
-+ status = "okay";
-+};
-+
-+&uart3 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_uart3>;
-+ fsl,uart-has-rtscts;
-+ status = "okay";
-+};
-+
-+&uart4 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_uart4>;
-+ status = "okay";
-+};
-+
-+&usbh1 {
-+ vbus-supply = <®_usb_h1_vbus>;
-+ reset-gpios = <&gpio7 11 0>;
-+ status = "okay";
-+};
-+
-+&usbotg {
-+ vbus-supply = <®_usb_otg_vbus>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_usbotg>;
-+ disable-over-current;
-+ status = "okay";
-+};
-+
-+&usdhc2 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_usdhc2>;
-+ cd-gpios = <&gpio1 4 0>;
-+ no-1-8-v;
-+ keep-power-in-suspend;
-+ enable-sdio-wakeup;
-+ status = "okay";
-+};
-+
-+&usdhc3 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_usdhc3 &pinctrl_usdhc3_reset>;
-+ bus-width = <8>;
-+ vmmc-supply = <&bperi>;
-+ no-1-8-v;
-+ non-removable;
-+ keep-power-in-suspend;
-+ status = "okay";
-+};
-+
-+&usdhc4 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_usdhc4>;
-+ bus-width = <8>;
-+ cd-gpios = <&gpio6 11 0>;
-+ no-1-8-v;
-+ keep-power-in-suspend;
-+ enable-sdio-wakeup;
-+ status = "okay";
-+};
-+
-+&vpu {
-+ pu-supply = <®_pu>;
-+};
-+
-+&sata {
-+ fsl,no-spread-spectrum;
-+ fsl,transmit-atten-16ths = <12>;
-+ fsl,transmit-boost-mdB = <3330>;
-+ fsl,transmit-level-mV = <1133>;
-+ fsl,receive-dpll-mode = <1>;
-+ status = "okay";
-+};
---
-2.5.0
-
diff --git a/recipes-kernel/linux/linux-ge-3.14/defconfig b/recipes-kernel/linux/linux-ge-3.14/defconfig
deleted file mode 100644
index 86c6caf..0000000
--- a/recipes-kernel/linux/linux-ge-3.14/defconfig
+++ /dev/null
@@ -1,453 +0,0 @@
-CONFIG_KERNEL_LZO=y
-CONFIG_SYSVIPC=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=18
-CONFIG_CGROUPS=y
-CONFIG_RELAY=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-CONFIG_KALLSYMS_ALL=y
-CONFIG_PERF_EVENTS=y
-# CONFIG_SLUB_DEBUG is not set
-# CONFIG_COMPAT_BRK is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_GPIO_PCA953X=y
-CONFIG_ARCH_MXC=y
-CONFIG_MACH_IMX51_DT=y
-CONFIG_MACH_EUKREA_CPUIMX51SD=y
-CONFIG_SOC_IMX50=y
-CONFIG_SOC_IMX53=y
-CONFIG_SOC_IMX6Q=y
-CONFIG_SOC_IMX6SL=y
-CONFIG_SOC_IMX6SX=y
-CONFIG_SOC_IMX6UL=y
-CONFIG_SOC_IMX7D=y
-CONFIG_SOC_VF610=y
-# CONFIG_SWP_EMULATE is not set
-CONFIG_PCI=y
-CONFIG_PCI_IMX6=y
-CONFIG_SMP=y
-CONFIG_HAVE_ARM_ARCH_TIMER=y
-CONFIG_VMSPLIT_2G=y
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-CONFIG_HIGHMEM=y
-CONFIG_CMA=y
-CONFIG_CMDLINE="noinitrd console=ttymxc0,115200"
-CONFIG_KEXEC=y
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_ARM_IMX6Q_CPUFREQ=y
-CONFIG_ARM_IMX7D_CPUFREQ=y
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_BINFMT_MISC=m
-CONFIG_PM_RUNTIME=y
-CONFIG_PM_DEBUG=y
-CONFIG_PM_TEST_SUSPEND=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_NETFILTER=y
-CONFIG_VLAN_8021Q=y
-CONFIG_LLC2=y
-CONFIG_CAN=y
-CONFIG_CAN_FLEXCAN=y
-CONFIG_CAN_M_CAN=y
-CONFIG_BT=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_BNEP_MC_FILTER=y
-CONFIG_BT_BNEP_PROTO_FILTER=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIBTUSB=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_BCSP=y
-CONFIG_BT_HCIUART_ATH3K=y
-CONFIG_BT_HCIBCM203X=y
-CONFIG_BT_ATH3K=y
-CONFIG_CFG80211=y
-CONFIG_MAC80211=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_STANDALONE is not set
-CONFIG_DMA_CMA=y
-CONFIG_CMA_SIZE_MBYTES=320
-CONFIG_IMX_WEIM=y
-CONFIG_CONNECTOR=y
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_JEDECPROBE=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_CFI_STAA=y
-CONFIG_MTD_PHYSMAP_OF=y
-CONFIG_MTD_DATAFLASH=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_SST25L=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_GPMI_NAND=y
-CONFIG_MTD_NAND_MXC=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_SPI_FSL_QUADSPI=y
-CONFIG_MTD_UBI=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=65536
-CONFIG_SENSORS_FXOS8700=y
-CONFIG_SENSORS_FXAS2100X=y
-CONFIG_EEPROM_AT24=y
-CONFIG_EEPROM_AT25=y
-# CONFIG_SCSI_PROC_FS is not set
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_SCSI_CONSTANTS=y
-CONFIG_SCSI_LOGGING=y
-CONFIG_SCSI_SCAN_ASYNC=y
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_ATA=y
-CONFIG_SATA_AHCI_PLATFORM=y
-CONFIG_AHCI_IMX=y
-CONFIG_PATA_IMX=y
-CONFIG_NETDEVICES=y
-# CONFIG_NET_VENDOR_BROADCOM is not set
-CONFIG_CS89x0=y
-CONFIG_CS89x0_PLATFORM=y
-# CONFIG_NET_VENDOR_FARADAY is not set
-CONFIG_IGB=y
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_MICROCHIP is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-CONFIG_SMC91X=y
-CONFIG_SMC911X=y
-CONFIG_SMSC911X=y
-# CONFIG_NET_VENDOR_STMICRO is not set
-CONFIG_MICREL_PHY=y
-CONFIG_USB_PEGASUS=m
-CONFIG_USB_RTL8150=m
-CONFIG_USB_RTL8152=m
-CONFIG_USB_USBNET=m
-CONFIG_USB_NET_CDC_EEM=m
-CONFIG_BCMDHD=m
-CONFIG_BCMDHD_SDIO=y
-CONFIG_BCMDHD_FW_PATH="/lib/firmware/bcm/fw_bcmdhd.bin"
-CONFIG_BCMDHD_NVRAM_PATH="/lib/firmware/bcm/bcmdhd.cal"
-# CONFIG_RTL_CARDS is not set
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_EVBUG=m
-CONFIG_KEYBOARD_GPIO=y
-CONFIG_KEYBOARD_IMX=y
-CONFIG_MOUSE_PS2=m
-CONFIG_MOUSE_PS2_ELANTECH=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_ADS7846=y
-CONFIG_TOUCHSCREEN_EGALAX=y
-CONFIG_TOUCHSCREEN_ELAN=y
-CONFIG_TOUCHSCREEN_MAX11801=y
-CONFIG_TOUCHSCREEN_IMX6UL_TSC=y
-CONFIG_TOUCHSCREEN_MC13783=y
-CONFIG_TOUCHSCREEN_TSC2007=y
-CONFIG_TOUCHSCREEN_STMPE=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_MMA8450=y
-CONFIG_INPUT_ISL29023=y
-CONFIG_INPUT_MPL3115=y
-CONFIG_SENSOR_FXLS8471=y
-CONFIG_SERIO_SERPORT=m
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_IMX=y
-CONFIG_SERIAL_IMX_CONSOLE=y
-CONFIG_SERIAL_FSL_LPUART=y
-CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
-CONFIG_FSL_OTP=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C_CHARDEV=y
-# CONFIG_I2C_HELPER_AUTO is not set
-CONFIG_I2C_ALGOPCF=m
-CONFIG_I2C_ALGOPCA=m
-CONFIG_I2C_IMX=y
-CONFIG_SPI=y
-CONFIG_SPI_GPIO=y
-CONFIG_SPI_IMX=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_MAX732X=y
-CONFIG_GPIO_74X164=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_SABRESD_MAX8903=y
-CONFIG_SENSORS_MAX17135=y
-CONFIG_SENSORS_MAG3110=y
-CONFIG_THERMAL=y
-CONFIG_CPU_THERMAL=y
-CONFIG_IMX_THERMAL=y
-CONFIG_DEVICE_THERMAL=y
-CONFIG_WATCHDOG=y
-CONFIG_IMX2_WDT=y
-CONFIG_MFD_DA9052_I2C=y
-CONFIG_MFD_DA9063=y
-CONFIG_MFD_MC13XXX_SPI=y
-CONFIG_MFD_MC13XXX_I2C=y
-CONFIG_MFD_MAX17135=y
-CONFIG_MFD_SI476X_CORE=y
-CONFIG_MFD_STMPE=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_REGULATOR_ANATOP=y
-CONFIG_REGULATOR_DA9052=y
-CONFIG_REGULATOR_DA9063=y
-CONFIG_REGULATOR_GPIO=y
-CONFIG_REGULATOR_MAX17135=y
-CONFIG_REGULATOR_MC13783=y
-CONFIG_REGULATOR_MC13892=y
-CONFIG_REGULATOR_PFUZE100=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_MEDIA_CAMERA_SUPPORT=y
-CONFIG_MEDIA_RADIO_SUPPORT=y
-CONFIG_MEDIA_RC_SUPPORT=y
-CONFIG_RC_DEVICES=y
-CONFIG_IR_GPIO_CIR=y
-CONFIG_MEDIA_USB_SUPPORT=y
-CONFIG_USB_VIDEO_CLASS=m
-CONFIG_V4L_PLATFORM_DRIVERS=y
-CONFIG_VIDEO_MXC_OUTPUT=y
-CONFIG_VIDEO_MXC_CAPTURE=m
-CONFIG_MXC_CAMERA_OV5640=m
-CONFIG_MXC_CAMERA_OV5642=m
-CONFIG_MXC_CAMERA_OV5640_MIPI=m
-CONFIG_MXC_TVIN_ADV7180=m
-CONFIG_MXC_IPU_DEVICE_QUEUE_SDC=m
-CONFIG_VIDEO_MXC_IPU_OUTPUT=y
-CONFIG_VIDEO_MXC_PXP_V4L2=y
-CONFIG_VIDEO_MXC_CSI_CAMERA=m
-CONFIG_MXC_VADC=m
-CONFIG_MXC_MIPI_CSI=m
-CONFIG_MXC_CAMERA_OV5647_MIPI=m
-CONFIG_SOC_CAMERA=y
-CONFIG_VIDEO_MX3=y
-CONFIG_V4L_MEM2MEM_DRIVERS=y
-CONFIG_VIDEO_CODA=y
-CONFIG_RADIO_SI476X=y
-CONFIG_SOC_CAMERA_OV2640=y
-CONFIG_DRM=y
-CONFIG_DRM_VIVANTE=y
-CONFIG_FB=y
-CONFIG_FB_MXS=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_LCD_CLASS_DEVICE=y
-CONFIG_LCD_L4F00242T03=y
-CONFIG_LCD_PLATFORM=y
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_PWM=y
-CONFIG_FB_MXC_SYNC_PANEL=y
-CONFIG_FB_MXC_LDB=y
-CONFIG_FB_MXC_MIPI_DSI=y
-CONFIG_FB_MXC_MIPI_DSI_SAMSUNG=y
-CONFIG_FB_MXC_TRULY_WVGA_SYNC_PANEL=y
-CONFIG_FB_MXC_HDMI=y
-CONFIG_FB_MXC_EINK_PANEL=y
-CONFIG_FB_MXC_EINK_V2_PANEL=y
-CONFIG_FB_MXS_SII902X=y
-CONFIG_FB_MXC_DCIC=m
-CONFIG_HANNSTAR_CABC=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
-CONFIG_LOGO=y
-CONFIG_SOUND=y
-CONFIG_SND=y
-CONFIG_SND_USB_AUDIO=m
-CONFIG_SND_SOC=y
-CONFIG_SND_IMX_SOC=y
-CONFIG_SND_SOC_EUKREA_TLV320=y
-CONFIG_SND_SOC_IMX_CS42888=y
-CONFIG_SND_SOC_IMX_SII902X=y
-CONFIG_SND_SOC_IMX_WM8958=y
-CONFIG_SND_SOC_IMX_WM8960=y
-CONFIG_SND_SOC_IMX_WM8962=y
-CONFIG_SND_SOC_IMX_SGTL5000=y
-CONFIG_SND_SOC_IMX_MQS=y
-CONFIG_SND_SOC_IMX_SPDIF=y
-CONFIG_SND_SOC_IMX_MC13783=y
-CONFIG_SND_SOC_IMX_HDMI=y
-CONFIG_SND_SOC_IMX_SI476X=y
-CONFIG_USB=y
-CONFIG_USB_OTG_WHITELIST=y
-CONFIG_USB_OTG_FSM=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_MXC=y
-CONFIG_USB_HCD_TEST_MODE=y
-CONFIG_USB_ACM=m
-CONFIG_USB_STORAGE=y
-CONFIG_USB_CHIPIDEA=y
-CONFIG_USB_CHIPIDEA_UDC=y
-CONFIG_USB_CHIPIDEA_HOST=y
-CONFIG_USB_SERIAL=m
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_FTDI_SIO=m
-CONFIG_USB_SERIAL_OPTION=m
-CONFIG_USB_EHSET_TEST_FIXTURE=y
-CONFIG_NOP_USB_XCEIV=y
-CONFIG_USB_MXS_PHY=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_CONFIGFS=m
-CONFIG_USB_CONFIGFS_SERIAL=y
-CONFIG_USB_CONFIGFS_ACM=y
-CONFIG_USB_CONFIGFS_OBEX=y
-CONFIG_USB_CONFIGFS_NCM=y
-CONFIG_USB_CONFIGFS_ECM=y
-CONFIG_USB_CONFIGFS_ECM_SUBSET=y
-CONFIG_USB_CONFIGFS_RNDIS=y
-CONFIG_USB_CONFIGFS_EEM=y
-CONFIG_USB_CONFIGFS_MASS_STORAGE=y
-CONFIG_USB_CONFIGFS_F_LB_SS=y
-CONFIG_USB_CONFIGFS_F_FS=y
-CONFIG_USB_ZERO=m
-CONFIG_USB_ETH=m
-CONFIG_USB_G_NCM=m
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_MASS_STORAGE=m
-CONFIG_USB_G_SERIAL=m
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MMC_SDHCI_ESDHC_IMX=y
-CONFIG_MXC_IPU=y
-CONFIG_MXC_GPU_VIV=y
-CONFIG_MXC_IPU_V3_PRE=y
-CONFIG_MXC_MIPI_CSI2=y
-CONFIG_MXC_SIM=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_TIMER=y
-CONFIG_LEDS_TRIGGER_ONESHOT=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_LEDS_TRIGGER_BACKLIGHT=y
-CONFIG_LEDS_TRIGGER_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_INTF_DEV_UIE_EMUL=y
-CONFIG_RTC_DRV_DA9063=y
-CONFIG_RTC_DRV_MC13XXX=y
-CONFIG_RTC_DRV_MXC=y
-CONFIG_RTC_DRV_SNVS=y
-CONFIG_DMADEVICES=y
-CONFIG_MXC_PXP_V2=y
-CONFIG_MXC_PXP_V3=y
-CONFIG_IMX_SDMA=y
-CONFIG_MXS_DMA=y
-CONFIG_STAGING=y
-CONFIG_STAGING_MEDIA=y
-# CONFIG_IOMMU_SUPPORT is not set
-CONFIG_IIO=y
-CONFIG_VF610_ADC=y
-CONFIG_AD2802A=y
-CONFIG_PWM=y
-CONFIG_PWM_IMX=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_POSIX_ACL=y
-CONFIG_EXT2_FS_SECURITY=y
-CONFIG_EXT3_FS=y
-CONFIG_EXT3_FS_POSIX_ACL=y
-CONFIG_EXT3_FS_SECURITY=y
-CONFIG_EXT4_FS=y
-CONFIG_EXT4_FS_POSIX_ACL=y
-CONFIG_EXT4_FS_SECURITY=y
-CONFIG_QUOTA=y
-CONFIG_QUOTA_NETLINK_INTERFACE=y
-# CONFIG_PRINT_QUOTA_WARNING is not set
-CONFIG_AUTOFS4_FS=y
-CONFIG_FUSE_FS=y
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_ZISOFS=y
-CONFIG_UDF_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_UBIFS_FS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3_ACL=y
-CONFIG_NFS_V4=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS_DEFAULT="cp437"
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_ISO8859_15=m
-CONFIG_NLS_UTF8=y
-CONFIG_DEBUG_FS=y
-CONFIG_MAGIC_SYSRQ=y
-# CONFIG_SCHED_DEBUG is not set
-# CONFIG_DEBUG_BUGVERBOSE is not set
-# CONFIG_FTRACE is not set
-CONFIG_CORESIGHT=y
-CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y
-CONFIG_CORESIGHT_SINK_TPIU=y
-CONFIG_CORESIGHT_SINK_ETBV10=y
-CONFIG_CORESIGHT_SOURCE_ETM3X=y
-CONFIG_SECURITYFS=y
-CONFIG_CRYPTO_USER=y
-CONFIG_CRYPTO_TEST=m
-CONFIG_CRYPTO_GCM=y
-CONFIG_CRYPTO_CBC=y
-CONFIG_CRYPTO_CTS=y
-CONFIG_CRYPTO_LRW=y
-CONFIG_CRYPTO_XTS=y
-CONFIG_CRYPTO_MD4=y
-CONFIG_CRYPTO_MD5=y
-CONFIG_CRYPTO_MICHAEL_MIC=y
-CONFIG_CRYPTO_RMD128=y
-CONFIG_CRYPTO_RMD160=y
-CONFIG_CRYPTO_RMD256=y
-CONFIG_CRYPTO_RMD320=y
-CONFIG_CRYPTO_SHA1=y
-CONFIG_CRYPTO_SHA512=y
-CONFIG_CRYPTO_TGR192=y
-CONFIG_CRYPTO_WP512=y
-CONFIG_CRYPTO_BLOWFISH=y
-CONFIG_CRYPTO_CAMELLIA=y
-CONFIG_CRYPTO_DES=y
-CONFIG_CRYPTO_TWOFISH=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRYPTO_DEV_FSL_CAAM=y
-CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y
-CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=y
-CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=y
-CONFIG_CRC_CCITT=m
-CONFIG_CRC_T10DIF=y
-CONFIG_CRC7=m
-CONFIG_LIBCRC32C=m
-CONFIG_FONTS=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
diff --git a/recipes-kernel/linux/linux-ge_3.14.bb b/recipes-kernel/linux/linux-ge_3.14.bb
deleted file mode 100644
index 6ccf0ab..0000000
--- a/recipes-kernel/linux/linux-ge_3.14.bb
+++ /dev/null
@@ -1,25 +0,0 @@
-# Copyright (C) 2016 Timesys Corporation
-# Copyright (C) 2016 General Electric Company
-# Released under the MIT license (see COPYING.MIT for the terms)
-
-include recipes-kernel/linux/linux-imx.inc
-include recipes-kernel/linux/linux-dtb.inc
-
-DEPENDS += "lzop-native bc-native"
-
-SRCREV = "5668cd93fe86889e121142440b42d4615afae984"
-LOCALVERSION = "-1.1.x-fslc-imx-elo"
-SRC_URI = "git://github.com/Freescale/linux-fslc.git;branch=3.14-1.1.x-imx \
- file://0001-rtc-rx8010-Add-driver-to-kernel.patch \
- file://0002-mfd-da9063-Add-support-for-production-silicon-varian.patch \
- file://0003-mfd-da9063-Upgrade-of-register-definitions-to-suppor.patch \
- file://0004-rtc-da9063-RTC-driver.patch \
- file://0005-mfd-da9063-Add-support-for-AD-silicon-variant.patch \
- file://0006-mfd-da9063-Get-irq-base-dynamically-before-registeri.patch \
- file://0007-mfd-da9063-Add-support-for-OnKey-driver.patch \
- file://0008-ahci_imx-Make-receive-DPLL-mode-configurable.patch \
- file://0009-PCI-imx6-Add-DT-bindings-to-configure-PHY-Tx-driver-.patch \
- file://0010-ARM-dts-imx-Add-support-for-Advantech-GE-ELO.patch \
- file://defconfig"
-
-COMPATIBLE_MACHINE = "(imx6q-elo)"
--
2.8.1
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