[meta-freescale] [meta-fsl-arm][PATCH] u-boot-fslc: Update to 1e82446 revision

[Otavio Salvador]

This brings following backports/fixes:

1e82446 mx6slevk: imximage.cfg: update to fix tINIT3 and tIH-CA violations
e578035 mx6qarm2: imximage_mx6dl.cfg update to fix tINIT3 violation
adc86d5 mx7_common: Define CONFIG_SYS_MALLOC_LEN in the board file
83195c2 warp7: Pass the UART base definition
87a2283 mx6sabresd: Remove unneeded enable_lvds() function
8f1927e arm: mxs: Update MX28EVK config
db8b958 mx6sabresd: Use VESA 1024x768 timings
49185d3 mx27: 16-bit wide watchdog registers
cfc4a96 mx6sabre_common: Fix U-Boot corruption after 'saveenv'
d955806 arm: mx5: Enable NAND TrimFFS on M53EVK
0aea495 imx: print ARM clock for clocks command
1a1ac16 imx: mx6ul configure the PMIC_STBY_REQ pin as open drain
6f8ee92 imx: mx6ul: skip setting ahb rate
60b774d imx: mx6: Fix incorrect clear mmdc_ch0 handshake mask
fe3704b Revert conversion for config_distro_bootcmd.h
8a68957 Revert "warp7: Add initial support"

Change-Id: I7a04b21f4ec9aac0a58adb1233d208b1ae2c3258
Signed-off-by: Otavio Salvador <otavio at ossystems.com.br>
---
 recipes-bsp/u-boot/u-boot-fslc-mxsboot_2016.03.bb | 2 +-
 recipes-bsp/u-boot/u-boot-fslc_2016.03.bb         | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/recipes-bsp/u-boot/u-boot-fslc-mxsboot_2016.03.bb b/recipes-bsp/u-boot/u-boot-fslc-mxsboot_2016.03.bb
index 4ec0357..609ce67 100644
--- a/recipes-bsp/u-boot/u-boot-fslc-mxsboot_2016.03.bb
+++ b/recipes-bsp/u-boot/u-boot-fslc-mxsboot_2016.03.bb
@@ -7,7 +7,7 @@ PROVIDES = "u-boot-mxsboot"
 
 PV = "v2016.03+git${SRCPV}"
 
-SRCREV = "fd6b196f574ca85d75d6bbe24cf9344e58366ae1"
+SRCREV = "1e82446ebd54b50a45dfb0a564a3e6763f309341"
 SRCBRANCH = "2016.03+fslc"
 
 SRC_URI = "git://github.com/Freescale/u-boot-fslc.git;branch=${SRCBRANCH}"
diff --git a/recipes-bsp/u-boot/u-boot-fslc_2016.03.bb b/recipes-bsp/u-boot/u-boot-fslc_2016.03.bb
index 2358de3..94b24e9 100644
--- a/recipes-bsp/u-boot/u-boot-fslc_2016.03.bb
+++ b/recipes-bsp/u-boot/u-boot-fslc_2016.03.bb
@@ -2,5 +2,5 @@ include u-boot-fslc.inc
 
 PV = "v2016.03+git${SRCPV}"
 
-SRCREV = "fd6b196f574ca85d75d6bbe24cf9344e58366ae1"
+SRCREV = "1e82446ebd54b50a45dfb0a564a3e6763f309341"
 SRCBRANCH = "2016.03+fslc"
-- 
2.8.0