[meta-freescale] [meta-fsl-arm][PATCH 5/5] u-boot-fslc: Add patches to enable boot with Vybrid Tower
Anthony Felice
tony.felice at timesys.com
Fri Oct 9 14:38:59 PDT 2015
These patches are necessary to boot Linux 3.13 with the Vybrid Tower. The
first, 'vf610twr: Enable all masks of CCGRx registers', fixes both Linux and
MQX boot issues due to peripheral clocks being disabled. The second, 'vf610twr:
Fix typo in DRAM init', fixes a hang in U-Boot with the Vybrid Tower platform.
These patches are pending upstream approval.
Signed-off-by: Anthony Felice <tony.felice at timesys.com>
---
...10twr-Enable-all-masks-of-CCGRx-registers.patch | 74 ++++++++++++++++++++++
.../0002-vf610twr-Fix-typo-in-DRAM-init.patch | 30 +++++++++
recipes-bsp/u-boot/u-boot-fslc_2015.10.bb | 4 ++
3 files changed, 108 insertions(+)
create mode 100644 recipes-bsp/u-boot/u-boot-fslc/0001-vf610twr-Enable-all-masks-of-CCGRx-registers.patch
create mode 100644 recipes-bsp/u-boot/u-boot-fslc/0002-vf610twr-Fix-typo-in-DRAM-init.patch
diff --git a/recipes-bsp/u-boot/u-boot-fslc/0001-vf610twr-Enable-all-masks-of-CCGRx-registers.patch b/recipes-bsp/u-boot/u-boot-fslc/0001-vf610twr-Enable-all-masks-of-CCGRx-registers.patch
new file mode 100644
index 0000000..fcc1c5f
--- /dev/null
+++ b/recipes-bsp/u-boot/u-boot-fslc/0001-vf610twr-Enable-all-masks-of-CCGRx-registers.patch
@@ -0,0 +1,74 @@
+From bba320359442541f65b7489b37c71e869aee31ff Mon Sep 17 00:00:00 2001
+From: Anthony Felice <tony.felice at timesys.com>
+Date: Wed, 7 Oct 2015 17:04:04 -0400
+Subject: [U-Boot] [PATCH 1/2] vf610twr: Enable all masks of CCGRx registers.
+
+The CCGRx registers, or clock gating registers, can be set to disable or enable
+clocks for devices on the vf610twr platform. Enabling masks for all CCGRx
+registers allows Linux drivers, like snvs_rtc, and also MQX applications, to
+work out-of-the-box. There are no real downsides to enabling all clocks, and
+this has been done in previous Freescale releases of U-Boot for the Vybrid
+Tower.
+
+Signed-off-by: Anthony Felice <tony.felice at timesys.com>
+---
+ arch/arm/include/asm/arch-vf610/crm_regs.h | 1 +
+ board/freescale/vf610twr/vf610twr.c | 22 +++++++++-------------
+ 2 files changed, 10 insertions(+), 13 deletions(-)
+
+diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h b/arch/arm/include/asm/arch-vf610/crm_regs.h
+index a46e396..11b87ec 100644
+--- a/arch/arm/include/asm/arch-vf610/crm_regs.h
++++ b/arch/arm/include/asm/arch-vf610/crm_regs.h
+@@ -187,6 +187,7 @@ struct anadig_reg {
+ #define CCM_CSCMR2_RMII_CLK_SEL(v) (((v) & 0x3) << 4)
+
+ #define CCM_REG_CTRL_MASK 0xffffffff
++#define CCM_CCGRX_ENABLE_ALL_CTRL_MASK (0xffffffff)
+ #define CCM_CCGR0_UART0_CTRL_MASK (0x3 << 14)
+ #define CCM_CCGR0_UART1_CTRL_MASK (0x3 << 16)
+ #define CCM_CCGR0_DSPI0_CTRL_MASK (0x3 << 24)
+diff --git a/board/freescale/vf610twr/vf610twr.c b/board/freescale/vf610twr/vf610twr.c
+index 7834931..a78e9e6 100644
+--- a/board/freescale/vf610twr/vf610twr.c
++++ b/board/freescale/vf610twr/vf610twr.c
+@@ -272,27 +272,23 @@ static void clock_init(void)
+ struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
+
+ clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,
+- CCM_CCGR0_UART1_CTRL_MASK);
++ CCM_CCGRX_ENABLE_ALL_CTRL_MASK);
+ clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,
+- CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK);
++ CCM_CCGRX_ENABLE_ALL_CTRL_MASK);
+ clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
+- CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK |
+- CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK |
+- CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK |
+- CCM_CCGR2_QSPI0_CTRL_MASK);
++ CCM_CCGRX_ENABLE_ALL_CTRL_MASK);
+ clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
+- CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK);
++ CCM_CCGRX_ENABLE_ALL_CTRL_MASK);
+ clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
+- CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
+- CCM_CCGR4_GPC_CTRL_MASK | CCM_CCGR4_I2C0_CTRL_MASK);
++ CCM_CCGRX_ENABLE_ALL_CTRL_MASK);
+ clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
+- CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK);
++ CCM_CCGRX_ENABLE_ALL_CTRL_MASK);
+ clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
+- CCM_CCGR7_SDHC1_CTRL_MASK);
++ CCM_CCGRX_ENABLE_ALL_CTRL_MASK);
+ clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
+- CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK);
++ CCM_CCGRX_ENABLE_ALL_CTRL_MASK);
+ clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK,
+- CCM_CCGR10_NFC_CTRL_MASK);
++ CCM_CCGRX_ENABLE_ALL_CTRL_MASK);
+
+ clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN,
+ ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT);
+--
+1.9.1
+
diff --git a/recipes-bsp/u-boot/u-boot-fslc/0002-vf610twr-Fix-typo-in-DRAM-init.patch b/recipes-bsp/u-boot/u-boot-fslc/0002-vf610twr-Fix-typo-in-DRAM-init.patch
new file mode 100644
index 0000000..eafb2cb
--- /dev/null
+++ b/recipes-bsp/u-boot/u-boot-fslc/0002-vf610twr-Fix-typo-in-DRAM-init.patch
@@ -0,0 +1,30 @@
+From 56228435eaad1e7361d0c840674540526ac7f31f Mon Sep 17 00:00:00 2001
+From: Anthony Felice <tony.felice at timesys.com>
+Date: Fri, 9 Oct 2015 14:52:45 -0400
+Subject: [U-Boot] [PATCH 2/2] vf610twr: Fix typo in DRAM init
+
+This commit fixes a typo in vf610twr DRAM init that was causing a hang in
+U-Boot for the Vybrid Tower. This typo was introduced in commit 3f353cecc
+(vf610: refactor DDRMC code).
+
+Signed-off-by: Anthony Felice <tony.felice at timesys.com>
+---
+ board/freescale/vf610twr/vf610twr.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/board/freescale/vf610twr/vf610twr.c b/board/freescale/vf610twr/vf610twr.c
+index a78e9e6..fa0075c 100644
+--- a/board/freescale/vf610twr/vf610twr.c
++++ b/board/freescale/vf610twr/vf610twr.c
+@@ -108,7 +108,7 @@ int dram_init(void)
+ .trcd_int = 6,
+ .tras_lockout = 0,
+ .tdal = 12,
+- .bstlen = 0,
++ .bstlen = 3,
+ .tdll = 512,
+ .trp_ab = 6,
+ .tref = 3120,
+--
+1.9.1
+
diff --git a/recipes-bsp/u-boot/u-boot-fslc_2015.10.bb b/recipes-bsp/u-boot/u-boot-fslc_2015.10.bb
index 3c1812b..0fe2f89 100644
--- a/recipes-bsp/u-boot/u-boot-fslc_2015.10.bb
+++ b/recipes-bsp/u-boot/u-boot-fslc_2015.10.bb
@@ -4,3 +4,7 @@ PV = "v2015.10+git${SRCPV}"
SRCREV = "1fb68c8c84068372cae4adf2e726e2a4ba712655"
SRCBRANCH = "2015.10+fslc"
+
+SRC_URI_append_twr-vf65gs10 = " \
+ file://0001-vf610twr-Enable-all-masks-of-CCGRx-registers.patch \
+ file://0002-vf610twr-Fix-typo-in-DRAM-init.patch"
--
1.9.1
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