[meta-freescale] Kernel 3.14.28 can't set ENET_REF_CLK to 50 MHz
Nikolay Dimitrov
picmaster at mail.bg
Mon Jun 15 07:50:51 PDT 2015
Hi gang,
FYI - some time ago I've had such issue, described in this ML thread:
https://lists.yoctoproject.org/pipermail/meta-freescale/2015-May/013786.html
The issue happens again on FSL kernel 3.14.28, under same HW conditions
(imx6q-based board, 100 MBit/s RMII PHY using 50 MHZ refclk from SoC
pin GPIO_16).
Last time Gary Thomas posted a solution for this issue, which works
with slight changes works on 3.14.28:
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index f0d8000..1cab088 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -568,8 +568,20 @@ static void __init imx6q_clocks_init(struct
device_node *ccm_node)
imx_clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY2_GATE]);
}
- /*Set enet_ref clock to 125M to supply for RGMII tx_clk */
- clk_set_rate(clk[IMX6QDL_CLK_ENET_REF], 125000000);
+ /* Set enet_ref clock to 125M to supply for RGMII tx_clk */
+ imx_clk_set_rate(clk[IMX6QDL_CLK_ENET_REF], 125000000);
+ np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-fec");
+ if (np) {
+ u32 clock_frequency;
+ int ret;
+ ret = of_property_read_u32(np, "ref-clock",
&clock_frequency);
+ if (ret == 0) {
+ printk("ref-clock: %d\n", clock_frequency);
+ imx_clk_set_rate(clk[IMX6QDL_CLK_ENET_REF],
clock_frequency);
+ }
+ }
+ // This clock may be needed very early on
+ imx_clk_prepare_enable(clk[IMX6QDL_CLK_ENET_REF]);
#ifdef CONFIG_MX6_VPU_352M
/*
Hope this helps.
Have a great week everyone,
Nikolay
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