[meta-freescale] Is there lcd support for imx6dl in kernel 3.17?

[Stefan]

I'm trying to enable seiko_wvga on wandboard, but am quite puzzled about
the correct approach doing it.

What I tried, was to add a display node (claavga from imx51-babbage.dts
with few changes),
enable ldb, and add the pincontrolgroup pinctrl_ipu1_1, which was part of
imx6qdl.dtsi in linux-imx 3.10.17

The result in dmesg looks like it wasn't possible to find a display:

imx-parallel-display display at di0: adding component (ops imx_pd_ops)
imx-ldb 2000000.aips-bus:ldb at 020e0008: adding component (ops imx_ldb_ops)
imx-ipuv3-crtc imx-ipuv3-crtc.0: adding component (ops ipu_crtc_ops)
imx-ipuv3-crtc imx-ipuv3-crtc.1: adding component (ops ipu_crtc_ops)
[drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
[drm] No driver support for vblank timestamp query.
imx-drm display-subsystem: bound imx-ipuv3-crtc.0 (ops ipu_crtc_ops)
imx-drm display-subsystem: bound imx-ipuv3-crtc.1 (ops ipu_crtc_ops)
imx-drm display-subsystem: No connectors reported connected with modes

Is this approach somehow in the correct direction or am I missing something
substantial?

Is lcdif meant to be outdated and parallel-display is the suggested
replacement?
Also is it supposed to work without a drm driver like etnaviv?

               display1: display at di0 {
                compatible = "fsl,imx-parallel-display";
                interface-pix-fmt = "rgb565";
                pinctrl-names = "default";
                pinctrl-0 = <&pinctrl_ipu1_1>;
                status = "ok";
                display-timings {
                        native-mode = <&timing1>;
                        timing1: claawvga {
                                clock-frequency = <27000000>;
                                hactive = <800>;
...
                                pixelclk-active = <0>;
                        };
                };

                port {
                        display1_in: endpoint {
                                remote-endpoint = <&ipu1_di0_lvds0>;
                        };
                };
        };



&ldb {
       status = "okay";
};


                pinctrl_ipu1_1: ipu1grp-1 {
                        fsl,pins = <
                                MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK
0x10
                                MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15
0x10
...
                                MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23
0x10
                        >;
                };
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