[meta-freescale] [meta-fsl-arm-extra][PATCH v3 4/4] cgtqmx6: Remove old files
Alex de Cabo
alejandro.de-cabo-garcia at congatec.com
Thu Aug 21 07:12:33 PDT 2014
Remove old recipes and patches that are not used.
Signed-off-by: Alex de Cabo <alejandro.de-cabo-garcia at congatec.com>
---
...Add-uboot-support-for-congatec-qmx6-board.patch | 3932 -----------
recipes-bsp/u-boot/u-boot-imx_2009.08.bbappend | 7 -
...pport-for-congatec-evaluation-board-qmx6q.patch | 7213 --------------------
...Fix-getrusage-related-build-failure-on-gl.patch | 43 -
...fix-memset-related-crashes-caused-by-rece.patch | 259 -
.../0003-ARM-7670-1-fix-the-memset-fix.patch | 87 -
...6-Fix-build-break-when-CONFIG_CLK_DEBUG-i.patch | 43 -
...0005-ENGR00271359-Add-Multi-touch-support.patch | 98 -
.../0006-Add-support-for-DVI-monitors.patch | 227 -
...0-gpu-viante-4.6.9p13-kernel-part-integra.patch | 6261 -----------------
.../linux/linux-congatec-3.0.35/defconfig | 2684 --------
...m-vivante-Add-00-sufix-in-returned-bus-Id.patch | 31 -
...-Rename-mxcfb_epdc_kernel.h-to-mxc_epdc.h.patch | 143 -
recipes-kernel/linux/linux-congatec_3.0.35.bb | 26 -
14 files changed, 21054 deletions(-)
delete mode 100644 recipes-bsp/u-boot/u-boot-imx/cgtqmx6/0001-Add-uboot-support-for-congatec-qmx6-board.patch
delete mode 100644 recipes-bsp/u-boot/u-boot-imx_2009.08.bbappend
delete mode 100644 recipes-kernel/linux/linux-congatec-3.0.35/0001-Add-linux-support-for-congatec-evaluation-board-qmx6q.patch
delete mode 100644 recipes-kernel/linux/linux-congatec-3.0.35/0001-perf-tools-Fix-getrusage-related-build-failure-on-gl.patch
delete mode 100644 recipes-kernel/linux/linux-congatec-3.0.35/0002-ARM-7668-1-fix-memset-related-crashes-caused-by-rece.patch
delete mode 100644 recipes-kernel/linux/linux-congatec-3.0.35/0003-ARM-7670-1-fix-the-memset-fix.patch
delete mode 100644 recipes-kernel/linux/linux-congatec-3.0.35/0004-ENGR00271136-Fix-build-break-when-CONFIG_CLK_DEBUG-i.patch
delete mode 100644 recipes-kernel/linux/linux-congatec-3.0.35/0005-ENGR00271359-Add-Multi-touch-support.patch
delete mode 100644 recipes-kernel/linux/linux-congatec-3.0.35/0006-Add-support-for-DVI-monitors.patch
delete mode 100644 recipes-kernel/linux/linux-congatec-3.0.35/ENGR00278350-gpu-viante-4.6.9p13-kernel-part-integra.patch
delete mode 100644 recipes-kernel/linux/linux-congatec-3.0.35/defconfig
delete mode 100644 recipes-kernel/linux/linux-congatec-3.0.35/drm-vivante-Add-00-sufix-in-returned-bus-Id.patch
delete mode 100644 recipes-kernel/linux/linux-congatec-3.0.35/epdc-Rename-mxcfb_epdc_kernel.h-to-mxc_epdc.h.patch
delete mode 100644 recipes-kernel/linux/linux-congatec_3.0.35.bb
diff --git a/recipes-bsp/u-boot/u-boot-imx/cgtqmx6/0001-Add-uboot-support-for-congatec-qmx6-board.patch b/recipes-bsp/u-boot/u-boot-imx/cgtqmx6/0001-Add-uboot-support-for-congatec-qmx6-board.patch
deleted file mode 100644
index c8dceb2..0000000
--- a/recipes-bsp/u-boot/u-boot-imx/cgtqmx6/0001-Add-uboot-support-for-congatec-qmx6-board.patch
+++ /dev/null
@@ -1,3932 +0,0 @@
-From a58f89ba75334edcb1759fa174a4d56afe1b55ce Mon Sep 17 00:00:00 2001
-From: Leo Sartre <lsartre at adeneo-embedded.com>
-Date: Wed, 29 May 2013 11:03:07 +0200
-Subject: [PATCH] Add support for congatec qmx6 board
-
-Add support for the Congatec Qseven evaluation board, the patch was
-originally written by Congatec Team, some minor changes and cleanup
-were applied to make it work with the new Freescale BSP 4.0.
----
- Makefile | 10 +
- board/freescale/cgt_qmx6/Makefile | 51 +
- board/freescale/cgt_qmx6/cgt_qmx6.c | 1726 ++++++++++++++++++++++
- board/freescale/cgt_qmx6/config.mk | 7 +
- board/freescale/cgt_qmx6/flash_header.S | 202 +++
- board/freescale/cgt_qmx6/flash_header_pn016101.S | 202 +++
- board/freescale/cgt_qmx6/flash_header_pn016104.S | 202 +++
- board/freescale/cgt_qmx6/lowlevel_init.S | 167 +++
- board/freescale/cgt_qmx6/u-boot.lds | 74 +
- common/cmd_mii.c | 17 +
- drivers/mtd/spi/imx_spi_nor_sst.c | 24 +-
- include/asm-arm/mach-types.h | 13 +
- include/configs/cgt_qmx6.h | 364 +++++
- include/configs/cgt_qmx6_android.h | 360 +++++
- include/configs/cgt_qmx6_mfg.h | 320 ++++
- localversion-qmx6 | 1 +
- 16 files changed, 3737 insertions(+), 3 deletions(-)
- create mode 100644 board/freescale/cgt_qmx6/Makefile
- create mode 100644 board/freescale/cgt_qmx6/cgt_qmx6.c
- create mode 100644 board/freescale/cgt_qmx6/config.mk
- create mode 100644 board/freescale/cgt_qmx6/flash_header.S
- create mode 100644 board/freescale/cgt_qmx6/flash_header_pn016101.S
- create mode 100644 board/freescale/cgt_qmx6/flash_header_pn016104.S
- create mode 100644 board/freescale/cgt_qmx6/lowlevel_init.S
- create mode 100644 board/freescale/cgt_qmx6/u-boot.lds
- create mode 100644 include/configs/cgt_qmx6.h
- create mode 100644 include/configs/cgt_qmx6_android.h
- create mode 100644 include/configs/cgt_qmx6_mfg.h
- create mode 100644 localversion-qmx6
-
-diff --git a/Makefile b/Makefile
-index 17c21cd..47e6cbe 100644
---- a/Makefile
-+++ b/Makefile
-@@ -3205,6 +3205,15 @@ apollon_config : unconfig
- @$(MKCONFIG) $(@:_config=) arm arm1136 apollon NULL omap24xx
- @echo "CONFIG_ONENAND_U_BOOT = y" >> $(obj)include/config.mk
-
-+cgt_qmx6_android_config \
-+cgt_qmx6_mfg_config \
-+cgt_qmx6_config : unconfig
-+ @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 cgt_qmx6 freescale mx6
-+ @if [ ! "$(shell sed -n '/^#define CONFIG_QMX6_PN0161/p' include/configs/$(@:_config=).h)" ] ; then \
-+ echo "ERROR: No CONFIG_QMX6_PN0161xx entry found." ; \
-+ echo "Please enable product specific configuration in configuration file!" ; \
-+ fi
-+
- mx23_evk_config : unconfig
- @$(MKCONFIG) $(@:_config=) arm arm926ejs mx23_evk freescale mx23
-
-@@ -3838,6 +3847,7 @@ grsim_leon2_config : unconfig
- #########################################################################
-
- clean:
-+ @rm -f $(obj)board/freescale/cgt_qmx6/flash_header.S
- @rm -f $(obj)examples/standalone/82559_eeprom \
- $(obj)examples/standalone/eepro100_eeprom \
- $(obj)examples/standalone/hello_world \
-diff --git a/board/freescale/cgt_qmx6/Makefile b/board/freescale/cgt_qmx6/Makefile
-new file mode 100644
-index 0000000..fa5e709
---- /dev/null
-+++ b/board/freescale/cgt_qmx6/Makefile
-@@ -0,0 +1,51 @@
-+#
-+# (C) Copyright 2011 Freescale Semiconductor, Inc.
-+#
-+# This program is free software; you can redistribute it and/or
-+# modify it under the terms of the GNU General Public License as
-+# published by the Free Software Foundation; either version 2 of
-+# the License, or (at your option) any later version.
-+#
-+# This program is distributed in the hope that it will be useful,
-+# but WITHOUT ANY WARRANTY; without even the implied warranty of
-+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+# GNU General Public License for more details.
-+#
-+# You should have received a copy of the GNU General Public License
-+# along with this program; if not, write to the Free Software
-+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+# MA 02111-1307 USA
-+#
-+
-+include $(TOPDIR)/config.mk
-+
-+LIB = $(obj)lib$(BOARD).a
-+
-+COBJS := $(BOARD).o
-+SOBJS := lowlevel_init.o flash_header.o
-+
-+
-+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-+OBJS := $(addprefix $(obj),$(COBJS))
-+SOBJS := $(addprefix $(obj),$(SOBJS))
-+
-+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
-+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
-+
-+flash_header.S: flash_header_pn$(CONFIG_QMX6_PN).S
-+ cp flash_header_pn$(CONFIG_QMX6_PN).S flash_header.S
-+
-+clean:
-+ rm -f $(SOBJS) $(OBJS) flash_header.S
-+
-+distclean: clean
-+ rm -f $(LIB) core *.bak .depend
-+
-+#########################################################################
-+
-+# defines $(obj).depend target
-+include $(SRCTREE)/rules.mk
-+
-+sinclude $(obj).depend
-+
-+#########################################################################
-diff --git a/board/freescale/cgt_qmx6/cgt_qmx6.c b/board/freescale/cgt_qmx6/cgt_qmx6.c
-new file mode 100644
-index 0000000..2f47e7e
---- /dev/null
-+++ b/board/freescale/cgt_qmx6/cgt_qmx6.c
-@@ -0,0 +1,1726 @@
-+/*
-+ * Copyright (C) 2011-2012 Freescale Semiconductor, Inc.
-+ *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ */
-+
-+#include <common.h>
-+#include <asm/io.h>
-+#include <asm/arch/mx6.h>
-+#include <asm/arch/mx6_pins.h>
-+
-+#if defined(CONFIG_SECURE_BOOT)
-+#include <asm/arch/mx6_secure.h>
-+#endif
-+#include <asm/arch/mx6dl_pins.h>
-+#include <asm/arch/iomux-v3.h>
-+#include <asm/arch/regs-anadig.h>
-+#include <asm/errno.h>
-+#ifdef CONFIG_MXC_FEC
-+#include <miiphy.h>
-+#endif
-+#if defined(CONFIG_VIDEO_MX5)
-+#include <asm/imx_pwm.h>
-+#include <linux/list.h>
-+#include <linux/fb.h>
-+#include <linux/mxcfb.h>
-+#include <ipu.h>
-+#include <lcd.h>
-+#endif
-+
-+#ifdef CONFIG_IMX_ECSPI
-+#include <imx_spi.h>
-+#endif
-+
-+#if CONFIG_I2C_MXC
-+#include <i2c.h>
-+#endif
-+
-+#ifdef CONFIG_CMD_MMC
-+#include <mmc.h>
-+#include <fsl_esdhc.h>
-+#endif
-+
-+#ifdef CONFIG_ARCH_MMU
-+#include <asm/mmu.h>
-+#include <asm/arch/mmu.h>
-+#endif
-+
-+#ifdef CONFIG_CMD_CLOCK
-+#include <asm/clock.h>
-+#endif
-+
-+#ifdef CONFIG_CMD_IMXOTP
-+#include <imx_otp.h>
-+#endif
-+
-+#ifdef CONFIG_MXC_GPIO
-+#include <asm/gpio.h>
-+#include <asm/arch/gpio.h>
-+#endif
-+#ifdef CONFIG_ANDROID_RECOVERY
-+#include <recovery.h>
-+#endif
-+
-+#ifdef CONFIG_DWC_AHSATA
-+#include <ahci.h>
-+#endif
-+DECLARE_GLOBAL_DATA_PTR;
-+
-+static enum boot_device boot_dev;
-+
-+void set_gpio_output_val(unsigned base, unsigned mask, unsigned val)
-+{
-+ unsigned reg = readl(base + GPIO_DR);
-+ if (val & 1)
-+ reg |= mask; /* set high */
-+ else
-+ reg &= ~mask; /* clear low */
-+ writel(reg, base + GPIO_DR);
-+
-+ reg = readl(base + GPIO_GDIR);
-+ reg |= mask; /* configure GPIO line as output */
-+ writel(reg, base + GPIO_GDIR);
-+}
-+
-+extern int sata_curr_device;
-+
-+#ifdef CONFIG_VIDEO_MX5
-+extern unsigned char fsl_bmp_reversed_600x400[];
-+extern int fsl_bmp_reversed_600x400_size;
-+extern int g_ipu_hw_rev;
-+
-+#if defined(CONFIG_BMP_8BPP)
-+unsigned short colormap[256];
-+#elif defined(CONFIG_BMP_16BPP)
-+unsigned short colormap[65536];
-+#else
-+unsigned short colormap[16777216];
-+#endif
-+
-+static struct pwm_device pwm0 = {
-+ .pwm_id = 3,
-+ .pwmo_invert = 0,
-+};
-+
-+static int di = 1;
-+
-+extern int ipuv3_fb_init(struct fb_videomode *mode, int di,
-+ int interface_pix_fmt,
-+ ipu_di_clk_parent_t di_clk_parent,
-+ int di_clk_val);
-+
-+static struct fb_videomode lvds_xga = {
-+ "XGA", 60, 1024, 768, 15385, 220, 40, 21, 7, 60, 10,
-+ FB_SYNC_EXT,
-+ FB_VMODE_NONINTERLACED,
-+ 0,
-+};
-+
-+vidinfo_t panel_info;
-+#endif
-+
-+static inline void setup_boot_device(void)
-+{
-+ uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
-+ uint bt_mem_ctl = (soc_sbmr & 0x000000FF) >> 4 ;
-+ uint bt_mem_type = (soc_sbmr & 0x00000008) >> 3;
-+
-+ switch (bt_mem_ctl) {
-+ case 0x0:
-+ if (bt_mem_type)
-+ boot_dev = ONE_NAND_BOOT;
-+ else
-+ boot_dev = WEIM_NOR_BOOT;
-+ break;
-+ case 0x2:
-+ boot_dev = SATA_BOOT;
-+ break;
-+ case 0x3:
-+ if (bt_mem_type)
-+ boot_dev = I2C_BOOT;
-+ else
-+ boot_dev = SPI_NOR_BOOT;
-+ break;
-+ case 0x4:
-+ case 0x5:
-+ boot_dev = SD_BOOT;
-+ break;
-+ case 0x6:
-+ case 0x7:
-+ boot_dev = MMC_BOOT;
-+ break;
-+ case 0x8 ... 0xf:
-+ boot_dev = NAND_BOOT;
-+ break;
-+ default:
-+ boot_dev = UNKNOWN_BOOT;
-+ break;
-+ }
-+}
-+
-+enum boot_device get_boot_device(void)
-+{
-+ return boot_dev;
-+}
-+
-+u32 get_board_rev(void)
-+{
-+ return fsl_system_rev;
-+}
-+
-+#ifdef CONFIG_ARCH_MMU
-+void board_mmu_init(void)
-+{
-+ unsigned long ttb_base = PHYS_SDRAM_1 + 0x4000;
-+ unsigned long i;
-+
-+ /*
-+ * Set the TTB register
-+ */
-+ asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/);
-+
-+ /*
-+ * Set the Domain Access Control Register
-+ */
-+ i = ARM_ACCESS_DACR_DEFAULT;
-+ asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
-+
-+ /*
-+ * First clear all TT entries - ie Set them to Faulting
-+ */
-+ memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
-+ /* Actual Virtual Size Attributes Function */
-+ /* Base Base MB cached? buffered? access permissions */
-+ /* xxx00000 xxx00000 */
-+ X_ARM_MMU_SECTION(0x000, 0x000, 0x001,
-+ ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
-+ ARM_ACCESS_PERM_RW_RW); /* ROM, 1M */
-+ X_ARM_MMU_SECTION(0x001, 0x001, 0x008,
-+ ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
-+ ARM_ACCESS_PERM_RW_RW); /* 8M */
-+ X_ARM_MMU_SECTION(0x009, 0x009, 0x001,
-+ ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
-+ ARM_ACCESS_PERM_RW_RW); /* IRAM */
-+ X_ARM_MMU_SECTION(0x00A, 0x00A, 0x0F6,
-+ ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
-+ ARM_ACCESS_PERM_RW_RW); /* 246M */
-+
-+ #ifdef CONFIG_QMX6_PN016104
-+ /* 2 GB memory starting at 0x10000000, only map 1.875 GB */
-+ X_ARM_MMU_SECTION(0x100, 0x100, 0x780,
-+ ARM_CACHEABLE, ARM_BUFFERABLE,
-+ ARM_ACCESS_PERM_RW_RW);
-+ /* uncached alias of the same 1.875 GB memory */
-+ X_ARM_MMU_SECTION(0x100, 0x880, 0x780,
-+ ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
-+ ARM_ACCESS_PERM_RW_RW);
-+ #endif
-+
-+ #ifdef CONFIG_QMX6_PN016101
-+ /* 1 GB memory starting at 0x10000000, only map 0.875 GB */
-+ X_ARM_MMU_SECTION(0x100, 0x100, 0x380,
-+ ARM_CACHEABLE, ARM_BUFFERABLE,
-+ ARM_ACCESS_PERM_RW_RW);
-+ /* uncached alias of the same 0.875 GB memory */
-+ X_ARM_MMU_SECTION(0x100, 0x880, 0x380,
-+ ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
-+ ARM_ACCESS_PERM_RW_RW);
-+ #endif
-+
-+ /* Enable MMU */
-+ MMU_ON();
-+}
-+#endif
-+
-+#ifdef CONFIG_DWC_AHSATA
-+
-+#define ANATOP_PLL_LOCK 0x80000000
-+#define ANATOP_PLL_ENABLE_MASK 0x00002000
-+#define ANATOP_PLL_BYPASS_MASK 0x00010000
-+#define ANATOP_PLL_LOCK 0x80000000
-+#define ANATOP_PLL_PWDN_MASK 0x00001000
-+#define ANATOP_PLL_HOLD_RING_OFF_MASK 0x00000800
-+#define ANATOP_SATA_CLK_ENABLE_MASK 0x00100000
-+
-+/* Staggered Spin-up */
-+#define HOST_CAP_SSS (1 << 27)
-+/* host version register*/
-+#define HOST_VERSIONR 0xfc
-+#define PORT_SATA_SR 0x128
-+#define PORT_PHY_CTL 0x178
-+#define PORT_PHY_CTL_PDDQ_LOC 0x100000
-+
-+int sata_initialize(void)
-+{
-+ u32 reg = 0;
-+ u32 iterations = 1000000;
-+
-+ if (sata_curr_device == -1) {
-+ /* Make sure that the PDDQ mode is disabled. */
-+ reg = readl(SATA_ARB_BASE_ADDR + PORT_PHY_CTL);
-+ writel(reg & (~PORT_PHY_CTL_PDDQ_LOC),
-+ SATA_ARB_BASE_ADDR + PORT_PHY_CTL);
-+
-+ /* Reset HBA */
-+ writel(HOST_RESET, SATA_ARB_BASE_ADDR + HOST_CTL);
-+
-+ reg = 0;
-+ while (readl(SATA_ARB_BASE_ADDR + HOST_VERSIONR) == 0) {
-+ reg++;
-+ if (reg > 1000000)
-+ break;
-+ }
-+
-+ reg = readl(SATA_ARB_BASE_ADDR + HOST_CAP);
-+ if (!(reg & HOST_CAP_SSS)) {
-+ reg |= HOST_CAP_SSS;
-+ writel(reg, SATA_ARB_BASE_ADDR + HOST_CAP);
-+ }
-+
-+ reg = readl(SATA_ARB_BASE_ADDR + HOST_PORTS_IMPL);
-+ if (!(reg & 0x1))
-+ writel((reg | 0x1),
-+ SATA_ARB_BASE_ADDR + HOST_PORTS_IMPL);
-+
-+ /* Release resources when there is no device on the port */
-+ do {
-+ reg = readl(SATA_ARB_BASE_ADDR + PORT_SATA_SR) & 0xF;
-+ if ((reg & 0xF) == 0)
-+ iterations--;
-+ else
-+ break;
-+
-+ } while (iterations > 0);
-+ }
-+
-+ return __sata_initialize();
-+}
-+
-+int setup_sata(void)
-+{
-+ u32 reg = 0;
-+ s32 timeout = 100000;
-+
-+ /* Enable sata clock */
-+ reg = readl(CCM_BASE_ADDR + 0x7c); /* CCGR5 */
-+ reg |= 0x30;
-+ writel(reg, CCM_BASE_ADDR + 0x7c);
-+
-+ /* Enable PLLs */
-+ reg = readl(ANATOP_BASE_ADDR + 0xe0); /* ENET PLL */
-+ reg &= ~ANATOP_PLL_PWDN_MASK;
-+ writel(reg, ANATOP_BASE_ADDR + 0xe0);
-+ reg |= ANATOP_PLL_ENABLE_MASK;
-+ while (timeout--) {
-+ if (readl(ANATOP_BASE_ADDR + 0xe0) & ANATOP_PLL_LOCK)
-+ break;
-+ }
-+ if (timeout <= 0)
-+ return -1;
-+ reg &= ~ANATOP_PLL_BYPASS_MASK;
-+ writel(reg, ANATOP_BASE_ADDR + 0xe0);
-+ reg |= ANATOP_SATA_CLK_ENABLE_MASK;
-+ writel(reg, ANATOP_BASE_ADDR + 0xe0);
-+
-+ /* Enable sata phy */
-+ reg = readl(IOMUXC_BASE_ADDR + 0x34); /* GPR13 */
-+
-+ reg &= ~0x07ffffff;
-+ /*
-+ * rx_eq_val_0 = 5 [26:24]
-+ * los_lvl = 0x12 [23:19]
-+ * rx_dpll_mode_0 = 0x3 [18:16]
-+ * mpll_ss_en = 0x0 [14]
-+ * tx_atten_0 = 0x4 [13:11]
-+ * tx_boost_0 = 0x0 [10:7]
-+ * tx_lvl = 0x11 [6:2]
-+ * mpll_ck_off_b = 0x1 [1]
-+ * tx_edgerate_0 = 0x0 [0]
-+ * */
-+ reg |= 0x59124c6;
-+ writel(reg, IOMUXC_BASE_ADDR + 0x34);
-+
-+ if (sata_curr_device == -1) {
-+
-+ reg = readl(SATA_ARB_BASE_ADDR + PORT_PHY_CTL);
-+ writel(reg | PORT_PHY_CTL_PDDQ_LOC,
-+ SATA_ARB_BASE_ADDR + PORT_PHY_CTL);
-+ }
-+
-+ return 0;
-+}
-+#endif
-+
-+int dram_init(void)
-+{
-+ /*
-+ * Switch PL301_FAST2 to DDR Dual-channel mapping
-+ * however this block the boot up, temperory redraw
-+ */
-+ /*
-+ * u32 reg = 1;
-+ * writel(reg, GPV0_BASE_ADDR);
-+ */
-+
-+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-+
-+ return 0;
-+}
-+
-+static void setup_uart(void)
-+{
-+ /* UART1 & UART2 */
-+#if defined CONFIG_MX6Q
-+#ifndef CONFIG_QMX6_TRACE
-+ mxc_iomux_v3_setup_pad(MX6Q_PAD_CSI0_DAT10__UART1_TXD);
-+ mxc_iomux_v3_setup_pad(MX6Q_PAD_CSI0_DAT11__UART1_RXD);
-+#endif
-+ mxc_iomux_v3_setup_pad(MX6Q_PAD_EIM_D26__UART2_TXD);
-+ mxc_iomux_v3_setup_pad(MX6Q_PAD_EIM_D27__UART2_RXD);
-+#elif defined CONFIG_MX6DL
-+#ifndef CONFIG_QMX6_TRACE
-+ mxc_iomux_v3_setup_pad(MX6DL_PAD_CSI0_DAT10__UART1_TXD);
-+ mxc_iomux_v3_setup_pad(MX6DL_PAD_CSI0_DAT11__UART1_RXD);
-+#endif
-+ mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_D26__UART2_TXD);
-+ mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_D27__UART2_RXD);
-+#endif
-+}
-+
-+#ifdef CONFIG_VIDEO_MX5
-+void setup_lvds_poweron(void)
-+{
-+ int reg;
-+ /* enable LVDS VDD */
-+#if defined CONFIG_MX6Q
-+ mxc_iomux_v3_setup_pad(MX6Q_PAD_GPIO_7__GPIO_1_7);
-+#elif defined CONFIG_MX6DL
-+ mxc_iomux_v3_setup_pad(MX6DL_PAD_GPIO_7__GPIO_1_7);
-+#endif
-+ set_gpio_output_val(GPIO1_BASE_ADDR, (1 << 7), 1);
-+}
-+#endif
-+
-+#ifdef CONFIG_I2C_MXC
-+#define I2C1_SDA_GPIO3_28_BIT_MASK (1 << 28)
-+#define I2C1_SCL_GPIO3_21_BIT_MASK (1 << 21)
-+#define I2C2_SCL_GPIO4_12_BIT_MASK (1 << 12)
-+#define I2C2_SDA_GPIO4_13_BIT_MASK (1 << 13)
-+#define I2C3_SCL_GPIO1_3_BIT_MASK (1 << 3)
-+#define I2C3_SDA_GPIO1_6_BIT_MASK (1 << 6)
-+
-+
-+static void setup_i2c(unsigned int module_base)
-+{
-+ unsigned int reg;
-+
-+ switch (module_base) {
-+ case I2C1_BASE_ADDR:
-+ /* i2c1 SDA & CLK */
-+#if defined CONFIG_MX6Q
-+ mxc_iomux_v3_setup_pad(MX6Q_PAD_EIM_D28__I2C1_SDA);
-+ mxc_iomux_v3_setup_pad(MX6Q_PAD_EIM_D21__I2C1_SCL);
-+#elif defined CONFIG_MX6DL
-+ mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_D28__I2C1_SDA);
-+ mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_D21__I2C1_SCL);
-+#endif
-+
-+ /* Enable i2c clock */
-+ reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR2);
-+ reg |= 0xC0;
-+ writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR2);
-+ break;
-+
-+ case I2C2_BASE_ADDR:
-+ /* i2c2 SDA & CLK */
-+#if defined CONFIG_MX6Q
-+ mxc_iomux_v3_setup_pad(MX6Q_PAD_KEY_ROW3__I2C2_SDA);
-+ mxc_iomux_v3_setup_pad(MX6Q_PAD_KEY_COL3__I2C2_SCL);
-+#elif defined CONFIG_MX6DL
-+ mxc_iomux_v3_setup_pad(MX6DL_PAD_KEY_ROW3__I2C2_SDA);
-+ mxc_iomux_v3_setup_pad(MX6DL_PAD_KEY_COL3__I2C2_SCL);
-+#endif
-+
-+ /* Enable i2c clock */
-+ reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR2);
-+ reg |= 0x300;
-+ writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR2);
-+ break;
-+
-+ case I2C3_BASE_ADDR:
-+ /* i2c3 SDA & CLK */
-+#if defined CONFIG_MX6Q
-+ mxc_iomux_v3_setup_pad(MX6Q_PAD_GPIO_3__I2C3_SCL);
-+ mxc_iomux_v3_setup_pad(MX6Q_PAD_GPIO_6__I2C3_SDA);
-+#elif defined CONFIG_MX6DL
-+ mxc_iomux_v3_setup_pad(MX6DL_PAD_GPIO_3__I2C3_SCL);
-+ mxc_iomux_v3_setup_pad(MX6DL_PAD_GPIO_6__I2C3_SDA);
-+#endif
-+
-+ /* Enable i2c clock */
-+ reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR2);
-+ reg |= 0xC00;
-+ writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR2);
-+ break;
-+
-+ default:
-+ printf("Invalid I2C base: 0x%x\n", module_base);
-+ break;
-+ }
-+}
-+/* Note: udelay() is not accurate for i2c timing */
-+static void __udelay(int time)
-+{
-+ int i, j;
-+
-+ for (i = 0; i < time; i++) {
-+ for (j = 0; j < 200; j++) {
-+ asm("nop");
-+ asm("nop");
-+ }
-+ }
-+}
-+static void mx6q_i2c_gpio_scl_direction(int bus, int output)
-+{
-+ u32 reg;
-+
-+ switch (bus) {
-+ case 1:
-+#if defined CONFIG_MX6Q
-+ mxc_iomux_v3_setup_pad(MX6Q_PAD_EIM_D21__GPIO_3_21);
-+#elif defined CONFIG_MX6DL
-+ mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_D21__GPIO_3_21);
-+#endif
-+ reg = readl(GPIO3_BASE_ADDR + GPIO_GDIR);
-+ if (output)
-+ reg |= I2C1_SCL_GPIO3_21_BIT_MASK;
-+ else
-+ reg &= ~I2C1_SCL_GPIO3_21_BIT_MASK;
-+ writel(reg, GPIO3_BASE_ADDR + GPIO_GDIR);
-+ break;
-+
-+ case 2:
-+#if defined CONFIG_MX6Q
-+ mxc_iomux_v3_setup_pad(MX6Q_PAD_KEY_COL3__GPIO_4_12);
-+#elif defined CONFIG_MX6DL
-+ mxc_iomux_v3_setup_pad(MX6DL_PAD_KEY_COL3__GPIO_4_12);
-+#endif
-+ reg = readl(GPIO4_BASE_ADDR + GPIO_GDIR);
-+ if (output)
-+ reg |= I2C2_SCL_GPIO4_12_BIT_MASK;
-+ else
-+ reg &= ~I2C2_SCL_GPIO4_12_BIT_MASK;
-+ writel(reg, GPIO4_BASE_ADDR + GPIO_GDIR);
-+ break;
-+
-+ case 3:
-+#if defined CONFIG_MX6Q
-+ mxc_iomux_v3_setup_pad(MX6Q_PAD_GPIO_3__GPIO_1_3);
-+#elif defined CONFIG_MX6DL
-+ mxc_iomux_v3_setup_pad(MX6DL_PAD_GPIO_3__GPIO_1_3);
-+#endif
-+ reg = readl(GPIO1_BASE_ADDR + GPIO_GDIR);
-+ if (output)
-+ reg |= I2C3_SCL_GPIO1_3_BIT_MASK;
-+ else
-+ reg &= I2C3_SCL_GPIO1_3_BIT_MASK;
-+ writel(reg, GPIO1_BASE_ADDR + GPIO_GDIR);
-+ break;
-+ }
-+}
-+
-+/* set 1 to output, sent 0 to input */
-+static void mx6q_i2c_gpio_sda_direction(int bus, int output)
-+{
-+ u32 reg;
-+
-+ switch (bus) {
-+ case 1:
-+#if defined CONFIG_MX6Q
-+ mxc_iomux_v3_setup_pad(MX6Q_PAD_EIM_D28__GPIO_3_28);
-+#elif defined CONFIG_MX6DL
-+ mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_D28__GPIO_3_28);
-+#endif
-+ reg = readl(GPIO3_BASE_ADDR + GPIO_GDIR);
-+ if (output)
-+ reg |= I2C1_SDA_GPIO3_28_BIT_MASK;
-+ else
-+ reg &= ~I2C1_SDA_GPIO3_28_BIT_MASK;
-+ writel(reg, GPIO3_BASE_ADDR + GPIO_GDIR);
-+ break;
-+
-+ case 2:
-+#if defined CONFIG_MX6Q
-+ mxc_iomux_v3_setup_pad(MX6Q_PAD_KEY_ROW3__GPIO_4_13);
-+#elif defined CONFIG_MX6DL
-+ mxc_iomux_v3_setup_pad(MX6DL_PAD_KEY_ROW3__GPIO_4_13);
-+#endif
-+ reg = readl(GPIO4_BASE_ADDR + GPIO_GDIR);
-+ if (output)
-+ reg |= I2C2_SDA_GPIO4_13_BIT_MASK;
-+ else
-+ reg &= ~I2C2_SDA_GPIO4_13_BIT_MASK;
-+ writel(reg, GPIO4_BASE_ADDR + GPIO_GDIR);
-+ break;
-+
-+ case 3:
-+#if defined CONFIG_MX6Q
-+ mxc_iomux_v3_setup_pad(MX6Q_PAD_GPIO_6__GPIO_1_6);
-+#elif defined CONFIG_MX6DL
-+ mxc_iomux_v3_setup_pad(MX6DL_PAD_GPIO_6__GPIO_1_6);
-+#endif
-+ reg = readl(GPIO1_BASE_ADDR + GPIO_GDIR);
-+ if (output)
-+ reg |= I2C3_SDA_GPIO1_6_BIT_MASK;
-+ else
-+ reg &= ~I2C3_SDA_GPIO1_6_BIT_MASK;
-+ writel(reg, GPIO1_BASE_ADDR + GPIO_GDIR);
-+ break;
-+
-+ default:
-+ break;
-+ }
-+}
-+
-+/* set 1 to high 0 to low */
-+static void mx6q_i2c_gpio_scl_set_level(int bus, int high)
-+{
-+ u32 reg;
-+
-+ switch (bus) {
-+ case 1:
-+ reg = readl(GPIO3_BASE_ADDR + GPIO_DR);
-+ if (high)
-+ reg |= I2C1_SCL_GPIO3_21_BIT_MASK;
-+ else
-+ reg &= ~I2C1_SCL_GPIO3_21_BIT_MASK;
-+ writel(reg, GPIO3_BASE_ADDR + GPIO_DR);
-+ break;
-+ case 2:
-+ reg = readl(GPIO4_BASE_ADDR + GPIO_DR);
-+ if (high)
-+ reg |= I2C2_SCL_GPIO4_12_BIT_MASK;
-+ else
-+ reg &= ~I2C2_SCL_GPIO4_12_BIT_MASK;
-+ writel(reg, GPIO4_BASE_ADDR + GPIO_DR);
-+ break;
-+ case 3:
-+ reg = readl(GPIO1_BASE_ADDR + GPIO_DR);
-+ if (high)
-+ reg |= I2C3_SCL_GPIO1_3_BIT_MASK;
-+ else
-+ reg &= ~I2C3_SCL_GPIO1_3_BIT_MASK;
-+ writel(reg, GPIO1_BASE_ADDR + GPIO_DR);
-+ break;
-+ }
-+}
-+
-+/* set 1 to high 0 to low */
-+static void mx6q_i2c_gpio_sda_set_level(int bus, int high)
-+{
-+ u32 reg;
-+
-+ switch (bus) {
-+ case 1:
-+ reg = readl(GPIO3_BASE_ADDR + GPIO_DR);
-+ if (high)
-+ reg |= I2C1_SDA_GPIO3_28_BIT_MASK;
-+ else
-+ reg &= ~I2C1_SDA_GPIO3_28_BIT_MASK;
-+ writel(reg, GPIO3_BASE_ADDR + GPIO_DR);
-+ break;
-+ case 2:
-+ reg = readl(GPIO4_BASE_ADDR + GPIO_DR);
-+ if (high)
-+ reg |= I2C2_SDA_GPIO4_13_BIT_MASK;
-+ else
-+ reg &= ~I2C2_SDA_GPIO4_13_BIT_MASK;
-+ writel(reg, GPIO4_BASE_ADDR + GPIO_DR);
-+ break;
-+ case 3:
-+ reg = readl(GPIO1_BASE_ADDR + GPIO_DR);
-+ if (high)
-+ reg |= I2C3_SDA_GPIO1_6_BIT_MASK;
-+ else
-+ reg &= ~I2C3_SDA_GPIO1_6_BIT_MASK;
-+ writel(reg, GPIO1_BASE_ADDR + GPIO_DR);
-+ break;
-+ }
-+}
-+
-+static int mx6q_i2c_gpio_check_sda(int bus)
-+{
-+ u32 reg;
-+ int result = 0;
-+
-+ switch (bus) {
-+ case 1:
-+ reg = readl(GPIO3_BASE_ADDR + GPIO_PSR);
-+ result = !!(reg & I2C1_SDA_GPIO3_28_BIT_MASK);
-+ break;
-+ case 2:
-+ reg = readl(GPIO4_BASE_ADDR + GPIO_PSR);
-+ result = !!(reg & I2C2_SDA_GPIO4_13_BIT_MASK);
-+ break;
-+ case 3:
-+ reg = readl(GPIO1_BASE_ADDR + GPIO_PSR);
-+ result = !!(reg & I2C3_SDA_GPIO1_6_BIT_MASK);
-+ break;
-+ }
-+
-+ return result;
-+}
-+
-+ /* Random reboot cause i2c SDA low issue:
-+ * the i2c bus busy because some device pull down the I2C SDA
-+ * line. This happens when Host is reading some byte from slave, and
-+ * then host is reset/reboot. Since in this case, device is
-+ * controlling i2c SDA line, the only thing host can do this give the
-+ * clock on SCL and sending NAK, and STOP to finish this
-+ * transaction.
-+ *
-+ * How to fix this issue:
-+ * detect if the SDA was low on bus send 8 dummy clock, and 1
-+ * clock + NAK, and STOP to finish i2c transaction the pending
-+ * transfer.
-+ */
-+int i2c_bus_recovery(void)
-+{
-+ int i, bus, result = 0;
-+
-+ for (bus = 1; bus <= 3; bus++) {
-+ mx6q_i2c_gpio_sda_direction(bus, 0);
-+
-+ if (mx6q_i2c_gpio_check_sda(bus) == 0) {
-+ printf("i2c: I2C%d SDA is low, start i2c recovery...\n", bus);
-+ mx6q_i2c_gpio_scl_direction(bus, 1);
-+ mx6q_i2c_gpio_scl_set_level(bus, 1);
-+ __udelay(10000);
-+
-+ for (i = 0; i < 9; i++) {
-+ mx6q_i2c_gpio_scl_set_level(bus, 1);
-+ __udelay(5);
-+ mx6q_i2c_gpio_scl_set_level(bus, 0);
-+ __udelay(5);
-+ }
-+
-+ /* 9th clock here, the slave should already
-+ release the SDA, we can set SDA as high to
-+ a NAK.*/
-+ mx6q_i2c_gpio_sda_direction(bus, 1);
-+ mx6q_i2c_gpio_sda_set_level(bus, 1);
-+ __udelay(1); /* Pull up SDA first */
-+ mx6q_i2c_gpio_scl_set_level(bus, 1);
-+ __udelay(5); /* plus pervious 1 us */
-+ mx6q_i2c_gpio_scl_set_level(bus, 0);
-+ __udelay(5);
-+ mx6q_i2c_gpio_sda_set_level(bus, 0);
-+ __udelay(5);
-+ mx6q_i2c_gpio_scl_set_level(bus, 1);
-+ __udelay(5);
-+ /* Here: SCL is high, and SDA from low to high, it's a
-+ * stop condition */
-+ mx6q_i2c_gpio_sda_set_level(bus, 1);
-+ __udelay(5);
-+
-+ mx6q_i2c_gpio_sda_direction(bus, 0);
-+ if (mx6q_i2c_gpio_check_sda(bus) == 1)
-+ printf("I2C%d Recovery success\n", bus);
-+ else {
-+ printf("I2C%d Recovery failed, I2C1 SDA still low!!!\n", bus);
-+ result |= 1 << bus;
-+ }
-+ }
-+
-+ /* configure back to i2c */
-+ switch (bus) {
-+ case 1:
-+ setup_i2c(I2C1_BASE_ADDR);
-+ break;
-+ case 2:
-+ setup_i2c(I2C2_BASE_ADDR);
-+ break;
-+ case 3:
-+ setup_i2c(I2C3_BASE_ADDR);
-+ break;
-+ }
-+ }
-+
-+ return result;
-+}
-+
-+/* check and set PMIC value */
-+static int setup_pmic_reg(uint addr, uchar val)
-+{
-+ uchar rdval;
-+
-+ if (i2c_read(0x8, addr, 1, &rdval, 1)) {
-+ printf("%s:i2c_read:error\n", __func__);
-+ return -1;
-+ }
-+ else
-+ {
-+ if (rdval != val)
-+ {
-+ printf("Warning: adjusted PFUZE value reg: 0x%02x old: 0x%02x new:0x%02x\n",addr,rdval,val);
-+ if (i2c_write(0x8, addr, 1, &val, 1)) {
-+ printf("%s:i2c_write:error\n",__func__);
-+ return -1;
-+ }
-+ }
-+ }
-+ return 0;
-+}
-+
-+static int setup_pmic_voltages(void)
-+{
-+ unsigned char id1 = 0, id2 = 0, value = 0 ;
-+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-+ if (!i2c_probe(0x8)) {
-+ if (i2c_read(0x8, 0, 1, &id1, 1)) {
-+ printf("%s:i2c_read:error\n", __func__);
-+ return -1;
-+ }
-+ if (i2c_read(0x8, 3, 1, &id2, 1)) {
-+ printf("%s:i2c_read:error\n", __func__);
-+ return -1;
-+ }
-+ #if CONFIG_MX6_INTER_LDO_BYPASS
-+ /*VDDCORE 1.1V at 800Mhz: SW1AB*/
-+ value = 0x20;
-+ if (i2c_write(0x8, 0x20, 1, &value, 1)) {
-+ printf("%s:i2c_write:error SW1AB\n",__func__);
-+ return -1;
-+ }
-+ /*VDDSOC 1.2V : SW1C*/
-+ value = 0x24;
-+ if (i2c_write(0x8, 0x2e, 1, &value, 1)) {
-+ printf("%s:i2c_write:error SW1C\n",__func__);
-+ return -1;
-+ }
-+ /* Bypass the VDDSOC from Anatop */
-+ val = REG_RD(ANATOP_BASE_ADDR, HW_ANADIG_REG_CORE);
-+ val &= ~BM_ANADIG_REG_CORE_REG2_TRG;
-+ val |= BF_ANADIG_REG_CORE_REG2_TRG(0x1f);
-+ REG_WR(ANATOP_BASE_ADDR, HW_ANADIG_REG_CORE, val);
-+
-+ /* Bypass the VDDCORE from Anatop */
-+ val = REG_RD(ANATOP_BASE_ADDR, HW_ANADIG_REG_CORE);
-+ val &= ~BM_ANADIG_REG_CORE_REG0_TRG;
-+ val |= BF_ANADIG_REG_CORE_REG0_TRG(0x1f);
-+ REG_WR(ANATOP_BASE_ADDR, HW_ANADIG_REG_CORE, val);
-+
-+ /* Bypass the VDDPU from Anatop */
-+ val = REG_RD(ANATOP_BASE_ADDR, HW_ANADIG_REG_CORE);
-+ val &= ~BM_ANADIG_REG_CORE_REG1_TRG;
-+ val |= BF_ANADIG_REG_CORE_REG1_TRG(0x1f);
-+ REG_WR(ANATOP_BASE_ADDR, HW_ANADIG_REG_CORE, val);
-+
-+ /*clear PowerDown Enable bit of WDOG1_WMCR*/
-+ writew(0, WDOG1_BASE_ADDR + 0x08);
-+ printf("hw_anadig_reg_core=%x\n",
-+ REG_RD(ANATOP_BASE_ADDR, HW_ANADIG_REG_CORE));
-+ #endif
-+
-+ switch (id2)
-+ {
-+ case 0x01:
-+ /* GEN1 PMIC (default programming), set correct values for PHY, EMMC, DDR VTT */
-+ printf("PFUZE100 1st Gen detected (0x%x/0x%x)\n", id1, id2);
-+
-+ /* VGEN5, 1.8V phy power supply */
-+ value = 0x10;
-+ if (i2c_write(0x8, 0x70, 1, &value, 1)) {
-+ printf("%s:i2c_write:error VGEN5\n",__func__);
-+ return -1;
-+ }
-+ /* VGEN6, 1.8V emmc vccio power supply */
-+ value = 0x10;
-+ if (i2c_write(0x8, 0x71, 1, &value, 1)) {
-+ printf("%s:i2c_write:error VGEN6\n",__func__);
-+ return -1;
-+ }
-+ /* SW4, 0.75V DDR VTT */
-+ value = 0x0e;
-+ if (i2c_write(0x8, 0x4a, 1, &value, 1)) {
-+ printf("%s:i2c_write:error SW4\n",__func__);
-+ return -1;
-+ }
-+ break;
-+
-+ case 0x10:
-+ case 0x11:
-+ /* GEN2 PMIC (OTP programmed) - check correct settings */
-+ printf("PFUZE100 2nd Gen (OTP) detected (0x%x/0x%x)\n", id1, id2);
-+
-+ if (setup_pmic_reg(0x70, 0x10))
-+ return -1;
-+ if (setup_pmic_reg(0x71, 0x10))
-+ return -1;
-+ if (setup_pmic_reg(0x4a, 0x0e))
-+ return -1;
-+ break;
-+
-+ default:
-+ /* unknown PMIC */
-+ printf("unknown PFUZE100 detected (0x%x/0x%x)\n", id1, id2);
-+
-+ if (setup_pmic_reg(0x70, 0x10))
-+ return -1;
-+ if (setup_pmic_reg(0x71, 0x10))
-+ return -1;
-+ if (setup_pmic_reg(0x4a, 0x0e))
-+ return -1;
-+ break;
-+ }
-+ }
-+ return 0;
-+}
-+#endif
-+
-+#ifdef CONFIG_IMX_ECSPI
-+s32 spi_get_cfg(struct imx_spi_dev_t *dev)
-+{
-+ switch (dev->slave.cs) {
-+ case 0:
-+ /* SPI-NOR */
-+ dev->base = ECSPI1_BASE_ADDR;
-+ dev->freq = 25000000;
-+ dev->ss_pol = IMX_SPI_ACTIVE_LOW;
-+ dev->ss = 0;
-+ dev->fifo_sz = 64 * 4;
-+ dev->us_delay = 0;
-+ break;
-+ case 1:
-+ /* SPI-NOR */
-+ dev->base = ECSPI1_BASE_ADDR;
-+ dev->freq = 25000000;
-+ dev->ss_pol = IMX_SPI_ACTIVE_LOW;
-+ dev->ss = 1;
-+ dev->fifo_sz = 64 * 4;
-+ dev->us_delay = 0;
-+ break;
-+ default:
-+ printf("Invalid Bus ID!\n");
-+ }
-+
-+ return 0;
-+}
-+
-+void spi_io_init(struct imx_spi_dev_t *dev)
-+{
-+ u32 reg;
-+
-+ switch (dev->base) {
-+ case ECSPI1_BASE_ADDR:
-+ /* Enable clock */
-+ reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR1);
-+ reg |= 0x3;
-+ writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR1);
-+
-+ /* SCLK, MISO, MOSI */
-+#if defined CONFIG_MX6Q
-+ mxc_iomux_v3_setup_pad(MX6Q_PAD_EIM_D16__ECSPI1_SCLK);
-+ mxc_iomux_v3_setup_pad(MX6Q_PAD_EIM_D17__ECSPI1_MISO);
-+ mxc_iomux_v3_setup_pad(MX6Q_PAD_EIM_D18__ECSPI1_MOSI);
-+ if (dev->ss == 1)
-+ mxc_iomux_v3_setup_pad(MX6Q_PAD_EIM_D19__ECSPI1_SS1);
-+#elif defined CONFIG_MX6DL
-+ mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_D16__ECSPI1_SCLK);
-+ mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_D17__ECSPI1_MISO);
-+ mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_D18__ECSPI1_MOSI);
-+ if (dev->ss == 1)
-+ mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_D19__ECSPI1_SS1);
-+#endif
-+ break;
-+ case ECSPI2_BASE_ADDR:
-+ case ECSPI3_BASE_ADDR:
-+ /* ecspi2-3 fall through */
-+ break;
-+ default:
-+ break;
-+ }
-+}
-+#endif
-+
-+#ifdef CONFIG_NET_MULTI
-+int board_eth_init(bd_t *bis)
-+{
-+ int rc = -ENODEV;
-+ return rc;
-+}
-+#endif
-+
-+#ifdef CONFIG_CMD_MMC
-+
-+struct fsl_esdhc_cfg usdhc_cfg[4] = {
-+ {USDHC2_BASE_ADDR, 1, 1, 1, 0},
-+ {USDHC3_BASE_ADDR, 1, 1, 1, 0},
-+ {USDHC4_BASE_ADDR, 1, 1, 1, 0},
-+};
-+
-+#if defined CONFIG_MX6Q
-+iomux_v3_cfg_t usdhc1_pads[] = {
-+ MX6Q_PAD_SD1_CLK__USDHC1_CLK,
-+ MX6Q_PAD_SD1_CMD__USDHC1_CMD,
-+ MX6Q_PAD_SD1_DAT0__USDHC1_DAT0,
-+ MX6Q_PAD_SD1_DAT1__USDHC1_DAT1,
-+ MX6Q_PAD_SD1_DAT2__USDHC1_DAT2,
-+ MX6Q_PAD_SD1_DAT3__USDHC1_DAT3,
-+};
-+
-+iomux_v3_cfg_t usdhc2_pads[] = {
-+ MX6Q_PAD_SD2_CLK__USDHC2_CLK,
-+ MX6Q_PAD_SD2_CMD__USDHC2_CMD,
-+ MX6Q_PAD_SD2_DAT0__USDHC2_DAT0,
-+ MX6Q_PAD_SD2_DAT1__USDHC2_DAT1,
-+ MX6Q_PAD_SD2_DAT2__USDHC2_DAT2,
-+ MX6Q_PAD_SD2_DAT3__USDHC2_DAT3,
-+};
-+
-+iomux_v3_cfg_t usdhc3_pads[] = {
-+ MX6Q_PAD_SD3_CLK__USDHC3_CLK,
-+ MX6Q_PAD_SD3_CMD__USDHC3_CMD,
-+ MX6Q_PAD_SD3_DAT0__USDHC3_DAT0,
-+ MX6Q_PAD_SD3_DAT1__USDHC3_DAT1,
-+ MX6Q_PAD_SD3_DAT2__USDHC3_DAT2,
-+ MX6Q_PAD_SD3_DAT3__USDHC3_DAT3,
-+ MX6Q_PAD_SD3_DAT4__USDHC3_DAT4,
-+ MX6Q_PAD_SD3_DAT5__USDHC3_DAT5,
-+ MX6Q_PAD_SD3_DAT6__USDHC3_DAT6,
-+ MX6Q_PAD_SD3_DAT7__USDHC3_DAT7,
-+ MX6Q_PAD_SD3_RST__USDHC3_RST,
-+};
-+
-+iomux_v3_cfg_t usdhc4_pads[] = {
-+ MX6Q_PAD_SD4_CLK__USDHC4_CLK,
-+ MX6Q_PAD_SD4_CMD__USDHC4_CMD,
-+ MX6Q_PAD_SD4_DAT0__USDHC4_DAT0,
-+ MX6Q_PAD_SD4_DAT1__USDHC4_DAT1,
-+ MX6Q_PAD_SD4_DAT2__USDHC4_DAT2,
-+ MX6Q_PAD_SD4_DAT3__USDHC4_DAT3,
-+ MX6Q_PAD_SD4_DAT4__USDHC4_DAT4,
-+ MX6Q_PAD_SD4_DAT5__USDHC4_DAT5,
-+ MX6Q_PAD_SD4_DAT6__USDHC4_DAT6,
-+ MX6Q_PAD_SD4_DAT7__USDHC4_DAT7,
-+};
-+#elif defined CONFIG_MX6DL
-+iomux_v3_cfg_t usdhc1_pads[] = {
-+ MX6DL_PAD_SD1_CLK__USDHC1_CLK,
-+ MX6DL_PAD_SD1_CMD__USDHC1_CMD,
-+ MX6DL_PAD_SD1_DAT0__USDHC1_DAT0,
-+ MX6DL_PAD_SD1_DAT1__USDHC1_DAT1,
-+ MX6DL_PAD_SD1_DAT2__USDHC1_DAT2,
-+ MX6DL_PAD_SD1_DAT3__USDHC1_DAT3,
-+};
-+
-+iomux_v3_cfg_t usdhc2_pads[] = {
-+ MX6DL_PAD_SD2_CLK__USDHC2_CLK,
-+ MX6DL_PAD_SD2_CMD__USDHC2_CMD,
-+ MX6DL_PAD_SD2_DAT0__USDHC2_DAT0,
-+ MX6DL_PAD_SD2_DAT1__USDHC2_DAT1,
-+ MX6DL_PAD_SD2_DAT2__USDHC2_DAT2,
-+ MX6DL_PAD_SD2_DAT3__USDHC2_DAT3,
-+};
-+
-+iomux_v3_cfg_t usdhc3_pads[] = {
-+ MX6DL_PAD_SD3_CLK__USDHC3_CLK,
-+ MX6DL_PAD_SD3_CMD__USDHC3_CMD,
-+ MX6DL_PAD_SD3_DAT0__USDHC3_DAT0,
-+ MX6DL_PAD_SD3_DAT1__USDHC3_DAT1,
-+ MX6DL_PAD_SD3_DAT2__USDHC3_DAT2,
-+ MX6DL_PAD_SD3_DAT3__USDHC3_DAT3,
-+ MX6DL_PAD_SD3_DAT4__USDHC3_DAT4,
-+ MX6DL_PAD_SD3_DAT5__USDHC3_DAT5,
-+ MX6DL_PAD_SD3_DAT6__USDHC3_DAT6,
-+ MX6DL_PAD_SD3_DAT7__USDHC3_DAT7,
-+ MX6DL_PAD_SD3_RST__USDHC3_RST,
-+};
-+
-+iomux_v3_cfg_t usdhc4_pads[] = {
-+ MX6DL_PAD_SD4_CLK__USDHC4_CLK,
-+ MX6DL_PAD_SD4_CMD__USDHC4_CMD,
-+ MX6DL_PAD_SD4_DAT0__USDHC4_DAT0,
-+ MX6DL_PAD_SD4_DAT1__USDHC4_DAT1,
-+ MX6DL_PAD_SD4_DAT2__USDHC4_DAT2,
-+ MX6DL_PAD_SD4_DAT3__USDHC4_DAT3,
-+ MX6DL_PAD_SD4_DAT4__USDHC4_DAT4,
-+ MX6DL_PAD_SD4_DAT5__USDHC4_DAT5,
-+ MX6DL_PAD_SD4_DAT6__USDHC4_DAT6,
-+ MX6DL_PAD_SD4_DAT7__USDHC4_DAT7,
-+};
-+#endif
-+
-+int usdhc_gpio_init(bd_t *bis)
-+{
-+ s32 status = 0;
-+ u32 index = 0;
-+
-+ for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM;
-+ ++index) {
-+ switch (index) {
-+ case 0:
-+ mxc_iomux_v3_setup_multiple_pads(usdhc3_pads,
-+ sizeof(usdhc3_pads) /
-+ sizeof(usdhc3_pads[0]));
-+ break;
-+ case 1:
-+ mxc_iomux_v3_setup_multiple_pads(usdhc4_pads,
-+ sizeof(usdhc4_pads) /
-+ sizeof(usdhc4_pads[0]));
-+ break;
-+ case 2:
-+ mxc_iomux_v3_setup_multiple_pads(usdhc2_pads,
-+ sizeof(usdhc2_pads) /
-+ sizeof(usdhc2_pads[0]));
-+ break;
-+ default:
-+ printf("Warning: you configured more USDHC controllers"
-+ "(%d) then supported by the board (%d)\n",
-+ index+1, CONFIG_SYS_FSL_USDHC_NUM);
-+ return status;
-+ }
-+ status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
-+ }
-+
-+ return status;
-+}
-+
-+int board_mmc_init(bd_t *bis)
-+{
-+ if (!usdhc_gpio_init(bis))
-+ return 0;
-+ else
-+ return -1;
-+}
-+
-+/* For DDR mode operation, provide target delay parameter for each SD port.
-+ * Use cfg->esdhc_base to distinguish the SD port #. The delay for each port
-+ * is dependent on signal layout for that particular port. If the following
-+ * CONFIG is not defined, then the default target delay value will be used.
-+ */
-+#ifdef CONFIG_GET_DDR_TARGET_DELAY
-+u32 get_ddr_delay(struct fsl_esdhc_cfg *cfg)
-+{
-+ /* No delay required */
-+ return 0;
-+}
-+#endif
-+
-+#endif
-+
-+#ifdef CONFIG_LCD
-+void lcd_enable(void)
-+{
-+ char *s;
-+ int ret;
-+ unsigned int reg;
-+
-+ s = getenv("lvds_num");
-+ di = simple_strtol(s, NULL, 10);
-+
-+ /*
-+ * hw_rev 2: IPUV3DEX
-+ * hw_rev 3: IPUV3M
-+ * hw_rev 4: IPUV3H
-+ */
-+ g_ipu_hw_rev = IPUV3_HW_REV_IPUV3H;
-+
-+ imx_pwm_config(pwm0, 25000, 50000);
-+ imx_pwm_enable(pwm0);
-+
-+ /* GPIO & PWM backlight */
-+#if defined CONFIG_MX6Q
-+ mxc_iomux_v3_setup_pad(MX6Q_PAD_SD1_DAT3__PWM1_PWMO);
-+ mxc_iomux_v3_setup_pad(MX6Q_PAD_GPIO_9__GPIO_1_9);
-+#elif defined CONFIG_MX6DL
-+ mxc_iomux_v3_setup_pad(MX6DL_PAD_SD1_DAT3__PWM1_PWMO);
-+ mxc_iomux_v3_setup_pad(MX6DL_PAD_GPIO_9__GPIO_1_9);
-+#endif
-+
-+ set_gpio_output_val(GPIO1_BASE_ADDR, (1 << 9), 1);
-+
-+#if defined CONFIG_MX6Q
-+ /*
-+ * Align IPU1 HSP clock and IPU1 DIx pixel clock
-+ * with kernel setting to avoid screen flick when
-+ * booting into kernel. Developer should change
-+ * the relevant setting if kernel setting changes.
-+ * IPU1 HSP clock tree:
-+ * osc_clk(24M)->pll2_528_bus_main_clk(528M)->
-+ * periph_clk(528M)->mmdc_ch0_axi_clk(528M)->
-+ * ipu1_clk(264M)
-+ */
-+ /* pll2_528_bus_main_clk */
-+ /* divider */
-+ writel(0x1, ANATOP_BASE_ADDR + 0x34);
-+
-+ /* periph_clk */
-+ /* source */
-+ reg = readl(CCM_BASE_ADDR + CLKCTL_CBCMR);
-+ reg &= ~(0x3 << 18);
-+ writel(reg, CCM_BASE_ADDR + CLKCTL_CBCMR);
-+
-+ reg = readl(CCM_BASE_ADDR + CLKCTL_CBCDR);
-+ reg &= ~(0x1 << 25);
-+ writel(reg, CCM_BASE_ADDR + CLKCTL_CBCDR);
-+
-+ /*
-+ * Check PERIPH_CLK_SEL_BUSY in
-+ * MXC_CCM_CDHIPR register.
-+ */
-+ do {
-+ udelay(5);
-+ reg = readl(CCM_BASE_ADDR + CLKCTL_CDHIPR);
-+ } while (reg & (0x1 << 5));
-+
-+ /* mmdc_ch0_axi_clk */
-+ /* divider */
-+ reg = readl(CCM_BASE_ADDR + CLKCTL_CBCDR);
-+ reg &= ~(0x7 << 19);
-+ writel(reg, CCM_BASE_ADDR + CLKCTL_CBCDR);
-+
-+ /*
-+ * Check MMDC_CH0PODF_BUSY in
-+ * MXC_CCM_CDHIPR register.
-+ */
-+ do {
-+ udelay(5);
-+ reg = readl(CCM_BASE_ADDR + CLKCTL_CDHIPR);
-+ } while (reg & (0x1 << 4));
-+
-+ /* ipu1_clk */
-+ reg = readl(CCM_BASE_ADDR + CLKCTL_CSCDR3);
-+ /* source */
-+ reg &= ~(0x3 << 9);
-+ /* divider */
-+ reg &= ~(0x7 << 11);
-+ reg |= (0x1 << 11);
-+ writel(reg, CCM_BASE_ADDR + CLKCTL_CSCDR3);
-+
-+ /*
-+ * ipu1_pixel_clk_x clock tree:
-+ * osc_clk(24M)->pll2_528_bus_main_clk(528M)->
-+ * pll2_pfd_352M(452.57M)->ldb_dix_clk(64.65M)->
-+ * ipu1_di_clk_x(64.65M)->ipu1_pixel_clk_x(64.65M)
-+ */
-+ /* pll2_pfd_352M */
-+ /* disable */
-+ writel(0x1 << 7, ANATOP_BASE_ADDR + 0x104);
-+ /* divider */
-+ writel(0x3F, ANATOP_BASE_ADDR + 0x108);
-+ writel(0x15, ANATOP_BASE_ADDR + 0x104);
-+
-+ /* ldb_dix_clk */
-+ /* source */
-+ reg = readl(CCM_BASE_ADDR + CLKCTL_CS2CDR);
-+ reg &= ~(0x3F << 9);
-+ reg |= (0x9 << 9);
-+ writel(reg, CCM_BASE_ADDR + CLKCTL_CS2CDR);
-+ /* divider */
-+ reg = readl(CCM_BASE_ADDR + CLKCTL_CSCMR2);
-+ reg |= (0x3 << 10);
-+ writel(reg, CCM_BASE_ADDR + CLKCTL_CSCMR2);
-+
-+ /* pll2_pfd_352M */
-+ /* enable after ldb_dix_clk source is set */
-+ writel(0x1 << 7, ANATOP_BASE_ADDR + 0x108);
-+
-+ /* ipu1_di_clk_x */
-+ /* source */
-+ reg = readl(CCM_BASE_ADDR + CLKCTL_CHSCCDR);
-+ reg &= ~0xE07;
-+ reg |= 0x803;
-+ writel(reg, CCM_BASE_ADDR + CLKCTL_CHSCCDR);
-+#elif defined CONFIG_MX6DL /* CONFIG_MX6Q */
-+ /*
-+ * IPU1 HSP clock tree:
-+ * osc_clk(24M)->pll3_usb_otg_main_clk(480M)->
-+ * pll3_pfd_540M(540M)->ipu1_clk(270M)
-+ */
-+ /* pll3_usb_otg_main_clk */
-+ /* divider */
-+ writel(0x3, ANATOP_BASE_ADDR + 0x18);
-+
-+ /* pll3_pfd_540M */
-+ /* divider */
-+ writel(0x3F << 8, ANATOP_BASE_ADDR + 0xF8);
-+ writel(0x10 << 8, ANATOP_BASE_ADDR + 0xF4);
-+ /* enable */
-+ writel(0x1 << 15, ANATOP_BASE_ADDR + 0xF8);
-+
-+ /* ipu1_clk */
-+ reg = readl(CCM_BASE_ADDR + CLKCTL_CSCDR3);
-+ /* source */
-+ reg |= (0x3 << 9);
-+ /* divider */
-+ reg &= ~(0x7 << 11);
-+ reg |= (0x1 << 11);
-+ writel(reg, CCM_BASE_ADDR + CLKCTL_CSCDR3);
-+
-+ /*
-+ * ipu1_pixel_clk_x clock tree:
-+ * osc_clk(24M)->pll2_528_bus_main_clk(528M)->
-+ * pll2_pfd_352M(452.57M)->ldb_dix_clk(64.65M)->
-+ * ipu1_di_clk_x(64.65M)->ipu1_pixel_clk_x(64.65M)
-+ */
-+ /* pll2_528_bus_main_clk */
-+ /* divider */
-+ writel(0x1, ANATOP_BASE_ADDR + 0x34);
-+
-+ /* pll2_pfd_352M */
-+ /* disable */
-+ writel(0x1 << 7, ANATOP_BASE_ADDR + 0x104);
-+ /* divider */
-+ writel(0x3F, ANATOP_BASE_ADDR + 0x108);
-+ writel(0x15, ANATOP_BASE_ADDR + 0x104);
-+
-+ /* ldb_dix_clk */
-+ /* source */
-+ reg = readl(CCM_BASE_ADDR + CLKCTL_CS2CDR);
-+ reg &= ~(0x3F << 9);
-+ reg |= (0x9 << 9);
-+ writel(reg, CCM_BASE_ADDR + CLKCTL_CS2CDR);
-+ /* divider */
-+ reg = readl(CCM_BASE_ADDR + CLKCTL_CSCMR2);
-+ reg |= (0x3 << 10);
-+ writel(reg, CCM_BASE_ADDR + CLKCTL_CSCMR2);
-+
-+ /* pll2_pfd_352M */
-+ /* enable after ldb_dix_clk source is set */
-+ writel(0x1 << 7, ANATOP_BASE_ADDR + 0x108);
-+
-+ /* ipu1_di_clk_x */
-+ /* source */
-+ reg = readl(CCM_BASE_ADDR + CLKCTL_CHSCCDR);
-+ reg &= ~0xE07;
-+ reg |= 0x803;
-+ writel(reg, CCM_BASE_ADDR + CLKCTL_CHSCCDR);
-+#endif /* CONFIG_MX6DL */
-+ if (di == 1) {
-+ reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR3);
-+ reg |= 0xC033;
-+ writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR3);
-+ } else {
-+ reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR3);
-+ reg |= 0x300F;
-+ writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR3);
-+ }
-+
-+ ret = ipuv3_fb_init(&lvds_xga, di, IPU_PIX_FMT_RGB666,
-+ DI_PCLK_LDB, 65000000);
-+ if (ret)
-+ puts("LCD cannot be configured\n");
-+
-+ /*
-+ * LVDS0 mux to IPU1 DI0.
-+ * LVDS1 mux to IPU1 DI1.
-+ */
-+ reg = readl(IOMUXC_BASE_ADDR + 0xC);
-+ reg &= ~(0x000003C0);
-+ reg |= 0x00000100;
-+ writel(reg, IOMUXC_BASE_ADDR + 0xC);
-+
-+ if (di == 1)
-+ writel(0x40C, IOMUXC_BASE_ADDR + 0x8);
-+ else
-+ writel(0x201, IOMUXC_BASE_ADDR + 0x8);
-+}
-+#endif
-+
-+#ifdef CONFIG_VIDEO_MX5
-+void panel_info_init(void)
-+{
-+ panel_info.vl_bpix = LCD_BPP;
-+ panel_info.vl_col = lvds_xga.xres;
-+ panel_info.vl_row = lvds_xga.yres;
-+ panel_info.cmap = colormap;
-+}
-+#endif
-+
-+#ifdef CONFIG_SPLASH_SCREEN
-+void setup_splash_image(void)
-+{
-+ char *s;
-+ ulong addr;
-+
-+ s = getenv("splashimage");
-+
-+ if (s != NULL) {
-+ addr = simple_strtoul(s, NULL, 16);
-+
-+#if defined(CONFIG_ARCH_MMU)
-+ addr = ioremap_nocache(iomem_to_phys(addr),
-+ fsl_bmp_reversed_600x400_size);
-+#endif
-+ memcpy((char *)addr, (char *)fsl_bmp_reversed_600x400,
-+ fsl_bmp_reversed_600x400_size);
-+ }
-+}
-+#endif
-+
-+int board_init(void)
-+{
-+/* need set Power Supply Glitch to 0x41736166
-+*and need clear Power supply Glitch Detect bit
-+* when POR or reboot or power on Otherwise system
-+*could not be power off anymore*/
-+ u32 reg;
-+ writel(0x41736166, SNVS_BASE_ADDR + 0x64);/*set LPPGDR*/
-+ udelay(10);
-+ reg = readl(SNVS_BASE_ADDR + 0x4c);
-+ reg |= (1 << 3);
-+ writel(reg, SNVS_BASE_ADDR + 0x4c);/*clear LPSR*/
-+
-+ mxc_iomux_v3_init((void *)IOMUXC_BASE_ADDR);
-+ setup_boot_device();
-+ fsl_set_system_rev();
-+
-+ /* board id for linux */
-+ gd->bd->bi_arch_number = MACH_TYPE_CGT_QMX6;
-+
-+ /* address of boot parameters */
-+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-+
-+ /* turn off backlight */
-+#if defined CONFIG_MX6Q
-+ mxc_iomux_v3_setup_pad(MX6Q_PAD_GPIO_9__GPIO_1_9);
-+#elif defined CONFIG_MX6DL
-+ mxc_iomux_v3_setup_pad(MX6DL_PAD_GPIO_9__GPIO_1_9);
-+#endif
-+ set_gpio_output_val(GPIO1_BASE_ADDR, (1 << 9), 0);
-+
-+ setup_uart();
-+
-+#ifdef CONFIG_DWC_AHSATA
-+ setup_sata();
-+#endif
-+
-+#ifdef CONFIG_VIDEO_MX5
-+ /* Enable lvds power */
-+ setup_lvds_poweron();
-+
-+ panel_info_init();
-+
-+ gd->fb_base = CONFIG_FB_BASE;
-+#ifdef CONFIG_ARCH_MMU
-+ gd->fb_base = ioremap_nocache(iomem_to_phys(gd->fb_base), 0);
-+#endif
-+#endif
-+
-+ return 0;
-+}
-+
-+
-+#ifdef CONFIG_ANDROID_RECOVERY
-+
-+int check_recovery_cmd_file(void)
-+{
-+ int button_pressed = 0;
-+ int recovery_mode = 0;
-+
-+ recovery_mode = check_and_clean_recovery_flag();
-+
-+ /* Check Recovery Combo Button press or not. */
-+#if defined CONFIG_MX6Q
-+ mxc_iomux_v3_setup_pad(MX6Q_PAD_GPIO_19__GPIO_4_5);
-+#elif defined CONFIG_MX6DL
-+ mxc_iomux_v3_setup_pad(MX6DL_PAD_GPIO_19__GPIO_4_5);
-+#endif
-+ reg = readl(GPIO4_BASE_ADDR + GPIO_GDIR);
-+ reg &= ~(1<<5);
-+ writel(reg, GPIO4_BASE_ADDR + GPIO_GDIR);
-+ reg = readl(GPIO4_BASE_ADDR + GPIO_PSR);
-+ if (!(reg & (1 << 5))) { /* VOL_DN key is low assert */
-+ button_pressed = 1;
-+ printf("Recovery key pressed\n");
-+ }
-+ return recovery_mode || button_pressed;
-+}
-+#endif
-+
-+int board_late_init(void)
-+{
-+ int ret = 0;
-+ #ifdef CONFIG_I2C_MXC
-+ setup_i2c(CONFIG_SYS_I2C_PORT);
-+ i2c_bus_recovery();
-+ ret = setup_pmic_voltages();
-+ if (ret)
-+ return -1;
-+ #endif
-+ return 0;
-+}
-+
-+#ifdef CONFIG_MXC_FEC
-+static int phy_read(char *devname, unsigned char addr, unsigned char reg,
-+ unsigned short *pdata)
-+{
-+ int ret = miiphy_read(devname, addr, reg, pdata);
-+ if (ret)
-+ printf("Error reading from %s PHY addr=%02x reg=%02x\n",
-+ devname, addr, reg);
-+ return ret;
-+}
-+
-+static int phy_write(char *devname, unsigned char addr, unsigned char reg,
-+ unsigned short value)
-+{
-+ int ret = miiphy_write(devname, addr, reg, value);
-+ if (ret)
-+ printf("Error writing to %s PHY addr=%02x reg=%02x\n", devname,
-+ addr, reg);
-+ return ret;
-+}
-+
-+int mx6_rgmii_rework(char *devname, int phy_addr)
-+{
-+ /* KSZ9031RN ethernet phy on rev. Y.0+ */
-+
-+ phy_write(devname, phy_addr, 0x0d, 2);
-+ phy_write(devname, phy_addr, 0x0e, 4);
-+ phy_write(devname, phy_addr, 0x0d, 0xc002);
-+ phy_write(devname, phy_addr, 0x0e, 0x0000);
-+
-+ phy_write(devname, phy_addr, 0x0d, 2);
-+ phy_write(devname, phy_addr, 0x0e, 5);
-+ phy_write(devname, phy_addr, 0x0d, 0xc002);
-+ phy_write(devname, phy_addr, 0x0e, 0x0000);
-+
-+ phy_write(devname, phy_addr, 0x0d, 2);
-+ phy_write(devname, phy_addr, 0x0e, 6);
-+ phy_write(devname, phy_addr, 0x0d, 0xc002);
-+ phy_write(devname, phy_addr, 0x0e, 0xFFFF);
-+
-+ phy_write(devname, phy_addr, 0x0d, 2);
-+ phy_write(devname, phy_addr, 0x0e, 8);
-+ phy_write(devname, phy_addr, 0x0d, 0xc002);
-+ phy_write(devname, phy_addr, 0x0e, 0x3FFF);
-+
-+ phy_write(devname, phy_addr, 0x0d, 0x0);
-+
-+ return 0;
-+}
-+#if defined CONFIG_MX6Q
-+iomux_v3_cfg_t enet_pads[] = {
-+ MX6Q_PAD_ENET_MDIO__ENET_MDIO,
-+ MX6Q_PAD_ENET_MDC__ENET_MDC,
-+ MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC,
-+ MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0,
-+ MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1,
-+ MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2,
-+ MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3,
-+ MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL,
-+ /* pin 35 - 1 (PHY_AD2) on reset */
-+ MX6Q_PAD_RGMII_RXC__GPIO_6_30,
-+ /* pin 32 - 1 - (MODE0) all */
-+ MX6Q_PAD_RGMII_RD0__GPIO_6_25,
-+ /* pin 31 - 1 - (MODE1) all */
-+ MX6Q_PAD_RGMII_RD1__GPIO_6_27,
-+ /* pin 28 - 1 - (MODE2) all */
-+ MX6Q_PAD_RGMII_RD2__GPIO_6_28,
-+ /* pin 27 - 1 - (MODE3) all */
-+ MX6Q_PAD_RGMII_RD3__GPIO_6_29,
-+ /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
-+ MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24,
-+ MX6Q_PAD_GPIO_0__CCM_CLKO,
-+ MX6Q_PAD_GPIO_3__CCM_CLKO2,
-+ MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK,
-+};
-+
-+iomux_v3_cfg_t enet_pads_final[] = {
-+ MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC,
-+ MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0,
-+ MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1,
-+ MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2,
-+ MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3,
-+ MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL,
-+};
-+#elif defined CONFIG_MX6DL
-+iomux_v3_cfg_t enet_pads[] = {
-+ MX6DL_PAD_ENET_MDIO__ENET_MDIO,
-+ MX6DL_PAD_ENET_MDC__ENET_MDC,
-+ MX6DL_PAD_RGMII_TXC__ENET_RGMII_TXC,
-+ MX6DL_PAD_RGMII_TD0__ENET_RGMII_TD0,
-+ MX6DL_PAD_RGMII_TD1__ENET_RGMII_TD1,
-+ MX6DL_PAD_RGMII_TD2__ENET_RGMII_TD2,
-+ MX6DL_PAD_RGMII_TD3__ENET_RGMII_TD3,
-+ MX6DL_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL,
-+ /* pin 35 - 1 (PHY_AD2) on reset */
-+ MX6DL_PAD_RGMII_RXC__GPIO_6_30,
-+ /* pin 32 - 1 - (MODE0) all */
-+ MX6DL_PAD_RGMII_RD0__GPIO_6_25,
-+ /* pin 31 - 1 - (MODE1) all */
-+ MX6DL_PAD_RGMII_RD1__GPIO_6_27,
-+ /* pin 28 - 1 - (MODE2) all */
-+ MX6DL_PAD_RGMII_RD2__GPIO_6_28,
-+ /* pin 27 - 1 - (MODE3) all */
-+ MX6DL_PAD_RGMII_RD3__GPIO_6_29,
-+ /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
-+ MX6DL_PAD_RGMII_RX_CTL__GPIO_6_24,
-+ MX6DL_PAD_GPIO_0__CCM_CLKO,
-+ MX6DL_PAD_GPIO_3__CCM_CLKO2,
-+ MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK,
-+};
-+
-+iomux_v3_cfg_t enet_pads_final[] = {
-+ MX6DL_PAD_RGMII_RXC__ENET_RGMII_RXC,
-+ MX6DL_PAD_RGMII_RD0__ENET_RGMII_RD0,
-+ MX6DL_PAD_RGMII_RD1__ENET_RGMII_RD1,
-+ MX6DL_PAD_RGMII_RD2__ENET_RGMII_RD2,
-+ MX6DL_PAD_RGMII_RD3__ENET_RGMII_RD3,
-+ MX6DL_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL,
-+};
-+#endif
-+
-+void enet_board_init(void)
-+{
-+ unsigned int reg;
-+#if defined CONFIG_MX6Q
-+ iomux_v3_cfg_t enet_reset =
-+ (MX6Q_PAD_EIM_D23__GPIO_3_23 &
-+ ~MUX_PAD_CTRL_MASK) | MUX_PAD_CTRL(0x48);
-+#elif defined CONFIG_MX6DL
-+ iomux_v3_cfg_t enet_reset =
-+ (MX6DL_PAD_EIM_D23__GPIO_3_23 &
-+ ~MUX_PAD_CTRL_MASK) | MUX_PAD_CTRL(0x48);
-+#endif
-+
-+ /* phy reset: gpio3-23 */
-+ set_gpio_output_val(GPIO3_BASE_ADDR, (1 << 23), 0);
-+ set_gpio_output_val(GPIO6_BASE_ADDR, (1 << 30),
-+ (CONFIG_FEC0_PHY_ADDR >> 2));
-+ set_gpio_output_val(GPIO6_BASE_ADDR, (1 << 25), 1);
-+ set_gpio_output_val(GPIO6_BASE_ADDR, (1 << 27), 1);
-+ set_gpio_output_val(GPIO6_BASE_ADDR, (1 << 28), 1);
-+ set_gpio_output_val(GPIO6_BASE_ADDR, (1 << 29), 1);
-+ mxc_iomux_v3_setup_multiple_pads(enet_pads,
-+ ARRAY_SIZE(enet_pads));
-+ mxc_iomux_v3_setup_pad(enet_reset);
-+ set_gpio_output_val(GPIO6_BASE_ADDR, (1 << 24), 1);
-+
-+ udelay(500);
-+ set_gpio_output_val(GPIO3_BASE_ADDR, (1 << 23), 1);
-+ mxc_iomux_v3_setup_multiple_pads(enet_pads_final,
-+ ARRAY_SIZE(enet_pads_final));
-+}
-+#endif
-+
-+int checkboard(void)
-+{
-+ printf("Board: %s-QMX6: Board: 0x%x [",
-+ mx6_chip_name(),
-+ fsl_system_rev);
-+
-+ switch (__REG(SRC_BASE_ADDR + 0x8)) {
-+ case 0x0001:
-+ printf("POR");
-+ break;
-+ case 0x0009:
-+ printf("RST");
-+ break;
-+ case 0x0010:
-+ case 0x0011:
-+ printf("WDOG");
-+ break;
-+ default:
-+ printf("unknown");
-+ }
-+ printf(" ]\n");
-+
-+ printf("Boot Device: ");
-+ switch (get_boot_device()) {
-+ case WEIM_NOR_BOOT:
-+ printf("NOR\n");
-+ break;
-+ case ONE_NAND_BOOT:
-+ printf("ONE NAND\n");
-+ break;
-+ case PATA_BOOT:
-+ printf("PATA\n");
-+ break;
-+ case SATA_BOOT:
-+ printf("SATA\n");
-+ break;
-+ case I2C_BOOT:
-+ printf("I2C\n");
-+ break;
-+ case SPI_NOR_BOOT:
-+ printf("SPI NOR\n");
-+ break;
-+ case SD_BOOT:
-+ printf("SD\n");
-+ break;
-+ case MMC_BOOT:
-+ printf("MMC\n");
-+ break;
-+ case NAND_BOOT:
-+ printf("NAND\n");
-+ break;
-+ case UNKNOWN_BOOT:
-+ default:
-+ printf("UNKNOWN\n");
-+ break;
-+ }
-+
-+#ifdef CONFIG_SECURE_BOOT
-+ if (check_hab_enable() == 1)
-+ get_hab_status();
-+#endif
-+
-+ return 0;
-+}
-+
-+
-+#ifdef CONFIG_IMX_UDC
-+void udc_pins_setting(void)
-+{
-+
-+#define GPIO_3_22_BIT_MASK (1<<22)
-+ u32 reg;
-+#if defined CONFIG_MX6Q
-+ mxc_iomux_v3_setup_pad(MX6Q_PAD_GPIO_1__USBOTG_ID);
-+#elif defined CONFIG_MX6DL
-+ mxc_iomux_v3_setup_pad(MX6DL_PAD_GPIO_1__USBOTG_ID);
-+#endif
-+
-+#ifdef CONFIG_USB_OTG_PWR
-+ /* USB_OTG_PWR */
-+#if defined CONFIG_MX6Q
-+ mxc_iomux_v3_setup_pad(MX6Q_PAD_EIM_D22__GPIO_3_22);
-+#elif defined CONFIG_MX6DL
-+ mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_D22__GPIO_3_22);
-+#endif
-+
-+ reg = readl(GPIO3_BASE_ADDR + GPIO_GDIR);
-+ /* set gpio_3_22 as output */
-+ reg |= GPIO_3_22_BIT_MASK;
-+ writel(reg, GPIO3_BASE_ADDR + GPIO_GDIR);
-+
-+ /* set USB_OTG_PWR to 0 */
-+ reg = readl(GPIO3_BASE_ADDR + GPIO_DR);
-+ reg &= ~GPIO_3_22_BIT_MASK;
-+ writel(reg, GPIO3_BASE_ADDR + GPIO_DR);
-+#endif
-+ /* USB_ID via GPIO_1 */
-+ mxc_iomux_set_gpr_register(1, 13, 1, 1);
-+}
-+#endif
-diff --git a/board/freescale/cgt_qmx6/config.mk b/board/freescale/cgt_qmx6/config.mk
-new file mode 100644
-index 0000000..a0ce2a1
---- /dev/null
-+++ b/board/freescale/cgt_qmx6/config.mk
-@@ -0,0 +1,7 @@
-+LDSCRIPT := $(SRCTREE)/board/$(VENDOR)/$(BOARD)/u-boot.lds
-+
-+sinclude $(OBJTREE)/board/$(VENDOR)/$(BOARD)/config.tmp
-+
-+ifndef TEXT_BASE
-+ TEXT_BASE = 0x27800000
-+endif
-diff --git a/board/freescale/cgt_qmx6/flash_header.S b/board/freescale/cgt_qmx6/flash_header.S
-new file mode 100644
-index 0000000..8bbef35
---- /dev/null
-+++ b/board/freescale/cgt_qmx6/flash_header.S
-@@ -0,0 +1,202 @@
-+/*
-+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ */
-+
-+#include <config.h>
-+#include <asm/arch/mx6.h>
-+
-+#ifdef CONFIG_FLASH_HEADER
-+#ifndef CONFIG_FLASH_HEADER_OFFSET
-+# error "Must define the offset of flash header"
-+#endif
-+
-+#define CPU_2_BE_32(l) \
-+ ((((l) & 0x000000FF) << 24) | \
-+ (((l) & 0x0000FF00) << 8) | \
-+ (((l) & 0x00FF0000) >> 8) | \
-+ (((l) & 0xFF000000) >> 24))
-+
-+#define MXC_DCD_ITEM(i, addr, val) \
-+dcd_node_##i: \
-+ .word CPU_2_BE_32(addr) ; \
-+ .word CPU_2_BE_32(val) ; \
-+
-+.section ".text.flasheader", "x"
-+ b _start
-+ .org CONFIG_FLASH_HEADER_OFFSET
-+
-+ivt_header: .word 0x402000D1 /* Tag=0xD1, Len=0x0020, Ver=0x40 */
-+app_code_jump_v: .word _start
-+reserv1: .word 0x0
-+dcd_ptr: .word dcd_hdr
-+boot_data_ptr: .word boot_data
-+self_ptr: .word ivt_header
-+app_code_csf: .word 0x0
-+reserv2: .word 0x0
-+
-+boot_data: .word TEXT_BASE
-+image_len: .word _end_of_copy - TEXT_BASE + CONFIG_FLASH_HEADER_OFFSET
-+plugin: .word 0x0
-+
-+dcd_hdr: .word 0x40F802D2 /* Tag=0xD2, Len=94*8 + 4 + 4, Ver=0x40 */
-+write_dcd_cmd: .word 0x04F402CC /* Tag=0xCC, Len=94*8 + 4, Param=0x04 */
-+
-+/* DCD */
-+
-+/* DDR IO TYPE */
-+MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x798, 0x000C0000)
-+MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x758, 0x00000000)
-+
-+/* clock */
-+MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x588, 0x00000030)
-+MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x594, 0x00000030)
-+
-+/* address */
-+MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x56c, 0x00000030)
-+MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x578, 0x00000030)
-+MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x74c, 0x00000030)
-+
-+/* control */
-+MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x57c, 0x00000030)
-+MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x590, 0x00003000)
-+MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x598, 0x00003000)
-+MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x58c, 0x00000000)
-+MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x59c, 0x00003030)
-+MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x5a0, 0x00003030)
-+MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x78c, 0x00000030)
-+
-+/* data strobe */
-+MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x750, 0x00020000)
-+
-+MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x5a8, 0x00000030)
-+MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x5b0, 0x00000030)
-+MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x524, 0x00000030)
-+MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x51c, 0x00000030)
-+MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x518, 0x00000030)
-+MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x50c, 0x00000030)
-+MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x5b8, 0x00000030)
-+MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x5c0, 0x00000030)
-+
-+/* data */
-+MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x774, 0x00020000)
-+
-+MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x784, 0x00000030)
-+MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x788, 0x00000030)
-+MXC_DCD_ITEM(27, IOMUXC_BASE_ADDR + 0x794, 0x00000030)
-+MXC_DCD_ITEM(28, IOMUXC_BASE_ADDR + 0x79c, 0x00000030)
-+MXC_DCD_ITEM(29, IOMUXC_BASE_ADDR + 0x7a0, 0x00000030)
-+MXC_DCD_ITEM(30, IOMUXC_BASE_ADDR + 0x7a4, 0x00000030)
-+MXC_DCD_ITEM(31, IOMUXC_BASE_ADDR + 0x7a8, 0x00000030)
-+MXC_DCD_ITEM(32, IOMUXC_BASE_ADDR + 0x748, 0x00000030)
-+
-+MXC_DCD_ITEM(33, IOMUXC_BASE_ADDR + 0x5ac, 0x00000030)
-+MXC_DCD_ITEM(34, IOMUXC_BASE_ADDR + 0x5b4, 0x00000030)
-+MXC_DCD_ITEM(35, IOMUXC_BASE_ADDR + 0x528, 0x00000030)
-+MXC_DCD_ITEM(36, IOMUXC_BASE_ADDR + 0x520, 0x00000030)
-+MXC_DCD_ITEM(37, IOMUXC_BASE_ADDR + 0x514, 0x00000030)
-+MXC_DCD_ITEM(38, IOMUXC_BASE_ADDR + 0x510, 0x00000030)
-+MXC_DCD_ITEM(39, IOMUXC_BASE_ADDR + 0x5bc, 0x00000030)
-+MXC_DCD_ITEM(40, IOMUXC_BASE_ADDR + 0x5c4, 0x00000030)
-+
-+/* calibrations */
-+/* ZQ */
-+MXC_DCD_ITEM(41, MMDC_P0_BASE_ADDR + 0x800, 0xA1390003)
-+MXC_DCD_ITEM(42, MMDC_P1_BASE_ADDR + 0x800, 0xA1390003)
-+
-+/* write leveling */
-+MXC_DCD_ITEM(43, MMDC_P0_BASE_ADDR + 0x80c, 0x001C001C)
-+MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x810, 0x0024001F)
-+
-+MXC_DCD_ITEM(45, MMDC_P1_BASE_ADDR + 0x80c, 0x001A0037)
-+MXC_DCD_ITEM(46, MMDC_P1_BASE_ADDR + 0x810, 0x001A002F)
-+
-+/* DQS gating, read delay, write delay calibration values based on calibration compare of 0x00ffff00 */
-+MXC_DCD_ITEM(47, MMDC_P0_BASE_ADDR + 0x83c, 0x43050315)
-+MXC_DCD_ITEM(48, MMDC_P0_BASE_ADDR + 0x840, 0x02720272)
-+MXC_DCD_ITEM(49, MMDC_P1_BASE_ADDR + 0x83c, 0x03220325)
-+MXC_DCD_ITEM(50, MMDC_P1_BASE_ADDR + 0x840, 0x0312026B)
-+
-+/* read calibration */
-+MXC_DCD_ITEM(51, MMDC_P0_BASE_ADDR + 0x848, 0x43393A3B)
-+MXC_DCD_ITEM(52, MMDC_P1_BASE_ADDR + 0x848, 0x3E433A43)
-+
-+/* write calibration */
-+MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x850, 0x47444C47)
-+MXC_DCD_ITEM(54, MMDC_P1_BASE_ADDR + 0x850, 0x4D334F46)
-+
-+/* read data bit delay: (3 is the recommended default value, although out of reset value is 0) */
-+MXC_DCD_ITEM(55, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333)
-+MXC_DCD_ITEM(56, MMDC_P0_BASE_ADDR + 0x820, 0x33333333)
-+MXC_DCD_ITEM(57, MMDC_P0_BASE_ADDR + 0x824, 0x33333333)
-+MXC_DCD_ITEM(58, MMDC_P0_BASE_ADDR + 0x828, 0x33333333)
-+MXC_DCD_ITEM(59, MMDC_P1_BASE_ADDR + 0x81c, 0x33333333)
-+MXC_DCD_ITEM(60, MMDC_P1_BASE_ADDR + 0x820, 0x33333333)
-+MXC_DCD_ITEM(61, MMDC_P1_BASE_ADDR + 0x824, 0x33333333)
-+MXC_DCD_ITEM(62, MMDC_P1_BASE_ADDR + 0x828, 0x33333333)
-+
-+/* complete calibration by forced measurment */
-+MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)
-+MXC_DCD_ITEM(64, MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800)
-+
-+/* MMDC init */
-+/* in DDR3, 64-bit mode, only MMDC0 is initiated */
-+MXC_DCD_ITEM(65, MMDC_P0_BASE_ADDR + 0x004, 0x00020036)
-+MXC_DCD_ITEM(66, MMDC_P0_BASE_ADDR + 0x008, 0x09444040)
-+MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x00c, 0x40445323)
-+MXC_DCD_ITEM(68, MMDC_P0_BASE_ADDR + 0x010, 0xB66E8C63)
-+MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x014, 0x01ff00db)
-+MXC_DCD_ITEM(70, MMDC_P0_BASE_ADDR + 0x018, 0x00091740)
-+
-+MXC_DCD_ITEM(71, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000)
-+
-+MXC_DCD_ITEM(72, MMDC_P0_BASE_ADDR + 0x02c, 0x000026d2)
-+MXC_DCD_ITEM(73, MMDC_P0_BASE_ADDR + 0x030, 0x005b0e21)
-+MXC_DCD_ITEM(74, MMDC_P0_BASE_ADDR + 0x040, 0x00000047)
-+
-+MXC_DCD_ITEM(75, MMDC_P0_BASE_ADDR + 0x000, 0x841A0000)
-+
-+/* Initialize 2GB DDR3 - Micron MT41J128M */
-+MXC_DCD_ITEM(76, MMDC_P0_BASE_ADDR + 0x01c, 0x04008032)
-+MXC_DCD_ITEM(77, MMDC_P0_BASE_ADDR + 0x01c, 0x0400803a)
-+MXC_DCD_ITEM(78, MMDC_P0_BASE_ADDR + 0x01c, 0x00008033)
-+MXC_DCD_ITEM(79, MMDC_P0_BASE_ADDR + 0x01c, 0x0000803b)
-+MXC_DCD_ITEM(80, MMDC_P0_BASE_ADDR + 0x01c, 0x00428031)
-+MXC_DCD_ITEM(81, MMDC_P0_BASE_ADDR + 0x01c, 0x00428039)
-+MXC_DCD_ITEM(82, MMDC_P0_BASE_ADDR + 0x01c, 0x07208030)
-+MXC_DCD_ITEM(83, MMDC_P0_BASE_ADDR + 0x01c, 0x07208038)
-+
-+/* DDR device ZQ calibration */
-+MXC_DCD_ITEM(84, MMDC_P0_BASE_ADDR + 0x01c, 0x04008040)
-+MXC_DCD_ITEM(85, MMDC_P0_BASE_ADDR + 0x01c, 0x04008048)
-+
-+/* final DDR setup, before operation start */
-+MXC_DCD_ITEM(86, MMDC_P0_BASE_ADDR + 0x020, 0x00005800)
-+MXC_DCD_ITEM(87, MMDC_P0_BASE_ADDR + 0x818, 0x00011117)
-+MXC_DCD_ITEM(88, MMDC_P1_BASE_ADDR + 0x818, 0x00011117)
-+
-+MXC_DCD_ITEM(89, MMDC_P0_BASE_ADDR + 0x004, 0x00025576)
-+MXC_DCD_ITEM(90, MMDC_P0_BASE_ADDR + 0x404, 0x00011006)
-+MXC_DCD_ITEM(91, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000)
-+
-+/* enable AXI cache for VDOA/VPU/IPU */
-+MXC_DCD_ITEM(92, IOMUXC_BASE_ADDR + 0x010, 0xf00000ff)
-+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-+MXC_DCD_ITEM(93, IOMUXC_BASE_ADDR + 0x018, 0x007f007f)
-+MXC_DCD_ITEM(94, IOMUXC_BASE_ADDR + 0x01c, 0x007f007f)
-+
-+#endif
-diff --git a/board/freescale/cgt_qmx6/flash_header_pn016101.S b/board/freescale/cgt_qmx6/flash_header_pn016101.S
-new file mode 100644
-index 0000000..1528d67
---- /dev/null
-+++ b/board/freescale/cgt_qmx6/flash_header_pn016101.S
-@@ -0,0 +1,202 @@
-+/*
-+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ */
-+
-+#include <config.h>
-+#include <asm/arch/mx6.h>
-+
-+#ifdef CONFIG_FLASH_HEADER
-+#ifndef CONFIG_FLASH_HEADER_OFFSET
-+# error "Must define the offset of flash header"
-+#endif
-+
-+#define CPU_2_BE_32(l) \
-+ ((((l) & 0x000000FF) << 24) | \
-+ (((l) & 0x0000FF00) << 8) | \
-+ (((l) & 0x00FF0000) >> 8) | \
-+ (((l) & 0xFF000000) >> 24))
-+
-+#define MXC_DCD_ITEM(i, addr, val) \
-+dcd_node_##i: \
-+ .word CPU_2_BE_32(addr) ; \
-+ .word CPU_2_BE_32(val) ; \
-+
-+.section ".text.flasheader", "x"
-+ b _start
-+ .org CONFIG_FLASH_HEADER_OFFSET
-+
-+ivt_header: .word 0x402000D1 /* Tag=0xD1, Len=0x0020, Ver=0x40 */
-+app_code_jump_v: .word _start
-+reserv1: .word 0x0
-+dcd_ptr: .word dcd_hdr
-+boot_data_ptr: .word boot_data
-+self_ptr: .word ivt_header
-+app_code_csf: .word 0x0
-+reserv2: .word 0x0
-+
-+boot_data: .word TEXT_BASE
-+image_len: .word _end_of_copy - TEXT_BASE + CONFIG_FLASH_HEADER_OFFSET
-+plugin: .word 0x0
-+
-+dcd_hdr: .word 0x40F802D2 /* Tag=0xD2, Len=94*8 + 4 + 4, Ver=0x40 */
-+write_dcd_cmd: .word 0x04F402CC /* Tag=0xCC, Len=94*8 + 4, Param=0x04 */
-+
-+/* DCD */
-+
-+/* DDR IO TYPE */
-+MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x798, 0x000C0000)
-+MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x758, 0x00000000)
-+
-+/* clock */
-+MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x588, 0x00000030)
-+MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x594, 0x00000030)
-+
-+/* address */
-+MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x56c, 0x00000030)
-+MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x578, 0x00000030)
-+MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x74c, 0x00000030)
-+
-+/* control */
-+MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x57c, 0x00000030)
-+MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x590, 0x00003000)
-+MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x598, 0x00003000)
-+MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x58c, 0x00000000)
-+MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x59c, 0x00003030)
-+MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x5a0, 0x00003030)
-+MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x78c, 0x00000030)
-+
-+/* data strobe */
-+MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x750, 0x00020000)
-+
-+MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x5a8, 0x00000030)
-+MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x5b0, 0x00000030)
-+MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x524, 0x00000030)
-+MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x51c, 0x00000030)
-+MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x518, 0x00000030)
-+MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x50c, 0x00000030)
-+MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x5b8, 0x00000030)
-+MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x5c0, 0x00000030)
-+
-+/* data */
-+MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x774, 0x00020000)
-+
-+MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x784, 0x00000030)
-+MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x788, 0x00000030)
-+MXC_DCD_ITEM(27, IOMUXC_BASE_ADDR + 0x794, 0x00000030)
-+MXC_DCD_ITEM(28, IOMUXC_BASE_ADDR + 0x79c, 0x00000030)
-+MXC_DCD_ITEM(29, IOMUXC_BASE_ADDR + 0x7a0, 0x00000030)
-+MXC_DCD_ITEM(30, IOMUXC_BASE_ADDR + 0x7a4, 0x00000030)
-+MXC_DCD_ITEM(31, IOMUXC_BASE_ADDR + 0x7a8, 0x00000030)
-+MXC_DCD_ITEM(32, IOMUXC_BASE_ADDR + 0x748, 0x00000030)
-+
-+MXC_DCD_ITEM(33, IOMUXC_BASE_ADDR + 0x5ac, 0x00000030)
-+MXC_DCD_ITEM(34, IOMUXC_BASE_ADDR + 0x5b4, 0x00000030)
-+MXC_DCD_ITEM(35, IOMUXC_BASE_ADDR + 0x528, 0x00000030)
-+MXC_DCD_ITEM(36, IOMUXC_BASE_ADDR + 0x520, 0x00000030)
-+MXC_DCD_ITEM(37, IOMUXC_BASE_ADDR + 0x514, 0x00000030)
-+MXC_DCD_ITEM(38, IOMUXC_BASE_ADDR + 0x510, 0x00000030)
-+MXC_DCD_ITEM(39, IOMUXC_BASE_ADDR + 0x5bc, 0x00000030)
-+MXC_DCD_ITEM(40, IOMUXC_BASE_ADDR + 0x5c4, 0x00000030)
-+
-+/* calibrations */
-+/* ZQ */
-+MXC_DCD_ITEM(41, MMDC_P0_BASE_ADDR + 0x800, 0xA1390003)
-+MXC_DCD_ITEM(42, MMDC_P1_BASE_ADDR + 0x800, 0xA1390003)
-+
-+/* write leveling */
-+MXC_DCD_ITEM(43, MMDC_P0_BASE_ADDR + 0x80c, 0x002C0030)
-+MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x810, 0x001C0022)
-+
-+MXC_DCD_ITEM(45, MMDC_P1_BASE_ADDR + 0x80c, 0x002E0031)
-+MXC_DCD_ITEM(46, MMDC_P1_BASE_ADDR + 0x810, 0x003A004A)
-+
-+/* DQS gating, read delay, write delay calibration values based on calibration compare of 0x00ffff00 */
-+MXC_DCD_ITEM(47, MMDC_P0_BASE_ADDR + 0x83c, 0x420A0207)
-+MXC_DCD_ITEM(48, MMDC_P0_BASE_ADDR + 0x840, 0x01710177)
-+MXC_DCD_ITEM(49, MMDC_P1_BASE_ADDR + 0x83c, 0x42160222)
-+MXC_DCD_ITEM(50, MMDC_P1_BASE_ADDR + 0x840, 0x02010213)
-+
-+/* read calibration */
-+MXC_DCD_ITEM(51, MMDC_P0_BASE_ADDR + 0x848, 0x484B4A48)
-+MXC_DCD_ITEM(52, MMDC_P1_BASE_ADDR + 0x848, 0x4B4F4C49)
-+
-+/* write calibration */
-+MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x850, 0x412A262B)
-+MXC_DCD_ITEM(54, MMDC_P1_BASE_ADDR + 0x850, 0x2E2F2F2C)
-+
-+/* read data bit delay: (3 is the recommended default value, although out of reset value is 0) */
-+MXC_DCD_ITEM(55, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333)
-+MXC_DCD_ITEM(56, MMDC_P0_BASE_ADDR + 0x820, 0x33333333)
-+MXC_DCD_ITEM(57, MMDC_P0_BASE_ADDR + 0x824, 0x33333333)
-+MXC_DCD_ITEM(58, MMDC_P0_BASE_ADDR + 0x828, 0x33333333)
-+MXC_DCD_ITEM(59, MMDC_P1_BASE_ADDR + 0x81c, 0x33333333)
-+MXC_DCD_ITEM(60, MMDC_P1_BASE_ADDR + 0x820, 0x33333333)
-+MXC_DCD_ITEM(61, MMDC_P1_BASE_ADDR + 0x824, 0x33333333)
-+MXC_DCD_ITEM(62, MMDC_P1_BASE_ADDR + 0x828, 0x33333333)
-+
-+/* complete calibration by forced measurment */
-+MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)
-+MXC_DCD_ITEM(64, MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800)
-+
-+/* MMDC init */
-+/* in DDR3, 64-bit mode, only MMDC0 is initiated */
-+MXC_DCD_ITEM(65, MMDC_P0_BASE_ADDR + 0x004, 0x00020036)
-+MXC_DCD_ITEM(66, MMDC_P0_BASE_ADDR + 0x008, 0x09444040)
-+MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x00c, 0x40445323)
-+MXC_DCD_ITEM(68, MMDC_P0_BASE_ADDR + 0x010, 0xB66E8C63)
-+MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x014, 0x01ff00db)
-+MXC_DCD_ITEM(70, MMDC_P0_BASE_ADDR + 0x018, 0x00081740)
-+
-+MXC_DCD_ITEM(71, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000)
-+
-+MXC_DCD_ITEM(72, MMDC_P0_BASE_ADDR + 0x02c, 0x000026d2)
-+MXC_DCD_ITEM(73, MMDC_P0_BASE_ADDR + 0x030, 0x005b0e21)
-+MXC_DCD_ITEM(74, MMDC_P0_BASE_ADDR + 0x040, 0x00000027)
-+
-+MXC_DCD_ITEM(75, MMDC_P0_BASE_ADDR + 0x000, 0x831A0000)
-+
-+/* Initialize 1GB DDR3 - Micron MT41J128M */
-+MXC_DCD_ITEM(76, MMDC_P0_BASE_ADDR + 0x01c, 0x04008032)
-+MXC_DCD_ITEM(77, MMDC_P0_BASE_ADDR + 0x01c, 0x0400803a)
-+MXC_DCD_ITEM(78, MMDC_P0_BASE_ADDR + 0x01c, 0x00008033)
-+MXC_DCD_ITEM(79, MMDC_P0_BASE_ADDR + 0x01c, 0x0000803b)
-+MXC_DCD_ITEM(80, MMDC_P0_BASE_ADDR + 0x01c, 0x00428031)
-+MXC_DCD_ITEM(81, MMDC_P0_BASE_ADDR + 0x01c, 0x00428039)
-+MXC_DCD_ITEM(82, MMDC_P0_BASE_ADDR + 0x01c, 0x09208030)
-+MXC_DCD_ITEM(83, MMDC_P0_BASE_ADDR + 0x01c, 0x09208038)
-+
-+/* DDR device ZQ calibration */
-+MXC_DCD_ITEM(84, MMDC_P0_BASE_ADDR + 0x01c, 0x04008040)
-+MXC_DCD_ITEM(85, MMDC_P0_BASE_ADDR + 0x01c, 0x04008048)
-+
-+/* final DDR setup, before operation start */
-+MXC_DCD_ITEM(86, MMDC_P0_BASE_ADDR + 0x020, 0x00005800)
-+MXC_DCD_ITEM(87, MMDC_P0_BASE_ADDR + 0x818, 0x00011117)
-+MXC_DCD_ITEM(88, MMDC_P1_BASE_ADDR + 0x818, 0x00011117)
-+
-+MXC_DCD_ITEM(89, MMDC_P0_BASE_ADDR + 0x004, 0x00025576)
-+MXC_DCD_ITEM(90, MMDC_P0_BASE_ADDR + 0x404, 0x00011006)
-+MXC_DCD_ITEM(91, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000)
-+
-+/* enable AXI cache for VDOA/VPU/IPU */
-+MXC_DCD_ITEM(92, IOMUXC_BASE_ADDR + 0x010, 0xf00000ff)
-+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-+MXC_DCD_ITEM(93, IOMUXC_BASE_ADDR + 0x018, 0x007f007f)
-+MXC_DCD_ITEM(94, IOMUXC_BASE_ADDR + 0x01c, 0x007f007f)
-+
-+#endif
-diff --git a/board/freescale/cgt_qmx6/flash_header_pn016104.S b/board/freescale/cgt_qmx6/flash_header_pn016104.S
-new file mode 100644
-index 0000000..8bbef35
---- /dev/null
-+++ b/board/freescale/cgt_qmx6/flash_header_pn016104.S
-@@ -0,0 +1,202 @@
-+/*
-+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ */
-+
-+#include <config.h>
-+#include <asm/arch/mx6.h>
-+
-+#ifdef CONFIG_FLASH_HEADER
-+#ifndef CONFIG_FLASH_HEADER_OFFSET
-+# error "Must define the offset of flash header"
-+#endif
-+
-+#define CPU_2_BE_32(l) \
-+ ((((l) & 0x000000FF) << 24) | \
-+ (((l) & 0x0000FF00) << 8) | \
-+ (((l) & 0x00FF0000) >> 8) | \
-+ (((l) & 0xFF000000) >> 24))
-+
-+#define MXC_DCD_ITEM(i, addr, val) \
-+dcd_node_##i: \
-+ .word CPU_2_BE_32(addr) ; \
-+ .word CPU_2_BE_32(val) ; \
-+
-+.section ".text.flasheader", "x"
-+ b _start
-+ .org CONFIG_FLASH_HEADER_OFFSET
-+
-+ivt_header: .word 0x402000D1 /* Tag=0xD1, Len=0x0020, Ver=0x40 */
-+app_code_jump_v: .word _start
-+reserv1: .word 0x0
-+dcd_ptr: .word dcd_hdr
-+boot_data_ptr: .word boot_data
-+self_ptr: .word ivt_header
-+app_code_csf: .word 0x0
-+reserv2: .word 0x0
-+
-+boot_data: .word TEXT_BASE
-+image_len: .word _end_of_copy - TEXT_BASE + CONFIG_FLASH_HEADER_OFFSET
-+plugin: .word 0x0
-+
-+dcd_hdr: .word 0x40F802D2 /* Tag=0xD2, Len=94*8 + 4 + 4, Ver=0x40 */
-+write_dcd_cmd: .word 0x04F402CC /* Tag=0xCC, Len=94*8 + 4, Param=0x04 */
-+
-+/* DCD */
-+
-+/* DDR IO TYPE */
-+MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x798, 0x000C0000)
-+MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x758, 0x00000000)
-+
-+/* clock */
-+MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x588, 0x00000030)
-+MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x594, 0x00000030)
-+
-+/* address */
-+MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x56c, 0x00000030)
-+MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x578, 0x00000030)
-+MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x74c, 0x00000030)
-+
-+/* control */
-+MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x57c, 0x00000030)
-+MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x590, 0x00003000)
-+MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x598, 0x00003000)
-+MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x58c, 0x00000000)
-+MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x59c, 0x00003030)
-+MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x5a0, 0x00003030)
-+MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x78c, 0x00000030)
-+
-+/* data strobe */
-+MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x750, 0x00020000)
-+
-+MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x5a8, 0x00000030)
-+MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x5b0, 0x00000030)
-+MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x524, 0x00000030)
-+MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x51c, 0x00000030)
-+MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x518, 0x00000030)
-+MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x50c, 0x00000030)
-+MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x5b8, 0x00000030)
-+MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x5c0, 0x00000030)
-+
-+/* data */
-+MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x774, 0x00020000)
-+
-+MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x784, 0x00000030)
-+MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x788, 0x00000030)
-+MXC_DCD_ITEM(27, IOMUXC_BASE_ADDR + 0x794, 0x00000030)
-+MXC_DCD_ITEM(28, IOMUXC_BASE_ADDR + 0x79c, 0x00000030)
-+MXC_DCD_ITEM(29, IOMUXC_BASE_ADDR + 0x7a0, 0x00000030)
-+MXC_DCD_ITEM(30, IOMUXC_BASE_ADDR + 0x7a4, 0x00000030)
-+MXC_DCD_ITEM(31, IOMUXC_BASE_ADDR + 0x7a8, 0x00000030)
-+MXC_DCD_ITEM(32, IOMUXC_BASE_ADDR + 0x748, 0x00000030)
-+
-+MXC_DCD_ITEM(33, IOMUXC_BASE_ADDR + 0x5ac, 0x00000030)
-+MXC_DCD_ITEM(34, IOMUXC_BASE_ADDR + 0x5b4, 0x00000030)
-+MXC_DCD_ITEM(35, IOMUXC_BASE_ADDR + 0x528, 0x00000030)
-+MXC_DCD_ITEM(36, IOMUXC_BASE_ADDR + 0x520, 0x00000030)
-+MXC_DCD_ITEM(37, IOMUXC_BASE_ADDR + 0x514, 0x00000030)
-+MXC_DCD_ITEM(38, IOMUXC_BASE_ADDR + 0x510, 0x00000030)
-+MXC_DCD_ITEM(39, IOMUXC_BASE_ADDR + 0x5bc, 0x00000030)
-+MXC_DCD_ITEM(40, IOMUXC_BASE_ADDR + 0x5c4, 0x00000030)
-+
-+/* calibrations */
-+/* ZQ */
-+MXC_DCD_ITEM(41, MMDC_P0_BASE_ADDR + 0x800, 0xA1390003)
-+MXC_DCD_ITEM(42, MMDC_P1_BASE_ADDR + 0x800, 0xA1390003)
-+
-+/* write leveling */
-+MXC_DCD_ITEM(43, MMDC_P0_BASE_ADDR + 0x80c, 0x001C001C)
-+MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x810, 0x0024001F)
-+
-+MXC_DCD_ITEM(45, MMDC_P1_BASE_ADDR + 0x80c, 0x001A0037)
-+MXC_DCD_ITEM(46, MMDC_P1_BASE_ADDR + 0x810, 0x001A002F)
-+
-+/* DQS gating, read delay, write delay calibration values based on calibration compare of 0x00ffff00 */
-+MXC_DCD_ITEM(47, MMDC_P0_BASE_ADDR + 0x83c, 0x43050315)
-+MXC_DCD_ITEM(48, MMDC_P0_BASE_ADDR + 0x840, 0x02720272)
-+MXC_DCD_ITEM(49, MMDC_P1_BASE_ADDR + 0x83c, 0x03220325)
-+MXC_DCD_ITEM(50, MMDC_P1_BASE_ADDR + 0x840, 0x0312026B)
-+
-+/* read calibration */
-+MXC_DCD_ITEM(51, MMDC_P0_BASE_ADDR + 0x848, 0x43393A3B)
-+MXC_DCD_ITEM(52, MMDC_P1_BASE_ADDR + 0x848, 0x3E433A43)
-+
-+/* write calibration */
-+MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x850, 0x47444C47)
-+MXC_DCD_ITEM(54, MMDC_P1_BASE_ADDR + 0x850, 0x4D334F46)
-+
-+/* read data bit delay: (3 is the recommended default value, although out of reset value is 0) */
-+MXC_DCD_ITEM(55, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333)
-+MXC_DCD_ITEM(56, MMDC_P0_BASE_ADDR + 0x820, 0x33333333)
-+MXC_DCD_ITEM(57, MMDC_P0_BASE_ADDR + 0x824, 0x33333333)
-+MXC_DCD_ITEM(58, MMDC_P0_BASE_ADDR + 0x828, 0x33333333)
-+MXC_DCD_ITEM(59, MMDC_P1_BASE_ADDR + 0x81c, 0x33333333)
-+MXC_DCD_ITEM(60, MMDC_P1_BASE_ADDR + 0x820, 0x33333333)
-+MXC_DCD_ITEM(61, MMDC_P1_BASE_ADDR + 0x824, 0x33333333)
-+MXC_DCD_ITEM(62, MMDC_P1_BASE_ADDR + 0x828, 0x33333333)
-+
-+/* complete calibration by forced measurment */
-+MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)
-+MXC_DCD_ITEM(64, MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800)
-+
-+/* MMDC init */
-+/* in DDR3, 64-bit mode, only MMDC0 is initiated */
-+MXC_DCD_ITEM(65, MMDC_P0_BASE_ADDR + 0x004, 0x00020036)
-+MXC_DCD_ITEM(66, MMDC_P0_BASE_ADDR + 0x008, 0x09444040)
-+MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x00c, 0x40445323)
-+MXC_DCD_ITEM(68, MMDC_P0_BASE_ADDR + 0x010, 0xB66E8C63)
-+MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x014, 0x01ff00db)
-+MXC_DCD_ITEM(70, MMDC_P0_BASE_ADDR + 0x018, 0x00091740)
-+
-+MXC_DCD_ITEM(71, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000)
-+
-+MXC_DCD_ITEM(72, MMDC_P0_BASE_ADDR + 0x02c, 0x000026d2)
-+MXC_DCD_ITEM(73, MMDC_P0_BASE_ADDR + 0x030, 0x005b0e21)
-+MXC_DCD_ITEM(74, MMDC_P0_BASE_ADDR + 0x040, 0x00000047)
-+
-+MXC_DCD_ITEM(75, MMDC_P0_BASE_ADDR + 0x000, 0x841A0000)
-+
-+/* Initialize 2GB DDR3 - Micron MT41J128M */
-+MXC_DCD_ITEM(76, MMDC_P0_BASE_ADDR + 0x01c, 0x04008032)
-+MXC_DCD_ITEM(77, MMDC_P0_BASE_ADDR + 0x01c, 0x0400803a)
-+MXC_DCD_ITEM(78, MMDC_P0_BASE_ADDR + 0x01c, 0x00008033)
-+MXC_DCD_ITEM(79, MMDC_P0_BASE_ADDR + 0x01c, 0x0000803b)
-+MXC_DCD_ITEM(80, MMDC_P0_BASE_ADDR + 0x01c, 0x00428031)
-+MXC_DCD_ITEM(81, MMDC_P0_BASE_ADDR + 0x01c, 0x00428039)
-+MXC_DCD_ITEM(82, MMDC_P0_BASE_ADDR + 0x01c, 0x07208030)
-+MXC_DCD_ITEM(83, MMDC_P0_BASE_ADDR + 0x01c, 0x07208038)
-+
-+/* DDR device ZQ calibration */
-+MXC_DCD_ITEM(84, MMDC_P0_BASE_ADDR + 0x01c, 0x04008040)
-+MXC_DCD_ITEM(85, MMDC_P0_BASE_ADDR + 0x01c, 0x04008048)
-+
-+/* final DDR setup, before operation start */
-+MXC_DCD_ITEM(86, MMDC_P0_BASE_ADDR + 0x020, 0x00005800)
-+MXC_DCD_ITEM(87, MMDC_P0_BASE_ADDR + 0x818, 0x00011117)
-+MXC_DCD_ITEM(88, MMDC_P1_BASE_ADDR + 0x818, 0x00011117)
-+
-+MXC_DCD_ITEM(89, MMDC_P0_BASE_ADDR + 0x004, 0x00025576)
-+MXC_DCD_ITEM(90, MMDC_P0_BASE_ADDR + 0x404, 0x00011006)
-+MXC_DCD_ITEM(91, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000)
-+
-+/* enable AXI cache for VDOA/VPU/IPU */
-+MXC_DCD_ITEM(92, IOMUXC_BASE_ADDR + 0x010, 0xf00000ff)
-+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-+MXC_DCD_ITEM(93, IOMUXC_BASE_ADDR + 0x018, 0x007f007f)
-+MXC_DCD_ITEM(94, IOMUXC_BASE_ADDR + 0x01c, 0x007f007f)
-+
-+#endif
-diff --git a/board/freescale/cgt_qmx6/lowlevel_init.S b/board/freescale/cgt_qmx6/lowlevel_init.S
-new file mode 100644
-index 0000000..4a31cb0
---- /dev/null
-+++ b/board/freescale/cgt_qmx6/lowlevel_init.S
-@@ -0,0 +1,167 @@
-+/*
-+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ */
-+
-+#include <config.h>
-+#include <asm/arch/mx6.h>
-+
-+/*
-+ Disable L2Cache because ROM turn it on when uboot use plug-in.
-+ If L2Cache is on default, there are cache coherence problem if kernel have
-+ not config L2Cache.
-+*/
-+.macro init_l2cc
-+ ldr r1, =0xa02000
-+ ldr r0, =0x0
-+ str r0, [r1, #0x100]
-+.endm /* init_l2cc */
-+
-+/* invalidate the D-CACHE */
-+.macro inv_dcache
-+ mov r0,#0
-+ mcr p15,2,r0,c0,c0,0 /* cache size selection register, select dcache */
-+ mrc p15,1,r0,c0,c0,0 /* cache size ID register */
-+ mov r0,r0,ASR #13
-+ ldr r3,=0xfff
-+ and r0,r0,r3
-+ cmp r0,#0x7f
-+ moveq r6,#0x1000
-+ beq size_done
-+ cmp r0,#0xff
-+ moveq r6,#0x2000
-+ movne r6,#0x4000
-+
-+size_done:
-+ mov r2,#0
-+ mov r3,#0x40000000
-+ mov r4,#0x80000000
-+ mov r5,#0xc0000000
-+
-+d_inv_loop:
-+ mcr p15,0,r2,c7,c6,2 /* invalidate dcache by set / way */
-+ mcr p15,0,r3,c7,c6,2 /* invalidate dcache by set / way */
-+ mcr p15,0,r4,c7,c6,2 /* invalidate dcache by set / way */
-+ mcr p15,0,r5,c7,c6,2 /* invalidate dcache by set / way */
-+ add r2,r2,#0x20
-+ add r3,r3,#0x20
-+ add r4,r4,#0x20
-+ add r5,r5,#0x20
-+
-+ cmp r2,r6
-+ bne d_inv_loop
-+.endm
-+
-+/* AIPS setup - Only setup MPROTx registers.
-+ * The PACR default values are good.*/
-+.macro init_aips
-+ /*
-+ * Set all MPROTx to be non-bufferable, trusted for R/W,
-+ * not forced to user-mode.
-+ */
-+ ldr r0, =AIPS1_ON_BASE_ADDR
-+ ldr r1, =0x77777777
-+ str r1, [r0, #0x0]
-+ str r1, [r0, #0x4]
-+ ldr r1, =0x0
-+ str r1, [r0, #0x40]
-+ str r1, [r0, #0x44]
-+ str r1, [r0, #0x48]
-+ str r1, [r0, #0x4C]
-+ str r1, [r0, #0x50]
-+
-+ ldr r0, =AIPS2_ON_BASE_ADDR
-+ ldr r1, =0x77777777
-+ str r1, [r0, #0x0]
-+ str r1, [r0, #0x4]
-+ ldr r1, =0x0
-+ str r1, [r0, #0x40]
-+ str r1, [r0, #0x44]
-+ str r1, [r0, #0x48]
-+ str r1, [r0, #0x4C]
-+ str r1, [r0, #0x50]
-+.endm /* init_aips */
-+
-+.macro setup_pll pll, freq
-+.endm
-+
-+.macro init_clock
-+
-+/* PLL1, PLL2, and PLL3 are enabled by ROM */
-+#ifdef CONFIG_PLL3
-+ /* enable PLL3 for UART */
-+ ldr r0, ANATOP_BASE_ADDR_W
-+
-+ /* power up PLL */
-+ ldr r1, [r0, #ANATOP_USB1]
-+ orr r1, r1, #0x1000
-+ str r1, [r0, #ANATOP_USB1]
-+
-+ /* enable PLL */
-+ ldr r1, [r0, #ANATOP_USB1]
-+ orr r1, r1, #0x2000
-+ str r1, [r0, #ANATOP_USB1]
-+
-+ /* wait PLL lock */
-+100:
-+ ldr r1, [r0, #ANATOP_USB1]
-+ mov r1, r1, lsr #31
-+ cmp r1, #0x1
-+ bne 100b
-+
-+ /* clear bypass bit */
-+ ldr r1, [r0, #ANATOP_USB1]
-+ and r1, r1, #0xfffeffff
-+ str r1, [r0, #ANATOP_USB1]
-+#endif
-+
-+ /* Restore the default values in the Gate registers */
-+ ldr r0, CCM_BASE_ADDR_W
-+ ldr r1, =0xC0003F
-+ str r1, [r0, #CLKCTL_CCGR0]
-+ ldr r1, =0x30FC00
-+ str r1, [r0, #CLKCTL_CCGR1]
-+ ldr r1, =0xFFFC000
-+ str r1, [r0, #CLKCTL_CCGR2]
-+ ldr r1, =0x3FF00000
-+ str r1, [r0, #CLKCTL_CCGR3]
-+ ldr r1, =0xFFF300
-+ str r1, [r0, #CLKCTL_CCGR4]
-+ ldr r1, =0xF0000C3
-+ str r1, [r0, #CLKCTL_CCGR5]
-+ ldr r1, =0x03FF
-+ str r1, [r0, #CLKCTL_CCGR6]
-+.endm
-+
-+.section ".text.init", "x"
-+
-+.globl lowlevel_init
-+lowlevel_init:
-+
-+ inv_dcache
-+
-+ init_l2cc
-+
-+ init_aips
-+
-+ init_clock
-+
-+ mov pc, lr
-+
-+/* Board level setting value */
-+ANATOP_BASE_ADDR_W: .word ANATOP_BASE_ADDR
-+CCM_BASE_ADDR_W: .word CCM_BASE_ADDR
-diff --git a/board/freescale/cgt_qmx6/u-boot.lds b/board/freescale/cgt_qmx6/u-boot.lds
-new file mode 100644
-index 0000000..28ee8e0
---- /dev/null
-+++ b/board/freescale/cgt_qmx6/u-boot.lds
-@@ -0,0 +1,74 @@
-+/*
-+ * January 2004 - Changed to support H4 device
-+ * Copyright (c) 2004 Texas Instruments
-+ *
-+ * (C) Copyright 2002
-+ * Gary Jennejohn, DENX Software Engineering, <gj at denx.de>
-+ *
-+ * (C) Copyright 2011 Freescale Semiconductor, Inc.
-+ *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ */
-+
-+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-+OUTPUT_ARCH(arm)
-+ENTRY(_start)
-+SECTIONS
-+{
-+ . = 0x00000000;
-+
-+ . = ALIGN(4);
-+ .text :
-+ {
-+ /* WARNING - the following is hand-optimized to fit within */
-+ /* the sector layout of our flash chips! XXX FIXME XXX */
-+ board/freescale/cgt_qmx6/flash_header.o (.text.flasheader)
-+ cpu/arm_cortexa8/start.o
-+ board/freescale/cgt_qmx6/libcgt_qmx6.a (.text)
-+ lib_arm/libarm.a (.text)
-+ net/libnet.a (.text)
-+ drivers/mtd/libmtd.a (.text)
-+ drivers/mmc/libmmc.a (.text)
-+
-+ . = DEFINED(env_offset) ? env_offset : .;
-+ common/env_embedded.o(.text)
-+
-+ *(.text)
-+ }
-+
-+ . = ALIGN(4);
-+ .rodata : { *(.rodata) }
-+
-+ . = ALIGN(4);
-+ .data : { *(.data) }
-+
-+ . = ALIGN(4);
-+ .got : { *(.got) }
-+
-+ . = .;
-+ __u_boot_cmd_start = .;
-+ .u_boot_cmd : { *(.u_boot_cmd) }
-+ __u_boot_cmd_end = .;
-+
-+ . = ALIGN(4);
-+ _end_of_copy = .; /* end_of ROM copy code here */
-+ __bss_start = .;
-+ .bss : { *(.bss) }
-+ _end = .;
-+}
-diff --git a/common/cmd_mii.c b/common/cmd_mii.c
-index 65e13c3..dfa45fe 100644
---- a/common/cmd_mii.c
-+++ b/common/cmd_mii.c
-@@ -300,12 +300,29 @@ int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
- unsigned short data;
- int rcode = 0;
- char *devname;
-+ struct eth_device *current;
-
- if (argc < 2) {
- cmd_usage(cmdtp);
- return 1;
- }
-
-+ current = eth_get_dev();
-+ if (!current) {
-+ puts ("No ethernet found.\n");
-+ return -1;
-+ }
-+
-+ if (current->state != ETH_STATE_ACTIVE)
-+ {
-+ eth_halt();
-+ eth_set_current();
-+ if (eth_init(NULL) < 0) {
-+ eth_halt();
-+ return(-1);
-+ }
-+ }
-+
- #if defined(CONFIG_MII_INIT)
- mii_init ();
- #endif
-diff --git a/drivers/mtd/spi/imx_spi_nor_sst.c b/drivers/mtd/spi/imx_spi_nor_sst.c
-index d484a51..19ba1bf 100644
---- a/drivers/mtd/spi/imx_spi_nor_sst.c
-+++ b/drivers/mtd/spi/imx_spi_nor_sst.c
-@@ -61,9 +61,9 @@ static const struct imx_spi_flash_params imx_spi_flash_table[] = {
- {
- .idcode1 = 0x25,
- .block_size = SZ_64K,
-- .block_count = 32,
-- .device_size = SZ_64K * 32,
-- .name = "SST25VF016B - 2MB",
-+ .block_count = 64,
-+ .device_size = SZ_64K * 64,
-+ .name = "SST25VF032B - 4MB",
- },
- };
-
-@@ -184,6 +184,15 @@ static int spi_nor_erase_block(struct spi_flash *flash,
- block_addr);
- return -1;
- }
-+
-+ #ifndef CONFIG_MFGAREA_UNPROTECT
-+ /* protect 16KB at the end of flash for manufacturing purpose */
-+ if ((addr + block_size) > (flash->size - 16*1024))
-+ {
-+ printf("Error - tried to erase reserved area\n");
-+ return -1;
-+ }
-+ #endif
-
- if (ENABLE_WRITE_STATUS(flash) != 0 ||
- spi_nor_write_status(flash, 0) != 0) {
-@@ -328,6 +337,15 @@ static int spi_nor_flash_write(struct spi_flash *flash, u32 offset,
- debug("%s(flash addr=0x%08x, ram=%p, len=0x%x)\n",
- __func__, offset, buf, len);
-
-+ #ifndef CONFIG_MFGAREA_UNPROTECT
-+ /* protect 16KB at the end of flash for manufacturing purpose */
-+ if ((d_addr + len) > (flash->size - 16*1024))
-+ {
-+ printf("Error - tried to write to reserved area\n");
-+ return -1;
-+ }
-+ #endif
-+
- if (ENABLE_WRITE_STATUS(flash) != 0 ||
- spi_nor_write_status(flash, 0) != 0) {
- printf("Error: %s: %d\n", __func__, __LINE__);
-diff --git a/include/asm-arm/mach-types.h b/include/asm-arm/mach-types.h
-index a1fee0e..06ec506 100644
---- a/include/asm-arm/mach-types.h
-+++ b/include/asm-arm/mach-types.h
-@@ -3259,6 +3259,7 @@ extern unsigned int __machine_arch_type;
- #define MACH_TYPE_MX6Q_ARM2 3837
- #define MACH_TYPE_MX6Q_SABRESD 3980
- #define MACH_TYPE_MX6SL_ARM2 4091
-+#define MACH_TYPE_CGT_QMX6 4122
- #define MACH_TYPE_MX6Q_HDMIDONGLE 4284
- #define MACH_TYPE_MX6SL_EVK 4307
-
-@@ -42214,6 +42215,18 @@ extern unsigned int __machine_arch_type;
- # define machine_is_mx6sl_evk() (0)
- #endif
-
-+#ifdef CONFIG_MACH_CGT_QMX6
-+# ifdef machine_arch_type
-+# undef machine_arch_type
-+# define machine_arch_type __machine_arch_type
-+# else
-+# define machine_arch_type MACH_TYPE_CGT_QMX6
-+# endif
-+# define machine_is_cgt_qmx6() (machine_arch_type == MACH_TYPE_CGT_QMX6)
-+#else
-+# define machine_is_cgt_qmx6() (0)
-+#endif
-+
- /*
- * These have not yet been registered
- */
-diff --git a/include/configs/cgt_qmx6.h b/include/configs/cgt_qmx6.h
-new file mode 100644
-index 0000000..fdfe5c1
---- /dev/null
-+++ b/include/configs/cgt_qmx6.h
-@@ -0,0 +1,364 @@
-+/*
-+ * Copyright (C) 2011-2012 Freescale Semiconductor, Inc.
-+ *
-+ * Configuration settings for the congatec QMX6 i.MX6 cpu module.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ */
-+
-+#ifndef __CONFIG_H
-+#define __CONFIG_H
-+
-+#include <asm/arch/mx6.h>
-+
-+/* congatec product selection */
-+/* uncomment one of the configuration switches below in order to build a bootloader for conga-QMX6 */
-+/* enabling CONFIG_QMX6_PN016104 builds a bootloader for conga-QMX6 module, part number 016104, equipped i.MX6 1GHz QuadCore, 2GByte onboard DDR3 memory */
-+/* enabling CONFIG_QMX6_PN016101 builds a bootloader for conga-QMX6 module, part number 016101, equipped i.MX6 1GHz DualCore Lite, 1GByte onboard DDR3 memory */
-+#define CONFIG_QMX6_PN016104
-+//#define CONFIG_QMX6_PN016101
-+
-+/* uncomment in order to build special trace version of bootloader */
-+// #define CONFIG_QMX6_TRACE
-+
-+ /* High Level Configuration Options */
-+#define CONFIG_ARMV7 /* This is armv7 Cortex-A9 CPU core */
-+#define CONFIG_MXC
-+
-+#ifdef CONFIG_QMX6_PN016101
-+#define CONFIG_QMX6_PN 016101
-+#define CONFIG_MX6DL
-+#endif
-+
-+#ifdef CONFIG_QMX6_PN016104
-+#define CONFIG_QMX6_PN 016104
-+#define CONFIG_MX6Q
-+#endif
-+
-+#define CONFIG_FLASH_HEADER
-+#define CONFIG_FLASH_HEADER_OFFSET 0x400
-+#define CONFIG_MX6_CLK32 32768
-+
-+#define CONFIG_SKIP_RELOCATE_UBOOT
-+
-+#define CONFIG_ARCH_CPU_INIT
-+#undef CONFIG_ARCH_MMU /* disable MMU first */
-+#define CONFIG_L2_OFF /* disable L2 cache first*/
-+
-+#define CONFIG_MX6_HCLK_FREQ 24000000
-+
-+#define CONFIG_DISPLAY_CPUINFO
-+#define CONFIG_DISPLAY_BOARDINFO
-+
-+#define CONFIG_SYS_64BIT_VSPRINTF
-+
-+#define BOARD_LATE_INIT
-+
-+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-+#define CONFIG_REVISION_TAG
-+#define CONFIG_SETUP_MEMORY_TAGS
-+#define CONFIG_INITRD_TAG
-+
-+/*
-+ * Size of malloc() pool
-+ */
-+#ifdef CONFIG_QMX6_PN016104
-+#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024)
-+#endif
-+#ifdef CONFIG_QMX6_PN016101
-+#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
-+#endif
-+/* size in bytes reserved for initial data */
-+#define CONFIG_SYS_GBL_DATA_SIZE 128
-+
-+/*
-+ * Hardware drivers
-+ */
-+#define CONFIG_MXC_UART
-+#define CONFIG_UART_BASE_ADDR UART2_BASE_ADDR
-+
-+/* allow to overwrite serial and ethaddr */
-+#define CONFIG_ENV_OVERWRITE
-+#define CONFIG_CONS_INDEX 1
-+#define CONFIG_BAUDRATE 115200
-+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
-+
-+/***********************************************************
-+ * Command definition
-+ ***********************************************************/
-+
-+#include <config_cmd_default.h>
-+
-+#define CONFIG_CMD_PING
-+#define CONFIG_CMD_DHCP
-+#define CONFIG_CMD_MII
-+#define CONFIG_CMD_NET
-+#define CONFIG_NET_RETRY_COUNT 100
-+#define CONFIG_NET_MULTI 1
-+#define CONFIG_BOOTP_SUBNETMASK
-+#define CONFIG_BOOTP_GATEWAY
-+#define CONFIG_BOOTP_DNS
-+
-+#define CONFIG_CMD_SPI
-+#define CONFIG_CMD_I2C
-+
-+/* Enable below configure when supporting nand */
-+
-+#define CONFIG_CMD_MMC
-+#define CONFIG_MMC_8BIT_PORTS 0x00000002
-+#define CONFIG_CMD_SF
-+#define CONFIG_CMD_ENV
-+#define CONFIG_CMD_REGUL
-+
-+#define CONFIG_CMD_CLOCK
-+#define CONFIG_REF_CLK_FREQ CONFIG_MX6_HCLK_FREQ
-+
-+#ifdef CONFIG_QMX6_PN016104
-+#define CONFIG_CMD_SATA
-+#endif
-+#undef CONFIG_CMD_IMLS
-+
-+#define CONFIG_CMD_IMX_DOWNLOAD_MODE
-+
-+#define CONFIG_BOOTDELAY 3
-+
-+#define CONFIG_PRIME "FEC0"
-+
-+#define CONFIG_LOADADDR 0x10800000 /* loadaddr env var */
-+#define CONFIG_RD_LOADADDR 0x11000000
-+
-+#define CONFIG_EXTRA_ENV_SETTINGS \
-+ "netdev=eth0\0" \
-+ "ethprime=FEC0\0" \
-+ "ethaddr=00:00:00:00:00:00\0" \
-+ "uboot=u-boot.bin\0" \
-+ "kernel=uImage\0" \
-+ "vid_dev0=hdmi,1920x1080M at 60,if=RGB24\0" \
-+ "vid_dev1=ldb,LDB-XGA,if=RGB666\0" \
-+ "bootargs=console=ttymxc1,115200\0" \
-+ "bootargs_base=setenv bootargs ${bootargs} " \
-+ "video=mxcfb0:dev=${vid_dev0} " \
-+ "video=mxcfb2:dev=${vid_dev1}\0" \
-+ "bootargs_mmc=setenv bootargs ${bootargs} rootwait enable_wait_mode=on\0" \
-+ "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\
-+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp " \
-+ "enable_wait_mode=off\0" \
-+ "bootcmd_net=dhcp; run bootargs_base bootargs_nfs;bootm\0" \
-+ "bootcmd_mmc=run bootargs_base bootargs_mmc;" \
-+ "for disk in 0 1 2; do mmc dev ${disk};" \
-+ "for fs in fat ext2 ; do " \
-+ "${fs}load mmc ${disk}:1 10008000 " \
-+ "/6q_bootscript && " \
-+ "source 10008000 ; " \
-+ "done ; " \
-+ "done\0" \
-+ "bootcmd=run bootcmd_mmc\0" \
-+ "clearenv=sf probe 1 && sf erase 0xc0000 0x2000 && " \
-+ "echo restored environment to factory default\0" \
-+ "upgradeu=for disk in 0 1 2; do mmc dev ${disk} ;" \
-+ "for fs in fat ext2 ; do " \
-+ "${fs}load mmc ${disk}:1 10008000 " \
-+ "/6q_upgrade && " \
-+ "source 10008000 ; " \
-+ "done ; " \
-+ "done\0" \
-+ "bootfile=_BOOT_FILE_PATH_IN_TFTP_\0" \
-+ "nfsroot=_ROOTFS_PATH_IN_NFS_\0"
-+
-+
-+#define CONFIG_ARP_TIMEOUT 200UL
-+
-+/*
-+ * Miscellaneous configurable options
-+ */
-+#define CONFIG_SYS_LONGHELP /* undef to save memory */
-+#define CONFIG_SYS_PROMPT "conga-QMX6 U-Boot > "
-+#define CONFIG_AUTO_COMPLETE
-+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-+/* Print Buffer Size */
-+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-+
-+#define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */
-+#define CONFIG_SYS_MEMTEST_END 0x10010000
-+
-+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
-+
-+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-+
-+#define CONFIG_SYS_HZ 1000
-+
-+#define CONFIG_CMDLINE_EDITING
-+#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
-+#ifdef CONFIG_SYS_HUSH_PARSER
-+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-+#endif
-+
-+#define CONFIG_FEC0_IOBASE ENET_BASE_ADDR
-+#define CONFIG_FEC0_PINMUX -1
-+#define CONFIG_FEC0_MIIBASE -1
-+#define CONFIG_GET_FEC_MAC_ADDR_FROM_ENV
-+#define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
-+#define CONFIG_MXC_FEC
-+#define CONFIG_FEC0_PHY_ADDR 6
-+#define CONFIG_ETH_PRIME
-+#define CONFIG_RMII
-+#define CONFIG_PHY_MICREL_KSZ9021
-+#define CONFIG_CMD_MII
-+#define CONFIG_CMD_DHCP
-+#define CONFIG_CMD_PING
-+#define CONFIG_IPADDR 192.168.1.103
-+
-+/*The IP ADDRESS of SERVERIP*/
-+#define CONFIG_SERVERIP _SERVER_IP_ADDR_
-+
-+#define CONFIG_NETMASK 255.255.255.0
-+
-+/*
-+ * OCOTP Configs
-+ */
-+#ifdef CONFIG_CMD_IMXOTP
-+ #define CONFIG_IMX_OTP
-+ #define IMX_OTP_BASE OCOTP_BASE_ADDR
-+ #define IMX_OTP_ADDR_MAX 0x7F
-+ #define IMX_OTP_DATA_ERROR_VAL 0xBADABADA
-+#endif
-+
-+/*
-+ * I2C Configs
-+ */
-+#ifdef CONFIG_CMD_I2C
-+ #define CONFIG_HARD_I2C 1
-+ #define CONFIG_I2C_MXC 1
-+ #define CONFIG_SYS_I2C_PORT I2C2_BASE_ADDR
-+ #define CONFIG_SYS_I2C_SPEED 100000
-+ #define CONFIG_SYS_I2C_SLAVE 0x08
-+#endif
-+
-+/*
-+ * SPI Configs
-+ */
-+#ifdef CONFIG_CMD_SF
-+ #define CONFIG_FSL_SF 1
-+ #define CONFIG_SPI_FLASH_IMX_SST 1
-+ #define CONFIG_SPI_FLASH_CS 1
-+ #define CONFIG_IMX_ECSPI
-+ #define IMX_CSPI_VER_2_3 1
-+ #define MAX_SPI_BYTES (64 * 4)
-+#endif
-+
-+/* Regulator Configs */
-+#ifdef CONFIG_CMD_REGUL
-+ #define CONFIG_ANATOP_REGULATOR
-+ #define CONFIG_CORE_REGULATOR_NAME "vdd1p1"
-+ #define CONFIG_PERIPH_REGULATOR_NAME "vdd1p1"
-+#endif
-+
-+/*
-+ * MMC Configs
-+ */
-+#ifdef CONFIG_CMD_MMC
-+ #define CONFIG_MMC
-+ #define CONFIG_GENERIC_MMC
-+ #define CONFIG_IMX_MMC
-+ #define CONFIG_SYS_FSL_USDHC_NUM 3
-+ #define CONFIG_SYS_FSL_ESDHC_ADDR 0
-+ #define CONFIG_SYS_MMC_ENV_DEV 2
-+ #define CONFIG_DOS_PARTITION 1
-+ #define CONFIG_CMD_FAT 1
-+ #define CONFIG_CMD_EXT2 1
-+
-+ /* detect whether SD1, 2, 3, or 4 is boot device */
-+ #define CONFIG_DYNAMIC_MMC_DEVNO
-+
-+ /* Setup target delay in DDR mode for each SD port */
-+ #define CONFIG_GET_DDR_TARGET_DELAY
-+#endif
-+
-+/*
-+ * SATA Configs
-+ */
-+#ifdef CONFIG_CMD_SATA
-+ #define CONFIG_DWC_AHSATA
-+ #define CONFIG_SYS_SATA_MAX_DEVICE 1
-+ #define CONFIG_DWC_AHSATA_PORT_ID 0
-+ #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
-+ #define CONFIG_LBA48
-+ #define CONFIG_LIBATA
-+
-+ #define CONFIG_DOS_PARTITION 1
-+ #define CONFIG_CMD_FAT 1
-+ #define CONFIG_CMD_EXT2 1
-+#endif
-+
-+/*
-+ * USB OTG
-+ */
-+#define CONFIG_IMX_UDC 1
-+
-+/*-----------------------------------------------------------------------
-+ * Stack sizes
-+ *
-+ * The stack sizes are set up in start.S using the settings below
-+ */
-+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
-+
-+/*-----------------------------------------------------------------------
-+ * Physical Memory Map
-+ */
-+#define CONFIG_NR_DRAM_BANKS 1
-+#define PHYS_SDRAM_1 CSD0_DDR_BASE_ADDR
-+#ifdef CONFIG_QMX6_PN016104
-+#define PHYS_SDRAM_1_SIZE (2u * 1024 * 1024 * 1024)
-+#endif
-+#ifdef CONFIG_QMX6_PN016101
-+#define PHYS_SDRAM_1_SIZE (1u * 1024 * 1024 * 1024)
-+#endif
-+#define iomem_valid_addr(addr, size) \
-+ (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))
-+
-+/*-----------------------------------------------------------------------
-+ * FLASH and environment organization
-+ */
-+#define CONFIG_SYS_NO_FLASH
-+
-+/* Monitor at beginning of flash */
-+/* #define CONFIG_FSL_ENV_IN_MMC */
-+/* #define CONFIG_FSL_ENV_IN_SATA */
-+#define CONFIG_FSL_ENV_IN_SF
-+
-+#define CONFIG_ENV_SECT_SIZE (8 * 1024)
-+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-+
-+#if defined(CONFIG_FSL_ENV_IN_NAND)
-+ #define CONFIG_ENV_IS_IN_NAND 1
-+ #define CONFIG_ENV_OFFSET 0x100000
-+#elif defined(CONFIG_FSL_ENV_IN_MMC)
-+ #define CONFIG_ENV_IS_IN_MMC 1
-+ #define CONFIG_ENV_OFFSET (768 * 1024)
-+#elif defined(CONFIG_FSL_ENV_IN_SATA)
-+ #define CONFIG_ENV_IS_IN_SATA 1
-+ #define CONFIG_SATA_ENV_DEV 0
-+ #define CONFIG_ENV_OFFSET (768 * 1024)
-+#elif defined(CONFIG_FSL_ENV_IN_SF)
-+ #define CONFIG_ENV_IS_IN_SPI_FLASH 1
-+ #define CONFIG_ENV_SPI_CS 1
-+ #define CONFIG_ENV_OFFSET (768 * 1024)
-+#else
-+ #define CONFIG_ENV_IS_NOWHERE 1
-+#endif
-+#endif /* __CONFIG_H */
-diff --git a/include/configs/cgt_qmx6_android.h b/include/configs/cgt_qmx6_android.h
-new file mode 100644
-index 0000000..9c3a80d
---- /dev/null
-+++ b/include/configs/cgt_qmx6_android.h
-@@ -0,0 +1,360 @@
-+/*
-+ * Copyright (C) 2011-2012 Freescale Semiconductor, Inc.
-+ *
-+ * Configuration settings for the MX6Q SABRE-Lite Freescale board.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ */
-+
-+#ifndef __CONFIG_H
-+#define __CONFIG_H
-+
-+#include <asm/arch/mx6.h>
-+
-+/* congatec product selection */
-+/* uncomment one of the configuration switches below in order to build a bootloader for conga-QMX6 */
-+/* enabling CONFIG_QMX6_PN016104 builds a bootloader for conga-QMX6 module, part number 016104, equipped i.MX6 1GHz QuadCore, 2GByte onboard DDR3 memory */
-+/* enabling CONFIG_QMX6_PN016101 builds a bootloader for conga-QMX6 module, part number 016101, equipped i.MX6 1GHz DualCore Lite, 1GByte onboard DDR3 memory */
-+//#define CONFIG_QMX6_PN016104
-+//#define CONFIG_QMX6_PN016101
-+
-+/* uncomment in order to build special trace version of bootloader */
-+// #define CONFIG_QMX6_TRACE
-+
-+ /* High Level Configuration Options */
-+#define CONFIG_ARMV7 /* This is armv7 Cortex-A9 CPU core */
-+#define CONFIG_MXC
-+
-+#ifdef CONFIG_QMX6_PN016101
-+#define CONFIG_QMX6_PN 016101
-+#define CONFIG_MX6DL
-+#endif
-+
-+#ifdef CONFIG_QMX6_PN016104
-+#define CONFIG_QMX6_PN 016104
-+#define CONFIG_MX6Q
-+#endif
-+
-+#define CONFIG_FLASH_HEADER
-+#define CONFIG_FLASH_HEADER_OFFSET 0x400
-+#define CONFIG_MX6_CLK32 32768
-+
-+#define CONFIG_SKIP_RELOCATE_UBOOT
-+
-+#define CONFIG_ARCH_CPU_INIT
-+#undef CONFIG_ARCH_MMU /* disable MMU first */
-+#define CONFIG_L2_OFF /* disable L2 cache first*/
-+
-+#define CONFIG_MX6_HCLK_FREQ 24000000
-+
-+#define CONFIG_DISPLAY_CPUINFO
-+#define CONFIG_DISPLAY_BOARDINFO
-+
-+#define CONFIG_SYS_64BIT_VSPRINTF
-+
-+#define BOARD_LATE_INIT
-+
-+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-+#define CONFIG_REVISION_TAG
-+#define CONFIG_SETUP_MEMORY_TAGS
-+#define CONFIG_INITRD_TAG
-+
-+/*
-+ * Size of malloc() pool
-+ */
-+#ifdef CONFIG_QMX6_PN016104
-+#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024)
-+#endif
-+#ifdef CONFIG_QMX6_PN016101
-+#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
-+#endif
-+/* size in bytes reserved for initial data */
-+#define CONFIG_SYS_GBL_DATA_SIZE 128
-+
-+/*
-+ * Hardware drivers
-+ */
-+#define CONFIG_MXC_UART
-+#define CONFIG_UART_BASE_ADDR UART2_BASE_ADDR
-+
-+/* allow to overwrite serial and ethaddr */
-+#define CONFIG_ENV_OVERWRITE
-+#define CONFIG_CONS_INDEX 1
-+#define CONFIG_BAUDRATE 115200
-+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
-+
-+/* Android related config */
-+#define CONFIG_USB_DEVICE
-+#define CONFIG_IMX_UDC 1
-+#define CONFIG_FASTBOOT 1
-+#define CONFIG_FASTBOOT_STORAGE_EMMC_SATA
-+#define CONFIG_FASTBOOT_VENDOR_ID 0xbb4
-+#define CONFIG_FASTBOOT_PRODUCT_ID 0xc01
-+#define CONFIG_FASTBOOT_BCD_DEVICE 0x311
-+#define CONFIG_FASTBOOT_MANUFACTURER_STR "Freescale"
-+#define CONFIG_FASTBOOT_PRODUCT_NAME_STR "i.mx6q qmx6"
-+#define CONFIG_FASTBOOT_INTERFACE_STR "Android fastboot"
-+#define CONFIG_FASTBOOT_CONFIGURATION_STR "Android fastboot"
-+#define CONFIG_FASTBOOT_SERIAL_NUM "12345"
-+#define CONFIG_FASTBOOT_SATA_NO 0
-+#define CONFIG_FASTBOOT_TRANSFER_BUF 0x30000000
-+#define CONFIG_FASTBOOT_TRANSFER_BUF_SIZE 0x10000000 /* 256M byte */
-+
-+#define CONFIG_CMD_BOOTI
-+#define CONFIG_ANDROID_RECOVERY
-+#define CONFIG_ANDROID_BOOT_PARTITION_MMC 1
-+#define CONFIG_ANDROID_SYSTEM_PARTITION_MMC 5
-+#define CONFIG_ANDROID_RECOVERY_PARTITION_MMC 2
-+#define CONFIG_ANDROID_CACHE_PARTITION_MMC 6
-+
-+#define CONFIG_ANDROID_RECOVERY_BOOTARGS_MMC NULL
-+#define CONFIG_ANDROID_RECOVERY_BOOTCMD_MMC \
-+ "booti mmc1 recovery"
-+#define CONFIG_ANDROID_RECOVERY_CMD_FILE "/recovery/command"
-+
-+/***********************************************************
-+ * Command definition
-+ ***********************************************************/
-+
-+#include <config_cmd_default.h>
-+
-+#define CONFIG_CMD_PING
-+#define CONFIG_CMD_DHCP
-+#define CONFIG_CMD_MII
-+#define CONFIG_CMD_NET
-+#define CONFIG_NET_RETRY_COUNT 100
-+#define CONFIG_NET_MULTI 1
-+#define CONFIG_BOOTP_SUBNETMASK
-+#define CONFIG_BOOTP_GATEWAY
-+#define CONFIG_BOOTP_DNS
-+
-+#define CONFIG_CMD_SPI
-+#define CONFIG_CMD_I2C
-+
-+/* Enable below configure when supporting nand */
-+
-+#define CONFIG_CMD_MMC
-+#define CONFIG_MMC_8BIT_PORTS 0x00000002
-+#define CONFIG_CMD_SF
-+#define CONFIG_CMD_ENV
-+#define CONFIG_CMD_REGUL
-+
-+#define CONFIG_CMD_CLOCK
-+#define CONFIG_REF_CLK_FREQ CONFIG_MX6_HCLK_FREQ
-+
-+#ifdef CONFIG_QMX6_PN016104
-+#define CONFIG_CMD_SATA
-+#endif
-+#undef CONFIG_CMD_IMLS
-+
-+#define CONFIG_CMD_IMX_DOWNLOAD_MODE
-+
-+#define CONFIG_BOOTDELAY 3
-+
-+#define CONFIG_PRIME "FEC0"
-+
-+#define CONFIG_LOADADDR 0x10800000 /* loadaddr env var */
-+#define CONFIG_RD_LOADADDR 0x11000000
-+
-+#define CONFIG_INITRD_TAG
-+
-+#define CONFIG_EXTRA_ENV_SETTINGS \
-+ "netdev=eth0\0" \
-+ "ethprime=FEC0\0" \
-+ "bootcmd=booti mmc1\0"
-+#define CONFIG_ARP_TIMEOUT 200UL
-+
-+/*
-+ * Miscellaneous configurable options
-+ */
-+#define CONFIG_SYS_LONGHELP /* undef to save memory */
-+#define CONFIG_SYS_PROMPT "conga-QMX6 U-Boot > "
-+#define CONFIG_AUTO_COMPLETE
-+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-+/* Print Buffer Size */
-+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-+
-+#define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */
-+#define CONFIG_SYS_MEMTEST_END 0x10010000
-+
-+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
-+
-+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-+
-+#define CONFIG_SYS_HZ 1000
-+
-+#define CONFIG_CMDLINE_EDITING
-+#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
-+#ifdef CONFIG_SYS_HUSH_PARSER
-+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-+#endif
-+
-+#define CONFIG_FEC0_IOBASE ENET_BASE_ADDR
-+#define CONFIG_FEC0_PINMUX -1
-+#define CONFIG_FEC0_MIIBASE -1
-+#define CONFIG_GET_FEC_MAC_ADDR_FROM_ENV
-+#define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
-+#define CONFIG_MXC_FEC
-+#define CONFIG_FEC0_PHY_ADDR 6
-+#define CONFIG_ETH_PRIME
-+#define CONFIG_RMII
-+#define CONFIG_PHY_MICREL_KSZ9021
-+#define CONFIG_CMD_MII
-+#define CONFIG_CMD_DHCP
-+#define CONFIG_CMD_PING
-+#define CONFIG_IPADDR 192.168.1.103
-+
-+/*The IP ADDRESS of SERVERIP*/
-+#define CONFIG_SERVERIP _SERVER_IP_ADDR_
-+
-+#define CONFIG_NETMASK 255.255.255.0
-+
-+/*
-+ * OCOTP Configs
-+ */
-+#ifdef CONFIG_CMD_IMXOTP
-+ #define CONFIG_IMX_OTP
-+ #define IMX_OTP_BASE OCOTP_BASE_ADDR
-+ #define IMX_OTP_ADDR_MAX 0x7F
-+ #define IMX_OTP_DATA_ERROR_VAL 0xBADABADA
-+#endif
-+
-+/*
-+ * I2C Configs
-+ */
-+#ifdef CONFIG_CMD_I2C
-+ #define CONFIG_HARD_I2C 1
-+ #define CONFIG_I2C_MXC 1
-+ #define CONFIG_SYS_I2C_PORT I2C2_BASE_ADDR
-+ #define CONFIG_SYS_I2C_SPEED 100000
-+ #define CONFIG_SYS_I2C_SLAVE 0x08
-+#endif
-+
-+/*
-+ * SPI Configs
-+ */
-+#ifdef CONFIG_CMD_SF
-+ #define CONFIG_FSL_SF 1
-+ #define CONFIG_SPI_FLASH_IMX_SST 1
-+ #define CONFIG_SPI_FLASH_CS 1
-+ #define CONFIG_IMX_ECSPI
-+ #define IMX_CSPI_VER_2_3 1
-+ #define MAX_SPI_BYTES (64 * 4)
-+#endif
-+
-+/* Regulator Configs */
-+#ifdef CONFIG_CMD_REGUL
-+ #define CONFIG_ANATOP_REGULATOR
-+ #define CONFIG_CORE_REGULATOR_NAME "vdd1p1"
-+ #define CONFIG_PERIPH_REGULATOR_NAME "vdd1p1"
-+#endif
-+
-+/*
-+ * MMC Configs
-+ */
-+#ifdef CONFIG_CMD_MMC
-+ #define CONFIG_MMC
-+ #define CONFIG_GENERIC_MMC
-+ #define CONFIG_IMX_MMC
-+ #define CONFIG_SYS_FSL_USDHC_NUM 3
-+ #define CONFIG_SYS_FSL_ESDHC_ADDR 0
-+ #define CONFIG_SYS_MMC_ENV_DEV 2
-+ #define CONFIG_DOS_PARTITION 1
-+ #define CONFIG_CMD_FAT 1
-+ #define CONFIG_CMD_EXT2 1
-+
-+ /* detect whether SD1, 2, 3, or 4 is boot device */
-+ #define CONFIG_DYNAMIC_MMC_DEVNO
-+
-+ /* Setup target delay in DDR mode for each SD port */
-+ #define CONFIG_GET_DDR_TARGET_DELAY
-+#endif
-+
-+/*
-+ * SATA Configs
-+ */
-+#ifdef CONFIG_CMD_SATA
-+ #define CONFIG_DWC_AHSATA
-+ #define CONFIG_SYS_SATA_MAX_DEVICE 1
-+ #define CONFIG_DWC_AHSATA_PORT_ID 0
-+ #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
-+ #define CONFIG_LBA48
-+ #define CONFIG_LIBATA
-+
-+ #define CONFIG_DOS_PARTITION 1
-+ #define CONFIG_CMD_FAT 1
-+ #define CONFIG_CMD_EXT2 1
-+#endif
-+
-+/*
-+ * USB OTG
-+ */
-+#define CONFIG_IMX_UDC 1
-+
-+/*-----------------------------------------------------------------------
-+ * Stack sizes
-+ *
-+ * The stack sizes are set up in start.S using the settings below
-+ */
-+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
-+
-+/*-----------------------------------------------------------------------
-+ * Physical Memory Map
-+ */
-+#define CONFIG_NR_DRAM_BANKS 1
-+#define PHYS_SDRAM_1 CSD0_DDR_BASE_ADDR
-+#ifdef CONFIG_QMX6_PN016104
-+#define PHYS_SDRAM_1_SIZE (2u * 1024 * 1024 * 1024)
-+#endif
-+#ifdef CONFIG_QMX6_PN016101
-+#define PHYS_SDRAM_1_SIZE (1u * 1024 * 1024 * 1024)
-+#endif
-+#define iomem_valid_addr(addr, size) \
-+ (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))
-+
-+/*-----------------------------------------------------------------------
-+ * FLASH and environment organization
-+ */
-+#define CONFIG_SYS_NO_FLASH
-+
-+/* Monitor at beginning of flash */
-+/* #define CONFIG_FSL_ENV_IN_MMC */
-+/* #define CONFIG_FSL_ENV_IN_SATA */
-+#define CONFIG_FSL_ENV_IN_SF
-+
-+#define CONFIG_ENV_SECT_SIZE (8 * 1024)
-+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-+
-+#if defined(CONFIG_FSL_ENV_IN_NAND)
-+ #define CONFIG_ENV_IS_IN_NAND 1
-+ #define CONFIG_ENV_OFFSET 0x100000
-+#elif defined(CONFIG_FSL_ENV_IN_MMC)
-+ #define CONFIG_ENV_IS_IN_MMC 1
-+ #define CONFIG_ENV_OFFSET (768 * 1024)
-+#elif defined(CONFIG_FSL_ENV_IN_SATA)
-+ #define CONFIG_ENV_IS_IN_SATA 1
-+ #define CONFIG_SATA_ENV_DEV 0
-+ #define CONFIG_ENV_OFFSET (768 * 1024)
-+#elif defined(CONFIG_FSL_ENV_IN_SF)
-+ #define CONFIG_ENV_IS_IN_SPI_FLASH 1
-+ #define CONFIG_ENV_SPI_CS 1
-+ #define CONFIG_ENV_OFFSET (768 * 1024)
-+#else
-+ #define CONFIG_ENV_IS_NOWHERE 1
-+#endif
-+#endif /* __CONFIG_H */
-diff --git a/include/configs/cgt_qmx6_mfg.h b/include/configs/cgt_qmx6_mfg.h
-new file mode 100644
-index 0000000..8a8ba20
---- /dev/null
-+++ b/include/configs/cgt_qmx6_mfg.h
-@@ -0,0 +1,320 @@
-+/*
-+ * Copyright (C) 2011-2012 Freescale Semiconductor, Inc.
-+ *
-+ * Configuration settings for the MX6Q SABRE-Lite Freescale board.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ */
-+
-+#ifndef __CONFIG_H
-+#define __CONFIG_H
-+
-+#include <asm/arch/mx6.h>
-+
-+/* congatec product selection */
-+/* uncomment one of the configuration switches below in order to build a bootloader for conga-QMX6 */
-+/* enabling CONFIG_QMX6_PN016104 builds a bootloader for conga-QMX6 module, part number 016104, equipped i.MX6 1GHz QuadCore, 2GByte onboard DDR3 memory */
-+/* enabling CONFIG_QMX6_PN016101 builds a bootloader for conga-QMX6 module, part number 016101, equipped i.MX6 1GHz DualCore Lite, 1GByte onboard DDR3 memory */
-+//#define CONFIG_QMX6_PN016104
-+//#define CONFIG_QMX6_PN016101
-+
-+/* uncomment in order to build special trace version of bootloader */
-+// #define CONFIG_QMX6_TRACE
-+
-+ /* High Level Configuration Options */
-+#define CONFIG_MFG
-+#define CONFIG_ARMV7 /* This is armv7 Cortex-A9 CPU core */
-+#define CONFIG_MXC
-+
-+#ifdef CONFIG_QMX6_PN016101
-+#define CONFIG_QMX6_PN 016101
-+#define CONFIG_MX6DL
-+#endif
-+
-+#ifdef CONFIG_QMX6_PN016104
-+#define CONFIG_QMX6_PN 016104
-+#define CONFIG_MX6Q
-+#endif
-+
-+#define CONFIG_FLASH_HEADER
-+#define CONFIG_FLASH_HEADER_OFFSET 0x400
-+#define CONFIG_MX6_CLK32 32768
-+
-+#define CONFIG_SKIP_RELOCATE_UBOOT
-+
-+#define CONFIG_ARCH_CPU_INIT
-+#undef CONFIG_ARCH_MMU /* disable MMU first */
-+#define CONFIG_L2_OFF /* disable L2 cache first*/
-+
-+#define CONFIG_MX6_HCLK_FREQ 24000000
-+
-+#define CONFIG_DISPLAY_CPUINFO
-+#define CONFIG_DISPLAY_BOARDINFO
-+
-+#define CONFIG_SYS_64BIT_VSPRINTF
-+
-+#define BOARD_LATE_INIT
-+
-+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-+#define CONFIG_REVISION_TAG
-+#define CONFIG_SETUP_MEMORY_TAGS
-+#define CONFIG_INITRD_TAG
-+
-+/*
-+ * Size of malloc() pool
-+ */
-+#ifdef CONFIG_QMX6_PN016104
-+#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024)
-+#endif
-+#ifdef CONFIG_QMX6_PN016101
-+#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
-+#endif
-+/* size in bytes reserved for initial data */
-+#define CONFIG_SYS_GBL_DATA_SIZE 128
-+
-+/*
-+ * Hardware drivers
-+ */
-+#define CONFIG_MXC_UART
-+#define CONFIG_UART_BASE_ADDR UART2_BASE_ADDR
-+
-+/* allow to overwrite serial and ethaddr */
-+#define CONFIG_ENV_OVERWRITE
-+#define CONFIG_CONS_INDEX 1
-+#define CONFIG_BAUDRATE 115200
-+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
-+
-+/***********************************************************
-+ * Command definition
-+ ***********************************************************/
-+
-+#include <config_cmd_default.h>
-+
-+#define CONFIG_CMD_PING
-+#define CONFIG_CMD_DHCP
-+#define CONFIG_CMD_MII
-+#define CONFIG_CMD_NET
-+#define CONFIG_NET_RETRY_COUNT 100
-+#define CONFIG_NET_MULTI 1
-+#define CONFIG_BOOTP_SUBNETMASK
-+#define CONFIG_BOOTP_GATEWAY
-+#define CONFIG_BOOTP_DNS
-+
-+#define CONFIG_CMD_SPI
-+#define CONFIG_CMD_I2C
-+#define CONFIG_CMD_IMXOTP
-+
-+/* Enable below configure when supporting nand */
-+
-+#define CONFIG_CMD_MMC
-+#define CONFIG_MMC_8BIT_PORTS 0x00000002
-+#define CONFIG_CMD_SF
-+#define CONFIG_CMD_ENV
-+#define CONFIG_CMD_REGUL
-+
-+#define CONFIG_CMD_CLOCK
-+#define CONFIG_REF_CLK_FREQ CONFIG_MX6_HCLK_FREQ
-+
-+#ifdef CONFIG_QMX6_PN016104
-+#define CONFIG_CMD_SATA
-+#endif
-+#undef CONFIG_CMD_IMLS
-+
-+#define CONFIG_BOOTDELAY 3
-+
-+#define CONFIG_PRIME "FEC0"
-+
-+#define CONFIG_LOADADDR 0x10800000 /* loadaddr env var */
-+#define CONFIG_RD_LOADADDR 0x11000000
-+
-+#define CONFIG_BOOTARGS "console=ttymxc1,115200 rdinit=/linuxrc rootwait root=/dev/ram0"
-+#define CONFIG_BOOTCOMMAND "bootm 0x10800000 0x11000000"
-+
-+#define CONFIG_EXTRA_ENV_SETTINGS \
-+ "netdev=eth0\0" \
-+ "ethprime=FEC0\0" \
-+ "uboot=u-boot.bin\0" \
-+ "kernel=uImage\0" \
-+
-+
-+#define CONFIG_ARP_TIMEOUT 200UL
-+
-+/*
-+ * Miscellaneous configurable options
-+ */
-+#define CONFIG_SYS_LONGHELP /* undef to save memory */
-+#define CONFIG_SYS_PROMPT "conga-QMX6-MFG U-Boot > "
-+#define CONFIG_AUTO_COMPLETE
-+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-+/* Print Buffer Size */
-+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-+
-+#define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */
-+#define CONFIG_SYS_MEMTEST_END 0x10010000
-+
-+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
-+
-+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-+
-+#define CONFIG_SYS_HZ 1000
-+
-+#define CONFIG_CMDLINE_EDITING
-+#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
-+#ifdef CONFIG_SYS_HUSH_PARSER
-+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-+#endif
-+
-+#define CONFIG_FEC0_IOBASE ENET_BASE_ADDR
-+#define CONFIG_FEC0_PINMUX -1
-+#define CONFIG_FEC0_MIIBASE -1
-+#define CONFIG_GET_FEC_MAC_ADDR_FROM_ENV
-+#define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
-+#define CONFIG_MXC_FEC
-+#define CONFIG_FEC0_PHY_ADDR 6
-+#define CONFIG_ETH_PRIME
-+#define CONFIG_RMII
-+#define CONFIG_PHY_MICREL_KSZ9021
-+#define CONFIG_CMD_MII
-+#define CONFIG_CMD_DHCP
-+#define CONFIG_CMD_PING
-+#define CONFIG_IPADDR 192.168.1.103
-+
-+/*The IP ADDRESS of SERVERIP*/
-+#define CONFIG_SERVERIP _SERVER_IP_ADDR_
-+
-+#define CONFIG_NETMASK 255.255.255.0
-+
-+/*
-+ * OCOTP Configs
-+ */
-+#ifdef CONFIG_CMD_IMXOTP
-+ #define CONFIG_IMX_OTP
-+ #define IMX_OTP_BASE OCOTP_BASE_ADDR
-+ #define IMX_OTP_ADDR_MAX 0x7F
-+ #define IMX_OTP_DATA_ERROR_VAL 0xBADABADA
-+#endif
-+
-+/*
-+ * I2C Configs
-+ */
-+#ifdef CONFIG_CMD_I2C
-+ #define CONFIG_HARD_I2C 1
-+ #define CONFIG_I2C_MXC 1
-+ #define CONFIG_SYS_I2C_PORT I2C2_BASE_ADDR
-+ #define CONFIG_SYS_I2C_SPEED 100000
-+ #define CONFIG_SYS_I2C_SLAVE 0x08
-+#endif
-+
-+/*
-+ * SPI Configs
-+ */
-+#ifdef CONFIG_CMD_SF
-+ #define CONFIG_FSL_SF 1
-+ #define CONFIG_SPI_FLASH_IMX_SST 1
-+ #define CONFIG_SPI_FLASH_CS 1
-+/* #define CONFIG_MFGAREA_UNPROTECT */
-+ #define CONFIG_IMX_ECSPI
-+ #define IMX_CSPI_VER_2_3 1
-+ #define MAX_SPI_BYTES (64 * 4)
-+#endif
-+
-+/* Regulator Configs */
-+#ifdef CONFIG_CMD_REGUL
-+ #define CONFIG_ANATOP_REGULATOR
-+ #define CONFIG_CORE_REGULATOR_NAME "vdd1p1"
-+ #define CONFIG_PERIPH_REGULATOR_NAME "vdd1p1"
-+#endif
-+
-+/*
-+ * MMC Configs
-+ */
-+#ifdef CONFIG_CMD_MMC
-+ #define CONFIG_MMC
-+ #define CONFIG_GENERIC_MMC
-+ #define CONFIG_IMX_MMC
-+ #define CONFIG_SYS_FSL_USDHC_NUM 3
-+ #define CONFIG_SYS_FSL_ESDHC_ADDR 0
-+ #define CONFIG_SYS_MMC_ENV_DEV 2
-+ #define CONFIG_DOS_PARTITION 1
-+ #define CONFIG_CMD_FAT 1
-+ #define CONFIG_CMD_EXT2 1
-+
-+ /* detect whether SD1, 2, 3, or 4 is boot device */
-+ #define CONFIG_DYNAMIC_MMC_DEVNO
-+
-+ /* Setup target delay in DDR mode for each SD port */
-+ #define CONFIG_GET_DDR_TARGET_DELAY
-+#endif
-+
-+/*
-+ * SATA Configs
-+ */
-+#ifdef CONFIG_CMD_SATA
-+ #define CONFIG_DWC_AHSATA
-+ #define CONFIG_SYS_SATA_MAX_DEVICE 1
-+ #define CONFIG_DWC_AHSATA_PORT_ID 0
-+ #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
-+ #define CONFIG_LBA48
-+ #define CONFIG_LIBATA
-+
-+ #define CONFIG_DOS_PARTITION 1
-+ #define CONFIG_CMD_FAT 1
-+ #define CONFIG_CMD_EXT2 1
-+#endif
-+
-+/*
-+ * USB OTG
-+ */
-+#define CONFIG_IMX_UDC 1
-+
-+/*-----------------------------------------------------------------------
-+ * Stack sizes
-+ *
-+ * The stack sizes are set up in start.S using the settings below
-+ */
-+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
-+
-+/*-----------------------------------------------------------------------
-+ * Physical Memory Map
-+ */
-+#define CONFIG_NR_DRAM_BANKS 1
-+#define PHYS_SDRAM_1 CSD0_DDR_BASE_ADDR
-+#ifdef CONFIG_QMX6_PN016104
-+#define PHYS_SDRAM_1_SIZE (2u * 1024 * 1024 * 1024)
-+#endif
-+#ifdef CONFIG_QMX6_PN016101
-+#define PHYS_SDRAM_1_SIZE (1u * 1024 * 1024 * 1024)
-+#endif
-+#define iomem_valid_addr(addr, size) \
-+ (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))
-+
-+/*-----------------------------------------------------------------------
-+ * FLASH and environment organization
-+ */
-+#define CONFIG_SYS_NO_FLASH
-+
-+/* Monitor at beginning of flash */
-+/* #define CONFIG_FSL_ENV_IN_MMC */
-+/* #define CONFIG_FSL_ENV_IN_SATA */
-+/* #define CONFIG_FSL_ENV_IN_SF */
-+
-+#define CONFIG_ENV_SECT_SIZE (8 * 1024)
-+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-+#define CONFIG_ENV_IS_NOWHERE 1
-+
-+#endif /* __CONFIG_H */
-diff --git a/localversion-qmx6 b/localversion-qmx6
-new file mode 100644
-index 0000000..5293f29
---- /dev/null
-+++ b/localversion-qmx6
-@@ -0,0 +1 @@
-+ QMX6R003
---
-1.7.10.4
-
diff --git a/recipes-bsp/u-boot/u-boot-imx_2009.08.bbappend b/recipes-bsp/u-boot/u-boot-imx_2009.08.bbappend
deleted file mode 100644
index 788fdb8..0000000
--- a/recipes-bsp/u-boot/u-boot-imx_2009.08.bbappend
+++ /dev/null
@@ -1,7 +0,0 @@
-FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}"
-
-SRC_URI_append_cgtqmx6 = " \
- file://cgtqmx6/0001-Add-uboot-support-for-congatec-qmx6-board.patch \
-"
-
-UBOOT_MACHINE_cgtqmx6 = "cgt_qmx6_config"
diff --git a/recipes-kernel/linux/linux-congatec-3.0.35/0001-Add-linux-support-for-congatec-evaluation-board-qmx6q.patch b/recipes-kernel/linux/linux-congatec-3.0.35/0001-Add-linux-support-for-congatec-evaluation-board-qmx6q.patch
deleted file mode 100644
index 1262df0..0000000
--- a/recipes-kernel/linux/linux-congatec-3.0.35/0001-Add-linux-support-for-congatec-evaluation-board-qmx6q.patch
+++ /dev/null
@@ -1,7213 +0,0 @@
-From 8848547bb783e01a9f00104b0d4fb1366893c245 Mon Sep 17 00:00:00 2001
-From: Leo Sartre <lsartre at adeneo-embedded.com>
-Date: Wed, 29 May 2013 09:46:23 +0200
-Subject: [PATCH] Add support for congatec evaluation board qmx6q and qmx6qdl
-Organization: O.S. Systems Software LTDA.
-
-Add support for congatec Qeval board, patch originaly written by
-Congatec team, some minor changes and cleanup were applied to make it
-work with the bsp 4.1 release.
----
- arch/arm/configs/qmx6_defconfig | 2659 +++++++++++++++++++++++++++
- arch/arm/configs/qmx6_updater_defconfig | 2367 ++++++++++++++++++++++++
- arch/arm/mach-mx6/Kconfig | 35 +
- arch/arm/mach-mx6/Makefile | 2 +
- arch/arm/mach-mx6/board-mx6dl_qmx6.h | 199 ++
- arch/arm/mach-mx6/board-mx6q_qmx6.c | 979 ++++++++++
- arch/arm/mach-mx6/board-mx6q_qmx6.h | 199 ++
- arch/arm/mach-mx6/mx6q_qmx6_pmic_pfuze100.c | 422 +++++
- arch/arm/plat-mxc/include/mach/esdhc.h | 1 +
- arch/arm/tools/mach-types | 1 +
- drivers/mmc/host/sdhci-esdhc-imx.c | 5 +-
- drivers/net/fec.c | 32 +-
- drivers/net/phy/micrel.c | 23 +
- include/linux/micrel_phy.h | 1 +
- sound/soc/imx/Kconfig | 2 +-
- sound/soc/imx/imx-sgtl5000.c | 2 +-
- 16 files changed, 6910 insertions(+), 19 deletions(-)
- create mode 100644 arch/arm/configs/qmx6_defconfig
- create mode 100644 arch/arm/configs/qmx6_updater_defconfig
- create mode 100644 arch/arm/mach-mx6/board-mx6dl_qmx6.h
- create mode 100644 arch/arm/mach-mx6/board-mx6q_qmx6.c
- create mode 100644 arch/arm/mach-mx6/board-mx6q_qmx6.h
- create mode 100644 arch/arm/mach-mx6/mx6q_qmx6_pmic_pfuze100.c
-
-diff --git a/arch/arm/configs/qmx6_defconfig b/arch/arm/configs/qmx6_defconfig
-new file mode 100644
-index 0000000..9aeb4a5
---- /dev/null
-+++ b/arch/arm/configs/qmx6_defconfig
-@@ -0,0 +1,2659 @@
-+#
-+# Automatically generated make config: don't edit
-+# Linux/arm 3.0.15 Kernel Configuration
-+#
-+CONFIG_ARM=y
-+CONFIG_HAVE_PWM=y
-+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-+CONFIG_HAVE_SCHED_CLOCK=y
-+CONFIG_GENERIC_GPIO=y
-+# CONFIG_ARCH_USES_GETTIMEOFFSET is not set
-+CONFIG_GENERIC_CLOCKEVENTS=y
-+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-+CONFIG_KTIME_SCALAR=y
-+CONFIG_HAVE_PROC_CPU=y
-+CONFIG_STACKTRACE_SUPPORT=y
-+CONFIG_LOCKDEP_SUPPORT=y
-+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-+CONFIG_HARDIRQS_SW_RESEND=y
-+CONFIG_GENERIC_IRQ_PROBE=y
-+CONFIG_GENERIC_LOCKBREAK=y
-+CONFIG_RWSEM_GENERIC_SPINLOCK=y
-+CONFIG_ARCH_HAS_CPUFREQ=y
-+CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y
-+CONFIG_GENERIC_HWEIGHT=y
-+CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_ZONE_DMA=y
-+CONFIG_NEED_DMA_MAP_STATE=y
-+CONFIG_FIQ=y
-+CONFIG_VECTORS_BASE=0xffff0000
-+# CONFIG_ARM_PATCH_PHYS_VIRT is not set
-+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-+CONFIG_HAVE_IRQ_WORK=y
-+CONFIG_IRQ_WORK=y
-+
-+#
-+# General setup
-+#
-+CONFIG_EXPERIMENTAL=y
-+CONFIG_INIT_ENV_ARG_LIMIT=32
-+CONFIG_CROSS_COMPILE=""
-+CONFIG_LOCALVERSION=""
-+CONFIG_LOCALVERSION_AUTO=y
-+CONFIG_HAVE_KERNEL_GZIP=y
-+CONFIG_HAVE_KERNEL_LZMA=y
-+CONFIG_HAVE_KERNEL_LZO=y
-+CONFIG_KERNEL_GZIP=y
-+# CONFIG_KERNEL_LZMA is not set
-+# CONFIG_KERNEL_LZO is not set
-+CONFIG_DEFAULT_HOSTNAME="(none)"
-+CONFIG_SWAP=y
-+CONFIG_SYSVIPC=y
-+CONFIG_SYSVIPC_SYSCTL=y
-+# CONFIG_POSIX_MQUEUE is not set
-+# CONFIG_BSD_PROCESS_ACCT is not set
-+# CONFIG_FHANDLE is not set
-+# CONFIG_TASKSTATS is not set
-+# CONFIG_AUDIT is not set
-+CONFIG_HAVE_GENERIC_HARDIRQS=y
-+
-+#
-+# IRQ subsystem
-+#
-+CONFIG_GENERIC_HARDIRQS=y
-+CONFIG_HAVE_SPARSE_IRQ=y
-+CONFIG_GENERIC_IRQ_SHOW=y
-+# CONFIG_SPARSE_IRQ is not set
-+
-+#
-+# RCU Subsystem
-+#
-+CONFIG_TREE_PREEMPT_RCU=y
-+CONFIG_PREEMPT_RCU=y
-+# CONFIG_RCU_TRACE is not set
-+CONFIG_RCU_FANOUT=32
-+# CONFIG_RCU_FANOUT_EXACT is not set
-+# CONFIG_TREE_RCU_TRACE is not set
-+# CONFIG_RCU_BOOST is not set
-+CONFIG_IKCONFIG=y
-+CONFIG_IKCONFIG_PROC=y
-+CONFIG_LOG_BUF_SHIFT=14
-+# CONFIG_CGROUPS is not set
-+# CONFIG_NAMESPACES is not set
-+# CONFIG_SCHED_AUTOGROUP is not set
-+# CONFIG_SYSFS_DEPRECATED is not set
-+# CONFIG_RELAY is not set
-+CONFIG_BLK_DEV_INITRD=y
-+CONFIG_INITRAMFS_SOURCE=""
-+CONFIG_RD_GZIP=y
-+# CONFIG_RD_BZIP2 is not set
-+# CONFIG_RD_LZMA is not set
-+# CONFIG_RD_XZ is not set
-+# CONFIG_RD_LZO is not set
-+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-+CONFIG_SYSCTL=y
-+CONFIG_ANON_INODES=y
-+CONFIG_EXPERT=y
-+CONFIG_UID16=y
-+CONFIG_SYSCTL_SYSCALL=y
-+CONFIG_KALLSYMS=y
-+CONFIG_HOTPLUG=y
-+CONFIG_PRINTK=y
-+CONFIG_BUG=y
-+CONFIG_ELF_CORE=y
-+CONFIG_BASE_FULL=y
-+CONFIG_FUTEX=y
-+CONFIG_EPOLL=y
-+CONFIG_SIGNALFD=y
-+CONFIG_TIMERFD=y
-+CONFIG_EVENTFD=y
-+CONFIG_SHMEM=y
-+CONFIG_AIO=y
-+CONFIG_EMBEDDED=y
-+CONFIG_HAVE_PERF_EVENTS=y
-+CONFIG_PERF_USE_VMALLOC=y
-+
-+#
-+# Kernel Performance Events And Counters
-+#
-+CONFIG_PERF_EVENTS=y
-+# CONFIG_PERF_COUNTERS is not set
-+CONFIG_VM_EVENT_COUNTERS=y
-+CONFIG_SLUB_DEBUG=y
-+CONFIG_COMPAT_BRK=y
-+# CONFIG_SLAB is not set
-+CONFIG_SLUB=y
-+# CONFIG_SLOB is not set
-+# CONFIG_PROFILING is not set
-+CONFIG_HAVE_OPROFILE=y
-+# CONFIG_KPROBES is not set
-+CONFIG_HAVE_KPROBES=y
-+CONFIG_HAVE_KRETPROBES=y
-+CONFIG_USE_GENERIC_SMP_HELPERS=y
-+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-+CONFIG_HAVE_CLK=y
-+CONFIG_HAVE_DMA_API_DEBUG=y
-+CONFIG_HAVE_HW_BREAKPOINT=y
-+
-+#
-+# GCOV-based kernel profiling
-+#
-+# CONFIG_GCOV_KERNEL is not set
-+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-+CONFIG_SLABINFO=y
-+CONFIG_RT_MUTEXES=y
-+CONFIG_BASE_SMALL=0
-+CONFIG_MODULES=y
-+# CONFIG_MODULE_FORCE_LOAD is not set
-+CONFIG_MODULE_UNLOAD=y
-+CONFIG_MODULE_FORCE_UNLOAD=y
-+CONFIG_MODVERSIONS=y
-+# CONFIG_MODULE_SRCVERSION_ALL is not set
-+CONFIG_STOP_MACHINE=y
-+CONFIG_BLOCK=y
-+CONFIG_LBDAF=y
-+# CONFIG_BLK_DEV_BSG is not set
-+# CONFIG_BLK_DEV_INTEGRITY is not set
-+
-+#
-+# IO Schedulers
-+#
-+CONFIG_IOSCHED_NOOP=y
-+CONFIG_IOSCHED_DEADLINE=y
-+CONFIG_IOSCHED_CFQ=y
-+# CONFIG_DEFAULT_DEADLINE is not set
-+CONFIG_DEFAULT_CFQ=y
-+# CONFIG_DEFAULT_NOOP is not set
-+CONFIG_DEFAULT_IOSCHED="cfq"
-+# CONFIG_INLINE_SPIN_TRYLOCK is not set
-+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
-+# CONFIG_INLINE_SPIN_LOCK is not set
-+# CONFIG_INLINE_SPIN_LOCK_BH is not set
-+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
-+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
-+# CONFIG_INLINE_SPIN_UNLOCK is not set
-+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
-+# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set
-+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
-+# CONFIG_INLINE_READ_TRYLOCK is not set
-+# CONFIG_INLINE_READ_LOCK is not set
-+# CONFIG_INLINE_READ_LOCK_BH is not set
-+# CONFIG_INLINE_READ_LOCK_IRQ is not set
-+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
-+# CONFIG_INLINE_READ_UNLOCK is not set
-+# CONFIG_INLINE_READ_UNLOCK_BH is not set
-+# CONFIG_INLINE_READ_UNLOCK_IRQ is not set
-+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
-+# CONFIG_INLINE_WRITE_TRYLOCK is not set
-+# CONFIG_INLINE_WRITE_LOCK is not set
-+# CONFIG_INLINE_WRITE_LOCK_BH is not set
-+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
-+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
-+# CONFIG_INLINE_WRITE_UNLOCK is not set
-+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
-+# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set
-+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
-+CONFIG_MUTEX_SPIN_ON_OWNER=y
-+CONFIG_FREEZER=y
-+
-+#
-+# System Type
-+#
-+CONFIG_MMU=y
-+# CONFIG_ARCH_INTEGRATOR is not set
-+# CONFIG_ARCH_REALVIEW is not set
-+# CONFIG_ARCH_VERSATILE is not set
-+# CONFIG_ARCH_VEXPRESS is not set
-+# CONFIG_ARCH_AT91 is not set
-+# CONFIG_ARCH_BCMRING is not set
-+# CONFIG_ARCH_CLPS711X is not set
-+# CONFIG_ARCH_CNS3XXX is not set
-+# CONFIG_ARCH_GEMINI is not set
-+# CONFIG_ARCH_EBSA110 is not set
-+# CONFIG_ARCH_EP93XX is not set
-+# CONFIG_ARCH_FOOTBRIDGE is not set
-+CONFIG_ARCH_MXC=y
-+# CONFIG_ARCH_MXS is not set
-+# CONFIG_ARCH_NETX is not set
-+# CONFIG_ARCH_H720X is not set
-+# CONFIG_ARCH_IOP13XX is not set
-+# CONFIG_ARCH_IOP32X is not set
-+# CONFIG_ARCH_IOP33X is not set
-+# CONFIG_ARCH_IXP23XX is not set
-+# CONFIG_ARCH_IXP2000 is not set
-+# CONFIG_ARCH_IXP4XX is not set
-+# CONFIG_ARCH_DOVE is not set
-+# CONFIG_ARCH_KIRKWOOD is not set
-+# CONFIG_ARCH_LOKI is not set
-+# CONFIG_ARCH_LPC32XX is not set
-+# CONFIG_ARCH_MV78XX0 is not set
-+# CONFIG_ARCH_ORION5X is not set
-+# CONFIG_ARCH_MMP is not set
-+# CONFIG_ARCH_KS8695 is not set
-+# CONFIG_ARCH_W90X900 is not set
-+# CONFIG_ARCH_NUC93X is not set
-+# CONFIG_ARCH_TEGRA is not set
-+# CONFIG_ARCH_PNX4008 is not set
-+# CONFIG_ARCH_PXA is not set
-+# CONFIG_ARCH_MSM is not set
-+# CONFIG_ARCH_SHMOBILE is not set
-+# CONFIG_ARCH_RPC is not set
-+# CONFIG_ARCH_SA1100 is not set
-+# CONFIG_ARCH_S3C2410 is not set
-+# CONFIG_ARCH_S3C64XX is not set
-+# CONFIG_ARCH_S5P64X0 is not set
-+# CONFIG_ARCH_S5PC100 is not set
-+# CONFIG_ARCH_S5PV210 is not set
-+# CONFIG_ARCH_EXYNOS4 is not set
-+# CONFIG_ARCH_SHARK is not set
-+# CONFIG_ARCH_TCC_926 is not set
-+# CONFIG_ARCH_U300 is not set
-+# CONFIG_ARCH_U8500 is not set
-+# CONFIG_ARCH_NOMADIK is not set
-+# CONFIG_ARCH_DAVINCI is not set
-+# CONFIG_ARCH_OMAP is not set
-+# CONFIG_PLAT_SPEAR is not set
-+# CONFIG_ARCH_VT8500 is not set
-+CONFIG_GPIO_PCA953X=y
-+# CONFIG_KEYBOARD_GPIO_POLLED is not set
-+CONFIG_IMX_HAVE_PLATFORM_DMA=y
-+CONFIG_IMX_HAVE_PLATFORM_FEC=y
-+CONFIG_IMX_HAVE_PLATFORM_FLEXCAN=y
-+CONFIG_IMX_HAVE_PLATFORM_FSL_USB2_UDC=y
-+CONFIG_IMX_HAVE_PLATFORM_GPMI_NFC=y
-+CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT=y
-+CONFIG_IMX_HAVE_PLATFORM_IMX_SNVS_RTC=y
-+CONFIG_IMX_HAVE_PLATFORM_IMX_I2C=y
-+CONFIG_IMX_HAVE_PLATFORM_IMX_SSI=y
-+CONFIG_IMX_HAVE_PLATFORM_IMX_UART=y
-+CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI=y
-+CONFIG_IMX_HAVE_PLATFORM_MXC_PWM=y
-+CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX=y
-+CONFIG_IMX_HAVE_PLATFORM_SPI_IMX=y
-+CONFIG_IMX_HAVE_PLATFORM_IMX_IPUV3=y
-+CONFIG_IMX_HAVE_PLATFORM_IMX_VPU=y
-+CONFIG_IMX_HAVE_PLATFORM_IMX_DVFS=y
-+CONFIG_IMX_HAVE_PLATFORM_AHCI=y
-+CONFIG_IMX_HAVE_PLATFORM_IMX_OCOTP=y
-+CONFIG_IMX_HAVE_PLATFORM_IMX_VIIM=y
-+CONFIG_IMX_HAVE_PLATFORM_LDB=y
-+CONFIG_IMX_HAVE_PLATFORM_IMX_SPDIF=y
-+CONFIG_IMX_HAVE_PLATFORM_VIV_GPU=y
-+CONFIG_IMX_HAVE_PLATFORM_MXC_HDMI=y
-+CONFIG_IMX_HAVE_PLATFORM_IMX_ANATOP_THERMAL=y
-+CONFIG_IMX_HAVE_PLATFORM_FSL_OTG=y
-+CONFIG_IMX_HAVE_PLATFORM_FSL_USB_WAKEUP=y
-+CONFIG_IMX_HAVE_PLATFORM_IMX_PM=y
-+CONFIG_IMX_HAVE_PLATFORM_IMX_ASRC=y
-+CONFIG_IMX_HAVE_PLATFORM_IMX_MIPI_CSI2=y
-+CONFIG_IMX_HAVE_PLATFORM_IMX_VDOA=y
-+CONFIG_IMX_HAVE_PLATFORM_IMX_PCIE=y
-+
-+#
-+# Freescale MXC Implementations
-+#
-+# CONFIG_ARCH_MX1 is not set
-+# CONFIG_ARCH_MX2 is not set
-+# CONFIG_ARCH_MX25 is not set
-+# CONFIG_ARCH_MX3 is not set
-+# CONFIG_ARCH_MX503 is not set
-+# CONFIG_ARCH_MX51 is not set
-+CONFIG_ARCH_MX6=y
-+CONFIG_ARCH_MX6Q=y
-+CONFIG_FORCE_MAX_ZONEORDER=14
-+CONFIG_SOC_IMX6Q=y
-+# CONFIG_MACH_MX6Q_ARM2 is not set
-+# CONFIG_MACH_MX6Q_SABRELITE is not set
-+CONFIG_MACH_MX6Q_QMX6=y
-+# CONFIG_MACH_MX6Q_SABRESD is not set
-+# CONFIG_MACH_MX6Q_SABREAUTO is not set
-+
-+#
-+# MX6 Options:
-+#
-+# CONFIG_IMX_PCIE is not set
-+CONFIG_ISP1504_MXC=y
-+# CONFIG_MXC_IRQ_PRIOR is not set
-+CONFIG_MXC_PWM=y
-+# CONFIG_MXC_DEBUG_BOARD is not set
-+CONFIG_ARCH_MXC_IOMUX_V3=y
-+CONFIG_ARCH_MXC_AUDMUX_V2=y
-+CONFIG_IRAM_ALLOC=y
-+CONFIG_CLK_DEBUG=y
-+CONFIG_DMA_ZONE_SIZE=184
-+
-+#
-+# System MMU
-+#
-+
-+#
-+# Processor Type
-+#
-+CONFIG_CPU_V7=y
-+CONFIG_CPU_32v6K=y
-+CONFIG_CPU_32v7=y
-+CONFIG_CPU_ABRT_EV7=y
-+CONFIG_CPU_PABRT_V7=y
-+CONFIG_CPU_CACHE_V7=y
-+CONFIG_CPU_CACHE_VIPT=y
-+CONFIG_CPU_COPY_V6=y
-+CONFIG_CPU_TLB_V7=y
-+CONFIG_CPU_HAS_ASID=y
-+CONFIG_CPU_CP15=y
-+CONFIG_CPU_CP15_MMU=y
-+
-+#
-+# Processor Features
-+#
-+CONFIG_ARM_THUMB=y
-+# CONFIG_ARM_THUMBEE is not set
-+# CONFIG_SWP_EMULATE is not set
-+# CONFIG_CPU_ICACHE_DISABLE is not set
-+# CONFIG_CPU_DCACHE_DISABLE is not set
-+# CONFIG_CPU_BPREDICT_DISABLE is not set
-+CONFIG_OUTER_CACHE=y
-+CONFIG_OUTER_CACHE_SYNC=y
-+CONFIG_CACHE_L2X0=y
-+CONFIG_CACHE_PL310=y
-+CONFIG_ARM_L1_CACHE_SHIFT=5
-+CONFIG_ARM_DMA_MEM_BUFFERABLE=y
-+CONFIG_CPU_HAS_PMU=y
-+# CONFIG_ARM_ERRATA_430973 is not set
-+# CONFIG_ARM_ERRATA_458693 is not set
-+# CONFIG_ARM_ERRATA_460075 is not set
-+# CONFIG_ARM_ERRATA_742230 is not set
-+# CONFIG_ARM_ERRATA_742231 is not set
-+# CONFIG_PL310_ERRATA_588369 is not set
-+# CONFIG_ARM_ERRATA_720789 is not set
-+# CONFIG_PL310_ERRATA_727915 is not set
-+CONFIG_ARM_ERRATA_743622=y
-+CONFIG_ARM_ERRATA_751472=y
-+# CONFIG_ARM_ERRATA_753970 is not set
-+CONFIG_ARM_ERRATA_754322=y
-+# CONFIG_ARM_ERRATA_754327 is not set
-+CONFIG_ARM_GIC=y
-+
-+#
-+# Bus support
-+#
-+# CONFIG_PCI_SYSCALL is not set
-+# CONFIG_ARCH_SUPPORTS_MSI is not set
-+# CONFIG_PCCARD is not set
-+CONFIG_ARM_ERRATA_764369=y
-+# CONFIG_PL310_ERRATA_769419 is not set
-+
-+#
-+# Kernel Features
-+#
-+CONFIG_TICK_ONESHOT=y
-+CONFIG_NO_HZ=y
-+CONFIG_HIGH_RES_TIMERS=y
-+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-+CONFIG_SMP=y
-+CONFIG_SMP_ON_UP=y
-+CONFIG_HAVE_ARM_SCU=y
-+CONFIG_HAVE_ARM_TWD=y
-+# CONFIG_VMSPLIT_3G is not set
-+CONFIG_VMSPLIT_2G=y
-+# CONFIG_VMSPLIT_1G is not set
-+CONFIG_PAGE_OFFSET=0x80000000
-+CONFIG_NR_CPUS=4
-+CONFIG_HOTPLUG_CPU=y
-+CONFIG_LOCAL_TIMERS=y
-+# CONFIG_PREEMPT_NONE is not set
-+# CONFIG_PREEMPT_VOLUNTARY is not set
-+CONFIG_PREEMPT=y
-+CONFIG_HZ=100
-+# CONFIG_THUMB2_KERNEL is not set
-+CONFIG_AEABI=y
-+# CONFIG_OABI_COMPAT is not set
-+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-+CONFIG_HAVE_ARCH_PFN_VALID=y
-+CONFIG_HIGHMEM=y
-+# CONFIG_HIGHPTE is not set
-+CONFIG_HW_PERF_EVENTS=y
-+CONFIG_SELECT_MEMORY_MODEL=y
-+CONFIG_FLATMEM_MANUAL=y
-+CONFIG_FLATMEM=y
-+CONFIG_FLAT_NODE_MEM_MAP=y
-+CONFIG_HAVE_MEMBLOCK=y
-+CONFIG_PAGEFLAGS_EXTENDED=y
-+CONFIG_SPLIT_PTLOCK_CPUS=4
-+CONFIG_COMPACTION=y
-+CONFIG_MIGRATION=y
-+# CONFIG_PHYS_ADDR_T_64BIT is not set
-+CONFIG_ZONE_DMA_FLAG=1
-+CONFIG_BOUNCE=y
-+CONFIG_VIRT_TO_BUS=y
-+CONFIG_KSM=y
-+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
-+# CONFIG_CLEANCACHE is not set
-+CONFIG_ALIGNMENT_TRAP=y
-+# CONFIG_UACCESS_WITH_MEMCPY is not set
-+# CONFIG_SECCOMP is not set
-+# CONFIG_CC_STACKPROTECTOR is not set
-+# CONFIG_DEPRECATED_PARAM_STRUCT is not set
-+
-+#
-+# Boot options
-+#
-+# CONFIG_USE_OF is not set
-+CONFIG_ZBOOT_ROM_TEXT=0x0
-+CONFIG_ZBOOT_ROM_BSS=0x0
-+CONFIG_CMDLINE="noinitrd console=ttymxc0,115200 root=/dev/mtdblock2 rw rootfstype=jffs2 ip=off"
-+CONFIG_CMDLINE_FROM_BOOTLOADER=y
-+# CONFIG_CMDLINE_EXTEND is not set
-+# CONFIG_CMDLINE_FORCE is not set
-+# CONFIG_XIP_KERNEL is not set
-+# CONFIG_KEXEC is not set
-+# CONFIG_CRASH_DUMP is not set
-+# CONFIG_AUTO_ZRELADDR is not set
-+
-+#
-+# CPU Power Management
-+#
-+
-+#
-+# CPU Frequency scaling
-+#
-+CONFIG_CPU_FREQ=y
-+CONFIG_CPU_FREQ_TABLE=y
-+CONFIG_CPU_FREQ_STAT=y
-+# CONFIG_CPU_FREQ_STAT_DETAILS is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
-+CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-+# CONFIG_CPU_FREQ_GOV_PERFORMANCE is not set
-+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-+CONFIG_CPU_FREQ_GOV_USERSPACE=y
-+# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
-+CONFIG_CPU_FREQ_GOV_INTERACTIVE=y
-+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-+CONFIG_CPU_FREQ_IMX=y
-+# CONFIG_CPU_IDLE is not set
-+
-+#
-+# Floating point emulation
-+#
-+
-+#
-+# At least one emulation must be selected
-+#
-+CONFIG_VFP=y
-+CONFIG_VFPv3=y
-+CONFIG_NEON=y
-+
-+#
-+# Userspace binary formats
-+#
-+CONFIG_BINFMT_ELF=y
-+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-+CONFIG_HAVE_AOUT=y
-+# CONFIG_BINFMT_AOUT is not set
-+# CONFIG_BINFMT_MISC is not set
-+
-+#
-+# Power management options
-+#
-+CONFIG_SUSPEND=y
-+# CONFIG_PM_TEST_SUSPEND is not set
-+CONFIG_SUSPEND_DEVICE_TIME_DEBUG=y
-+CONFIG_SUSPEND_FREEZER=y
-+CONFIG_PM_SLEEP=y
-+CONFIG_PM_SLEEP_SMP=y
-+CONFIG_PM_RUNTIME=y
-+CONFIG_PM=y
-+CONFIG_PM_DEBUG=y
-+# CONFIG_PM_ADVANCED_DEBUG is not set
-+CONFIG_CAN_PM_TRACE=y
-+CONFIG_APM_EMULATION=y
-+CONFIG_PM_RUNTIME_CLK=y
-+CONFIG_ARCH_SUSPEND_POSSIBLE=y
-+CONFIG_NET=y
-+
-+#
-+# Networking options
-+#
-+CONFIG_PACKET=y
-+CONFIG_UNIX=y
-+CONFIG_XFRM=y
-+# CONFIG_XFRM_USER is not set
-+# CONFIG_XFRM_SUB_POLICY is not set
-+# CONFIG_XFRM_MIGRATE is not set
-+# CONFIG_XFRM_STATISTICS is not set
-+# CONFIG_NET_KEY is not set
-+CONFIG_INET=y
-+CONFIG_IP_MULTICAST=y
-+# CONFIG_IP_ADVANCED_ROUTER is not set
-+CONFIG_IP_PNP=y
-+CONFIG_IP_PNP_DHCP=y
-+CONFIG_IP_PNP_BOOTP=y
-+# CONFIG_IP_PNP_RARP is not set
-+# CONFIG_NET_IPIP is not set
-+# CONFIG_NET_IPGRE_DEMUX is not set
-+# CONFIG_IP_MROUTE is not set
-+# CONFIG_ARPD is not set
-+# CONFIG_SYN_COOKIES is not set
-+# CONFIG_INET_AH is not set
-+# CONFIG_INET_ESP is not set
-+# CONFIG_INET_IPCOMP is not set
-+# CONFIG_INET_XFRM_TUNNEL is not set
-+# CONFIG_INET_TUNNEL is not set
-+CONFIG_INET_XFRM_MODE_TRANSPORT=y
-+CONFIG_INET_XFRM_MODE_TUNNEL=y
-+CONFIG_INET_XFRM_MODE_BEET=y
-+# CONFIG_INET_LRO is not set
-+CONFIG_INET_DIAG=y
-+CONFIG_INET_TCP_DIAG=y
-+# CONFIG_TCP_CONG_ADVANCED is not set
-+CONFIG_TCP_CONG_CUBIC=y
-+CONFIG_DEFAULT_TCP_CONG="cubic"
-+# CONFIG_TCP_MD5SIG is not set
-+# CONFIG_IPV6 is not set
-+# CONFIG_NETWORK_SECMARK is not set
-+# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
-+# CONFIG_NETFILTER is not set
-+# CONFIG_IP_DCCP is not set
-+# CONFIG_IP_SCTP is not set
-+# CONFIG_RDS is not set
-+# CONFIG_TIPC is not set
-+# CONFIG_ATM is not set
-+# CONFIG_L2TP is not set
-+# CONFIG_BRIDGE is not set
-+# CONFIG_NET_DSA is not set
-+# CONFIG_VLAN_8021Q is not set
-+# CONFIG_DECNET is not set
-+# CONFIG_LLC2 is not set
-+# CONFIG_IPX is not set
-+# CONFIG_ATALK is not set
-+# CONFIG_X25 is not set
-+# CONFIG_LAPB is not set
-+# CONFIG_ECONET is not set
-+# CONFIG_WAN_ROUTER is not set
-+# CONFIG_PHONET is not set
-+# CONFIG_IEEE802154 is not set
-+# CONFIG_NET_SCHED is not set
-+# CONFIG_DCB is not set
-+# CONFIG_BATMAN_ADV is not set
-+CONFIG_RPS=y
-+CONFIG_RFS_ACCEL=y
-+CONFIG_XPS=y
-+
-+#
-+# Network testing
-+#
-+# CONFIG_NET_PKTGEN is not set
-+# CONFIG_HAMRADIO is not set
-+CONFIG_CAN=y
-+CONFIG_CAN_RAW=y
-+CONFIG_CAN_BCM=y
-+
-+#
-+# CAN Device Drivers
-+#
-+CONFIG_CAN_VCAN=y
-+# CONFIG_CAN_SLCAN is not set
-+CONFIG_CAN_DEV=y
-+CONFIG_CAN_CALC_BITTIMING=y
-+# CONFIG_CAN_MCP251X is not set
-+CONFIG_HAVE_CAN_FLEXCAN=y
-+CONFIG_CAN_FLEXCAN=y
-+# CONFIG_CAN_SJA1000 is not set
-+# CONFIG_CAN_C_CAN is not set
-+
-+#
-+# CAN USB interfaces
-+#
-+# CONFIG_CAN_EMS_USB is not set
-+# CONFIG_CAN_ESD_USB2 is not set
-+# CONFIG_CAN_SOFTING is not set
-+# CONFIG_CAN_DEBUG_DEVICES is not set
-+# CONFIG_IRDA is not set
-+CONFIG_BT=y
-+CONFIG_BT_L2CAP=y
-+CONFIG_BT_SCO=y
-+CONFIG_BT_RFCOMM=y
-+CONFIG_BT_RFCOMM_TTY=y
-+CONFIG_BT_BNEP=y
-+CONFIG_BT_BNEP_MC_FILTER=y
-+CONFIG_BT_BNEP_PROTO_FILTER=y
-+CONFIG_BT_HIDP=y
-+
-+#
-+# Bluetooth device drivers
-+#
-+CONFIG_BT_HCIBTUSB=y
-+# CONFIG_BT_HCIBTSDIO is not set
-+CONFIG_BT_HCIUART=y
-+# CONFIG_BT_HCIUART_H4 is not set
-+# CONFIG_BT_HCIUART_BCSP is not set
-+CONFIG_BT_HCIUART_ATH3K=y
-+# CONFIG_BT_HCIUART_LL is not set
-+# CONFIG_BT_HCIBCM203X is not set
-+# CONFIG_BT_HCIBPA10X is not set
-+# CONFIG_BT_HCIBFUSB is not set
-+CONFIG_BT_HCIVHCI=y
-+# CONFIG_BT_MRVL is not set
-+# CONFIG_BT_ATH3K is not set
-+# CONFIG_AF_RXRPC is not set
-+CONFIG_WIRELESS=y
-+CONFIG_WIRELESS_EXT=y
-+CONFIG_WEXT_CORE=y
-+CONFIG_WEXT_PROC=y
-+CONFIG_WEXT_SPY=y
-+CONFIG_WEXT_PRIV=y
-+CONFIG_CFG80211=y
-+# CONFIG_NL80211_TESTMODE is not set
-+# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
-+# CONFIG_CFG80211_REG_DEBUG is not set
-+CONFIG_CFG80211_DEFAULT_PS=y
-+# CONFIG_CFG80211_DEBUGFS is not set
-+# CONFIG_CFG80211_INTERNAL_REGDB is not set
-+CONFIG_CFG80211_WEXT=y
-+CONFIG_WIRELESS_EXT_SYSFS=y
-+CONFIG_LIB80211=y
-+CONFIG_LIB80211_CRYPT_WEP=y
-+CONFIG_LIB80211_CRYPT_CCMP=y
-+CONFIG_LIB80211_CRYPT_TKIP=y
-+# CONFIG_LIB80211_DEBUG is not set
-+# CONFIG_MAC80211 is not set
-+# CONFIG_WIMAX is not set
-+CONFIG_RFKILL=y
-+CONFIG_RFKILL_INPUT=y
-+# CONFIG_RFKILL_REGULATOR is not set
-+# CONFIG_RFKILL_GPIO is not set
-+# CONFIG_NET_9P is not set
-+# CONFIG_CAIF is not set
-+# CONFIG_CEPH_LIB is not set
-+
-+#
-+# Device Drivers
-+#
-+
-+#
-+# Generic Driver Options
-+#
-+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-+# CONFIG_DEVTMPFS is not set
-+CONFIG_STANDALONE=y
-+CONFIG_PREVENT_FIRMWARE_BUILD=y
-+CONFIG_FW_LOADER=y
-+CONFIG_FIRMWARE_IN_KERNEL=y
-+CONFIG_EXTRA_FIRMWARE=""
-+# CONFIG_SYS_HYPERVISOR is not set
-+CONFIG_CONNECTOR=y
-+CONFIG_PROC_EVENTS=y
-+CONFIG_MTD=y
-+# CONFIG_MTD_DEBUG is not set
-+# CONFIG_MTD_TESTS is not set
-+# CONFIG_MTD_REDBOOT_PARTS is not set
-+CONFIG_MTD_CMDLINE_PARTS=y
-+# CONFIG_MTD_AFS_PARTS is not set
-+# CONFIG_MTD_AR7_PARTS is not set
-+
-+#
-+# User Modules And Translation Layers
-+#
-+CONFIG_MTD_CHAR=y
-+CONFIG_MTD_BLKDEVS=y
-+CONFIG_MTD_BLOCK=y
-+# CONFIG_FTL is not set
-+# CONFIG_NFTL is not set
-+# CONFIG_INFTL is not set
-+# CONFIG_RFD_FTL is not set
-+# CONFIG_SSFDC is not set
-+# CONFIG_SM_FTL is not set
-+# CONFIG_MTD_OOPS is not set
-+# CONFIG_MTD_SWAP is not set
-+
-+#
-+# RAM/ROM/Flash chip drivers
-+#
-+# CONFIG_MTD_CFI is not set
-+# CONFIG_MTD_JEDECPROBE is not set
-+CONFIG_MTD_MAP_BANK_WIDTH_1=y
-+CONFIG_MTD_MAP_BANK_WIDTH_2=y
-+CONFIG_MTD_MAP_BANK_WIDTH_4=y
-+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-+CONFIG_MTD_CFI_I1=y
-+CONFIG_MTD_CFI_I2=y
-+# CONFIG_MTD_CFI_I4 is not set
-+# CONFIG_MTD_CFI_I8 is not set
-+# CONFIG_MTD_RAM is not set
-+# CONFIG_MTD_ROM is not set
-+# CONFIG_MTD_ABSENT is not set
-+
-+#
-+# Mapping drivers for chip access
-+#
-+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-+# CONFIG_MTD_PLATRAM is not set
-+
-+#
-+# Self-contained MTD device drivers
-+#
-+# CONFIG_MTD_DATAFLASH is not set
-+CONFIG_MTD_M25P80=y
-+CONFIG_M25PXX_USE_FAST_READ=y
-+# CONFIG_MTD_SST25L is not set
-+# CONFIG_MTD_SLRAM is not set
-+# CONFIG_MTD_PHRAM is not set
-+# CONFIG_MTD_MTDRAM is not set
-+# CONFIG_MTD_BLOCK2MTD is not set
-+
-+#
-+# Disk-On-Chip Device Drivers
-+#
-+# CONFIG_MTD_DOC2000 is not set
-+# CONFIG_MTD_DOC2001 is not set
-+# CONFIG_MTD_DOC2001PLUS is not set
-+CONFIG_MTD_NAND_ECC=y
-+# CONFIG_MTD_NAND_ECC_SMC is not set
-+CONFIG_MTD_NAND=y
-+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
-+# CONFIG_MTD_NAND_ECC_BCH is not set
-+# CONFIG_MTD_SM_COMMON is not set
-+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
-+# CONFIG_MTD_NAND_GPIO is not set
-+CONFIG_MTD_NAND_IDS=y
-+# CONFIG_MTD_NAND_DISKONCHIP is not set
-+# CONFIG_MTD_NAND_NANDSIM is not set
-+# CONFIG_MTD_NAND_GPMI_NAND is not set
-+# CONFIG_MTD_NAND_PLATFORM is not set
-+# CONFIG_MTD_ALAUDA is not set
-+# CONFIG_MTD_ONENAND is not set
-+
-+#
-+# LPDDR flash memory drivers
-+#
-+# CONFIG_MTD_LPDDR is not set
-+CONFIG_MTD_UBI=y
-+CONFIG_MTD_UBI_WL_THRESHOLD=4096
-+CONFIG_MTD_UBI_BEB_RESERVE=1
-+# CONFIG_MTD_UBI_GLUEBI is not set
-+# CONFIG_MTD_UBI_DEBUG is not set
-+# CONFIG_PARPORT is not set
-+CONFIG_BLK_DEV=y
-+# CONFIG_BLK_DEV_COW_COMMON is not set
-+CONFIG_BLK_DEV_LOOP=y
-+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
-+# CONFIG_BLK_DEV_DRBD is not set
-+# CONFIG_BLK_DEV_NBD is not set
-+# CONFIG_BLK_DEV_UB is not set
-+CONFIG_BLK_DEV_RAM=y
-+CONFIG_BLK_DEV_RAM_COUNT=16
-+CONFIG_BLK_DEV_RAM_SIZE=4096
-+# CONFIG_BLK_DEV_XIP is not set
-+# CONFIG_CDROM_PKTCDVD is not set
-+# CONFIG_ATA_OVER_ETH is not set
-+# CONFIG_MG_DISK is not set
-+# CONFIG_BLK_DEV_RBD is not set
-+# CONFIG_SENSORS_LIS3LV02D is not set
-+CONFIG_MISC_DEVICES=y
-+# CONFIG_AD525X_DPOT is not set
-+# CONFIG_INTEL_MID_PTI is not set
-+# CONFIG_ICS932S401 is not set
-+# CONFIG_ENCLOSURE_SERVICES is not set
-+# CONFIG_APDS9802ALS is not set
-+# CONFIG_ISL29003 is not set
-+# CONFIG_ISL29020 is not set
-+# CONFIG_SENSORS_TSL2550 is not set
-+# CONFIG_SENSORS_BH1780 is not set
-+# CONFIG_SENSORS_BH1770 is not set
-+# CONFIG_SENSORS_APDS990X is not set
-+# CONFIG_HMC6352 is not set
-+# CONFIG_DS1682 is not set
-+# CONFIG_TI_DAC7512 is not set
-+# CONFIG_BMP085 is not set
-+CONFIG_MXS_PERFMON=m
-+# CONFIG_C2PORT is not set
-+
-+#
-+# EEPROM support
-+#
-+# CONFIG_EEPROM_AT24 is not set
-+# CONFIG_EEPROM_AT25 is not set
-+# CONFIG_EEPROM_LEGACY is not set
-+# CONFIG_EEPROM_MAX6875 is not set
-+# CONFIG_EEPROM_93CX6 is not set
-+# CONFIG_IWMC3200TOP is not set
-+
-+#
-+# Texas Instruments shared transport line discipline
-+#
-+# CONFIG_TI_ST is not set
-+# CONFIG_SENSORS_LIS3_SPI is not set
-+# CONFIG_SENSORS_LIS3_I2C is not set
-+CONFIG_HAVE_IDE=y
-+# CONFIG_IDE is not set
-+
-+#
-+# SCSI device support
-+#
-+CONFIG_SCSI_MOD=y
-+# CONFIG_RAID_ATTRS is not set
-+CONFIG_SCSI=y
-+CONFIG_SCSI_DMA=y
-+# CONFIG_SCSI_TGT is not set
-+# CONFIG_SCSI_NETLINK is not set
-+CONFIG_SCSI_PROC_FS=y
-+
-+#
-+# SCSI support type (disk, tape, CD-ROM)
-+#
-+CONFIG_BLK_DEV_SD=y
-+# CONFIG_CHR_DEV_ST is not set
-+# CONFIG_CHR_DEV_OSST is not set
-+# CONFIG_BLK_DEV_SR is not set
-+# CONFIG_CHR_DEV_SG is not set
-+# CONFIG_CHR_DEV_SCH is not set
-+CONFIG_SCSI_MULTI_LUN=y
-+# CONFIG_SCSI_CONSTANTS is not set
-+# CONFIG_SCSI_LOGGING is not set
-+# CONFIG_SCSI_SCAN_ASYNC is not set
-+CONFIG_SCSI_WAIT_SCAN=m
-+
-+#
-+# SCSI Transports
-+#
-+# CONFIG_SCSI_SPI_ATTRS is not set
-+# CONFIG_SCSI_FC_ATTRS is not set
-+# CONFIG_SCSI_ISCSI_ATTRS is not set
-+# CONFIG_SCSI_SAS_ATTRS is not set
-+# CONFIG_SCSI_SAS_LIBSAS is not set
-+# CONFIG_SCSI_SRP_ATTRS is not set
-+CONFIG_SCSI_LOWLEVEL=y
-+# CONFIG_ISCSI_TCP is not set
-+# CONFIG_ISCSI_BOOT_SYSFS is not set
-+# CONFIG_LIBFC is not set
-+# CONFIG_LIBFCOE is not set
-+# CONFIG_SCSI_DEBUG is not set
-+# CONFIG_SCSI_DH is not set
-+# CONFIG_SCSI_OSD_INITIATOR is not set
-+CONFIG_ATA=y
-+# CONFIG_ATA_NONSTANDARD is not set
-+CONFIG_ATA_VERBOSE_ERROR=y
-+# CONFIG_SATA_PMP is not set
-+
-+#
-+# Controllers with non-SFF native interface
-+#
-+CONFIG_SATA_AHCI_PLATFORM=y
-+CONFIG_ATA_SFF=y
-+
-+#
-+# SFF controllers with custom DMA interface
-+#
-+CONFIG_ATA_BMDMA=y
-+
-+#
-+# SATA SFF controllers with BMDMA
-+#
-+# CONFIG_SATA_MV is not set
-+
-+#
-+# PATA SFF controllers with BMDMA
-+#
-+# CONFIG_PATA_ARASAN_CF is not set
-+
-+#
-+# PIO-only SFF controllers
-+#
-+# CONFIG_PATA_PLATFORM is not set
-+
-+#
-+# Generic fallback / legacy drivers
-+#
-+# CONFIG_MD is not set
-+# CONFIG_TARGET_CORE is not set
-+CONFIG_NETDEVICES=y
-+# CONFIG_DUMMY is not set
-+# CONFIG_BONDING is not set
-+# CONFIG_MACVLAN is not set
-+# CONFIG_EQUALIZER is not set
-+# CONFIG_TUN is not set
-+# CONFIG_VETH is not set
-+CONFIG_MII=y
-+CONFIG_PHYLIB=y
-+
-+#
-+# MII PHY device drivers
-+#
-+# CONFIG_MARVELL_PHY is not set
-+# CONFIG_DAVICOM_PHY is not set
-+# CONFIG_QSEMI_PHY is not set
-+# CONFIG_LXT_PHY is not set
-+# CONFIG_CICADA_PHY is not set
-+# CONFIG_VITESSE_PHY is not set
-+# CONFIG_SMSC_PHY is not set
-+# CONFIG_BROADCOM_PHY is not set
-+# CONFIG_ICPLUS_PHY is not set
-+# CONFIG_REALTEK_PHY is not set
-+# CONFIG_NATIONAL_PHY is not set
-+# CONFIG_STE10XP is not set
-+# CONFIG_LSI_ET1011C_PHY is not set
-+CONFIG_MICREL_PHY=y
-+# CONFIG_FIXED_PHY is not set
-+# CONFIG_MDIO_BITBANG is not set
-+CONFIG_NET_ETHERNET=y
-+# CONFIG_AX88796 is not set
-+# CONFIG_SMC91X is not set
-+# CONFIG_DM9000 is not set
-+# CONFIG_ENC28J60 is not set
-+# CONFIG_ETHOC is not set
-+# CONFIG_SMC911X is not set
-+CONFIG_SMSC911X=y
-+# CONFIG_SMSC911X_ARCH_HOOKS is not set
-+# CONFIG_DNET is not set
-+# CONFIG_IBM_NEW_EMAC_ZMII is not set
-+# CONFIG_IBM_NEW_EMAC_RGMII is not set
-+# CONFIG_IBM_NEW_EMAC_TAH is not set
-+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
-+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
-+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
-+# CONFIG_B44 is not set
-+# CONFIG_KS8842 is not set
-+# CONFIG_KS8851 is not set
-+# CONFIG_KS8851_MLL is not set
-+CONFIG_FEC=y
-+# CONFIG_FEC_1588 is not set
-+# CONFIG_FTMAC100 is not set
-+# CONFIG_NETDEV_1000 is not set
-+# CONFIG_NETDEV_10000 is not set
-+CONFIG_WLAN=y
-+# CONFIG_USB_ZD1201 is not set
-+# CONFIG_USB_NET_RNDIS_WLAN is not set
-+CONFIG_ATH_COMMON=m
-+# CONFIG_ATH_DEBUG is not set
-+CONFIG_ATH6KL=m
-+# CONFIG_ATH6KL_DEBUG is not set
-+CONFIG_HOSTAP=y
-+# CONFIG_HOSTAP_FIRMWARE is not set
-+# CONFIG_IWM is not set
-+# CONFIG_LIBERTAS is not set
-+# CONFIG_MWIFIEX is not set
-+
-+#
-+# Enable WiMAX (Networking options) to see the WiMAX drivers
-+#
-+
-+#
-+# USB Network Adapters
-+#
-+# CONFIG_USB_CATC is not set
-+# CONFIG_USB_KAWETH is not set
-+# CONFIG_USB_PEGASUS is not set
-+# CONFIG_USB_RTL8150 is not set
-+# CONFIG_USB_USBNET is not set
-+# CONFIG_USB_HSO is not set
-+# CONFIG_USB_IPHETH is not set
-+# CONFIG_WAN is not set
-+
-+#
-+# CAIF transport drivers
-+#
-+# CONFIG_PPP is not set
-+# CONFIG_SLIP is not set
-+# CONFIG_NETCONSOLE is not set
-+# CONFIG_NETPOLL is not set
-+# CONFIG_NET_POLL_CONTROLLER is not set
-+# CONFIG_ISDN is not set
-+# CONFIG_PHONE is not set
-+
-+#
-+# Input device support
-+#
-+CONFIG_INPUT=y
-+# CONFIG_INPUT_FF_MEMLESS is not set
-+CONFIG_INPUT_POLLDEV=y
-+# CONFIG_INPUT_SPARSEKMAP is not set
-+
-+#
-+# Userland interfaces
-+#
-+CONFIG_INPUT_MOUSEDEV=y
-+CONFIG_INPUT_MOUSEDEV_PSAUX=y
-+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-+# CONFIG_INPUT_JOYDEV is not set
-+CONFIG_INPUT_EVDEV=y
-+# CONFIG_INPUT_EVBUG is not set
-+# CONFIG_INPUT_APMPOWER is not set
-+
-+#
-+# Input Device Drivers
-+#
-+CONFIG_INPUT_KEYBOARD=y
-+# CONFIG_KEYBOARD_ADP5588 is not set
-+# CONFIG_KEYBOARD_ADP5589 is not set
-+CONFIG_KEYBOARD_ATKBD=y
-+# CONFIG_KEYBOARD_QT1070 is not set
-+# CONFIG_KEYBOARD_QT2160 is not set
-+# CONFIG_KEYBOARD_LKKBD is not set
-+CONFIG_KEYBOARD_GPIO=y
-+# CONFIG_KEYBOARD_TCA6416 is not set
-+# CONFIG_KEYBOARD_MATRIX is not set
-+# CONFIG_KEYBOARD_LM8323 is not set
-+# CONFIG_KEYBOARD_MAX7359 is not set
-+# CONFIG_KEYBOARD_MCS is not set
-+# CONFIG_KEYBOARD_MPR121 is not set
-+# CONFIG_KEYBOARD_IMX is not set
-+# CONFIG_KEYBOARD_NEWTON is not set
-+# CONFIG_KEYBOARD_OPENCORES is not set
-+# CONFIG_KEYBOARD_STOWAWAY is not set
-+# CONFIG_KEYBOARD_SUNKBD is not set
-+# CONFIG_KEYBOARD_XTKBD is not set
-+# CONFIG_KEYBOARD_MXC is not set
-+# CONFIG_INPUT_MOUSE is not set
-+# CONFIG_INPUT_JOYSTICK is not set
-+# CONFIG_INPUT_TABLET is not set
-+CONFIG_INPUT_TOUCHSCREEN=y
-+# CONFIG_TOUCHSCREEN_ADS7846 is not set
-+# CONFIG_TOUCHSCREEN_AD7877 is not set
-+# CONFIG_TOUCHSCREEN_AD7879 is not set
-+# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
-+# CONFIG_TOUCHSCREEN_BU21013 is not set
-+# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set
-+# CONFIG_TOUCHSCREEN_DYNAPRO is not set
-+# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
-+# CONFIG_TOUCHSCREEN_EETI is not set
-+CONFIG_TOUCHSCREEN_EGALAX=y
-+# CONFIG_TOUCHSCREEN_FUJITSU is not set
-+# CONFIG_TOUCHSCREEN_GUNZE is not set
-+# CONFIG_TOUCHSCREEN_ELO is not set
-+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
-+# CONFIG_TOUCHSCREEN_MAX11801 is not set
-+# CONFIG_TOUCHSCREEN_MCS5000 is not set
-+# CONFIG_TOUCHSCREEN_MTOUCH is not set
-+# CONFIG_TOUCHSCREEN_INEXIO is not set
-+# CONFIG_TOUCHSCREEN_MK712 is not set
-+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
-+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
-+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
-+# CONFIG_TOUCHSCREEN_WM97XX is not set
-+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
-+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
-+# CONFIG_TOUCHSCREEN_TSC2005 is not set
-+# CONFIG_TOUCHSCREEN_TSC2007 is not set
-+# CONFIG_TOUCHSCREEN_W90X900 is not set
-+# CONFIG_TOUCHSCREEN_ST1232 is not set
-+# CONFIG_TOUCHSCREEN_P1003 is not set
-+# CONFIG_TOUCHSCREEN_TPS6507X is not set
-+CONFIG_INPUT_MISC=y
-+# CONFIG_INPUT_AD714X is not set
-+# CONFIG_INPUT_ATI_REMOTE is not set
-+# CONFIG_INPUT_ATI_REMOTE2 is not set
-+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
-+# CONFIG_INPUT_POWERMATE is not set
-+# CONFIG_INPUT_YEALINK is not set
-+# CONFIG_INPUT_CM109 is not set
-+CONFIG_INPUT_UINPUT=y
-+# CONFIG_INPUT_PCF8574 is not set
-+# CONFIG_INPUT_PWM_BEEPER is not set
-+# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
-+# CONFIG_INPUT_ADXL34X is not set
-+# CONFIG_INPUT_CMA3000 is not set
-+CONFIG_INPUT_ISL29023=y
-+
-+#
-+# Hardware I/O ports
-+#
-+CONFIG_SERIO=y
-+CONFIG_SERIO_SERPORT=y
-+CONFIG_SERIO_LIBPS2=y
-+# CONFIG_SERIO_RAW is not set
-+# CONFIG_SERIO_ALTERA_PS2 is not set
-+# CONFIG_SERIO_PS2MULT is not set
-+# CONFIG_GAMEPORT is not set
-+
-+#
-+# Character devices
-+#
-+CONFIG_VT=y
-+CONFIG_CONSOLE_TRANSLATIONS=y
-+CONFIG_VT_CONSOLE=y
-+CONFIG_HW_CONSOLE=y
-+# CONFIG_VT_HW_CONSOLE_BINDING is not set
-+CONFIG_UNIX98_PTYS=y
-+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
-+CONFIG_LEGACY_PTYS=y
-+CONFIG_LEGACY_PTY_COUNT=256
-+# CONFIG_SERIAL_NONSTANDARD is not set
-+# CONFIG_N_GSM is not set
-+# CONFIG_TRACE_SINK is not set
-+CONFIG_DEVKMEM=y
-+
-+#
-+# Serial drivers
-+#
-+# CONFIG_SERIAL_8250 is not set
-+
-+#
-+# Non-8250 serial port support
-+#
-+# CONFIG_SERIAL_MAX3100 is not set
-+# CONFIG_SERIAL_MAX3107 is not set
-+CONFIG_SERIAL_IMX=y
-+CONFIG_SERIAL_IMX_CONSOLE=y
-+CONFIG_SERIAL_CORE=y
-+CONFIG_SERIAL_CORE_CONSOLE=y
-+# CONFIG_SERIAL_TIMBERDALE is not set
-+# CONFIG_SERIAL_ALTERA_JTAGUART is not set
-+# CONFIG_SERIAL_ALTERA_UART is not set
-+# CONFIG_SERIAL_IFX6X60 is not set
-+# CONFIG_SERIAL_XILINX_PS_UART is not set
-+# CONFIG_TTY_PRINTK is not set
-+CONFIG_FSL_OTP=y
-+# CONFIG_HVC_DCC is not set
-+# CONFIG_IPMI_HANDLER is not set
-+CONFIG_HW_RANDOM=y
-+# CONFIG_HW_RANDOM_TIMERIOMEM is not set
-+# CONFIG_R3964 is not set
-+# CONFIG_RAW_DRIVER is not set
-+# CONFIG_TCG_TPM is not set
-+# CONFIG_RAMOOPS is not set
-+CONFIG_MXS_VIIM=y
-+CONFIG_I2C=y
-+CONFIG_I2C_BOARDINFO=y
-+CONFIG_I2C_COMPAT=y
-+CONFIG_I2C_CHARDEV=y
-+# CONFIG_I2C_MUX is not set
-+CONFIG_I2C_HELPER_AUTO=y
-+
-+#
-+# I2C Hardware Bus support
-+#
-+
-+#
-+# I2C system bus drivers (mostly embedded / system-on-chip)
-+#
-+# CONFIG_I2C_DESIGNWARE is not set
-+# CONFIG_I2C_GPIO is not set
-+CONFIG_I2C_IMX=y
-+# CONFIG_I2C_OCORES is not set
-+# CONFIG_I2C_PCA_PLATFORM is not set
-+# CONFIG_I2C_PXA_PCI is not set
-+# CONFIG_I2C_SIMTEC is not set
-+# CONFIG_I2C_XILINX is not set
-+
-+#
-+# External I2C/SMBus adapter drivers
-+#
-+# CONFIG_I2C_DIOLAN_U2C is not set
-+# CONFIG_I2C_PARPORT_LIGHT is not set
-+# CONFIG_I2C_TAOS_EVM is not set
-+# CONFIG_I2C_TINY_USB is not set
-+
-+#
-+# Other I2C/SMBus bus drivers
-+#
-+# CONFIG_I2C_STUB is not set
-+# CONFIG_I2C_DEBUG_CORE is not set
-+# CONFIG_I2C_DEBUG_ALGO is not set
-+# CONFIG_I2C_DEBUG_BUS is not set
-+CONFIG_SPI=y
-+CONFIG_SPI_MASTER=y
-+
-+#
-+# SPI Master Controller Drivers
-+#
-+# CONFIG_SPI_ALTERA is not set
-+CONFIG_SPI_BITBANG=y
-+# CONFIG_SPI_GPIO is not set
-+CONFIG_SPI_IMX_VER_2_3=y
-+CONFIG_SPI_IMX=y
-+# CONFIG_SPI_OC_TINY is not set
-+# CONFIG_SPI_PXA2XX_PCI is not set
-+# CONFIG_SPI_XILINX is not set
-+# CONFIG_SPI_DESIGNWARE is not set
-+
-+#
-+# SPI Protocol Masters
-+#
-+# CONFIG_SPI_SPIDEV is not set
-+# CONFIG_SPI_TLE62X0 is not set
-+
-+#
-+# PPS support
-+#
-+# CONFIG_PPS is not set
-+
-+#
-+# PPS generators support
-+#
-+
-+#
-+# PTP clock support
-+#
-+
-+#
-+# Enable Device Drivers -> PPS to see the PTP clock options.
-+#
-+CONFIG_ARCH_REQUIRE_GPIOLIB=y
-+CONFIG_GPIOLIB=y
-+CONFIG_GPIO_SYSFS=y
-+
-+#
-+# Memory mapped GPIO drivers:
-+#
-+# CONFIG_GPIO_BASIC_MMIO is not set
-+# CONFIG_GPIO_IT8761E is not set
-+
-+#
-+# I2C GPIO expanders:
-+#
-+# CONFIG_GPIO_MAX7300 is not set
-+# CONFIG_GPIO_MAX732X is not set
-+# CONFIG_GPIO_PCA953X_IRQ is not set
-+# CONFIG_GPIO_PCF857X is not set
-+# CONFIG_GPIO_SX150X is not set
-+# CONFIG_GPIO_WM8994 is not set
-+# CONFIG_GPIO_ADP5588 is not set
-+
-+#
-+# PCI GPIO expanders:
-+#
-+
-+#
-+# SPI GPIO expanders:
-+#
-+# CONFIG_GPIO_MAX7301 is not set
-+# CONFIG_GPIO_MCP23S08 is not set
-+# CONFIG_GPIO_MC33880 is not set
-+# CONFIG_GPIO_74X164 is not set
-+
-+#
-+# AC97 GPIO expanders:
-+#
-+
-+#
-+# MODULbus GPIO expanders:
-+#
-+# CONFIG_W1 is not set
-+CONFIG_POWER_SUPPLY=y
-+# CONFIG_POWER_SUPPLY_DEBUG is not set
-+# CONFIG_PDA_POWER is not set
-+# CONFIG_APM_POWER is not set
-+# CONFIG_TEST_POWER is not set
-+# CONFIG_BATTERY_DS2780 is not set
-+# CONFIG_BATTERY_DS2782 is not set
-+# CONFIG_BATTERY_BQ20Z75 is not set
-+# CONFIG_BATTERY_BQ27x00 is not set
-+# CONFIG_BATTERY_MAX17040 is not set
-+# CONFIG_BATTERY_MAX17042 is not set
-+# CONFIG_CHARGER_ISP1704 is not set
-+CONFIG_CHARGER_MAX8903=y
-+# CONFIG_CHARGER_GPIO is not set
-+CONFIG_HWMON=y
-+# CONFIG_HWMON_VID is not set
-+# CONFIG_HWMON_DEBUG_CHIP is not set
-+
-+#
-+# Native drivers
-+#
-+# CONFIG_SENSORS_AD7414 is not set
-+# CONFIG_SENSORS_AD7418 is not set
-+# CONFIG_SENSORS_ADCXX is not set
-+# CONFIG_SENSORS_ADM1021 is not set
-+# CONFIG_SENSORS_ADM1025 is not set
-+# CONFIG_SENSORS_ADM1026 is not set
-+# CONFIG_SENSORS_ADM1029 is not set
-+# CONFIG_SENSORS_ADM1031 is not set
-+# CONFIG_SENSORS_ADM9240 is not set
-+# CONFIG_SENSORS_ADT7411 is not set
-+# CONFIG_SENSORS_ADT7462 is not set
-+# CONFIG_SENSORS_ADT7470 is not set
-+# CONFIG_SENSORS_ADT7475 is not set
-+# CONFIG_SENSORS_ASC7621 is not set
-+# CONFIG_SENSORS_ATXP1 is not set
-+# CONFIG_SENSORS_DS620 is not set
-+# CONFIG_SENSORS_DS1621 is not set
-+# CONFIG_SENSORS_F71805F is not set
-+# CONFIG_SENSORS_F71882FG is not set
-+# CONFIG_SENSORS_F75375S is not set
-+# CONFIG_SENSORS_G760A is not set
-+# CONFIG_SENSORS_GL518SM is not set
-+# CONFIG_SENSORS_GL520SM is not set
-+# CONFIG_SENSORS_GPIO_FAN is not set
-+# CONFIG_SENSORS_IT87 is not set
-+# CONFIG_SENSORS_JC42 is not set
-+# CONFIG_SENSORS_LINEAGE is not set
-+# CONFIG_SENSORS_LM63 is not set
-+# CONFIG_SENSORS_LM70 is not set
-+# CONFIG_SENSORS_LM73 is not set
-+# CONFIG_SENSORS_LM75 is not set
-+# CONFIG_SENSORS_LM77 is not set
-+# CONFIG_SENSORS_LM78 is not set
-+# CONFIG_SENSORS_LM80 is not set
-+# CONFIG_SENSORS_LM83 is not set
-+# CONFIG_SENSORS_LM85 is not set
-+# CONFIG_SENSORS_LM87 is not set
-+# CONFIG_SENSORS_LM90 is not set
-+# CONFIG_SENSORS_LM92 is not set
-+# CONFIG_SENSORS_LM93 is not set
-+# CONFIG_SENSORS_LTC4151 is not set
-+# CONFIG_SENSORS_LTC4215 is not set
-+# CONFIG_SENSORS_LTC4245 is not set
-+# CONFIG_SENSORS_LTC4261 is not set
-+# CONFIG_SENSORS_LM95241 is not set
-+# CONFIG_SENSORS_MAX1111 is not set
-+# CONFIG_SENSORS_MAX16065 is not set
-+# CONFIG_SENSORS_MAX1619 is not set
-+# CONFIG_SENSORS_MAX6639 is not set
-+# CONFIG_SENSORS_MAX6642 is not set
-+# CONFIG_SENSORS_MAX17135 is not set
-+# CONFIG_SENSORS_MAX6650 is not set
-+# CONFIG_SENSORS_PC87360 is not set
-+# CONFIG_SENSORS_PC87427 is not set
-+# CONFIG_SENSORS_PCF8591 is not set
-+# CONFIG_PMBUS is not set
-+# CONFIG_SENSORS_SHT15 is not set
-+# CONFIG_SENSORS_SHT21 is not set
-+# CONFIG_SENSORS_SMM665 is not set
-+# CONFIG_SENSORS_DME1737 is not set
-+# CONFIG_SENSORS_EMC1403 is not set
-+# CONFIG_SENSORS_EMC2103 is not set
-+# CONFIG_SENSORS_EMC6W201 is not set
-+# CONFIG_SENSORS_SMSC47M1 is not set
-+# CONFIG_SENSORS_SMSC47M192 is not set
-+# CONFIG_SENSORS_SMSC47B397 is not set
-+# CONFIG_SENSORS_SCH5627 is not set
-+# CONFIG_SENSORS_ADS1015 is not set
-+# CONFIG_SENSORS_ADS7828 is not set
-+# CONFIG_SENSORS_ADS7871 is not set
-+# CONFIG_SENSORS_AMC6821 is not set
-+# CONFIG_SENSORS_THMC50 is not set
-+# CONFIG_SENSORS_TMP102 is not set
-+# CONFIG_SENSORS_TMP401 is not set
-+# CONFIG_SENSORS_TMP421 is not set
-+# CONFIG_SENSORS_VT1211 is not set
-+# CONFIG_SENSORS_W83781D is not set
-+# CONFIG_SENSORS_W83791D is not set
-+# CONFIG_SENSORS_W83792D is not set
-+# CONFIG_SENSORS_W83793 is not set
-+# CONFIG_SENSORS_W83795 is not set
-+# CONFIG_SENSORS_W83L785TS is not set
-+# CONFIG_SENSORS_W83L786NG is not set
-+# CONFIG_SENSORS_W83627HF is not set
-+# CONFIG_SENSORS_W83627EHF is not set
-+CONFIG_SENSORS_MAG3110=y
-+# CONFIG_MXC_MMA8450 is not set
-+CONFIG_MXC_MMA8451=y
-+CONFIG_THERMAL=y
-+# CONFIG_THERMAL_HWMON is not set
-+CONFIG_WATCHDOG=y
-+CONFIG_WATCHDOG_NOWAYOUT=y
-+
-+#
-+# Watchdog Device Drivers
-+#
-+# CONFIG_SOFT_WATCHDOG is not set
-+# CONFIG_MPCORE_WATCHDOG is not set
-+# CONFIG_MAX63XX_WATCHDOG is not set
-+CONFIG_IMX2_WDT=y
-+
-+#
-+# USB-based Watchdog Cards
-+#
-+# CONFIG_USBPCWATCHDOG is not set
-+CONFIG_SSB_POSSIBLE=y
-+
-+#
-+# Sonics Silicon Backplane
-+#
-+# CONFIG_SSB is not set
-+CONFIG_BCMA_POSSIBLE=y
-+
-+#
-+# Broadcom specific AMBA
-+#
-+# CONFIG_BCMA is not set
-+CONFIG_MFD_SUPPORT=y
-+CONFIG_MFD_CORE=y
-+# CONFIG_MFD_88PM860X is not set
-+# CONFIG_MFD_SM501 is not set
-+# CONFIG_MFD_ASIC3 is not set
-+# CONFIG_HTC_EGPIO is not set
-+# CONFIG_HTC_PASIC3 is not set
-+# CONFIG_HTC_I2CPLD is not set
-+# CONFIG_UCB1400_CORE is not set
-+# CONFIG_TPS6105X is not set
-+# CONFIG_TPS65010 is not set
-+# CONFIG_TPS6507X is not set
-+# CONFIG_MFD_TPS6586X is not set
-+# CONFIG_TWL4030_CORE is not set
-+# CONFIG_MFD_STMPE is not set
-+# CONFIG_MFD_TC3589X is not set
-+# CONFIG_MFD_TMIO is not set
-+# CONFIG_MFD_T7L66XB is not set
-+# CONFIG_MFD_TC6387XB is not set
-+# CONFIG_MFD_TC6393XB is not set
-+# CONFIG_PMIC_DA903X is not set
-+# CONFIG_PMIC_ADP5520 is not set
-+# CONFIG_MFD_MAX8925 is not set
-+# CONFIG_MFD_MAX8997 is not set
-+# CONFIG_MFD_MAX8998 is not set
-+# CONFIG_MFD_WM8400 is not set
-+# CONFIG_MFD_WM831X_I2C is not set
-+# CONFIG_MFD_WM831X_SPI is not set
-+# CONFIG_MFD_WM8350_I2C is not set
-+CONFIG_MFD_WM8994=y
-+# CONFIG_MFD_PCF50633 is not set
-+# CONFIG_PMIC_DIALOG is not set
-+# CONFIG_MFD_MC_PMIC is not set
-+# CONFIG_MFD_MC34708 is not set
-+CONFIG_MFD_PFUZE=y
-+# CONFIG_MFD_MC13XXX is not set
-+# CONFIG_ABX500_CORE is not set
-+# CONFIG_EZX_PCAP is not set
-+# CONFIG_MFD_WL1273_CORE is not set
-+# CONFIG_MFD_TPS65910 is not set
-+# CONFIG_MFD_MAX17135 is not set
-+CONFIG_MFD_MXC_HDMI=y
-+CONFIG_REGULATOR=y
-+# CONFIG_REGULATOR_DEBUG is not set
-+# CONFIG_REGULATOR_DUMMY is not set
-+CONFIG_REGULATOR_FIXED_VOLTAGE=y
-+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
-+# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
-+# CONFIG_REGULATOR_BQ24022 is not set
-+# CONFIG_REGULATOR_MAX1586 is not set
-+# CONFIG_REGULATOR_MAX8649 is not set
-+# CONFIG_REGULATOR_MAX8660 is not set
-+# CONFIG_REGULATOR_MAX8952 is not set
-+# CONFIG_REGULATOR_WM8994 is not set
-+# CONFIG_REGULATOR_LP3971 is not set
-+# CONFIG_REGULATOR_LP3972 is not set
-+# CONFIG_REGULATOR_MC34708 is not set
-+CONFIG_REGULATOR_PFUZE100=y
-+# CONFIG_REGULATOR_TPS65023 is not set
-+# CONFIG_REGULATOR_TPS6507X is not set
-+# CONFIG_REGULATOR_ISL6271A is not set
-+# CONFIG_REGULATOR_AD5398 is not set
-+CONFIG_REGULATOR_ANATOP=y
-+# CONFIG_REGULATOR_TPS6524X is not set
-+CONFIG_MEDIA_SUPPORT=y
-+
-+#
-+# Multimedia core support
-+#
-+# CONFIG_MEDIA_CONTROLLER is not set
-+CONFIG_VIDEO_DEV=y
-+CONFIG_VIDEO_V4L2_COMMON=y
-+# CONFIG_DVB_CORE is not set
-+CONFIG_VIDEO_MEDIA=y
-+
-+#
-+# Multimedia drivers
-+#
-+# CONFIG_RC_CORE is not set
-+# CONFIG_MEDIA_ATTACH is not set
-+CONFIG_MEDIA_TUNER=y
-+# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
-+CONFIG_MEDIA_TUNER_SIMPLE=y
-+CONFIG_MEDIA_TUNER_TDA8290=y
-+CONFIG_MEDIA_TUNER_TDA827X=y
-+CONFIG_MEDIA_TUNER_TDA18271=y
-+CONFIG_MEDIA_TUNER_TDA9887=y
-+CONFIG_MEDIA_TUNER_TEA5761=y
-+CONFIG_MEDIA_TUNER_TEA5767=y
-+CONFIG_MEDIA_TUNER_MT20XX=y
-+CONFIG_MEDIA_TUNER_XC2028=y
-+CONFIG_MEDIA_TUNER_XC5000=y
-+CONFIG_MEDIA_TUNER_MC44S803=y
-+CONFIG_VIDEO_V4L2=y
-+CONFIG_VIDEOBUF_GEN=y
-+CONFIG_VIDEOBUF_DMA_CONTIG=y
-+CONFIG_VIDEO_CAPTURE_DRIVERS=y
-+# CONFIG_VIDEO_ADV_DEBUG is not set
-+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
-+# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
-+
-+#
-+# Encoders, decoders, sensors and other helper chips
-+#
-+
-+#
-+# Audio decoders, processors and mixers
-+#
-+# CONFIG_VIDEO_TVAUDIO is not set
-+# CONFIG_VIDEO_TDA7432 is not set
-+# CONFIG_VIDEO_TDA9840 is not set
-+# CONFIG_VIDEO_TEA6415C is not set
-+# CONFIG_VIDEO_TEA6420 is not set
-+# CONFIG_VIDEO_MSP3400 is not set
-+# CONFIG_VIDEO_CS5345 is not set
-+# CONFIG_VIDEO_CS53L32A is not set
-+# CONFIG_VIDEO_TLV320AIC23B is not set
-+# CONFIG_VIDEO_WM8775 is not set
-+# CONFIG_VIDEO_WM8739 is not set
-+# CONFIG_VIDEO_VP27SMPX is not set
-+
-+#
-+# RDS decoders
-+#
-+# CONFIG_VIDEO_SAA6588 is not set
-+
-+#
-+# Video decoders
-+#
-+# CONFIG_VIDEO_ADV7180 is not set
-+# CONFIG_VIDEO_BT819 is not set
-+# CONFIG_VIDEO_BT856 is not set
-+# CONFIG_VIDEO_BT866 is not set
-+# CONFIG_VIDEO_KS0127 is not set
-+# CONFIG_VIDEO_SAA7110 is not set
-+# CONFIG_VIDEO_SAA711X is not set
-+# CONFIG_VIDEO_SAA7191 is not set
-+# CONFIG_VIDEO_TVP514X is not set
-+# CONFIG_VIDEO_TVP5150 is not set
-+# CONFIG_VIDEO_TVP7002 is not set
-+# CONFIG_VIDEO_VPX3220 is not set
-+
-+#
-+# Video and audio decoders
-+#
-+# CONFIG_VIDEO_SAA717X is not set
-+# CONFIG_VIDEO_CX25840 is not set
-+
-+#
-+# MPEG video encoders
-+#
-+# CONFIG_VIDEO_CX2341X is not set
-+
-+#
-+# Video encoders
-+#
-+# CONFIG_VIDEO_SAA7127 is not set
-+# CONFIG_VIDEO_SAA7185 is not set
-+# CONFIG_VIDEO_ADV7170 is not set
-+# CONFIG_VIDEO_ADV7175 is not set
-+# CONFIG_VIDEO_ADV7343 is not set
-+# CONFIG_VIDEO_AK881X is not set
-+
-+#
-+# Camera sensor devices
-+#
-+# CONFIG_VIDEO_OV7670 is not set
-+# CONFIG_VIDEO_MT9V011 is not set
-+# CONFIG_VIDEO_TCM825X is not set
-+
-+#
-+# Video improvement chips
-+#
-+# CONFIG_VIDEO_UPD64031A is not set
-+# CONFIG_VIDEO_UPD64083 is not set
-+
-+#
-+# Miscelaneous helper chips
-+#
-+# CONFIG_VIDEO_THS7303 is not set
-+# CONFIG_VIDEO_M52790 is not set
-+# CONFIG_VIDEO_VIVI is not set
-+CONFIG_VIDEO_MXC_CAMERA=m
-+
-+#
-+# MXC Camera/V4L2 PRP Features support
-+#
-+CONFIG_VIDEO_MXC_IPU_CAMERA=y
-+# CONFIG_VIDEO_MXC_CSI_CAMERA is not set
-+# CONFIG_MXC_CAMERA_MICRON111 is not set
-+# CONFIG_MXC_CAMERA_OV2640 is not set
-+CONFIG_MXC_CAMERA_OV3640=m
-+CONFIG_MXC_CAMERA_OV5640=m
-+CONFIG_MXC_CAMERA_OV5640_MIPI=m
-+CONFIG_MXC_CAMERA_OV8820_MIPI=m
-+CONFIG_MXC_CAMERA_OV5642=m
-+CONFIG_MXC_CAMERA_SENSOR_CLK=m
-+CONFIG_MXC_IPU_PRP_VF_SDC=m
-+CONFIG_MXC_IPU_PRP_ENC=m
-+CONFIG_MXC_IPU_CSI_ENC=m
-+CONFIG_VIDEO_MXC_OUTPUT=y
-+CONFIG_VIDEO_MXC_IPU_OUTPUT=y
-+# CONFIG_VIDEO_MXC_IPUV1_WVGA_OUTPUT is not set
-+# CONFIG_VIDEO_MXC_OPL is not set
-+# CONFIG_VIDEO_CPIA2 is not set
-+# CONFIG_VIDEO_TIMBERDALE is not set
-+# CONFIG_VIDEO_SR030PC30 is not set
-+# CONFIG_VIDEO_NOON010PC30 is not set
-+# CONFIG_SOC_CAMERA is not set
-+CONFIG_V4L_USB_DRIVERS=y
-+CONFIG_USB_VIDEO_CLASS=m
-+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
-+CONFIG_USB_GSPCA=m
-+# CONFIG_USB_M5602 is not set
-+# CONFIG_USB_STV06XX is not set
-+# CONFIG_USB_GL860 is not set
-+# CONFIG_USB_GSPCA_BENQ is not set
-+# CONFIG_USB_GSPCA_CONEX is not set
-+# CONFIG_USB_GSPCA_CPIA1 is not set
-+# CONFIG_USB_GSPCA_ETOMS is not set
-+# CONFIG_USB_GSPCA_FINEPIX is not set
-+# CONFIG_USB_GSPCA_JEILINJ is not set
-+# CONFIG_USB_GSPCA_KINECT is not set
-+# CONFIG_USB_GSPCA_KONICA is not set
-+# CONFIG_USB_GSPCA_MARS is not set
-+# CONFIG_USB_GSPCA_MR97310A is not set
-+# CONFIG_USB_GSPCA_NW80X is not set
-+# CONFIG_USB_GSPCA_OV519 is not set
-+# CONFIG_USB_GSPCA_OV534 is not set
-+# CONFIG_USB_GSPCA_OV534_9 is not set
-+# CONFIG_USB_GSPCA_PAC207 is not set
-+# CONFIG_USB_GSPCA_PAC7302 is not set
-+# CONFIG_USB_GSPCA_PAC7311 is not set
-+# CONFIG_USB_GSPCA_SN9C2028 is not set
-+# CONFIG_USB_GSPCA_SN9C20X is not set
-+# CONFIG_USB_GSPCA_SONIXB is not set
-+# CONFIG_USB_GSPCA_SONIXJ is not set
-+# CONFIG_USB_GSPCA_SPCA500 is not set
-+# CONFIG_USB_GSPCA_SPCA501 is not set
-+# CONFIG_USB_GSPCA_SPCA505 is not set
-+# CONFIG_USB_GSPCA_SPCA506 is not set
-+# CONFIG_USB_GSPCA_SPCA508 is not set
-+# CONFIG_USB_GSPCA_SPCA561 is not set
-+# CONFIG_USB_GSPCA_SPCA1528 is not set
-+# CONFIG_USB_GSPCA_SQ905 is not set
-+# CONFIG_USB_GSPCA_SQ905C is not set
-+# CONFIG_USB_GSPCA_SQ930X is not set
-+# CONFIG_USB_GSPCA_STK014 is not set
-+# CONFIG_USB_GSPCA_STV0680 is not set
-+# CONFIG_USB_GSPCA_SUNPLUS is not set
-+# CONFIG_USB_GSPCA_T613 is not set
-+# CONFIG_USB_GSPCA_TV8532 is not set
-+# CONFIG_USB_GSPCA_VC032X is not set
-+# CONFIG_USB_GSPCA_VICAM is not set
-+# CONFIG_USB_GSPCA_XIRLINK_CIT is not set
-+# CONFIG_USB_GSPCA_ZC3XX is not set
-+# CONFIG_VIDEO_PVRUSB2 is not set
-+# CONFIG_VIDEO_HDPVR is not set
-+# CONFIG_VIDEO_USBVISION is not set
-+# CONFIG_USB_ET61X251 is not set
-+# CONFIG_USB_SN9C102 is not set
-+# CONFIG_USB_PWC is not set
-+# CONFIG_USB_ZR364XX is not set
-+# CONFIG_USB_STKWEBCAM is not set
-+# CONFIG_USB_S2255 is not set
-+# CONFIG_V4L_MEM2MEM_DRIVERS is not set
-+# CONFIG_RADIO_ADAPTERS is not set
-+
-+#
-+# Graphics support
-+#
-+# CONFIG_DRM is not set
-+# CONFIG_VGASTATE is not set
-+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
-+CONFIG_FB=y
-+# CONFIG_FIRMWARE_EDID is not set
-+# CONFIG_FB_DDC is not set
-+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
-+CONFIG_FB_CFB_FILLRECT=y
-+CONFIG_FB_CFB_COPYAREA=y
-+CONFIG_FB_CFB_IMAGEBLIT=y
-+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
-+# CONFIG_FB_SYS_FILLRECT is not set
-+# CONFIG_FB_SYS_COPYAREA is not set
-+# CONFIG_FB_SYS_IMAGEBLIT is not set
-+# CONFIG_FB_FOREIGN_ENDIAN is not set
-+# CONFIG_FB_SYS_FOPS is not set
-+# CONFIG_FB_WMT_GE_ROPS is not set
-+CONFIG_FB_DEFERRED_IO=y
-+# CONFIG_FB_SVGALIB is not set
-+# CONFIG_FB_MACMODES is not set
-+# CONFIG_FB_BACKLIGHT is not set
-+CONFIG_FB_MODE_HELPERS=y
-+# CONFIG_FB_TILEBLITTING is not set
-+
-+#
-+# Frame buffer hardware drivers
-+#
-+# CONFIG_FB_UVESA is not set
-+# CONFIG_FB_S1D13XXX is not set
-+# CONFIG_FB_TMIO is not set
-+# CONFIG_FB_UDL is not set
-+# CONFIG_FB_VIRTUAL is not set
-+# CONFIG_FB_METRONOME is not set
-+# CONFIG_FB_BROADSHEET is not set
-+CONFIG_BACKLIGHT_LCD_SUPPORT=y
-+# CONFIG_LCD_CLASS_DEVICE is not set
-+CONFIG_BACKLIGHT_CLASS_DEVICE=y
-+# CONFIG_BACKLIGHT_GENERIC is not set
-+CONFIG_BACKLIGHT_PWM=y
-+# CONFIG_BACKLIGHT_ADP8860 is not set
-+# CONFIG_BACKLIGHT_ADP8870 is not set
-+
-+#
-+# Display device support
-+#
-+# CONFIG_DISPLAY_SUPPORT is not set
-+CONFIG_FB_MXC=y
-+CONFIG_FB_MXC_EDID=y
-+CONFIG_FB_MXC_SYNC_PANEL=y
-+# CONFIG_FB_MXC_EPSON_VGA_SYNC_PANEL is not set
-+CONFIG_FB_MXC_LDB=y
-+CONFIG_FB_MXC_MIPI_DSI=y
-+CONFIG_FB_MXC_TRULY_WVGA_SYNC_PANEL=y
-+# CONFIG_FB_MXC_CLAA_WVGA_SYNC_PANEL is not set
-+# CONFIG_FB_MXC_SEIKO_WVGA_SYNC_PANEL is not set
-+# CONFIG_FB_MXC_SII902X is not set
-+# CONFIG_FB_MXC_CH7026 is not set
-+# CONFIG_FB_MXC_TVOUT_CH7024 is not set
-+# CONFIG_FB_MXC_ASYNC_PANEL is not set
-+CONFIG_FB_MXC_EINK_PANEL=y
-+# CONFIG_FB_MXC_EINK_AUTO_UPDATE_MODE is not set
-+# CONFIG_FB_MXC_ELCDIF_FB is not set
-+CONFIG_FB_MXC_HDMI=y
-+
-+#
-+# Console display driver support
-+#
-+CONFIG_DUMMY_CONSOLE=y
-+CONFIG_FRAMEBUFFER_CONSOLE=y
-+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
-+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
-+CONFIG_FONTS=y
-+# CONFIG_FONT_8x8 is not set
-+CONFIG_FONT_8x16=y
-+# CONFIG_FONT_6x11 is not set
-+# CONFIG_FONT_7x14 is not set
-+# CONFIG_FONT_PEARL_8x8 is not set
-+# CONFIG_FONT_ACORN_8x8 is not set
-+# CONFIG_FONT_MINI_4x6 is not set
-+# CONFIG_FONT_SUN8x16 is not set
-+# CONFIG_FONT_SUN12x22 is not set
-+# CONFIG_FONT_10x18 is not set
-+CONFIG_LOGO=y
-+CONFIG_LOGO_LINUX_MONO=y
-+CONFIG_LOGO_LINUX_VGA16=y
-+CONFIG_LOGO_LINUX_CLUT224=y
-+CONFIG_SOUND=y
-+# CONFIG_SOUND_OSS_CORE is not set
-+CONFIG_SND=y
-+CONFIG_SND_TIMER=y
-+CONFIG_SND_PCM=y
-+CONFIG_SND_HWDEP=y
-+CONFIG_SND_RAWMIDI=y
-+CONFIG_SND_JACK=y
-+# CONFIG_SND_SEQUENCER is not set
-+# CONFIG_SND_MIXER_OSS is not set
-+# CONFIG_SND_PCM_OSS is not set
-+# CONFIG_SND_HRTIMER is not set
-+# CONFIG_SND_DYNAMIC_MINORS is not set
-+CONFIG_SND_SUPPORT_OLD_API=y
-+CONFIG_SND_VERBOSE_PROCFS=y
-+# CONFIG_SND_VERBOSE_PRINTK is not set
-+# CONFIG_SND_DEBUG is not set
-+# CONFIG_SND_RAWMIDI_SEQ is not set
-+# CONFIG_SND_OPL3_LIB_SEQ is not set
-+# CONFIG_SND_OPL4_LIB_SEQ is not set
-+# CONFIG_SND_SBAWE_SEQ is not set
-+# CONFIG_SND_EMU10K1_SEQ is not set
-+CONFIG_SND_DRIVERS=y
-+# CONFIG_SND_DUMMY is not set
-+# CONFIG_SND_ALOOP is not set
-+# CONFIG_SND_MTPAV is not set
-+# CONFIG_SND_SERIAL_U16550 is not set
-+# CONFIG_SND_MPU401 is not set
-+CONFIG_SND_ARM=y
-+CONFIG_SND_SPI=y
-+CONFIG_SND_USB=y
-+CONFIG_SND_USB_AUDIO=y
-+# CONFIG_SND_USB_UA101 is not set
-+# CONFIG_SND_USB_CAIAQ is not set
-+# CONFIG_SND_USB_6FIRE is not set
-+CONFIG_SND_SOC=y
-+# CONFIG_SND_SOC_CACHE_LZO is not set
-+CONFIG_SND_SOC_AC97_BUS=y
-+CONFIG_SND_IMX_SOC=y
-+CONFIG_SND_MXC_SOC_MX2=y
-+CONFIG_SND_MXC_SOC_SPDIF_DAI=y
-+CONFIG_SND_SOC_IMX_SGTL5000=y
-+CONFIG_SND_SOC_IMX_WM8958=y
-+CONFIG_SND_SOC_IMX_WM8962=y
-+CONFIG_SND_SOC_IMX_SPDIF=y
-+CONFIG_SND_SOC_IMX_HDMI=y
-+CONFIG_SND_SOC_I2C_AND_SPI=y
-+# CONFIG_SND_SOC_ALL_CODECS is not set
-+CONFIG_SND_SOC_WM_HUBS=y
-+CONFIG_SND_SOC_MXC_HDMI=y
-+CONFIG_SND_SOC_MXC_SPDIF=y
-+CONFIG_SND_SOC_SGTL5000=y
-+CONFIG_SND_SOC_WM8962=y
-+CONFIG_SND_SOC_WM8994=y
-+# CONFIG_SOUND_PRIME is not set
-+CONFIG_AC97_BUS=y
-+CONFIG_HID_SUPPORT=y
-+CONFIG_HID=y
-+CONFIG_HIDRAW=y
-+
-+#
-+# USB Input Devices
-+#
-+CONFIG_USB_HID=y
-+# CONFIG_HID_PID is not set
-+# CONFIG_USB_HIDDEV is not set
-+
-+#
-+# Special HID drivers
-+#
-+CONFIG_HID_A4TECH=m
-+# CONFIG_HID_ACRUX is not set
-+CONFIG_HID_APPLE=m
-+CONFIG_HID_BELKIN=m
-+CONFIG_HID_CHERRY=m
-+CONFIG_HID_CHICONY=m
-+# CONFIG_HID_PRODIKEYS is not set
-+CONFIG_HID_CYPRESS=m
-+# CONFIG_HID_DRAGONRISE is not set
-+# CONFIG_HID_EMS_FF is not set
-+# CONFIG_HID_ELECOM is not set
-+CONFIG_HID_EZKEY=m
-+# CONFIG_HID_KEYTOUCH is not set
-+# CONFIG_HID_KYE is not set
-+# CONFIG_HID_UCLOGIC is not set
-+# CONFIG_HID_WALTOP is not set
-+CONFIG_HID_GYRATION=m
-+# CONFIG_HID_TWINHAN is not set
-+# CONFIG_HID_KENSINGTON is not set
-+# CONFIG_HID_LCPOWER is not set
-+CONFIG_HID_LOGITECH=m
-+# CONFIG_LOGITECH_FF is not set
-+# CONFIG_LOGIRUMBLEPAD2_FF is not set
-+# CONFIG_LOGIG940_FF is not set
-+# CONFIG_LOGIWII_FF is not set
-+# CONFIG_HID_MAGICMOUSE is not set
-+CONFIG_HID_MICROSOFT=m
-+CONFIG_HID_MONTEREY=m
-+# CONFIG_HID_MULTITOUCH is not set
-+# CONFIG_HID_NTRIG is not set
-+# CONFIG_HID_ORTEK is not set
-+CONFIG_HID_PANTHERLORD=m
-+# CONFIG_PANTHERLORD_FF is not set
-+CONFIG_HID_PETALYNX=m
-+# CONFIG_HID_PICOLCD is not set
-+# CONFIG_HID_QUANTA is not set
-+# CONFIG_HID_ROCCAT is not set
-+# CONFIG_HID_ROCCAT_ARVO is not set
-+# CONFIG_HID_ROCCAT_KONE is not set
-+# CONFIG_HID_ROCCAT_KONEPLUS is not set
-+# CONFIG_HID_ROCCAT_KOVAPLUS is not set
-+# CONFIG_HID_ROCCAT_PYRA is not set
-+CONFIG_HID_SAMSUNG=m
-+CONFIG_HID_SONY=m
-+CONFIG_HID_SUNPLUS=m
-+# CONFIG_HID_GREENASIA is not set
-+# CONFIG_HID_SMARTJOYPLUS is not set
-+# CONFIG_HID_TOPSEED is not set
-+# CONFIG_HID_THRUSTMASTER is not set
-+# CONFIG_HID_WACOM is not set
-+# CONFIG_HID_ZEROPLUS is not set
-+# CONFIG_HID_ZYDACRON is not set
-+CONFIG_USB_SUPPORT=y
-+CONFIG_USB_ARCH_HAS_HCD=y
-+# CONFIG_USB_ARCH_HAS_OHCI is not set
-+CONFIG_USB_ARCH_HAS_EHCI=y
-+CONFIG_USB=y
-+# CONFIG_USB_DEBUG is not set
-+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
-+
-+#
-+# Miscellaneous USB options
-+#
-+# CONFIG_USB_DEVICEFS is not set
-+# CONFIG_USB_DEVICE_CLASS is not set
-+# CONFIG_USB_DYNAMIC_MINORS is not set
-+CONFIG_USB_SUSPEND=y
-+CONFIG_USB_OTG=y
-+# CONFIG_USB_OTG_WHITELIST is not set
-+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
-+# CONFIG_USB_MON is not set
-+# CONFIG_USB_WUSB is not set
-+# CONFIG_USB_WUSB_CBAF is not set
-+
-+#
-+# USB Host Controller Drivers
-+#
-+# CONFIG_USB_C67X00_HCD is not set
-+CONFIG_USB_EHCI_HCD=y
-+CONFIG_USB_EHCI_ARC=y
-+CONFIG_USB_EHCI_ARC_OTG=y
-+# CONFIG_USB_EHCI_ARC_HSIC is not set
-+# CONFIG_USB_STATIC_IRAM is not set
-+CONFIG_USB_EHCI_ROOT_HUB_TT=y
-+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
-+# CONFIG_USB_EHCI_MXC is not set
-+# CONFIG_USB_OXU210HP_HCD is not set
-+# CONFIG_USB_ISP116X_HCD is not set
-+# CONFIG_USB_ISP1760_HCD is not set
-+# CONFIG_USB_ISP1362_HCD is not set
-+# CONFIG_USB_SL811_HCD is not set
-+# CONFIG_USB_R8A66597_HCD is not set
-+# CONFIG_USB_HWA_HCD is not set
-+# CONFIG_USB_MUSB_HDRC is not set
-+
-+#
-+# USB Device Class drivers
-+#
-+# CONFIG_USB_ACM is not set
-+# CONFIG_USB_PRINTER is not set
-+# CONFIG_USB_WDM is not set
-+# CONFIG_USB_TMC is not set
-+
-+#
-+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
-+#
-+
-+#
-+# also be needed; see USB_STORAGE Help for more info
-+#
-+CONFIG_USB_STORAGE=y
-+# CONFIG_USB_STORAGE_DEBUG is not set
-+# CONFIG_USB_STORAGE_REALTEK is not set
-+# CONFIG_USB_STORAGE_DATAFAB is not set
-+# CONFIG_USB_STORAGE_FREECOM is not set
-+# CONFIG_USB_STORAGE_ISD200 is not set
-+# CONFIG_USB_STORAGE_USBAT is not set
-+# CONFIG_USB_STORAGE_SDDR09 is not set
-+# CONFIG_USB_STORAGE_SDDR55 is not set
-+# CONFIG_USB_STORAGE_JUMPSHOT is not set
-+# CONFIG_USB_STORAGE_ALAUDA is not set
-+# CONFIG_USB_STORAGE_ONETOUCH is not set
-+# CONFIG_USB_STORAGE_KARMA is not set
-+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
-+# CONFIG_USB_STORAGE_ENE_UB6250 is not set
-+# CONFIG_USB_UAS is not set
-+# CONFIG_USB_LIBUSUAL is not set
-+
-+#
-+# USB Imaging devices
-+#
-+# CONFIG_USB_MDC800 is not set
-+# CONFIG_USB_MICROTEK is not set
-+
-+#
-+# USB port drivers
-+#
-+# CONFIG_USB_SERIAL is not set
-+
-+#
-+# USB Miscellaneous drivers
-+#
-+# CONFIG_USB_EMI62 is not set
-+# CONFIG_USB_EMI26 is not set
-+# CONFIG_USB_ADUTUX is not set
-+# CONFIG_USB_SEVSEG is not set
-+# CONFIG_USB_RIO500 is not set
-+# CONFIG_USB_LEGOTOWER is not set
-+# CONFIG_USB_LCD is not set
-+# CONFIG_USB_LED is not set
-+# CONFIG_USB_CYPRESS_CY7C63 is not set
-+# CONFIG_USB_CYTHERM is not set
-+# CONFIG_USB_IDMOUSE is not set
-+# CONFIG_USB_FTDI_ELAN is not set
-+# CONFIG_USB_APPLEDISPLAY is not set
-+# CONFIG_USB_SISUSBVGA is not set
-+# CONFIG_USB_LD is not set
-+# CONFIG_USB_TRANCEVIBRATOR is not set
-+# CONFIG_USB_IOWARRIOR is not set
-+# CONFIG_USB_TEST is not set
-+# CONFIG_USB_ISIGHTFW is not set
-+# CONFIG_USB_YUREX is not set
-+CONFIG_USB_GADGET=y
-+# CONFIG_USB_GADGET_DEBUG_FILES is not set
-+# CONFIG_USB_GADGET_DEBUG_FS is not set
-+CONFIG_USB_GADGET_VBUS_DRAW=2
-+CONFIG_USB_GADGET_SELECTED=y
-+CONFIG_USB_GADGET_ARC=y
-+CONFIG_USB_ARC=y
-+# CONFIG_USB_GADGET_FSL_USB2 is not set
-+# CONFIG_USB_GADGET_FUSB300 is not set
-+# CONFIG_USB_GADGET_R8A66597 is not set
-+# CONFIG_USB_GADGET_PXA_U2O is not set
-+# CONFIG_USB_GADGET_M66592 is not set
-+# CONFIG_USB_GADGET_DUMMY_HCD is not set
-+CONFIG_USB_GADGET_DUALSPEED=y
-+# CONFIG_USB_ZERO is not set
-+CONFIG_USB_AUDIO=m
-+CONFIG_USB_ETH=m
-+CONFIG_USB_ETH_RNDIS=y
-+# CONFIG_USB_ETH_EEM is not set
-+# CONFIG_USB_G_NCM is not set
-+# CONFIG_USB_GADGETFS is not set
-+# CONFIG_USB_FUNCTIONFS is not set
-+CONFIG_USB_FILE_STORAGE=m
-+# CONFIG_FSL_UTP is not set
-+# CONFIG_USB_FILE_STORAGE_TEST is not set
-+# CONFIG_USB_MASS_STORAGE is not set
-+CONFIG_USB_G_SERIAL=m
-+# CONFIG_USB_MIDI_GADGET is not set
-+# CONFIG_USB_G_PRINTER is not set
-+# CONFIG_USB_CDC_COMPOSITE is not set
-+# CONFIG_USB_G_MULTI is not set
-+# CONFIG_USB_G_HID is not set
-+# CONFIG_USB_G_DBGP is not set
-+# CONFIG_USB_G_WEBCAM is not set
-+
-+#
-+# OTG and related infrastructure
-+#
-+CONFIG_USB_OTG_UTILS=y
-+# CONFIG_USB_GPIO_VBUS is not set
-+# CONFIG_USB_ULPI is not set
-+# CONFIG_NOP_USB_XCEIV is not set
-+CONFIG_MXC_OTG=y
-+CONFIG_MMC=y
-+# CONFIG_MMC_DEBUG is not set
-+CONFIG_MMC_UNSAFE_RESUME=y
-+# CONFIG_MMC_CLKGATE is not set
-+
-+#
-+# MMC/SD/SDIO Card Drivers
-+#
-+CONFIG_MMC_BLOCK=y
-+CONFIG_MMC_BLOCK_MINORS=8
-+CONFIG_MMC_BLOCK_BOUNCE=y
-+# CONFIG_SDIO_UART is not set
-+# CONFIG_MMC_TEST is not set
-+
-+#
-+# MMC/SD/SDIO Host Controller Drivers
-+#
-+CONFIG_MMC_SDHCI=y
-+CONFIG_MMC_SDHCI_IO_ACCESSORS=y
-+CONFIG_MMC_SDHCI_PLTFM=y
-+CONFIG_MMC_SDHCI_ESDHC_IMX=y
-+# CONFIG_MMC_DW is not set
-+# CONFIG_MMC_VUB300 is not set
-+# CONFIG_MMC_USHC is not set
-+# CONFIG_MEMSTICK is not set
-+CONFIG_NEW_LEDS=y
-+CONFIG_LEDS_CLASS=y
-+
-+#
-+# LED drivers
-+#
-+# CONFIG_LEDS_LM3530 is not set
-+# CONFIG_LEDS_PCA9532 is not set
-+# CONFIG_LEDS_GPIO is not set
-+# CONFIG_LEDS_LP3944 is not set
-+# CONFIG_LEDS_LP5521 is not set
-+# CONFIG_LEDS_LP5523 is not set
-+# CONFIG_LEDS_PCA955X is not set
-+# CONFIG_LEDS_DAC124S085 is not set
-+# CONFIG_LEDS_PWM is not set
-+# CONFIG_LEDS_REGULATOR is not set
-+# CONFIG_LEDS_BD2802 is not set
-+# CONFIG_LEDS_LT3593 is not set
-+# CONFIG_LEDS_TRIGGERS is not set
-+
-+#
-+# LED Triggers
-+#
-+
-+#
-+# LED Triggers
-+#
-+# CONFIG_NFC_DEVICES is not set
-+# CONFIG_ACCESSIBILITY is not set
-+CONFIG_RTC_LIB=y
-+CONFIG_RTC_CLASS=y
-+CONFIG_RTC_HCTOSYS=y
-+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
-+# CONFIG_RTC_DEBUG is not set
-+
-+#
-+# RTC interfaces
-+#
-+CONFIG_RTC_INTF_SYSFS=y
-+CONFIG_RTC_INTF_PROC=y
-+CONFIG_RTC_INTF_DEV=y
-+CONFIG_RTC_INTF_DEV_UIE_EMUL=y
-+# CONFIG_RTC_DRV_TEST is not set
-+
-+#
-+# I2C RTC drivers
-+#
-+# CONFIG_RTC_DRV_DS1307 is not set
-+# CONFIG_RTC_DRV_DS1374 is not set
-+# CONFIG_RTC_DRV_DS1672 is not set
-+# CONFIG_RTC_DRV_DS3232 is not set
-+# CONFIG_RTC_DRV_MAX6900 is not set
-+# CONFIG_RTC_DRV_RS5C372 is not set
-+# CONFIG_RTC_DRV_ISL1208 is not set
-+# CONFIG_RTC_DRV_ISL12022 is not set
-+# CONFIG_RTC_DRV_X1205 is not set
-+# CONFIG_RTC_DRV_PCF8563 is not set
-+# CONFIG_RTC_DRV_PCF8583 is not set
-+# CONFIG_RTC_DRV_M41T80 is not set
-+# CONFIG_RTC_DRV_BQ32K is not set
-+# CONFIG_RTC_DRV_S35390A is not set
-+# CONFIG_RTC_DRV_FM3130 is not set
-+# CONFIG_RTC_DRV_RX8581 is not set
-+# CONFIG_RTC_DRV_RX8025 is not set
-+# CONFIG_RTC_DRV_EM3027 is not set
-+# CONFIG_RTC_DRV_RV3029C2 is not set
-+
-+#
-+# SPI RTC drivers
-+#
-+# CONFIG_RTC_DRV_M41T93 is not set
-+# CONFIG_RTC_DRV_M41T94 is not set
-+# CONFIG_RTC_DRV_DS1305 is not set
-+# CONFIG_RTC_DRV_DS1390 is not set
-+# CONFIG_RTC_DRV_MAX6902 is not set
-+# CONFIG_RTC_DRV_R9701 is not set
-+# CONFIG_RTC_DRV_RS5C348 is not set
-+# CONFIG_RTC_DRV_DS3234 is not set
-+# CONFIG_RTC_DRV_PCF2123 is not set
-+
-+#
-+# Platform RTC drivers
-+#
-+# CONFIG_RTC_DRV_CMOS is not set
-+# CONFIG_RTC_DRV_DS1286 is not set
-+# CONFIG_RTC_DRV_DS1511 is not set
-+# CONFIG_RTC_DRV_DS1553 is not set
-+# CONFIG_RTC_DRV_DS1742 is not set
-+# CONFIG_RTC_DRV_STK17TA8 is not set
-+# CONFIG_RTC_DRV_M48T86 is not set
-+# CONFIG_RTC_DRV_M48T35 is not set
-+# CONFIG_RTC_DRV_M48T59 is not set
-+# CONFIG_RTC_DRV_MSM6242 is not set
-+# CONFIG_RTC_MXC is not set
-+# CONFIG_RTC_DRV_MXC_V2 is not set
-+CONFIG_RTC_DRV_SNVS=y
-+# CONFIG_RTC_DRV_BQ4802 is not set
-+# CONFIG_RTC_DRV_RP5C01 is not set
-+# CONFIG_RTC_DRV_V3020 is not set
-+
-+#
-+# on-CPU RTC drivers
-+#
-+CONFIG_DMADEVICES=y
-+# CONFIG_DMADEVICES_DEBUG is not set
-+
-+#
-+# DMA Devices
-+#
-+# CONFIG_DW_DMAC is not set
-+CONFIG_MXC_PXP_V2=y
-+CONFIG_MXC_PXP_CLIENT_DEVICE=y
-+# CONFIG_TIMB_DMA is not set
-+CONFIG_IMX_SDMA=y
-+# CONFIG_MXS_DMA is not set
-+CONFIG_DMA_ENGINE=y
-+
-+#
-+# DMA Clients
-+#
-+# CONFIG_NET_DMA is not set
-+# CONFIG_ASYNC_TX_DMA is not set
-+# CONFIG_DMATEST is not set
-+# CONFIG_AUXDISPLAY is not set
-+# CONFIG_UIO is not set
-+# CONFIG_STAGING is not set
-+CONFIG_CLKDEV_LOOKUP=y
-+CONFIG_CLKSRC_MMIO=y
-+
-+#
-+# MXC support drivers
-+#
-+CONFIG_MXC_IPU=y
-+CONFIG_MXC_IPU_V3=y
-+CONFIG_MXC_IPU_V3H=y
-+
-+#
-+# MXC SSI support
-+#
-+# CONFIG_MXC_SSI is not set
-+
-+#
-+# MXC Digital Audio Multiplexer support
-+#
-+# CONFIG_MXC_DAM is not set
-+
-+#
-+# MXC PMIC support
-+#
-+# CONFIG_MXC_PMIC_MC13783 is not set
-+# CONFIG_MXC_PMIC_MC13892 is not set
-+# CONFIG_MXC_PMIC_MC34704 is not set
-+# CONFIG_MXC_PMIC_MC9SDZ60 is not set
-+# CONFIG_MXC_PMIC_MC9S08DZ60 is not set
-+
-+#
-+# MXC Security Drivers
-+#
-+# CONFIG_MXC_SECURITY_SCC is not set
-+# CONFIG_MXC_SECURITY_RNG is not set
-+
-+#
-+# MXC MPEG4 Encoder Kernel module support
-+#
-+# CONFIG_MXC_HMP4E is not set
-+
-+#
-+# MXC HARDWARE EVENT
-+#
-+# CONFIG_MXC_HWEVENT is not set
-+
-+#
-+# MXC VPU(Video Processing Unit) support
-+#
-+CONFIG_MXC_VPU=y
-+# CONFIG_MXC_VPU_DEBUG is not set
-+
-+#
-+# MXC Asynchronous Sample Rate Converter support
-+#
-+CONFIG_MXC_ASRC=y
-+
-+#
-+# MXC Bluetooth support
-+#
-+
-+#
-+# Broadcom GPS ioctrl support
-+#
-+
-+#
-+# MXC Media Local Bus Driver
-+#
-+CONFIG_MXC_MLB=y
-+CONFIG_MXC_MLB150=m
-+
-+#
-+# i.MX ADC support
-+#
-+# CONFIG_IMX_ADC is not set
-+
-+#
-+# MXC Vivante GPU support
-+#
-+CONFIG_MXC_GPU_VIV=m
-+
-+#
-+# ANATOP_THERMAL
-+#
-+CONFIG_ANATOP_THERMAL=y
-+
-+#
-+# MXC MIPI Support
-+#
-+CONFIG_MXC_MIPI_CSI2=y
-+
-+#
-+# File systems
-+#
-+CONFIG_EXT2_FS=y
-+# CONFIG_EXT2_FS_XATTR is not set
-+# CONFIG_EXT2_FS_XIP is not set
-+CONFIG_EXT3_FS=y
-+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
-+CONFIG_EXT3_FS_XATTR=y
-+# CONFIG_EXT3_FS_POSIX_ACL is not set
-+# CONFIG_EXT3_FS_SECURITY is not set
-+CONFIG_EXT4_FS=y
-+CONFIG_EXT4_FS_XATTR=y
-+# CONFIG_EXT4_FS_POSIX_ACL is not set
-+# CONFIG_EXT4_FS_SECURITY is not set
-+# CONFIG_EXT4_DEBUG is not set
-+CONFIG_JBD=y
-+# CONFIG_JBD_DEBUG is not set
-+CONFIG_JBD2=y
-+# CONFIG_JBD2_DEBUG is not set
-+CONFIG_FS_MBCACHE=y
-+# CONFIG_REISERFS_FS is not set
-+# CONFIG_JFS_FS is not set
-+# CONFIG_XFS_FS is not set
-+# CONFIG_GFS2_FS is not set
-+# CONFIG_BTRFS_FS is not set
-+# CONFIG_NILFS2_FS is not set
-+# CONFIG_FS_POSIX_ACL is not set
-+CONFIG_FILE_LOCKING=y
-+CONFIG_FSNOTIFY=y
-+CONFIG_DNOTIFY=y
-+CONFIG_INOTIFY_USER=y
-+# CONFIG_FANOTIFY is not set
-+# CONFIG_QUOTA is not set
-+# CONFIG_QUOTACTL is not set
-+CONFIG_AUTOFS4_FS=m
-+# CONFIG_FUSE_FS is not set
-+
-+#
-+# Caches
-+#
-+# CONFIG_FSCACHE is not set
-+
-+#
-+# CD-ROM/DVD Filesystems
-+#
-+# CONFIG_ISO9660_FS is not set
-+# CONFIG_UDF_FS is not set
-+
-+#
-+# DOS/FAT/NT Filesystems
-+#
-+CONFIG_FAT_FS=y
-+CONFIG_MSDOS_FS=y
-+CONFIG_VFAT_FS=y
-+CONFIG_FAT_DEFAULT_CODEPAGE=437
-+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-+# CONFIG_NTFS_FS is not set
-+
-+#
-+# Pseudo filesystems
-+#
-+CONFIG_PROC_FS=y
-+CONFIG_PROC_SYSCTL=y
-+CONFIG_PROC_PAGE_MONITOR=y
-+CONFIG_SYSFS=y
-+CONFIG_TMPFS=y
-+# CONFIG_TMPFS_POSIX_ACL is not set
-+# CONFIG_TMPFS_XATTR is not set
-+# CONFIG_HUGETLB_PAGE is not set
-+# CONFIG_CONFIGFS_FS is not set
-+CONFIG_MISC_FILESYSTEMS=y
-+# CONFIG_ADFS_FS is not set
-+# CONFIG_AFFS_FS is not set
-+# CONFIG_HFS_FS is not set
-+# CONFIG_HFSPLUS_FS is not set
-+# CONFIG_BEFS_FS is not set
-+# CONFIG_BFS_FS is not set
-+# CONFIG_EFS_FS is not set
-+CONFIG_JFFS2_FS=y
-+CONFIG_JFFS2_FS_DEBUG=0
-+CONFIG_JFFS2_FS_WRITEBUFFER=y
-+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
-+# CONFIG_JFFS2_SUMMARY is not set
-+# CONFIG_JFFS2_FS_XATTR is not set
-+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
-+CONFIG_JFFS2_ZLIB=y
-+# CONFIG_JFFS2_LZO is not set
-+CONFIG_JFFS2_RTIME=y
-+# CONFIG_JFFS2_RUBIN is not set
-+CONFIG_UBIFS_FS=y
-+# CONFIG_UBIFS_FS_XATTR is not set
-+# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
-+CONFIG_UBIFS_FS_LZO=y
-+CONFIG_UBIFS_FS_ZLIB=y
-+# CONFIG_UBIFS_FS_DEBUG is not set
-+# CONFIG_LOGFS is not set
-+CONFIG_CRAMFS=y
-+# CONFIG_SQUASHFS is not set
-+# CONFIG_VXFS_FS is not set
-+# CONFIG_MINIX_FS is not set
-+# CONFIG_OMFS_FS is not set
-+# CONFIG_HPFS_FS is not set
-+# CONFIG_QNX4FS_FS is not set
-+# CONFIG_ROMFS_FS is not set
-+# CONFIG_PSTORE is not set
-+# CONFIG_SYSV_FS is not set
-+# CONFIG_UFS_FS is not set
-+CONFIG_NETWORK_FILESYSTEMS=y
-+CONFIG_NFS_FS=y
-+CONFIG_NFS_V3=y
-+# CONFIG_NFS_V3_ACL is not set
-+# CONFIG_NFS_V4 is not set
-+CONFIG_ROOT_NFS=y
-+# CONFIG_NFSD is not set
-+CONFIG_LOCKD=y
-+CONFIG_LOCKD_V4=y
-+CONFIG_NFS_COMMON=y
-+CONFIG_SUNRPC=y
-+# CONFIG_CEPH_FS is not set
-+# CONFIG_CIFS is not set
-+# CONFIG_NCP_FS is not set
-+# CONFIG_CODA_FS is not set
-+# CONFIG_AFS_FS is not set
-+
-+#
-+# Partition Types
-+#
-+CONFIG_PARTITION_ADVANCED=y
-+# CONFIG_ACORN_PARTITION is not set
-+# CONFIG_OSF_PARTITION is not set
-+# CONFIG_AMIGA_PARTITION is not set
-+# CONFIG_ATARI_PARTITION is not set
-+# CONFIG_MAC_PARTITION is not set
-+CONFIG_MSDOS_PARTITION=y
-+# CONFIG_BSD_DISKLABEL is not set
-+# CONFIG_MINIX_SUBPARTITION is not set
-+# CONFIG_SOLARIS_X86_PARTITION is not set
-+# CONFIG_UNIXWARE_DISKLABEL is not set
-+# CONFIG_LDM_PARTITION is not set
-+# CONFIG_SGI_PARTITION is not set
-+# CONFIG_ULTRIX_PARTITION is not set
-+# CONFIG_SUN_PARTITION is not set
-+# CONFIG_KARMA_PARTITION is not set
-+CONFIG_EFI_PARTITION=y
-+# CONFIG_SYSV68_PARTITION is not set
-+CONFIG_NLS=y
-+CONFIG_NLS_DEFAULT="iso8859-1"
-+CONFIG_NLS_CODEPAGE_437=y
-+# CONFIG_NLS_CODEPAGE_737 is not set
-+# CONFIG_NLS_CODEPAGE_775 is not set
-+# CONFIG_NLS_CODEPAGE_850 is not set
-+# CONFIG_NLS_CODEPAGE_852 is not set
-+# CONFIG_NLS_CODEPAGE_855 is not set
-+# CONFIG_NLS_CODEPAGE_857 is not set
-+# CONFIG_NLS_CODEPAGE_860 is not set
-+# CONFIG_NLS_CODEPAGE_861 is not set
-+# CONFIG_NLS_CODEPAGE_862 is not set
-+# CONFIG_NLS_CODEPAGE_863 is not set
-+# CONFIG_NLS_CODEPAGE_864 is not set
-+# CONFIG_NLS_CODEPAGE_865 is not set
-+# CONFIG_NLS_CODEPAGE_866 is not set
-+# CONFIG_NLS_CODEPAGE_869 is not set
-+# CONFIG_NLS_CODEPAGE_936 is not set
-+# CONFIG_NLS_CODEPAGE_950 is not set
-+# CONFIG_NLS_CODEPAGE_932 is not set
-+# CONFIG_NLS_CODEPAGE_949 is not set
-+# CONFIG_NLS_CODEPAGE_874 is not set
-+# CONFIG_NLS_ISO8859_8 is not set
-+# CONFIG_NLS_CODEPAGE_1250 is not set
-+# CONFIG_NLS_CODEPAGE_1251 is not set
-+CONFIG_NLS_ASCII=m
-+CONFIG_NLS_ISO8859_1=y
-+# CONFIG_NLS_ISO8859_2 is not set
-+# CONFIG_NLS_ISO8859_3 is not set
-+# CONFIG_NLS_ISO8859_4 is not set
-+# CONFIG_NLS_ISO8859_5 is not set
-+# CONFIG_NLS_ISO8859_6 is not set
-+# CONFIG_NLS_ISO8859_7 is not set
-+# CONFIG_NLS_ISO8859_9 is not set
-+# CONFIG_NLS_ISO8859_13 is not set
-+# CONFIG_NLS_ISO8859_14 is not set
-+# CONFIG_NLS_ISO8859_15 is not set
-+# CONFIG_NLS_KOI8_R is not set
-+# CONFIG_NLS_KOI8_U is not set
-+CONFIG_NLS_UTF8=m
-+
-+#
-+# Kernel hacking
-+#
-+# CONFIG_PRINTK_TIME is not set
-+CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
-+CONFIG_ENABLE_WARN_DEPRECATED=y
-+CONFIG_ENABLE_MUST_CHECK=y
-+CONFIG_FRAME_WARN=1024
-+# CONFIG_MAGIC_SYSRQ is not set
-+# CONFIG_STRIP_ASM_SYMS is not set
-+# CONFIG_UNUSED_SYMBOLS is not set
-+CONFIG_DEBUG_FS=y
-+# CONFIG_HEADERS_CHECK is not set
-+# CONFIG_DEBUG_SECTION_MISMATCH is not set
-+# CONFIG_DEBUG_KERNEL is not set
-+# CONFIG_HARDLOCKUP_DETECTOR is not set
-+# CONFIG_SLUB_DEBUG_ON is not set
-+# CONFIG_SLUB_STATS is not set
-+# CONFIG_SPARSE_RCU_POINTER is not set
-+CONFIG_DEBUG_BUGVERBOSE=y
-+# CONFIG_DEBUG_MEMORY_INIT is not set
-+CONFIG_RCU_CPU_STALL_TIMEOUT=60
-+CONFIG_RCU_CPU_STALL_VERBOSE=y
-+# CONFIG_LKDTM is not set
-+CONFIG_SYSCTL_SYSCALL_CHECK=y
-+CONFIG_HAVE_FUNCTION_TRACER=y
-+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-+CONFIG_HAVE_DYNAMIC_FTRACE=y
-+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-+CONFIG_HAVE_C_RECORDMCOUNT=y
-+CONFIG_TRACING_SUPPORT=y
-+# CONFIG_FTRACE is not set
-+# CONFIG_DYNAMIC_DEBUG is not set
-+# CONFIG_DMA_API_DEBUG is not set
-+# CONFIG_ATOMIC64_SELFTEST is not set
-+# CONFIG_SAMPLES is not set
-+CONFIG_HAVE_ARCH_KGDB=y
-+# CONFIG_TEST_KSTRTOX is not set
-+# CONFIG_STRICT_DEVMEM is not set
-+CONFIG_ARM_UNWIND=y
-+# CONFIG_DEBUG_USER is not set
-+# CONFIG_OC_ETM is not set
-+
-+#
-+# Security options
-+#
-+# CONFIG_KEYS is not set
-+# CONFIG_SECURITY_DMESG_RESTRICT is not set
-+# CONFIG_SECURITY is not set
-+# CONFIG_SECURITYFS is not set
-+CONFIG_DEFAULT_SECURITY_DAC=y
-+CONFIG_DEFAULT_SECURITY=""
-+CONFIG_CRYPTO=y
-+
-+#
-+# Crypto core or helper
-+#
-+CONFIG_CRYPTO_ALGAPI=y
-+CONFIG_CRYPTO_ALGAPI2=y
-+CONFIG_CRYPTO_AEAD2=y
-+CONFIG_CRYPTO_BLKCIPHER=y
-+CONFIG_CRYPTO_BLKCIPHER2=y
-+CONFIG_CRYPTO_HASH=y
-+CONFIG_CRYPTO_HASH2=y
-+CONFIG_CRYPTO_RNG2=y
-+CONFIG_CRYPTO_PCOMP2=y
-+CONFIG_CRYPTO_MANAGER=y
-+CONFIG_CRYPTO_MANAGER2=y
-+CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
-+# CONFIG_CRYPTO_GF128MUL is not set
-+# CONFIG_CRYPTO_NULL is not set
-+# CONFIG_CRYPTO_PCRYPT is not set
-+CONFIG_CRYPTO_WORKQUEUE=y
-+# CONFIG_CRYPTO_CRYPTD is not set
-+# CONFIG_CRYPTO_AUTHENC is not set
-+CONFIG_CRYPTO_TEST=m
-+# CONFIG_CRYPTO_CRYPTODEV is not set
-+
-+#
-+# Authenticated Encryption with Associated Data
-+#
-+# CONFIG_CRYPTO_CCM is not set
-+# CONFIG_CRYPTO_GCM is not set
-+# CONFIG_CRYPTO_SEQIV is not set
-+
-+#
-+# Block modes
-+#
-+CONFIG_CRYPTO_CBC=y
-+# CONFIG_CRYPTO_CTR is not set
-+# CONFIG_CRYPTO_CTS is not set
-+CONFIG_CRYPTO_ECB=y
-+# CONFIG_CRYPTO_LRW is not set
-+# CONFIG_CRYPTO_PCBC is not set
-+# CONFIG_CRYPTO_XTS is not set
-+
-+#
-+# Hash modes
-+#
-+# CONFIG_CRYPTO_HMAC is not set
-+# CONFIG_CRYPTO_XCBC is not set
-+# CONFIG_CRYPTO_VMAC is not set
-+
-+#
-+# Digest
-+#
-+# CONFIG_CRYPTO_CRC32C is not set
-+# CONFIG_CRYPTO_GHASH is not set
-+# CONFIG_CRYPTO_MD4 is not set
-+# CONFIG_CRYPTO_MD5 is not set
-+CONFIG_CRYPTO_MICHAEL_MIC=y
-+# CONFIG_CRYPTO_RMD128 is not set
-+# CONFIG_CRYPTO_RMD160 is not set
-+# CONFIG_CRYPTO_RMD256 is not set
-+# CONFIG_CRYPTO_RMD320 is not set
-+# CONFIG_CRYPTO_SHA1 is not set
-+# CONFIG_CRYPTO_SHA256 is not set
-+# CONFIG_CRYPTO_SHA512 is not set
-+# CONFIG_CRYPTO_TGR192 is not set
-+# CONFIG_CRYPTO_WP512 is not set
-+
-+#
-+# Ciphers
-+#
-+CONFIG_CRYPTO_AES=y
-+# CONFIG_CRYPTO_ANUBIS is not set
-+CONFIG_CRYPTO_ARC4=y
-+# CONFIG_CRYPTO_BLOWFISH is not set
-+# CONFIG_CRYPTO_CAMELLIA is not set
-+# CONFIG_CRYPTO_CAST5 is not set
-+# CONFIG_CRYPTO_CAST6 is not set
-+# CONFIG_CRYPTO_DES is not set
-+# CONFIG_CRYPTO_FCRYPT is not set
-+# CONFIG_CRYPTO_KHAZAD is not set
-+# CONFIG_CRYPTO_SALSA20 is not set
-+# CONFIG_CRYPTO_SEED is not set
-+# CONFIG_CRYPTO_SERPENT is not set
-+# CONFIG_CRYPTO_TEA is not set
-+# CONFIG_CRYPTO_TWOFISH is not set
-+
-+#
-+# Compression
-+#
-+CONFIG_CRYPTO_DEFLATE=y
-+# CONFIG_CRYPTO_ZLIB is not set
-+CONFIG_CRYPTO_LZO=y
-+
-+#
-+# Random Number Generation
-+#
-+# CONFIG_CRYPTO_ANSI_CPRNG is not set
-+# CONFIG_CRYPTO_USER_API_HASH is not set
-+# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
-+CONFIG_CRYPTO_HW=y
-+# CONFIG_BINARY_PRINTF is not set
-+
-+#
-+# Library routines
-+#
-+CONFIG_BITREVERSE=y
-+CONFIG_RATIONAL=y
-+CONFIG_CRC_CCITT=m
-+CONFIG_CRC16=y
-+# CONFIG_CRC_T10DIF is not set
-+# CONFIG_CRC_ITU_T is not set
-+CONFIG_CRC32=y
-+# CONFIG_CRC7 is not set
-+# CONFIG_LIBCRC32C is not set
-+CONFIG_ZLIB_INFLATE=y
-+CONFIG_ZLIB_DEFLATE=y
-+CONFIG_LZO_COMPRESS=y
-+CONFIG_LZO_DECOMPRESS=y
-+# CONFIG_XZ_DEC is not set
-+# CONFIG_XZ_DEC_BCJ is not set
-+CONFIG_DECOMPRESS_GZIP=y
-+CONFIG_GENERIC_ALLOCATOR=y
-+CONFIG_HAS_IOMEM=y
-+CONFIG_HAS_IOPORT=y
-+CONFIG_HAS_DMA=y
-+CONFIG_CPU_RMAP=y
-+CONFIG_NLATTR=y
-+# CONFIG_AVERAGE is not set
-diff --git a/arch/arm/configs/qmx6_updater_defconfig b/arch/arm/configs/qmx6_updater_defconfig
-new file mode 100644
-index 0000000..0b0c165
---- /dev/null
-+++ b/arch/arm/configs/qmx6_updater_defconfig
-@@ -0,0 +1,2367 @@
-+#
-+# Automatically generated make config: don't edit
-+# Linux/arm 3.0.15 Kernel Configuration
-+#
-+CONFIG_ARM=y
-+CONFIG_HAVE_PWM=y
-+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-+CONFIG_HAVE_SCHED_CLOCK=y
-+CONFIG_GENERIC_GPIO=y
-+# CONFIG_ARCH_USES_GETTIMEOFFSET is not set
-+CONFIG_GENERIC_CLOCKEVENTS=y
-+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-+CONFIG_KTIME_SCALAR=y
-+CONFIG_HAVE_PROC_CPU=y
-+CONFIG_STACKTRACE_SUPPORT=y
-+CONFIG_LOCKDEP_SUPPORT=y
-+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-+CONFIG_HARDIRQS_SW_RESEND=y
-+CONFIG_GENERIC_IRQ_PROBE=y
-+CONFIG_GENERIC_LOCKBREAK=y
-+CONFIG_RWSEM_GENERIC_SPINLOCK=y
-+CONFIG_ARCH_HAS_CPUFREQ=y
-+CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y
-+CONFIG_GENERIC_HWEIGHT=y
-+CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_ZONE_DMA=y
-+CONFIG_NEED_DMA_MAP_STATE=y
-+CONFIG_FIQ=y
-+CONFIG_VECTORS_BASE=0xffff0000
-+# CONFIG_ARM_PATCH_PHYS_VIRT is not set
-+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-+CONFIG_HAVE_IRQ_WORK=y
-+CONFIG_IRQ_WORK=y
-+
-+#
-+# General setup
-+#
-+CONFIG_EXPERIMENTAL=y
-+CONFIG_INIT_ENV_ARG_LIMIT=32
-+CONFIG_CROSS_COMPILE=""
-+CONFIG_LOCALVERSION=""
-+CONFIG_LOCALVERSION_AUTO=y
-+CONFIG_HAVE_KERNEL_GZIP=y
-+CONFIG_HAVE_KERNEL_LZMA=y
-+CONFIG_HAVE_KERNEL_LZO=y
-+CONFIG_KERNEL_GZIP=y
-+# CONFIG_KERNEL_LZMA is not set
-+# CONFIG_KERNEL_LZO is not set
-+CONFIG_DEFAULT_HOSTNAME="(none)"
-+CONFIG_SWAP=y
-+CONFIG_SYSVIPC=y
-+CONFIG_SYSVIPC_SYSCTL=y
-+# CONFIG_POSIX_MQUEUE is not set
-+# CONFIG_BSD_PROCESS_ACCT is not set
-+# CONFIG_FHANDLE is not set
-+# CONFIG_TASKSTATS is not set
-+# CONFIG_AUDIT is not set
-+CONFIG_HAVE_GENERIC_HARDIRQS=y
-+
-+#
-+# IRQ subsystem
-+#
-+CONFIG_GENERIC_HARDIRQS=y
-+CONFIG_HAVE_SPARSE_IRQ=y
-+CONFIG_GENERIC_IRQ_SHOW=y
-+# CONFIG_SPARSE_IRQ is not set
-+
-+#
-+# RCU Subsystem
-+#
-+CONFIG_TREE_PREEMPT_RCU=y
-+CONFIG_PREEMPT_RCU=y
-+# CONFIG_RCU_TRACE is not set
-+CONFIG_RCU_FANOUT=32
-+# CONFIG_RCU_FANOUT_EXACT is not set
-+# CONFIG_TREE_RCU_TRACE is not set
-+# CONFIG_RCU_BOOST is not set
-+CONFIG_IKCONFIG=y
-+CONFIG_IKCONFIG_PROC=y
-+CONFIG_LOG_BUF_SHIFT=14
-+# CONFIG_CGROUPS is not set
-+# CONFIG_NAMESPACES is not set
-+# CONFIG_SCHED_AUTOGROUP is not set
-+# CONFIG_SYSFS_DEPRECATED is not set
-+# CONFIG_RELAY is not set
-+CONFIG_BLK_DEV_INITRD=y
-+CONFIG_INITRAMFS_SOURCE=""
-+CONFIG_RD_GZIP=y
-+# CONFIG_RD_BZIP2 is not set
-+# CONFIG_RD_LZMA is not set
-+# CONFIG_RD_XZ is not set
-+# CONFIG_RD_LZO is not set
-+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-+CONFIG_SYSCTL=y
-+CONFIG_ANON_INODES=y
-+CONFIG_EXPERT=y
-+CONFIG_UID16=y
-+CONFIG_SYSCTL_SYSCALL=y
-+CONFIG_KALLSYMS=y
-+CONFIG_HOTPLUG=y
-+CONFIG_PRINTK=y
-+CONFIG_BUG=y
-+CONFIG_ELF_CORE=y
-+CONFIG_BASE_FULL=y
-+CONFIG_FUTEX=y
-+CONFIG_EPOLL=y
-+CONFIG_SIGNALFD=y
-+CONFIG_TIMERFD=y
-+CONFIG_EVENTFD=y
-+CONFIG_SHMEM=y
-+CONFIG_AIO=y
-+CONFIG_EMBEDDED=y
-+CONFIG_HAVE_PERF_EVENTS=y
-+CONFIG_PERF_USE_VMALLOC=y
-+
-+#
-+# Kernel Performance Events And Counters
-+#
-+CONFIG_PERF_EVENTS=y
-+# CONFIG_PERF_COUNTERS is not set
-+CONFIG_VM_EVENT_COUNTERS=y
-+CONFIG_SLUB_DEBUG=y
-+CONFIG_COMPAT_BRK=y
-+# CONFIG_SLAB is not set
-+CONFIG_SLUB=y
-+# CONFIG_SLOB is not set
-+# CONFIG_PROFILING is not set
-+CONFIG_HAVE_OPROFILE=y
-+# CONFIG_KPROBES is not set
-+CONFIG_HAVE_KPROBES=y
-+CONFIG_HAVE_KRETPROBES=y
-+CONFIG_USE_GENERIC_SMP_HELPERS=y
-+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-+CONFIG_HAVE_CLK=y
-+CONFIG_HAVE_DMA_API_DEBUG=y
-+CONFIG_HAVE_HW_BREAKPOINT=y
-+
-+#
-+# GCOV-based kernel profiling
-+#
-+# CONFIG_GCOV_KERNEL is not set
-+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-+CONFIG_SLABINFO=y
-+CONFIG_RT_MUTEXES=y
-+CONFIG_BASE_SMALL=0
-+CONFIG_MODULES=y
-+# CONFIG_MODULE_FORCE_LOAD is not set
-+CONFIG_MODULE_UNLOAD=y
-+CONFIG_MODULE_FORCE_UNLOAD=y
-+CONFIG_MODVERSIONS=y
-+# CONFIG_MODULE_SRCVERSION_ALL is not set
-+CONFIG_STOP_MACHINE=y
-+CONFIG_BLOCK=y
-+CONFIG_LBDAF=y
-+# CONFIG_BLK_DEV_BSG is not set
-+# CONFIG_BLK_DEV_INTEGRITY is not set
-+
-+#
-+# IO Schedulers
-+#
-+CONFIG_IOSCHED_NOOP=y
-+CONFIG_IOSCHED_DEADLINE=y
-+CONFIG_IOSCHED_CFQ=y
-+# CONFIG_DEFAULT_DEADLINE is not set
-+CONFIG_DEFAULT_CFQ=y
-+# CONFIG_DEFAULT_NOOP is not set
-+CONFIG_DEFAULT_IOSCHED="cfq"
-+# CONFIG_INLINE_SPIN_TRYLOCK is not set
-+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
-+# CONFIG_INLINE_SPIN_LOCK is not set
-+# CONFIG_INLINE_SPIN_LOCK_BH is not set
-+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
-+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
-+# CONFIG_INLINE_SPIN_UNLOCK is not set
-+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
-+# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set
-+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
-+# CONFIG_INLINE_READ_TRYLOCK is not set
-+# CONFIG_INLINE_READ_LOCK is not set
-+# CONFIG_INLINE_READ_LOCK_BH is not set
-+# CONFIG_INLINE_READ_LOCK_IRQ is not set
-+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
-+# CONFIG_INLINE_READ_UNLOCK is not set
-+# CONFIG_INLINE_READ_UNLOCK_BH is not set
-+# CONFIG_INLINE_READ_UNLOCK_IRQ is not set
-+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
-+# CONFIG_INLINE_WRITE_TRYLOCK is not set
-+# CONFIG_INLINE_WRITE_LOCK is not set
-+# CONFIG_INLINE_WRITE_LOCK_BH is not set
-+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
-+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
-+# CONFIG_INLINE_WRITE_UNLOCK is not set
-+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
-+# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set
-+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
-+CONFIG_MUTEX_SPIN_ON_OWNER=y
-+CONFIG_FREEZER=y
-+
-+#
-+# System Type
-+#
-+CONFIG_MMU=y
-+# CONFIG_ARCH_INTEGRATOR is not set
-+# CONFIG_ARCH_REALVIEW is not set
-+# CONFIG_ARCH_VERSATILE is not set
-+# CONFIG_ARCH_VEXPRESS is not set
-+# CONFIG_ARCH_AT91 is not set
-+# CONFIG_ARCH_BCMRING is not set
-+# CONFIG_ARCH_CLPS711X is not set
-+# CONFIG_ARCH_CNS3XXX is not set
-+# CONFIG_ARCH_GEMINI is not set
-+# CONFIG_ARCH_EBSA110 is not set
-+# CONFIG_ARCH_EP93XX is not set
-+# CONFIG_ARCH_FOOTBRIDGE is not set
-+CONFIG_ARCH_MXC=y
-+# CONFIG_ARCH_MXS is not set
-+# CONFIG_ARCH_NETX is not set
-+# CONFIG_ARCH_H720X is not set
-+# CONFIG_ARCH_IOP13XX is not set
-+# CONFIG_ARCH_IOP32X is not set
-+# CONFIG_ARCH_IOP33X is not set
-+# CONFIG_ARCH_IXP23XX is not set
-+# CONFIG_ARCH_IXP2000 is not set
-+# CONFIG_ARCH_IXP4XX is not set
-+# CONFIG_ARCH_DOVE is not set
-+# CONFIG_ARCH_KIRKWOOD is not set
-+# CONFIG_ARCH_LOKI is not set
-+# CONFIG_ARCH_LPC32XX is not set
-+# CONFIG_ARCH_MV78XX0 is not set
-+# CONFIG_ARCH_ORION5X is not set
-+# CONFIG_ARCH_MMP is not set
-+# CONFIG_ARCH_KS8695 is not set
-+# CONFIG_ARCH_W90X900 is not set
-+# CONFIG_ARCH_NUC93X is not set
-+# CONFIG_ARCH_TEGRA is not set
-+# CONFIG_ARCH_PNX4008 is not set
-+# CONFIG_ARCH_PXA is not set
-+# CONFIG_ARCH_MSM is not set
-+# CONFIG_ARCH_SHMOBILE is not set
-+# CONFIG_ARCH_RPC is not set
-+# CONFIG_ARCH_SA1100 is not set
-+# CONFIG_ARCH_S3C2410 is not set
-+# CONFIG_ARCH_S3C64XX is not set
-+# CONFIG_ARCH_S5P64X0 is not set
-+# CONFIG_ARCH_S5PC100 is not set
-+# CONFIG_ARCH_S5PV210 is not set
-+# CONFIG_ARCH_EXYNOS4 is not set
-+# CONFIG_ARCH_SHARK is not set
-+# CONFIG_ARCH_TCC_926 is not set
-+# CONFIG_ARCH_U300 is not set
-+# CONFIG_ARCH_U8500 is not set
-+# CONFIG_ARCH_NOMADIK is not set
-+# CONFIG_ARCH_DAVINCI is not set
-+# CONFIG_ARCH_OMAP is not set
-+# CONFIG_PLAT_SPEAR is not set
-+# CONFIG_ARCH_VT8500 is not set
-+CONFIG_GPIO_PCA953X=y
-+CONFIG_IMX_HAVE_PLATFORM_DMA=y
-+CONFIG_IMX_HAVE_PLATFORM_MXC_MLB=y
-+CONFIG_IMX_HAVE_PLATFORM_FEC=y
-+CONFIG_IMX_HAVE_PLATFORM_FLEXCAN=y
-+CONFIG_IMX_HAVE_PLATFORM_FSL_USB2_UDC=y
-+CONFIG_IMX_HAVE_PLATFORM_GPMI_NFC=y
-+CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT=y
-+CONFIG_IMX_HAVE_PLATFORM_IMX_SNVS_RTC=y
-+CONFIG_IMX_HAVE_PLATFORM_IMX_I2C=y
-+CONFIG_IMX_HAVE_PLATFORM_IMX_SSI=y
-+CONFIG_IMX_HAVE_PLATFORM_IMX_ESAI=y
-+CONFIG_IMX_HAVE_PLATFORM_IMX_UART=y
-+CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI=y
-+CONFIG_IMX_HAVE_PLATFORM_MXC_PWM=y
-+CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX=y
-+CONFIG_IMX_HAVE_PLATFORM_SPI_IMX=y
-+CONFIG_IMX_HAVE_PLATFORM_IMX_IPUV3=y
-+CONFIG_IMX_HAVE_PLATFORM_IMX_VPU=y
-+CONFIG_IMX_HAVE_PLATFORM_IMX_DVFS=y
-+CONFIG_IMX_HAVE_PLATFORM_AHCI=y
-+CONFIG_IMX_HAVE_PLATFORM_IMX_OCOTP=y
-+CONFIG_IMX_HAVE_PLATFORM_IMX_VIIM=y
-+CONFIG_IMX_HAVE_PLATFORM_PERFMON=y
-+CONFIG_IMX_HAVE_PLATFORM_LDB=y
-+CONFIG_IMX_HAVE_PLATFORM_IMX_PXP=y
-+# CONFIG_IMX_HAVE_PLATFORM_IMX_EPDC is not set
-+CONFIG_IMX_HAVE_PLATFORM_IMX_SPDIF=y
-+CONFIG_IMX_HAVE_PLATFORM_VIV_GPU=y
-+CONFIG_IMX_HAVE_PLATFORM_MXC_HDMI=y
-+CONFIG_IMX_HAVE_PLATFORM_IMX_ANATOP_THERMAL=y
-+CONFIG_IMX_HAVE_PLATFORM_FSL_OTG=y
-+CONFIG_IMX_HAVE_PLATFORM_FSL_USB_WAKEUP=y
-+CONFIG_IMX_HAVE_PLATFORM_IMX_PM=y
-+CONFIG_IMX_HAVE_PLATFORM_IMX_ASRC=y
-+CONFIG_IMX_HAVE_PLATFORM_IMX_MIPI_DSI=y
-+CONFIG_IMX_HAVE_PLATFORM_IMX_MIPI_CSI2=y
-+
-+#
-+# Freescale MXC Implementations
-+#
-+# CONFIG_ARCH_MX1 is not set
-+# CONFIG_ARCH_MX2 is not set
-+# CONFIG_ARCH_MX25 is not set
-+# CONFIG_ARCH_MX3 is not set
-+# CONFIG_ARCH_MX503 is not set
-+# CONFIG_ARCH_MX51 is not set
-+CONFIG_ARCH_MX6=y
-+CONFIG_ARCH_MX6Q=y
-+CONFIG_FORCE_MAX_ZONEORDER=13
-+CONFIG_SOC_IMX6Q=y
-+# CONFIG_MACH_MX6Q_ARM2 is not set
-+# CONFIG_MACH_MX6Q_SABRELITE is not set
-+# CONFIG_MACH_MX6Q_SABRESD is not set
-+# CONFIG_MACH_MX6Q_SABREAUTO is not set
-+CONFIG_MACH_MX6Q_QMX6=y
-+
-+#
-+# MX6 Options:
-+#
-+# CONFIG_IMX_PCIE is not set
-+CONFIG_ISP1504_MXC=y
-+# CONFIG_MXC_IRQ_PRIOR is not set
-+CONFIG_MXC_PWM=y
-+# CONFIG_MXC_DEBUG_BOARD is not set
-+CONFIG_ARCH_MXC_IOMUX_V3=y
-+CONFIG_ARCH_MXC_AUDMUX_V2=y
-+CONFIG_IRAM_ALLOC=y
-+CONFIG_CLK_DEBUG=y
-+CONFIG_DMA_ZONE_SIZE=184
-+
-+#
-+# System MMU
-+#
-+
-+#
-+# Processor Type
-+#
-+CONFIG_CPU_V7=y
-+CONFIG_CPU_32v6K=y
-+CONFIG_CPU_32v7=y
-+CONFIG_CPU_ABRT_EV7=y
-+CONFIG_CPU_PABRT_V7=y
-+CONFIG_CPU_CACHE_V7=y
-+CONFIG_CPU_CACHE_VIPT=y
-+CONFIG_CPU_COPY_V6=y
-+CONFIG_CPU_TLB_V7=y
-+CONFIG_CPU_HAS_ASID=y
-+CONFIG_CPU_CP15=y
-+CONFIG_CPU_CP15_MMU=y
-+
-+#
-+# Processor Features
-+#
-+CONFIG_ARM_THUMB=y
-+# CONFIG_ARM_THUMBEE is not set
-+# CONFIG_SWP_EMULATE is not set
-+# CONFIG_CPU_ICACHE_DISABLE is not set
-+# CONFIG_CPU_DCACHE_DISABLE is not set
-+# CONFIG_CPU_BPREDICT_DISABLE is not set
-+CONFIG_OUTER_CACHE=y
-+CONFIG_OUTER_CACHE_SYNC=y
-+CONFIG_CACHE_L2X0=y
-+CONFIG_CACHE_PL310=y
-+CONFIG_ARM_L1_CACHE_SHIFT=5
-+CONFIG_ARM_DMA_MEM_BUFFERABLE=y
-+CONFIG_CPU_HAS_PMU=y
-+# CONFIG_ARM_ERRATA_430973 is not set
-+# CONFIG_ARM_ERRATA_458693 is not set
-+# CONFIG_ARM_ERRATA_460075 is not set
-+# CONFIG_ARM_ERRATA_742230 is not set
-+# CONFIG_ARM_ERRATA_742231 is not set
-+# CONFIG_PL310_ERRATA_588369 is not set
-+# CONFIG_ARM_ERRATA_720789 is not set
-+# CONFIG_PL310_ERRATA_727915 is not set
-+CONFIG_ARM_ERRATA_743622=y
-+CONFIG_ARM_ERRATA_751472=y
-+# CONFIG_ARM_ERRATA_753970 is not set
-+CONFIG_ARM_ERRATA_754322=y
-+# CONFIG_ARM_ERRATA_754327 is not set
-+CONFIG_ARM_GIC=y
-+
-+#
-+# Bus support
-+#
-+# CONFIG_PCI_SYSCALL is not set
-+# CONFIG_ARCH_SUPPORTS_MSI is not set
-+# CONFIG_PCCARD is not set
-+# CONFIG_ARM_ERRATA_764369 is not set
-+# CONFIG_PL310_ERRATA_769419 is not set
-+
-+#
-+# Kernel Features
-+#
-+CONFIG_TICK_ONESHOT=y
-+CONFIG_NO_HZ=y
-+CONFIG_HIGH_RES_TIMERS=y
-+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-+CONFIG_SMP=y
-+CONFIG_SMP_ON_UP=y
-+CONFIG_HAVE_ARM_SCU=y
-+CONFIG_HAVE_ARM_TWD=y
-+# CONFIG_VMSPLIT_3G is not set
-+CONFIG_VMSPLIT_2G=y
-+# CONFIG_VMSPLIT_1G is not set
-+CONFIG_PAGE_OFFSET=0x80000000
-+CONFIG_NR_CPUS=4
-+CONFIG_HOTPLUG_CPU=y
-+CONFIG_LOCAL_TIMERS=y
-+# CONFIG_PREEMPT_NONE is not set
-+# CONFIG_PREEMPT_VOLUNTARY is not set
-+CONFIG_PREEMPT=y
-+CONFIG_HZ=100
-+# CONFIG_THUMB2_KERNEL is not set
-+CONFIG_AEABI=y
-+# CONFIG_OABI_COMPAT is not set
-+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-+CONFIG_HAVE_ARCH_PFN_VALID=y
-+CONFIG_HIGHMEM=y
-+# CONFIG_HIGHPTE is not set
-+CONFIG_HW_PERF_EVENTS=y
-+CONFIG_SELECT_MEMORY_MODEL=y
-+CONFIG_FLATMEM_MANUAL=y
-+CONFIG_FLATMEM=y
-+CONFIG_FLAT_NODE_MEM_MAP=y
-+CONFIG_HAVE_MEMBLOCK=y
-+CONFIG_PAGEFLAGS_EXTENDED=y
-+CONFIG_SPLIT_PTLOCK_CPUS=4
-+# CONFIG_COMPACTION is not set
-+# CONFIG_PHYS_ADDR_T_64BIT is not set
-+CONFIG_ZONE_DMA_FLAG=1
-+CONFIG_BOUNCE=y
-+CONFIG_VIRT_TO_BUS=y
-+# CONFIG_KSM is not set
-+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
-+# CONFIG_CLEANCACHE is not set
-+CONFIG_ALIGNMENT_TRAP=y
-+# CONFIG_UACCESS_WITH_MEMCPY is not set
-+# CONFIG_SECCOMP is not set
-+# CONFIG_CC_STACKPROTECTOR is not set
-+# CONFIG_DEPRECATED_PARAM_STRUCT is not set
-+
-+#
-+# Boot options
-+#
-+# CONFIG_USE_OF is not set
-+CONFIG_ZBOOT_ROM_TEXT=0x0
-+CONFIG_ZBOOT_ROM_BSS=0x0
-+CONFIG_CMDLINE="noinitrd console=ttymxc0,115200 root=/dev/mtdblock2 rw rootfstype=jffs2 ip=off"
-+CONFIG_CMDLINE_FROM_BOOTLOADER=y
-+# CONFIG_CMDLINE_EXTEND is not set
-+# CONFIG_CMDLINE_FORCE is not set
-+# CONFIG_XIP_KERNEL is not set
-+# CONFIG_KEXEC is not set
-+# CONFIG_CRASH_DUMP is not set
-+# CONFIG_AUTO_ZRELADDR is not set
-+
-+#
-+# CPU Power Management
-+#
-+
-+#
-+# CPU Frequency scaling
-+#
-+CONFIG_CPU_FREQ=y
-+CONFIG_CPU_FREQ_TABLE=y
-+CONFIG_CPU_FREQ_STAT=y
-+# CONFIG_CPU_FREQ_STAT_DETAILS is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
-+CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
-+# CONFIG_CPU_FREQ_GOV_PERFORMANCE is not set
-+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-+CONFIG_CPU_FREQ_GOV_USERSPACE=y
-+# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
-+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-+CONFIG_CPU_FREQ_IMX=y
-+# CONFIG_CPU_IDLE is not set
-+
-+#
-+# Floating point emulation
-+#
-+
-+#
-+# At least one emulation must be selected
-+#
-+CONFIG_VFP=y
-+CONFIG_VFPv3=y
-+CONFIG_NEON=y
-+
-+#
-+# Userspace binary formats
-+#
-+CONFIG_BINFMT_ELF=y
-+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-+CONFIG_HAVE_AOUT=y
-+# CONFIG_BINFMT_AOUT is not set
-+# CONFIG_BINFMT_MISC is not set
-+
-+#
-+# Power management options
-+#
-+CONFIG_SUSPEND=y
-+# CONFIG_PM_TEST_SUSPEND is not set
-+CONFIG_SUSPEND_DEVICE_TIME_DEBUG=y
-+CONFIG_SUSPEND_FREEZER=y
-+CONFIG_PM_SLEEP=y
-+CONFIG_PM_SLEEP_SMP=y
-+CONFIG_PM_RUNTIME=y
-+CONFIG_PM=y
-+CONFIG_PM_DEBUG=y
-+# CONFIG_PM_ADVANCED_DEBUG is not set
-+CONFIG_CAN_PM_TRACE=y
-+CONFIG_APM_EMULATION=y
-+CONFIG_PM_RUNTIME_CLK=y
-+CONFIG_ARCH_SUSPEND_POSSIBLE=y
-+CONFIG_NET=y
-+
-+#
-+# Networking options
-+#
-+CONFIG_PACKET=y
-+CONFIG_UNIX=y
-+CONFIG_XFRM=y
-+# CONFIG_XFRM_USER is not set
-+# CONFIG_XFRM_SUB_POLICY is not set
-+# CONFIG_XFRM_MIGRATE is not set
-+# CONFIG_XFRM_STATISTICS is not set
-+# CONFIG_NET_KEY is not set
-+CONFIG_INET=y
-+CONFIG_IP_MULTICAST=y
-+# CONFIG_IP_ADVANCED_ROUTER is not set
-+CONFIG_IP_PNP=y
-+CONFIG_IP_PNP_DHCP=y
-+CONFIG_IP_PNP_BOOTP=y
-+# CONFIG_IP_PNP_RARP is not set
-+# CONFIG_NET_IPIP is not set
-+# CONFIG_NET_IPGRE_DEMUX is not set
-+# CONFIG_IP_MROUTE is not set
-+# CONFIG_ARPD is not set
-+# CONFIG_SYN_COOKIES is not set
-+# CONFIG_INET_AH is not set
-+# CONFIG_INET_ESP is not set
-+# CONFIG_INET_IPCOMP is not set
-+# CONFIG_INET_XFRM_TUNNEL is not set
-+# CONFIG_INET_TUNNEL is not set
-+CONFIG_INET_XFRM_MODE_TRANSPORT=y
-+CONFIG_INET_XFRM_MODE_TUNNEL=y
-+CONFIG_INET_XFRM_MODE_BEET=y
-+# CONFIG_INET_LRO is not set
-+CONFIG_INET_DIAG=y
-+CONFIG_INET_TCP_DIAG=y
-+# CONFIG_TCP_CONG_ADVANCED is not set
-+CONFIG_TCP_CONG_CUBIC=y
-+CONFIG_DEFAULT_TCP_CONG="cubic"
-+# CONFIG_TCP_MD5SIG is not set
-+# CONFIG_IPV6 is not set
-+# CONFIG_NETWORK_SECMARK is not set
-+# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
-+# CONFIG_NETFILTER is not set
-+# CONFIG_IP_DCCP is not set
-+# CONFIG_IP_SCTP is not set
-+# CONFIG_RDS is not set
-+# CONFIG_TIPC is not set
-+# CONFIG_ATM is not set
-+# CONFIG_L2TP is not set
-+# CONFIG_BRIDGE is not set
-+# CONFIG_NET_DSA is not set
-+# CONFIG_VLAN_8021Q is not set
-+# CONFIG_DECNET is not set
-+# CONFIG_LLC2 is not set
-+# CONFIG_IPX is not set
-+# CONFIG_ATALK is not set
-+# CONFIG_X25 is not set
-+# CONFIG_LAPB is not set
-+# CONFIG_ECONET is not set
-+# CONFIG_WAN_ROUTER is not set
-+# CONFIG_PHONET is not set
-+# CONFIG_IEEE802154 is not set
-+# CONFIG_NET_SCHED is not set
-+# CONFIG_DCB is not set
-+# CONFIG_BATMAN_ADV is not set
-+CONFIG_RPS=y
-+CONFIG_RFS_ACCEL=y
-+CONFIG_XPS=y
-+
-+#
-+# Network testing
-+#
-+# CONFIG_NET_PKTGEN is not set
-+# CONFIG_HAMRADIO is not set
-+CONFIG_CAN=y
-+CONFIG_CAN_RAW=y
-+CONFIG_CAN_BCM=y
-+
-+#
-+# CAN Device Drivers
-+#
-+CONFIG_CAN_VCAN=y
-+# CONFIG_CAN_SLCAN is not set
-+# CONFIG_CAN_DEV is not set
-+CONFIG_HAVE_CAN_FLEXCAN=y
-+CONFIG_CAN_DEBUG_DEVICES=y
-+# CONFIG_IRDA is not set
-+CONFIG_BT=y
-+CONFIG_BT_L2CAP=y
-+CONFIG_BT_SCO=y
-+CONFIG_BT_RFCOMM=y
-+CONFIG_BT_RFCOMM_TTY=y
-+CONFIG_BT_BNEP=y
-+CONFIG_BT_BNEP_MC_FILTER=y
-+CONFIG_BT_BNEP_PROTO_FILTER=y
-+CONFIG_BT_HIDP=y
-+
-+#
-+# Bluetooth device drivers
-+#
-+CONFIG_BT_HCIBTUSB=y
-+# CONFIG_BT_HCIBTSDIO is not set
-+# CONFIG_BT_HCIUART is not set
-+# CONFIG_BT_HCIBCM203X is not set
-+# CONFIG_BT_HCIBPA10X is not set
-+# CONFIG_BT_HCIBFUSB is not set
-+CONFIG_BT_HCIVHCI=y
-+# CONFIG_BT_MRVL is not set
-+# CONFIG_BT_ATH3K is not set
-+# CONFIG_AF_RXRPC is not set
-+CONFIG_WIRELESS=y
-+# CONFIG_CFG80211 is not set
-+# CONFIG_LIB80211 is not set
-+
-+#
-+# CFG80211 needs to be enabled for MAC80211
-+#
-+# CONFIG_WIMAX is not set
-+CONFIG_RFKILL=y
-+CONFIG_RFKILL_INPUT=y
-+# CONFIG_RFKILL_REGULATOR is not set
-+# CONFIG_RFKILL_GPIO is not set
-+# CONFIG_NET_9P is not set
-+# CONFIG_CAIF is not set
-+# CONFIG_CEPH_LIB is not set
-+
-+#
-+# Device Drivers
-+#
-+
-+#
-+# Generic Driver Options
-+#
-+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-+# CONFIG_DEVTMPFS is not set
-+CONFIG_STANDALONE=y
-+CONFIG_PREVENT_FIRMWARE_BUILD=y
-+CONFIG_FW_LOADER=y
-+CONFIG_FIRMWARE_IN_KERNEL=y
-+CONFIG_EXTRA_FIRMWARE=""
-+# CONFIG_SYS_HYPERVISOR is not set
-+CONFIG_CONNECTOR=y
-+CONFIG_PROC_EVENTS=y
-+CONFIG_MTD=y
-+# CONFIG_MTD_DEBUG is not set
-+# CONFIG_MTD_TESTS is not set
-+# CONFIG_MTD_REDBOOT_PARTS is not set
-+CONFIG_MTD_CMDLINE_PARTS=y
-+# CONFIG_MTD_AFS_PARTS is not set
-+# CONFIG_MTD_AR7_PARTS is not set
-+
-+#
-+# User Modules And Translation Layers
-+#
-+CONFIG_MTD_CHAR=y
-+CONFIG_MTD_BLKDEVS=y
-+CONFIG_MTD_BLOCK=y
-+# CONFIG_FTL is not set
-+# CONFIG_NFTL is not set
-+# CONFIG_INFTL is not set
-+# CONFIG_RFD_FTL is not set
-+# CONFIG_SSFDC is not set
-+# CONFIG_SM_FTL is not set
-+# CONFIG_MTD_OOPS is not set
-+# CONFIG_MTD_SWAP is not set
-+
-+#
-+# RAM/ROM/Flash chip drivers
-+#
-+# CONFIG_MTD_CFI is not set
-+# CONFIG_MTD_JEDECPROBE is not set
-+CONFIG_MTD_MAP_BANK_WIDTH_1=y
-+CONFIG_MTD_MAP_BANK_WIDTH_2=y
-+CONFIG_MTD_MAP_BANK_WIDTH_4=y
-+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-+CONFIG_MTD_CFI_I1=y
-+CONFIG_MTD_CFI_I2=y
-+# CONFIG_MTD_CFI_I4 is not set
-+# CONFIG_MTD_CFI_I8 is not set
-+# CONFIG_MTD_RAM is not set
-+# CONFIG_MTD_ROM is not set
-+# CONFIG_MTD_ABSENT is not set
-+
-+#
-+# Mapping drivers for chip access
-+#
-+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-+# CONFIG_MTD_PLATRAM is not set
-+
-+#
-+# Self-contained MTD device drivers
-+#
-+# CONFIG_MTD_DATAFLASH is not set
-+CONFIG_MTD_M25P80=y
-+CONFIG_M25PXX_USE_FAST_READ=y
-+# CONFIG_MTD_SST25L is not set
-+# CONFIG_MTD_SLRAM is not set
-+# CONFIG_MTD_PHRAM is not set
-+# CONFIG_MTD_MTDRAM is not set
-+# CONFIG_MTD_BLOCK2MTD is not set
-+
-+#
-+# Disk-On-Chip Device Drivers
-+#
-+# CONFIG_MTD_DOC2000 is not set
-+# CONFIG_MTD_DOC2001 is not set
-+# CONFIG_MTD_DOC2001PLUS is not set
-+CONFIG_MTD_NAND_ECC=y
-+# CONFIG_MTD_NAND_ECC_SMC is not set
-+CONFIG_MTD_NAND=y
-+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
-+# CONFIG_MTD_NAND_ECC_BCH is not set
-+# CONFIG_MTD_SM_COMMON is not set
-+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
-+# CONFIG_MTD_NAND_GPIO is not set
-+CONFIG_MTD_NAND_IDS=y
-+# CONFIG_MTD_NAND_DISKONCHIP is not set
-+# CONFIG_MTD_NAND_NANDSIM is not set
-+# CONFIG_MTD_NAND_GPMI_NAND is not set
-+# CONFIG_MTD_NAND_PLATFORM is not set
-+# CONFIG_MTD_ALAUDA is not set
-+# CONFIG_MTD_ONENAND is not set
-+
-+#
-+# LPDDR flash memory drivers
-+#
-+# CONFIG_MTD_LPDDR is not set
-+CONFIG_MTD_UBI=y
-+CONFIG_MTD_UBI_WL_THRESHOLD=4096
-+CONFIG_MTD_UBI_BEB_RESERVE=1
-+# CONFIG_MTD_UBI_GLUEBI is not set
-+# CONFIG_MTD_UBI_DEBUG is not set
-+# CONFIG_PARPORT is not set
-+CONFIG_BLK_DEV=y
-+# CONFIG_BLK_DEV_COW_COMMON is not set
-+CONFIG_BLK_DEV_LOOP=y
-+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
-+# CONFIG_BLK_DEV_DRBD is not set
-+# CONFIG_BLK_DEV_NBD is not set
-+# CONFIG_BLK_DEV_UB is not set
-+# CONFIG_BLK_DEV_RAM is not set
-+# CONFIG_CDROM_PKTCDVD is not set
-+# CONFIG_ATA_OVER_ETH is not set
-+# CONFIG_MG_DISK is not set
-+# CONFIG_BLK_DEV_RBD is not set
-+# CONFIG_SENSORS_LIS3LV02D is not set
-+# CONFIG_MISC_DEVICES is not set
-+CONFIG_HAVE_IDE=y
-+# CONFIG_IDE is not set
-+
-+#
-+# SCSI device support
-+#
-+CONFIG_SCSI_MOD=y
-+# CONFIG_RAID_ATTRS is not set
-+CONFIG_SCSI=y
-+CONFIG_SCSI_DMA=y
-+# CONFIG_SCSI_TGT is not set
-+# CONFIG_SCSI_NETLINK is not set
-+CONFIG_SCSI_PROC_FS=y
-+
-+#
-+# SCSI support type (disk, tape, CD-ROM)
-+#
-+CONFIG_BLK_DEV_SD=y
-+# CONFIG_CHR_DEV_ST is not set
-+# CONFIG_CHR_DEV_OSST is not set
-+# CONFIG_BLK_DEV_SR is not set
-+# CONFIG_CHR_DEV_SG is not set
-+# CONFIG_CHR_DEV_SCH is not set
-+CONFIG_SCSI_MULTI_LUN=y
-+# CONFIG_SCSI_CONSTANTS is not set
-+# CONFIG_SCSI_LOGGING is not set
-+# CONFIG_SCSI_SCAN_ASYNC is not set
-+CONFIG_SCSI_WAIT_SCAN=m
-+
-+#
-+# SCSI Transports
-+#
-+# CONFIG_SCSI_SPI_ATTRS is not set
-+# CONFIG_SCSI_FC_ATTRS is not set
-+# CONFIG_SCSI_ISCSI_ATTRS is not set
-+# CONFIG_SCSI_SAS_ATTRS is not set
-+# CONFIG_SCSI_SAS_LIBSAS is not set
-+# CONFIG_SCSI_SRP_ATTRS is not set
-+CONFIG_SCSI_LOWLEVEL=y
-+# CONFIG_ISCSI_TCP is not set
-+# CONFIG_ISCSI_BOOT_SYSFS is not set
-+# CONFIG_LIBFC is not set
-+# CONFIG_LIBFCOE is not set
-+# CONFIG_SCSI_DEBUG is not set
-+# CONFIG_SCSI_DH is not set
-+# CONFIG_SCSI_OSD_INITIATOR is not set
-+CONFIG_ATA=m
-+# CONFIG_ATA_NONSTANDARD is not set
-+CONFIG_ATA_VERBOSE_ERROR=y
-+# CONFIG_SATA_PMP is not set
-+
-+#
-+# Controllers with non-SFF native interface
-+#
-+CONFIG_SATA_AHCI_PLATFORM=m
-+CONFIG_ATA_SFF=y
-+
-+#
-+# SFF controllers with custom DMA interface
-+#
-+CONFIG_ATA_BMDMA=y
-+
-+#
-+# SATA SFF controllers with BMDMA
-+#
-+# CONFIG_SATA_MV is not set
-+
-+#
-+# PATA SFF controllers with BMDMA
-+#
-+# CONFIG_PATA_ARASAN_CF is not set
-+
-+#
-+# PIO-only SFF controllers
-+#
-+# CONFIG_PATA_PLATFORM is not set
-+
-+#
-+# Generic fallback / legacy drivers
-+#
-+# CONFIG_MD is not set
-+# CONFIG_TARGET_CORE is not set
-+CONFIG_NETDEVICES=y
-+# CONFIG_DUMMY is not set
-+# CONFIG_BONDING is not set
-+# CONFIG_MACVLAN is not set
-+# CONFIG_EQUALIZER is not set
-+# CONFIG_TUN is not set
-+# CONFIG_VETH is not set
-+CONFIG_MII=y
-+CONFIG_PHYLIB=y
-+
-+#
-+# MII PHY device drivers
-+#
-+# CONFIG_MARVELL_PHY is not set
-+# CONFIG_DAVICOM_PHY is not set
-+# CONFIG_QSEMI_PHY is not set
-+# CONFIG_LXT_PHY is not set
-+# CONFIG_CICADA_PHY is not set
-+# CONFIG_VITESSE_PHY is not set
-+# CONFIG_SMSC_PHY is not set
-+# CONFIG_BROADCOM_PHY is not set
-+# CONFIG_ICPLUS_PHY is not set
-+# CONFIG_REALTEK_PHY is not set
-+# CONFIG_NATIONAL_PHY is not set
-+# CONFIG_STE10XP is not set
-+# CONFIG_LSI_ET1011C_PHY is not set
-+CONFIG_MICREL_PHY=y
-+# CONFIG_FIXED_PHY is not set
-+# CONFIG_MDIO_BITBANG is not set
-+CONFIG_NET_ETHERNET=y
-+# CONFIG_AX88796 is not set
-+# CONFIG_SMC91X is not set
-+# CONFIG_DM9000 is not set
-+# CONFIG_ENC28J60 is not set
-+# CONFIG_ETHOC is not set
-+# CONFIG_SMC911X is not set
-+CONFIG_SMSC911X=y
-+# CONFIG_SMSC911X_ARCH_HOOKS is not set
-+# CONFIG_DNET is not set
-+# CONFIG_IBM_NEW_EMAC_ZMII is not set
-+# CONFIG_IBM_NEW_EMAC_RGMII is not set
-+# CONFIG_IBM_NEW_EMAC_TAH is not set
-+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
-+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
-+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
-+# CONFIG_B44 is not set
-+# CONFIG_KS8842 is not set
-+# CONFIG_KS8851 is not set
-+# CONFIG_KS8851_MLL is not set
-+CONFIG_FEC=y
-+# CONFIG_FEC_1588 is not set
-+# CONFIG_FTMAC100 is not set
-+# CONFIG_NETDEV_1000 is not set
-+# CONFIG_NETDEV_10000 is not set
-+CONFIG_WLAN=y
-+# CONFIG_USB_ZD1201 is not set
-+# CONFIG_HOSTAP is not set
-+
-+#
-+# Enable WiMAX (Networking options) to see the WiMAX drivers
-+#
-+
-+#
-+# USB Network Adapters
-+#
-+# CONFIG_USB_CATC is not set
-+# CONFIG_USB_KAWETH is not set
-+# CONFIG_USB_PEGASUS is not set
-+# CONFIG_USB_RTL8150 is not set
-+# CONFIG_USB_USBNET is not set
-+# CONFIG_USB_HSO is not set
-+# CONFIG_USB_IPHETH is not set
-+# CONFIG_WAN is not set
-+
-+#
-+# CAIF transport drivers
-+#
-+# CONFIG_PPP is not set
-+# CONFIG_SLIP is not set
-+# CONFIG_NETCONSOLE is not set
-+# CONFIG_NETPOLL is not set
-+# CONFIG_NET_POLL_CONTROLLER is not set
-+# CONFIG_ISDN is not set
-+# CONFIG_PHONE is not set
-+
-+#
-+# Input device support
-+#
-+CONFIG_INPUT=y
-+# CONFIG_INPUT_FF_MEMLESS is not set
-+CONFIG_INPUT_POLLDEV=y
-+# CONFIG_INPUT_SPARSEKMAP is not set
-+
-+#
-+# Userland interfaces
-+#
-+CONFIG_INPUT_MOUSEDEV=y
-+CONFIG_INPUT_MOUSEDEV_PSAUX=y
-+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-+# CONFIG_INPUT_JOYDEV is not set
-+CONFIG_INPUT_EVDEV=y
-+# CONFIG_INPUT_EVBUG is not set
-+# CONFIG_INPUT_APMPOWER is not set
-+
-+#
-+# Input Device Drivers
-+#
-+# CONFIG_INPUT_KEYBOARD is not set
-+# CONFIG_INPUT_MOUSE is not set
-+# CONFIG_INPUT_JOYSTICK is not set
-+# CONFIG_INPUT_TABLET is not set
-+CONFIG_INPUT_TOUCHSCREEN=y
-+# CONFIG_TOUCHSCREEN_ADS7846 is not set
-+# CONFIG_TOUCHSCREEN_AD7877 is not set
-+# CONFIG_TOUCHSCREEN_AD7879 is not set
-+# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
-+# CONFIG_TOUCHSCREEN_BU21013 is not set
-+# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set
-+# CONFIG_TOUCHSCREEN_DYNAPRO is not set
-+# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
-+# CONFIG_TOUCHSCREEN_EETI is not set
-+CONFIG_TOUCHSCREEN_EGALAX=y
-+# CONFIG_TOUCHSCREEN_FUJITSU is not set
-+# CONFIG_TOUCHSCREEN_GUNZE is not set
-+# CONFIG_TOUCHSCREEN_ELO is not set
-+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
-+# CONFIG_TOUCHSCREEN_MAX11801 is not set
-+# CONFIG_TOUCHSCREEN_MCS5000 is not set
-+# CONFIG_TOUCHSCREEN_MTOUCH is not set
-+# CONFIG_TOUCHSCREEN_INEXIO is not set
-+# CONFIG_TOUCHSCREEN_MK712 is not set
-+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
-+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
-+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
-+# CONFIG_TOUCHSCREEN_WM97XX is not set
-+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
-+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
-+# CONFIG_TOUCHSCREEN_TSC2005 is not set
-+# CONFIG_TOUCHSCREEN_TSC2007 is not set
-+# CONFIG_TOUCHSCREEN_W90X900 is not set
-+# CONFIG_TOUCHSCREEN_ST1232 is not set
-+# CONFIG_TOUCHSCREEN_P1003 is not set
-+# CONFIG_TOUCHSCREEN_TPS6507X is not set
-+CONFIG_INPUT_MISC=y
-+# CONFIG_INPUT_AD714X is not set
-+# CONFIG_INPUT_ATI_REMOTE is not set
-+# CONFIG_INPUT_ATI_REMOTE2 is not set
-+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
-+# CONFIG_INPUT_POWERMATE is not set
-+# CONFIG_INPUT_YEALINK is not set
-+# CONFIG_INPUT_CM109 is not set
-+CONFIG_INPUT_UINPUT=y
-+# CONFIG_INPUT_PCF8574 is not set
-+# CONFIG_INPUT_PWM_BEEPER is not set
-+# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
-+# CONFIG_INPUT_ADXL34X is not set
-+# CONFIG_INPUT_CMA3000 is not set
-+# CONFIG_INPUT_ISL29023 is not set
-+
-+#
-+# Hardware I/O ports
-+#
-+# CONFIG_SERIO is not set
-+# CONFIG_GAMEPORT is not set
-+
-+#
-+# Character devices
-+#
-+CONFIG_VT=y
-+CONFIG_CONSOLE_TRANSLATIONS=y
-+CONFIG_VT_CONSOLE=y
-+CONFIG_HW_CONSOLE=y
-+# CONFIG_VT_HW_CONSOLE_BINDING is not set
-+CONFIG_UNIX98_PTYS=y
-+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
-+CONFIG_LEGACY_PTYS=y
-+CONFIG_LEGACY_PTY_COUNT=256
-+# CONFIG_SERIAL_NONSTANDARD is not set
-+# CONFIG_N_GSM is not set
-+# CONFIG_TRACE_SINK is not set
-+CONFIG_DEVKMEM=y
-+
-+#
-+# Serial drivers
-+#
-+# CONFIG_SERIAL_8250 is not set
-+
-+#
-+# Non-8250 serial port support
-+#
-+# CONFIG_SERIAL_MAX3100 is not set
-+# CONFIG_SERIAL_MAX3107 is not set
-+CONFIG_SERIAL_IMX=y
-+CONFIG_SERIAL_IMX_CONSOLE=y
-+CONFIG_SERIAL_CORE=y
-+CONFIG_SERIAL_CORE_CONSOLE=y
-+# CONFIG_SERIAL_TIMBERDALE is not set
-+# CONFIG_SERIAL_ALTERA_JTAGUART is not set
-+# CONFIG_SERIAL_ALTERA_UART is not set
-+# CONFIG_SERIAL_IFX6X60 is not set
-+# CONFIG_SERIAL_XILINX_PS_UART is not set
-+# CONFIG_TTY_PRINTK is not set
-+CONFIG_FSL_OTP=y
-+# CONFIG_HVC_DCC is not set
-+# CONFIG_IPMI_HANDLER is not set
-+CONFIG_HW_RANDOM=y
-+# CONFIG_HW_RANDOM_TIMERIOMEM is not set
-+# CONFIG_R3964 is not set
-+# CONFIG_RAW_DRIVER is not set
-+# CONFIG_TCG_TPM is not set
-+# CONFIG_RAMOOPS is not set
-+CONFIG_MXS_VIIM=y
-+CONFIG_I2C=y
-+CONFIG_I2C_BOARDINFO=y
-+CONFIG_I2C_COMPAT=y
-+CONFIG_I2C_CHARDEV=y
-+# CONFIG_I2C_MUX is not set
-+CONFIG_I2C_HELPER_AUTO=y
-+
-+#
-+# I2C Hardware Bus support
-+#
-+
-+#
-+# I2C system bus drivers (mostly embedded / system-on-chip)
-+#
-+# CONFIG_I2C_DESIGNWARE is not set
-+# CONFIG_I2C_GPIO is not set
-+CONFIG_I2C_IMX=y
-+# CONFIG_I2C_OCORES is not set
-+# CONFIG_I2C_PCA_PLATFORM is not set
-+# CONFIG_I2C_PXA_PCI is not set
-+# CONFIG_I2C_SIMTEC is not set
-+# CONFIG_I2C_XILINX is not set
-+
-+#
-+# External I2C/SMBus adapter drivers
-+#
-+# CONFIG_I2C_DIOLAN_U2C is not set
-+# CONFIG_I2C_PARPORT_LIGHT is not set
-+# CONFIG_I2C_TAOS_EVM is not set
-+# CONFIG_I2C_TINY_USB is not set
-+
-+#
-+# Other I2C/SMBus bus drivers
-+#
-+# CONFIG_I2C_STUB is not set
-+# CONFIG_I2C_DEBUG_CORE is not set
-+# CONFIG_I2C_DEBUG_ALGO is not set
-+# CONFIG_I2C_DEBUG_BUS is not set
-+CONFIG_SPI=y
-+CONFIG_SPI_MASTER=y
-+
-+#
-+# SPI Master Controller Drivers
-+#
-+# CONFIG_SPI_ALTERA is not set
-+CONFIG_SPI_BITBANG=y
-+# CONFIG_SPI_GPIO is not set
-+CONFIG_SPI_IMX_VER_2_3=y
-+CONFIG_SPI_IMX=y
-+# CONFIG_SPI_OC_TINY is not set
-+# CONFIG_SPI_PXA2XX_PCI is not set
-+# CONFIG_SPI_XILINX is not set
-+# CONFIG_SPI_DESIGNWARE is not set
-+
-+#
-+# SPI Protocol Masters
-+#
-+# CONFIG_SPI_SPIDEV is not set
-+# CONFIG_SPI_TLE62X0 is not set
-+
-+#
-+# PPS support
-+#
-+# CONFIG_PPS is not set
-+
-+#
-+# PPS generators support
-+#
-+
-+#
-+# PTP clock support
-+#
-+
-+#
-+# Enable Device Drivers -> PPS to see the PTP clock options.
-+#
-+CONFIG_ARCH_REQUIRE_GPIOLIB=y
-+CONFIG_GPIOLIB=y
-+# CONFIG_GPIO_SYSFS is not set
-+
-+#
-+# Memory mapped GPIO drivers:
-+#
-+# CONFIG_GPIO_BASIC_MMIO is not set
-+# CONFIG_GPIO_IT8761E is not set
-+
-+#
-+# I2C GPIO expanders:
-+#
-+# CONFIG_GPIO_MAX7300 is not set
-+# CONFIG_GPIO_MAX732X is not set
-+# CONFIG_GPIO_PCA953X_IRQ is not set
-+# CONFIG_GPIO_PCF857X is not set
-+# CONFIG_GPIO_SX150X is not set
-+# CONFIG_GPIO_ADP5588 is not set
-+
-+#
-+# PCI GPIO expanders:
-+#
-+
-+#
-+# SPI GPIO expanders:
-+#
-+# CONFIG_GPIO_MAX7301 is not set
-+# CONFIG_GPIO_MCP23S08 is not set
-+# CONFIG_GPIO_MC33880 is not set
-+# CONFIG_GPIO_74X164 is not set
-+
-+#
-+# AC97 GPIO expanders:
-+#
-+
-+#
-+# MODULbus GPIO expanders:
-+#
-+# CONFIG_W1 is not set
-+# CONFIG_POWER_SUPPLY is not set
-+# CONFIG_HWMON is not set
-+CONFIG_THERMAL=y
-+CONFIG_WATCHDOG=y
-+CONFIG_WATCHDOG_NOWAYOUT=y
-+
-+#
-+# Watchdog Device Drivers
-+#
-+# CONFIG_SOFT_WATCHDOG is not set
-+# CONFIG_MAX63XX_WATCHDOG is not set
-+CONFIG_IMX2_WDT=y
-+
-+#
-+# USB-based Watchdog Cards
-+#
-+# CONFIG_USBPCWATCHDOG is not set
-+CONFIG_SSB_POSSIBLE=y
-+
-+#
-+# Sonics Silicon Backplane
-+#
-+# CONFIG_SSB is not set
-+CONFIG_BCMA_POSSIBLE=y
-+
-+#
-+# Broadcom specific AMBA
-+#
-+# CONFIG_BCMA is not set
-+CONFIG_MFD_SUPPORT=y
-+CONFIG_MFD_CORE=y
-+# CONFIG_MFD_88PM860X is not set
-+# CONFIG_MFD_SM501 is not set
-+# CONFIG_MFD_ASIC3 is not set
-+# CONFIG_HTC_EGPIO is not set
-+# CONFIG_HTC_PASIC3 is not set
-+# CONFIG_HTC_I2CPLD is not set
-+# CONFIG_UCB1400_CORE is not set
-+# CONFIG_TPS6105X is not set
-+# CONFIG_TPS65010 is not set
-+# CONFIG_TPS6507X is not set
-+# CONFIG_MFD_TPS6586X is not set
-+# CONFIG_TWL4030_CORE is not set
-+# CONFIG_MFD_STMPE is not set
-+# CONFIG_MFD_TC3589X is not set
-+# CONFIG_MFD_TMIO is not set
-+# CONFIG_MFD_T7L66XB is not set
-+# CONFIG_MFD_TC6387XB is not set
-+# CONFIG_MFD_TC6393XB is not set
-+# CONFIG_PMIC_DA903X is not set
-+# CONFIG_PMIC_ADP5520 is not set
-+# CONFIG_MFD_MAX8925 is not set
-+# CONFIG_MFD_MAX8997 is not set
-+# CONFIG_MFD_MAX8998 is not set
-+# CONFIG_MFD_WM8400 is not set
-+# CONFIG_MFD_WM831X_I2C is not set
-+# CONFIG_MFD_WM831X_SPI is not set
-+# CONFIG_MFD_WM8350_I2C is not set
-+# CONFIG_MFD_WM8994 is not set
-+# CONFIG_MFD_PCF50633 is not set
-+# CONFIG_PMIC_DIALOG is not set
-+# CONFIG_MFD_MC_PMIC is not set
-+# CONFIG_MFD_MC34708 is not set
-+CONFIG_MFD_PFUZE=y
-+# CONFIG_MFD_MC13XXX is not set
-+# CONFIG_ABX500_CORE is not set
-+# CONFIG_EZX_PCAP is not set
-+# CONFIG_MFD_WL1273_CORE is not set
-+# CONFIG_MFD_TPS65910 is not set
-+# CONFIG_MFD_MAX17135 is not set
-+CONFIG_MFD_MXC_HDMI=y
-+CONFIG_REGULATOR=y
-+# CONFIG_REGULATOR_DEBUG is not set
-+# CONFIG_REGULATOR_DUMMY is not set
-+CONFIG_REGULATOR_FIXED_VOLTAGE=y
-+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
-+# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
-+# CONFIG_REGULATOR_BQ24022 is not set
-+# CONFIG_REGULATOR_MAX1586 is not set
-+# CONFIG_REGULATOR_MAX8649 is not set
-+# CONFIG_REGULATOR_MAX8660 is not set
-+# CONFIG_REGULATOR_MAX8952 is not set
-+# CONFIG_REGULATOR_LP3971 is not set
-+# CONFIG_REGULATOR_LP3972 is not set
-+# CONFIG_REGULATOR_MC34708 is not set
-+CONFIG_REGULATOR_PFUZE100=y
-+# CONFIG_REGULATOR_TPS65023 is not set
-+# CONFIG_REGULATOR_TPS6507X is not set
-+# CONFIG_REGULATOR_ISL6271A is not set
-+# CONFIG_REGULATOR_AD5398 is not set
-+CONFIG_REGULATOR_ANATOP=y
-+# CONFIG_REGULATOR_TPS6524X is not set
-+# CONFIG_REGULATOR_MAX17135 is not set
-+CONFIG_MEDIA_SUPPORT=y
-+
-+#
-+# Multimedia core support
-+#
-+# CONFIG_MEDIA_CONTROLLER is not set
-+CONFIG_VIDEO_DEV=y
-+CONFIG_VIDEO_V4L2_COMMON=y
-+# CONFIG_DVB_CORE is not set
-+CONFIG_VIDEO_MEDIA=y
-+
-+#
-+# Multimedia drivers
-+#
-+# CONFIG_RC_CORE is not set
-+# CONFIG_MEDIA_ATTACH is not set
-+CONFIG_MEDIA_TUNER=y
-+# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
-+CONFIG_MEDIA_TUNER_SIMPLE=y
-+CONFIG_MEDIA_TUNER_TDA8290=y
-+CONFIG_MEDIA_TUNER_TDA827X=y
-+CONFIG_MEDIA_TUNER_TDA18271=y
-+CONFIG_MEDIA_TUNER_TDA9887=y
-+CONFIG_MEDIA_TUNER_TEA5761=y
-+CONFIG_MEDIA_TUNER_TEA5767=y
-+CONFIG_MEDIA_TUNER_MT20XX=y
-+CONFIG_MEDIA_TUNER_XC2028=y
-+CONFIG_MEDIA_TUNER_XC5000=y
-+CONFIG_MEDIA_TUNER_MC44S803=y
-+CONFIG_VIDEO_V4L2=y
-+CONFIG_VIDEOBUF_GEN=y
-+CONFIG_VIDEOBUF_DMA_CONTIG=y
-+CONFIG_VIDEO_CAPTURE_DRIVERS=y
-+# CONFIG_VIDEO_ADV_DEBUG is not set
-+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
-+# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
-+
-+#
-+# Encoders, decoders, sensors and other helper chips
-+#
-+
-+#
-+# Audio decoders, processors and mixers
-+#
-+# CONFIG_VIDEO_TVAUDIO is not set
-+# CONFIG_VIDEO_TDA7432 is not set
-+# CONFIG_VIDEO_TDA9840 is not set
-+# CONFIG_VIDEO_TEA6415C is not set
-+# CONFIG_VIDEO_TEA6420 is not set
-+# CONFIG_VIDEO_MSP3400 is not set
-+# CONFIG_VIDEO_CS5345 is not set
-+# CONFIG_VIDEO_CS53L32A is not set
-+# CONFIG_VIDEO_TLV320AIC23B is not set
-+# CONFIG_VIDEO_WM8775 is not set
-+# CONFIG_VIDEO_WM8739 is not set
-+# CONFIG_VIDEO_VP27SMPX is not set
-+
-+#
-+# RDS decoders
-+#
-+# CONFIG_VIDEO_SAA6588 is not set
-+
-+#
-+# Video decoders
-+#
-+# CONFIG_VIDEO_ADV7180 is not set
-+# CONFIG_VIDEO_BT819 is not set
-+# CONFIG_VIDEO_BT856 is not set
-+# CONFIG_VIDEO_BT866 is not set
-+# CONFIG_VIDEO_KS0127 is not set
-+# CONFIG_VIDEO_SAA7110 is not set
-+# CONFIG_VIDEO_SAA711X is not set
-+# CONFIG_VIDEO_SAA7191 is not set
-+# CONFIG_VIDEO_TVP514X is not set
-+# CONFIG_VIDEO_TVP5150 is not set
-+# CONFIG_VIDEO_TVP7002 is not set
-+# CONFIG_VIDEO_VPX3220 is not set
-+
-+#
-+# Video and audio decoders
-+#
-+# CONFIG_VIDEO_SAA717X is not set
-+# CONFIG_VIDEO_CX25840 is not set
-+
-+#
-+# MPEG video encoders
-+#
-+# CONFIG_VIDEO_CX2341X is not set
-+
-+#
-+# Video encoders
-+#
-+# CONFIG_VIDEO_SAA7127 is not set
-+# CONFIG_VIDEO_SAA7185 is not set
-+# CONFIG_VIDEO_ADV7170 is not set
-+# CONFIG_VIDEO_ADV7175 is not set
-+# CONFIG_VIDEO_ADV7343 is not set
-+# CONFIG_VIDEO_AK881X is not set
-+
-+#
-+# Camera sensor devices
-+#
-+# CONFIG_VIDEO_OV7670 is not set
-+# CONFIG_VIDEO_MT9V011 is not set
-+# CONFIG_VIDEO_TCM825X is not set
-+
-+#
-+# Video improvement chips
-+#
-+# CONFIG_VIDEO_UPD64031A is not set
-+# CONFIG_VIDEO_UPD64083 is not set
-+
-+#
-+# Miscelaneous helper chips
-+#
-+# CONFIG_VIDEO_THS7303 is not set
-+# CONFIG_VIDEO_M52790 is not set
-+# CONFIG_VIDEO_VIVI is not set
-+CONFIG_VIDEO_MXC_CAMERA=m
-+
-+#
-+# MXC Camera/V4L2 PRP Features support
-+#
-+CONFIG_VIDEO_MXC_IPU_CAMERA=y
-+# CONFIG_VIDEO_MXC_CSI_CAMERA is not set
-+# CONFIG_MXC_CAMERA_MICRON111 is not set
-+# CONFIG_MXC_CAMERA_OV2640 is not set
-+CONFIG_MXC_CAMERA_OV3640=m
-+CONFIG_MXC_CAMERA_OV5640=m
-+# CONFIG_MXC_CAMERA_OV5640_MIPI is not set
-+# CONFIG_MXC_CAMERA_OV8820_MIPI is not set
-+CONFIG_MXC_CAMERA_OV5642=m
-+# CONFIG_MXC_TVIN_ADV7180 is not set
-+CONFIG_MXC_CAMERA_SENSOR_CLK=m
-+CONFIG_MXC_IPU_PRP_VF_SDC=m
-+CONFIG_MXC_IPU_PRP_ENC=m
-+CONFIG_MXC_IPU_CSI_ENC=m
-+CONFIG_VIDEO_MXC_OUTPUT=y
-+CONFIG_VIDEO_MXC_IPU_OUTPUT=y
-+# CONFIG_VIDEO_MXC_IPUV1_WVGA_OUTPUT is not set
-+# CONFIG_VIDEO_MXC_OPL is not set
-+# CONFIG_VIDEO_CPIA2 is not set
-+# CONFIG_VIDEO_TIMBERDALE is not set
-+# CONFIG_VIDEO_SR030PC30 is not set
-+# CONFIG_VIDEO_NOON010PC30 is not set
-+# CONFIG_SOC_CAMERA is not set
-+# CONFIG_V4L_USB_DRIVERS is not set
-+# CONFIG_V4L_MEM2MEM_DRIVERS is not set
-+# CONFIG_RADIO_ADAPTERS is not set
-+
-+#
-+# Graphics support
-+#
-+# CONFIG_DRM is not set
-+# CONFIG_VGASTATE is not set
-+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
-+CONFIG_FB=y
-+# CONFIG_FIRMWARE_EDID is not set
-+# CONFIG_FB_DDC is not set
-+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
-+CONFIG_FB_CFB_FILLRECT=y
-+CONFIG_FB_CFB_COPYAREA=y
-+CONFIG_FB_CFB_IMAGEBLIT=y
-+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
-+# CONFIG_FB_SYS_FILLRECT is not set
-+# CONFIG_FB_SYS_COPYAREA is not set
-+# CONFIG_FB_SYS_IMAGEBLIT is not set
-+# CONFIG_FB_FOREIGN_ENDIAN is not set
-+# CONFIG_FB_SYS_FOPS is not set
-+# CONFIG_FB_WMT_GE_ROPS is not set
-+# CONFIG_FB_SVGALIB is not set
-+# CONFIG_FB_MACMODES is not set
-+# CONFIG_FB_BACKLIGHT is not set
-+CONFIG_FB_MODE_HELPERS=y
-+# CONFIG_FB_TILEBLITTING is not set
-+
-+#
-+# Frame buffer hardware drivers
-+#
-+# CONFIG_FB_UVESA is not set
-+# CONFIG_FB_S1D13XXX is not set
-+# CONFIG_FB_TMIO is not set
-+# CONFIG_FB_UDL is not set
-+# CONFIG_FB_VIRTUAL is not set
-+# CONFIG_FB_METRONOME is not set
-+# CONFIG_FB_BROADSHEET is not set
-+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-+
-+#
-+# Display device support
-+#
-+# CONFIG_DISPLAY_SUPPORT is not set
-+CONFIG_FB_MXC=y
-+CONFIG_FB_MXC_EDID=y
-+CONFIG_FB_MXC_SYNC_PANEL=y
-+# CONFIG_FB_MXC_EPSON_VGA_SYNC_PANEL is not set
-+CONFIG_FB_MXC_LDB=y
-+# CONFIG_FB_MXC_MIPI_DSI is not set
-+# CONFIG_FB_MXC_CLAA_WVGA_SYNC_PANEL is not set
-+# CONFIG_FB_MXC_SEIKO_WVGA_SYNC_PANEL is not set
-+# CONFIG_FB_MXC_SII902X is not set
-+# CONFIG_FB_MXC_CH7026 is not set
-+# CONFIG_FB_MXC_TVOUT_CH7024 is not set
-+# CONFIG_FB_MXC_ASYNC_PANEL is not set
-+# CONFIG_FB_MXC_EINK_PANEL is not set
-+# CONFIG_FB_MXC_ELCDIF_FB is not set
-+CONFIG_FB_MXC_HDMI=y
-+
-+#
-+# Console display driver support
-+#
-+CONFIG_DUMMY_CONSOLE=y
-+CONFIG_FRAMEBUFFER_CONSOLE=y
-+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
-+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
-+CONFIG_FONTS=y
-+# CONFIG_FONT_8x8 is not set
-+CONFIG_FONT_8x16=y
-+# CONFIG_FONT_6x11 is not set
-+# CONFIG_FONT_7x14 is not set
-+# CONFIG_FONT_PEARL_8x8 is not set
-+# CONFIG_FONT_ACORN_8x8 is not set
-+# CONFIG_FONT_MINI_4x6 is not set
-+# CONFIG_FONT_SUN8x16 is not set
-+# CONFIG_FONT_SUN12x22 is not set
-+# CONFIG_FONT_10x18 is not set
-+CONFIG_LOGO=y
-+CONFIG_LOGO_LINUX_MONO=y
-+CONFIG_LOGO_LINUX_VGA16=y
-+CONFIG_LOGO_LINUX_CLUT224=y
-+CONFIG_SOUND=y
-+# CONFIG_SOUND_OSS_CORE is not set
-+CONFIG_SND=y
-+CONFIG_SND_TIMER=y
-+CONFIG_SND_PCM=y
-+CONFIG_SND_JACK=y
-+# CONFIG_SND_SEQUENCER is not set
-+# CONFIG_SND_MIXER_OSS is not set
-+# CONFIG_SND_PCM_OSS is not set
-+# CONFIG_SND_HRTIMER is not set
-+# CONFIG_SND_DYNAMIC_MINORS is not set
-+CONFIG_SND_SUPPORT_OLD_API=y
-+CONFIG_SND_VERBOSE_PROCFS=y
-+# CONFIG_SND_VERBOSE_PRINTK is not set
-+# CONFIG_SND_DEBUG is not set
-+# CONFIG_SND_RAWMIDI_SEQ is not set
-+# CONFIG_SND_OPL3_LIB_SEQ is not set
-+# CONFIG_SND_OPL4_LIB_SEQ is not set
-+# CONFIG_SND_SBAWE_SEQ is not set
-+# CONFIG_SND_EMU10K1_SEQ is not set
-+CONFIG_SND_DRIVERS=y
-+# CONFIG_SND_DUMMY is not set
-+# CONFIG_SND_ALOOP is not set
-+# CONFIG_SND_MTPAV is not set
-+# CONFIG_SND_SERIAL_U16550 is not set
-+# CONFIG_SND_MPU401 is not set
-+CONFIG_SND_ARM=y
-+CONFIG_SND_SPI=y
-+CONFIG_SND_USB=y
-+# CONFIG_SND_USB_AUDIO is not set
-+# CONFIG_SND_USB_UA101 is not set
-+# CONFIG_SND_USB_CAIAQ is not set
-+# CONFIG_SND_USB_6FIRE is not set
-+CONFIG_SND_SOC=y
-+# CONFIG_SND_SOC_CACHE_LZO is not set
-+CONFIG_SND_SOC_AC97_BUS=y
-+CONFIG_SND_IMX_SOC=y
-+CONFIG_SND_MXC_SOC_MX2=y
-+# CONFIG_SND_SOC_IMX_SGTL5000 is not set
-+CONFIG_SND_SOC_IMX_CS42888=y
-+# CONFIG_SND_SOC_IMX_SPDIF is not set
-+# CONFIG_SND_SOC_IMX_HDMI is not set
-+CONFIG_SND_SOC_I2C_AND_SPI=y
-+# CONFIG_SND_SOC_ALL_CODECS is not set
-+CONFIG_SND_SOC_CS42888=y
-+# CONFIG_SOUND_PRIME is not set
-+CONFIG_AC97_BUS=y
-+CONFIG_HID_SUPPORT=y
-+CONFIG_HID=y
-+# CONFIG_HIDRAW is not set
-+
-+#
-+# USB Input Devices
-+#
-+CONFIG_USB_HID=y
-+# CONFIG_HID_PID is not set
-+# CONFIG_USB_HIDDEV is not set
-+
-+#
-+# Special HID drivers
-+#
-+CONFIG_HID_A4TECH=m
-+# CONFIG_HID_ACRUX is not set
-+CONFIG_HID_APPLE=m
-+CONFIG_HID_BELKIN=m
-+CONFIG_HID_CHERRY=m
-+CONFIG_HID_CHICONY=m
-+# CONFIG_HID_PRODIKEYS is not set
-+CONFIG_HID_CYPRESS=m
-+# CONFIG_HID_DRAGONRISE is not set
-+# CONFIG_HID_EMS_FF is not set
-+# CONFIG_HID_ELECOM is not set
-+CONFIG_HID_EZKEY=m
-+# CONFIG_HID_KEYTOUCH is not set
-+# CONFIG_HID_KYE is not set
-+# CONFIG_HID_UCLOGIC is not set
-+# CONFIG_HID_WALTOP is not set
-+CONFIG_HID_GYRATION=m
-+# CONFIG_HID_TWINHAN is not set
-+# CONFIG_HID_KENSINGTON is not set
-+# CONFIG_HID_LCPOWER is not set
-+CONFIG_HID_LOGITECH=m
-+# CONFIG_LOGITECH_FF is not set
-+# CONFIG_LOGIRUMBLEPAD2_FF is not set
-+# CONFIG_LOGIG940_FF is not set
-+# CONFIG_LOGIWII_FF is not set
-+# CONFIG_HID_MAGICMOUSE is not set
-+CONFIG_HID_MICROSOFT=m
-+CONFIG_HID_MONTEREY=m
-+# CONFIG_HID_MULTITOUCH is not set
-+# CONFIG_HID_NTRIG is not set
-+# CONFIG_HID_ORTEK is not set
-+CONFIG_HID_PANTHERLORD=m
-+# CONFIG_PANTHERLORD_FF is not set
-+CONFIG_HID_PETALYNX=m
-+# CONFIG_HID_PICOLCD is not set
-+# CONFIG_HID_QUANTA is not set
-+# CONFIG_HID_ROCCAT is not set
-+# CONFIG_HID_ROCCAT_ARVO is not set
-+# CONFIG_HID_ROCCAT_KONE is not set
-+# CONFIG_HID_ROCCAT_KONEPLUS is not set
-+# CONFIG_HID_ROCCAT_KOVAPLUS is not set
-+# CONFIG_HID_ROCCAT_PYRA is not set
-+CONFIG_HID_SAMSUNG=m
-+CONFIG_HID_SONY=m
-+CONFIG_HID_SUNPLUS=m
-+# CONFIG_HID_GREENASIA is not set
-+# CONFIG_HID_SMARTJOYPLUS is not set
-+# CONFIG_HID_TOPSEED is not set
-+# CONFIG_HID_THRUSTMASTER is not set
-+# CONFIG_HID_WACOM is not set
-+# CONFIG_HID_ZEROPLUS is not set
-+# CONFIG_HID_ZYDACRON is not set
-+CONFIG_USB_SUPPORT=y
-+CONFIG_USB_ARCH_HAS_HCD=y
-+# CONFIG_USB_ARCH_HAS_OHCI is not set
-+CONFIG_USB_ARCH_HAS_EHCI=y
-+CONFIG_USB=y
-+# CONFIG_USB_DEBUG is not set
-+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
-+
-+#
-+# Miscellaneous USB options
-+#
-+# CONFIG_USB_DEVICEFS is not set
-+# CONFIG_USB_DEVICE_CLASS is not set
-+# CONFIG_USB_DYNAMIC_MINORS is not set
-+CONFIG_USB_SUSPEND=y
-+# CONFIG_USB_OTG is not set
-+# CONFIG_USB_OTG_WHITELIST is not set
-+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
-+# CONFIG_USB_MON is not set
-+# CONFIG_USB_WUSB is not set
-+# CONFIG_USB_WUSB_CBAF is not set
-+
-+#
-+# USB Host Controller Drivers
-+#
-+# CONFIG_USB_C67X00_HCD is not set
-+# CONFIG_USB_EHCI_HCD is not set
-+# CONFIG_USB_OXU210HP_HCD is not set
-+# CONFIG_USB_ISP116X_HCD is not set
-+# CONFIG_USB_ISP1760_HCD is not set
-+# CONFIG_USB_ISP1362_HCD is not set
-+# CONFIG_USB_SL811_HCD is not set
-+# CONFIG_USB_R8A66597_HCD is not set
-+# CONFIG_USB_HWA_HCD is not set
-+# CONFIG_USB_MUSB_HDRC is not set
-+
-+#
-+# USB Device Class drivers
-+#
-+# CONFIG_USB_ACM is not set
-+# CONFIG_USB_PRINTER is not set
-+# CONFIG_USB_WDM is not set
-+# CONFIG_USB_TMC is not set
-+
-+#
-+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
-+#
-+
-+#
-+# also be needed; see USB_STORAGE Help for more info
-+#
-+CONFIG_USB_STORAGE=y
-+# CONFIG_USB_STORAGE_DEBUG is not set
-+# CONFIG_USB_STORAGE_REALTEK is not set
-+# CONFIG_USB_STORAGE_DATAFAB is not set
-+# CONFIG_USB_STORAGE_FREECOM is not set
-+# CONFIG_USB_STORAGE_ISD200 is not set
-+# CONFIG_USB_STORAGE_USBAT is not set
-+# CONFIG_USB_STORAGE_SDDR09 is not set
-+# CONFIG_USB_STORAGE_SDDR55 is not set
-+# CONFIG_USB_STORAGE_JUMPSHOT is not set
-+# CONFIG_USB_STORAGE_ALAUDA is not set
-+# CONFIG_USB_STORAGE_ONETOUCH is not set
-+# CONFIG_USB_STORAGE_KARMA is not set
-+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
-+# CONFIG_USB_STORAGE_ENE_UB6250 is not set
-+# CONFIG_USB_UAS is not set
-+# CONFIG_USB_LIBUSUAL is not set
-+
-+#
-+# USB Imaging devices
-+#
-+# CONFIG_USB_MDC800 is not set
-+# CONFIG_USB_MICROTEK is not set
-+
-+#
-+# USB port drivers
-+#
-+# CONFIG_USB_SERIAL is not set
-+
-+#
-+# USB Miscellaneous drivers
-+#
-+# CONFIG_USB_EMI62 is not set
-+# CONFIG_USB_EMI26 is not set
-+# CONFIG_USB_ADUTUX is not set
-+# CONFIG_USB_SEVSEG is not set
-+# CONFIG_USB_RIO500 is not set
-+# CONFIG_USB_LEGOTOWER is not set
-+# CONFIG_USB_LCD is not set
-+# CONFIG_USB_LED is not set
-+# CONFIG_USB_CYPRESS_CY7C63 is not set
-+# CONFIG_USB_CYTHERM is not set
-+# CONFIG_USB_IDMOUSE is not set
-+# CONFIG_USB_FTDI_ELAN is not set
-+# CONFIG_USB_APPLEDISPLAY is not set
-+# CONFIG_USB_LD is not set
-+# CONFIG_USB_TRANCEVIBRATOR is not set
-+# CONFIG_USB_IOWARRIOR is not set
-+# CONFIG_USB_TEST is not set
-+# CONFIG_USB_ISIGHTFW is not set
-+# CONFIG_USB_YUREX is not set
-+CONFIG_USB_GADGET=y
-+# CONFIG_USB_GADGET_DEBUG_FILES is not set
-+# CONFIG_USB_GADGET_DEBUG_FS is not set
-+CONFIG_USB_GADGET_VBUS_DRAW=2
-+CONFIG_USB_GADGET_SELECTED=y
-+CONFIG_USB_GADGET_ARC=y
-+CONFIG_USB_ARC=y
-+# CONFIG_USB_GADGET_FSL_USB2 is not set
-+# CONFIG_USB_GADGET_FUSB300 is not set
-+# CONFIG_USB_GADGET_R8A66597 is not set
-+# CONFIG_USB_GADGET_PXA_U2O is not set
-+# CONFIG_USB_GADGET_M66592 is not set
-+# CONFIG_USB_GADGET_DUMMY_HCD is not set
-+CONFIG_USB_GADGET_DUALSPEED=y
-+# CONFIG_USB_ZERO is not set
-+# CONFIG_USB_AUDIO is not set
-+# CONFIG_USB_ETH is not set
-+# CONFIG_USB_G_NCM is not set
-+# CONFIG_USB_GADGETFS is not set
-+# CONFIG_USB_FUNCTIONFS is not set
-+CONFIG_USB_FILE_STORAGE=y
-+CONFIG_FSL_UTP=y
-+# CONFIG_USB_FILE_STORAGE_TEST is not set
-+# CONFIG_USB_MASS_STORAGE is not set
-+# CONFIG_USB_G_SERIAL is not set
-+# CONFIG_USB_MIDI_GADGET is not set
-+# CONFIG_USB_G_PRINTER is not set
-+# CONFIG_USB_CDC_COMPOSITE is not set
-+# CONFIG_USB_G_MULTI is not set
-+# CONFIG_USB_G_HID is not set
-+# CONFIG_USB_G_DBGP is not set
-+# CONFIG_USB_G_WEBCAM is not set
-+
-+#
-+# OTG and related infrastructure
-+#
-+CONFIG_USB_OTG_UTILS=y
-+# CONFIG_USB_GPIO_VBUS is not set
-+# CONFIG_USB_ULPI is not set
-+# CONFIG_NOP_USB_XCEIV is not set
-+CONFIG_MMC=y
-+# CONFIG_MMC_DEBUG is not set
-+CONFIG_MMC_UNSAFE_RESUME=y
-+# CONFIG_MMC_CLKGATE is not set
-+
-+#
-+# MMC/SD/SDIO Card Drivers
-+#
-+CONFIG_MMC_BLOCK=y
-+CONFIG_MMC_BLOCK_MINORS=8
-+CONFIG_MMC_BLOCK_BOUNCE=y
-+# CONFIG_SDIO_UART is not set
-+# CONFIG_MMC_TEST is not set
-+
-+#
-+# MMC/SD/SDIO Host Controller Drivers
-+#
-+CONFIG_MMC_SDHCI=y
-+CONFIG_MMC_SDHCI_IO_ACCESSORS=y
-+CONFIG_MMC_SDHCI_PLTFM=y
-+CONFIG_MMC_SDHCI_ESDHC_IMX=y
-+# CONFIG_MMC_DW is not set
-+# CONFIG_MMC_VUB300 is not set
-+# CONFIG_MMC_USHC is not set
-+# CONFIG_MEMSTICK is not set
-+# CONFIG_NEW_LEDS is not set
-+# CONFIG_NFC_DEVICES is not set
-+# CONFIG_ACCESSIBILITY is not set
-+CONFIG_RTC_LIB=y
-+CONFIG_RTC_CLASS=y
-+CONFIG_RTC_HCTOSYS=y
-+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
-+# CONFIG_RTC_DEBUG is not set
-+
-+#
-+# RTC interfaces
-+#
-+CONFIG_RTC_INTF_SYSFS=y
-+CONFIG_RTC_INTF_PROC=y
-+CONFIG_RTC_INTF_DEV=y
-+CONFIG_RTC_INTF_DEV_UIE_EMUL=y
-+# CONFIG_RTC_DRV_TEST is not set
-+
-+#
-+# I2C RTC drivers
-+#
-+# CONFIG_RTC_DRV_DS1307 is not set
-+# CONFIG_RTC_DRV_DS1374 is not set
-+# CONFIG_RTC_DRV_DS1672 is not set
-+# CONFIG_RTC_DRV_DS3232 is not set
-+# CONFIG_RTC_DRV_MAX6900 is not set
-+# CONFIG_RTC_DRV_RS5C372 is not set
-+# CONFIG_RTC_DRV_ISL1208 is not set
-+# CONFIG_RTC_DRV_ISL12022 is not set
-+# CONFIG_RTC_DRV_X1205 is not set
-+# CONFIG_RTC_DRV_PCF8563 is not set
-+# CONFIG_RTC_DRV_PCF8583 is not set
-+# CONFIG_RTC_DRV_M41T80 is not set
-+# CONFIG_RTC_DRV_BQ32K is not set
-+# CONFIG_RTC_DRV_S35390A is not set
-+# CONFIG_RTC_DRV_FM3130 is not set
-+# CONFIG_RTC_DRV_RX8581 is not set
-+# CONFIG_RTC_DRV_RX8025 is not set
-+# CONFIG_RTC_DRV_EM3027 is not set
-+# CONFIG_RTC_DRV_RV3029C2 is not set
-+
-+#
-+# SPI RTC drivers
-+#
-+# CONFIG_RTC_DRV_M41T93 is not set
-+# CONFIG_RTC_DRV_M41T94 is not set
-+# CONFIG_RTC_DRV_DS1305 is not set
-+# CONFIG_RTC_DRV_DS1390 is not set
-+# CONFIG_RTC_DRV_MAX6902 is not set
-+# CONFIG_RTC_DRV_R9701 is not set
-+# CONFIG_RTC_DRV_RS5C348 is not set
-+# CONFIG_RTC_DRV_DS3234 is not set
-+# CONFIG_RTC_DRV_PCF2123 is not set
-+
-+#
-+# Platform RTC drivers
-+#
-+# CONFIG_RTC_DRV_CMOS is not set
-+# CONFIG_RTC_DRV_DS1286 is not set
-+# CONFIG_RTC_DRV_DS1511 is not set
-+# CONFIG_RTC_DRV_DS1553 is not set
-+# CONFIG_RTC_DRV_DS1742 is not set
-+# CONFIG_RTC_DRV_STK17TA8 is not set
-+# CONFIG_RTC_DRV_M48T86 is not set
-+# CONFIG_RTC_DRV_M48T35 is not set
-+# CONFIG_RTC_DRV_M48T59 is not set
-+# CONFIG_RTC_DRV_MSM6242 is not set
-+# CONFIG_RTC_MXC is not set
-+# CONFIG_RTC_DRV_MXC_V2 is not set
-+CONFIG_RTC_DRV_SNVS=y
-+# CONFIG_RTC_DRV_BQ4802 is not set
-+# CONFIG_RTC_DRV_RP5C01 is not set
-+# CONFIG_RTC_DRV_V3020 is not set
-+
-+#
-+# on-CPU RTC drivers
-+#
-+CONFIG_DMADEVICES=y
-+# CONFIG_DMADEVICES_DEBUG is not set
-+
-+#
-+# DMA Devices
-+#
-+# CONFIG_DW_DMAC is not set
-+# CONFIG_MXC_PXP is not set
-+# CONFIG_MXC_PXP_V2 is not set
-+# CONFIG_TIMB_DMA is not set
-+CONFIG_IMX_SDMA=y
-+# CONFIG_MXS_DMA is not set
-+CONFIG_DMA_ENGINE=y
-+
-+#
-+# DMA Clients
-+#
-+# CONFIG_NET_DMA is not set
-+# CONFIG_ASYNC_TX_DMA is not set
-+# CONFIG_DMATEST is not set
-+# CONFIG_AUXDISPLAY is not set
-+# CONFIG_UIO is not set
-+CONFIG_STAGING=y
-+# CONFIG_USBIP_CORE is not set
-+# CONFIG_ECHO is not set
-+# CONFIG_BRCMUTIL is not set
-+# CONFIG_ASUS_OLED is not set
-+# CONFIG_R8712U is not set
-+# CONFIG_TRANZPORT is not set
-+# CONFIG_POHMELFS is not set
-+# CONFIG_LINE6_USB is not set
-+# CONFIG_VT6656 is not set
-+# CONFIG_IIO is not set
-+# CONFIG_XVMALLOC is not set
-+# CONFIG_ZRAM is not set
-+# CONFIG_FB_SM7XX is not set
-+# CONFIG_EASYCAP is not set
-+CONFIG_MACH_NO_WESTBRIDGE=y
-+# CONFIG_USB_ENESTORAGE is not set
-+# CONFIG_BCM_WIMAX is not set
-+# CONFIG_FT1000 is not set
-+
-+#
-+# Speakup console speech
-+#
-+# CONFIG_SPEAKUP is not set
-+# CONFIG_TOUCHSCREEN_CLEARPAD_TM1217 is not set
-+# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set
-+
-+#
-+# Altera FPGA firmware download module
-+#
-+# CONFIG_ALTERA_STAPL is not set
-+CONFIG_CLKDEV_LOOKUP=y
-+CONFIG_CLKSRC_MMIO=y
-+
-+#
-+# MXC support drivers
-+#
-+CONFIG_MXC_IPU=y
-+CONFIG_MXC_IPU_V3=y
-+CONFIG_MXC_IPU_V3H=y
-+
-+#
-+# MXC SSI support
-+#
-+# CONFIG_MXC_SSI is not set
-+
-+#
-+# MXC Digital Audio Multiplexer support
-+#
-+# CONFIG_MXC_DAM is not set
-+
-+#
-+# MXC PMIC support
-+#
-+# CONFIG_MXC_PMIC_MC13783 is not set
-+# CONFIG_MXC_PMIC_MC13892 is not set
-+# CONFIG_MXC_PMIC_MC34704 is not set
-+# CONFIG_MXC_PMIC_MC9SDZ60 is not set
-+# CONFIG_MXC_PMIC_MC9S08DZ60 is not set
-+
-+#
-+# MXC Security Drivers
-+#
-+# CONFIG_MXC_SECURITY_SCC is not set
-+# CONFIG_MXC_SECURITY_RNG is not set
-+
-+#
-+# MXC MPEG4 Encoder Kernel module support
-+#
-+# CONFIG_MXC_HMP4E is not set
-+
-+#
-+# MXC HARDWARE EVENT
-+#
-+# CONFIG_MXC_HWEVENT is not set
-+
-+#
-+# MXC VPU(Video Processing Unit) support
-+#
-+CONFIG_MXC_VPU=y
-+# CONFIG_MXC_VPU_DEBUG is not set
-+
-+#
-+# MXC Asynchronous Sample Rate Converter support
-+#
-+CONFIG_MXC_ASRC=y
-+
-+#
-+# MXC Bluetooth support
-+#
-+
-+#
-+# Broadcom GPS ioctrl support
-+#
-+
-+#
-+# MXC Media Local Bus Driver
-+#
-+# CONFIG_MXC_MLB150 is not set
-+
-+#
-+# i.MX ADC support
-+#
-+# CONFIG_IMX_ADC is not set
-+
-+#
-+# MXC Vivante GPU support
-+#
-+# CONFIG_MXC_GPU_VIV is not set
-+
-+#
-+# ANATOP_THERMAL
-+#
-+# CONFIG_ANATOP_THERMAL is not set
-+
-+#
-+# MXC MIPI Support
-+#
-+# CONFIG_MXC_MIPI_CSI2 is not set
-+
-+#
-+# File systems
-+#
-+CONFIG_EXT2_FS=y
-+# CONFIG_EXT2_FS_XATTR is not set
-+# CONFIG_EXT2_FS_XIP is not set
-+CONFIG_EXT3_FS=y
-+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
-+CONFIG_EXT3_FS_XATTR=y
-+# CONFIG_EXT3_FS_POSIX_ACL is not set
-+# CONFIG_EXT3_FS_SECURITY is not set
-+CONFIG_EXT4_FS=y
-+CONFIG_EXT4_FS_XATTR=y
-+# CONFIG_EXT4_FS_POSIX_ACL is not set
-+# CONFIG_EXT4_FS_SECURITY is not set
-+# CONFIG_EXT4_DEBUG is not set
-+CONFIG_JBD=y
-+# CONFIG_JBD_DEBUG is not set
-+CONFIG_JBD2=y
-+# CONFIG_JBD2_DEBUG is not set
-+CONFIG_FS_MBCACHE=y
-+# CONFIG_REISERFS_FS is not set
-+# CONFIG_JFS_FS is not set
-+# CONFIG_XFS_FS is not set
-+# CONFIG_GFS2_FS is not set
-+# CONFIG_BTRFS_FS is not set
-+# CONFIG_NILFS2_FS is not set
-+# CONFIG_FS_POSIX_ACL is not set
-+CONFIG_FILE_LOCKING=y
-+CONFIG_FSNOTIFY=y
-+CONFIG_DNOTIFY=y
-+CONFIG_INOTIFY_USER=y
-+# CONFIG_FANOTIFY is not set
-+# CONFIG_QUOTA is not set
-+# CONFIG_QUOTACTL is not set
-+CONFIG_AUTOFS4_FS=m
-+# CONFIG_FUSE_FS is not set
-+
-+#
-+# Caches
-+#
-+# CONFIG_FSCACHE is not set
-+
-+#
-+# CD-ROM/DVD Filesystems
-+#
-+# CONFIG_ISO9660_FS is not set
-+# CONFIG_UDF_FS is not set
-+
-+#
-+# DOS/FAT/NT Filesystems
-+#
-+CONFIG_FAT_FS=y
-+CONFIG_MSDOS_FS=y
-+CONFIG_VFAT_FS=y
-+CONFIG_FAT_DEFAULT_CODEPAGE=437
-+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-+# CONFIG_NTFS_FS is not set
-+
-+#
-+# Pseudo filesystems
-+#
-+CONFIG_PROC_FS=y
-+CONFIG_PROC_SYSCTL=y
-+CONFIG_PROC_PAGE_MONITOR=y
-+CONFIG_SYSFS=y
-+CONFIG_TMPFS=y
-+# CONFIG_TMPFS_POSIX_ACL is not set
-+# CONFIG_TMPFS_XATTR is not set
-+# CONFIG_HUGETLB_PAGE is not set
-+# CONFIG_CONFIGFS_FS is not set
-+CONFIG_MISC_FILESYSTEMS=y
-+# CONFIG_ADFS_FS is not set
-+# CONFIG_AFFS_FS is not set
-+# CONFIG_HFS_FS is not set
-+# CONFIG_HFSPLUS_FS is not set
-+# CONFIG_BEFS_FS is not set
-+# CONFIG_BFS_FS is not set
-+# CONFIG_EFS_FS is not set
-+CONFIG_JFFS2_FS=y
-+CONFIG_JFFS2_FS_DEBUG=0
-+CONFIG_JFFS2_FS_WRITEBUFFER=y
-+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
-+# CONFIG_JFFS2_SUMMARY is not set
-+# CONFIG_JFFS2_FS_XATTR is not set
-+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
-+CONFIG_JFFS2_ZLIB=y
-+# CONFIG_JFFS2_LZO is not set
-+CONFIG_JFFS2_RTIME=y
-+# CONFIG_JFFS2_RUBIN is not set
-+CONFIG_UBIFS_FS=y
-+# CONFIG_UBIFS_FS_XATTR is not set
-+# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
-+CONFIG_UBIFS_FS_LZO=y
-+CONFIG_UBIFS_FS_ZLIB=y
-+# CONFIG_UBIFS_FS_DEBUG is not set
-+# CONFIG_LOGFS is not set
-+CONFIG_CRAMFS=y
-+# CONFIG_SQUASHFS is not set
-+# CONFIG_VXFS_FS is not set
-+# CONFIG_MINIX_FS is not set
-+# CONFIG_OMFS_FS is not set
-+# CONFIG_HPFS_FS is not set
-+# CONFIG_QNX4FS_FS is not set
-+# CONFIG_ROMFS_FS is not set
-+# CONFIG_PSTORE is not set
-+# CONFIG_SYSV_FS is not set
-+# CONFIG_UFS_FS is not set
-+CONFIG_NETWORK_FILESYSTEMS=y
-+CONFIG_NFS_FS=y
-+CONFIG_NFS_V3=y
-+# CONFIG_NFS_V3_ACL is not set
-+# CONFIG_NFS_V4 is not set
-+CONFIG_ROOT_NFS=y
-+# CONFIG_NFSD is not set
-+CONFIG_LOCKD=y
-+CONFIG_LOCKD_V4=y
-+CONFIG_NFS_COMMON=y
-+CONFIG_SUNRPC=y
-+# CONFIG_CEPH_FS is not set
-+# CONFIG_CIFS is not set
-+# CONFIG_NCP_FS is not set
-+# CONFIG_CODA_FS is not set
-+# CONFIG_AFS_FS is not set
-+
-+#
-+# Partition Types
-+#
-+CONFIG_PARTITION_ADVANCED=y
-+# CONFIG_ACORN_PARTITION is not set
-+# CONFIG_OSF_PARTITION is not set
-+# CONFIG_AMIGA_PARTITION is not set
-+# CONFIG_ATARI_PARTITION is not set
-+# CONFIG_MAC_PARTITION is not set
-+CONFIG_MSDOS_PARTITION=y
-+# CONFIG_BSD_DISKLABEL is not set
-+# CONFIG_MINIX_SUBPARTITION is not set
-+# CONFIG_SOLARIS_X86_PARTITION is not set
-+# CONFIG_UNIXWARE_DISKLABEL is not set
-+# CONFIG_LDM_PARTITION is not set
-+# CONFIG_SGI_PARTITION is not set
-+# CONFIG_ULTRIX_PARTITION is not set
-+# CONFIG_SUN_PARTITION is not set
-+# CONFIG_KARMA_PARTITION is not set
-+CONFIG_EFI_PARTITION=y
-+# CONFIG_SYSV68_PARTITION is not set
-+CONFIG_NLS=y
-+CONFIG_NLS_DEFAULT="iso8859-1"
-+CONFIG_NLS_CODEPAGE_437=y
-+# CONFIG_NLS_CODEPAGE_737 is not set
-+# CONFIG_NLS_CODEPAGE_775 is not set
-+# CONFIG_NLS_CODEPAGE_850 is not set
-+# CONFIG_NLS_CODEPAGE_852 is not set
-+# CONFIG_NLS_CODEPAGE_855 is not set
-+# CONFIG_NLS_CODEPAGE_857 is not set
-+# CONFIG_NLS_CODEPAGE_860 is not set
-+# CONFIG_NLS_CODEPAGE_861 is not set
-+# CONFIG_NLS_CODEPAGE_862 is not set
-+# CONFIG_NLS_CODEPAGE_863 is not set
-+# CONFIG_NLS_CODEPAGE_864 is not set
-+# CONFIG_NLS_CODEPAGE_865 is not set
-+# CONFIG_NLS_CODEPAGE_866 is not set
-+# CONFIG_NLS_CODEPAGE_869 is not set
-+# CONFIG_NLS_CODEPAGE_936 is not set
-+# CONFIG_NLS_CODEPAGE_950 is not set
-+# CONFIG_NLS_CODEPAGE_932 is not set
-+# CONFIG_NLS_CODEPAGE_949 is not set
-+# CONFIG_NLS_CODEPAGE_874 is not set
-+# CONFIG_NLS_ISO8859_8 is not set
-+# CONFIG_NLS_CODEPAGE_1250 is not set
-+# CONFIG_NLS_CODEPAGE_1251 is not set
-+CONFIG_NLS_ASCII=m
-+CONFIG_NLS_ISO8859_1=y
-+# CONFIG_NLS_ISO8859_2 is not set
-+# CONFIG_NLS_ISO8859_3 is not set
-+# CONFIG_NLS_ISO8859_4 is not set
-+# CONFIG_NLS_ISO8859_5 is not set
-+# CONFIG_NLS_ISO8859_6 is not set
-+# CONFIG_NLS_ISO8859_7 is not set
-+# CONFIG_NLS_ISO8859_9 is not set
-+# CONFIG_NLS_ISO8859_13 is not set
-+# CONFIG_NLS_ISO8859_14 is not set
-+# CONFIG_NLS_ISO8859_15 is not set
-+# CONFIG_NLS_KOI8_R is not set
-+# CONFIG_NLS_KOI8_U is not set
-+CONFIG_NLS_UTF8=m
-+
-+#
-+# Kernel hacking
-+#
-+# CONFIG_PRINTK_TIME is not set
-+CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
-+CONFIG_ENABLE_WARN_DEPRECATED=y
-+CONFIG_ENABLE_MUST_CHECK=y
-+CONFIG_FRAME_WARN=1024
-+# CONFIG_MAGIC_SYSRQ is not set
-+# CONFIG_STRIP_ASM_SYMS is not set
-+# CONFIG_UNUSED_SYMBOLS is not set
-+CONFIG_DEBUG_FS=y
-+# CONFIG_HEADERS_CHECK is not set
-+# CONFIG_DEBUG_SECTION_MISMATCH is not set
-+# CONFIG_DEBUG_KERNEL is not set
-+# CONFIG_HARDLOCKUP_DETECTOR is not set
-+# CONFIG_SLUB_DEBUG_ON is not set
-+# CONFIG_SLUB_STATS is not set
-+# CONFIG_SPARSE_RCU_POINTER is not set
-+CONFIG_DEBUG_BUGVERBOSE=y
-+# CONFIG_DEBUG_MEMORY_INIT is not set
-+CONFIG_RCU_CPU_STALL_TIMEOUT=60
-+CONFIG_RCU_CPU_STALL_VERBOSE=y
-+# CONFIG_LKDTM is not set
-+CONFIG_SYSCTL_SYSCALL_CHECK=y
-+CONFIG_HAVE_FUNCTION_TRACER=y
-+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-+CONFIG_HAVE_DYNAMIC_FTRACE=y
-+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-+CONFIG_HAVE_C_RECORDMCOUNT=y
-+CONFIG_TRACING_SUPPORT=y
-+# CONFIG_FTRACE is not set
-+# CONFIG_DYNAMIC_DEBUG is not set
-+# CONFIG_DMA_API_DEBUG is not set
-+# CONFIG_ATOMIC64_SELFTEST is not set
-+# CONFIG_SAMPLES is not set
-+CONFIG_HAVE_ARCH_KGDB=y
-+# CONFIG_TEST_KSTRTOX is not set
-+# CONFIG_STRICT_DEVMEM is not set
-+CONFIG_ARM_UNWIND=y
-+# CONFIG_DEBUG_USER is not set
-+# CONFIG_OC_ETM is not set
-+
-+#
-+# Security options
-+#
-+# CONFIG_KEYS is not set
-+# CONFIG_SECURITY_DMESG_RESTRICT is not set
-+# CONFIG_SECURITY is not set
-+# CONFIG_SECURITYFS is not set
-+CONFIG_DEFAULT_SECURITY_DAC=y
-+CONFIG_DEFAULT_SECURITY=""
-+CONFIG_CRYPTO=y
-+
-+#
-+# Crypto core or helper
-+#
-+CONFIG_CRYPTO_ALGAPI=y
-+CONFIG_CRYPTO_ALGAPI2=y
-+CONFIG_CRYPTO_AEAD2=y
-+CONFIG_CRYPTO_BLKCIPHER=y
-+CONFIG_CRYPTO_BLKCIPHER2=y
-+CONFIG_CRYPTO_HASH2=y
-+CONFIG_CRYPTO_RNG2=y
-+CONFIG_CRYPTO_PCOMP2=y
-+CONFIG_CRYPTO_MANAGER=y
-+CONFIG_CRYPTO_MANAGER2=y
-+CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
-+# CONFIG_CRYPTO_GF128MUL is not set
-+# CONFIG_CRYPTO_NULL is not set
-+# CONFIG_CRYPTO_PCRYPT is not set
-+CONFIG_CRYPTO_WORKQUEUE=y
-+# CONFIG_CRYPTO_CRYPTD is not set
-+# CONFIG_CRYPTO_AUTHENC is not set
-+CONFIG_CRYPTO_TEST=m
-+CONFIG_CRYPTO_CRYPTODEV=y
-+
-+#
-+# Authenticated Encryption with Associated Data
-+#
-+# CONFIG_CRYPTO_CCM is not set
-+# CONFIG_CRYPTO_GCM is not set
-+# CONFIG_CRYPTO_SEQIV is not set
-+
-+#
-+# Block modes
-+#
-+CONFIG_CRYPTO_CBC=y
-+# CONFIG_CRYPTO_CTR is not set
-+# CONFIG_CRYPTO_CTS is not set
-+CONFIG_CRYPTO_ECB=y
-+# CONFIG_CRYPTO_LRW is not set
-+# CONFIG_CRYPTO_PCBC is not set
-+# CONFIG_CRYPTO_XTS is not set
-+
-+#
-+# Hash modes
-+#
-+# CONFIG_CRYPTO_HMAC is not set
-+# CONFIG_CRYPTO_XCBC is not set
-+# CONFIG_CRYPTO_VMAC is not set
-+
-+#
-+# Digest
-+#
-+# CONFIG_CRYPTO_CRC32C is not set
-+# CONFIG_CRYPTO_GHASH is not set
-+# CONFIG_CRYPTO_MD4 is not set
-+# CONFIG_CRYPTO_MD5 is not set
-+# CONFIG_CRYPTO_MICHAEL_MIC is not set
-+# CONFIG_CRYPTO_RMD128 is not set
-+# CONFIG_CRYPTO_RMD160 is not set
-+# CONFIG_CRYPTO_RMD256 is not set
-+# CONFIG_CRYPTO_RMD320 is not set
-+# CONFIG_CRYPTO_SHA1 is not set
-+# CONFIG_CRYPTO_SHA256 is not set
-+# CONFIG_CRYPTO_SHA512 is not set
-+# CONFIG_CRYPTO_TGR192 is not set
-+# CONFIG_CRYPTO_WP512 is not set
-+
-+#
-+# Ciphers
-+#
-+CONFIG_CRYPTO_AES=y
-+# CONFIG_CRYPTO_ANUBIS is not set
-+# CONFIG_CRYPTO_ARC4 is not set
-+# CONFIG_CRYPTO_BLOWFISH is not set
-+# CONFIG_CRYPTO_CAMELLIA is not set
-+# CONFIG_CRYPTO_CAST5 is not set
-+# CONFIG_CRYPTO_CAST6 is not set
-+# CONFIG_CRYPTO_DES is not set
-+# CONFIG_CRYPTO_FCRYPT is not set
-+# CONFIG_CRYPTO_KHAZAD is not set
-+# CONFIG_CRYPTO_SALSA20 is not set
-+# CONFIG_CRYPTO_SEED is not set
-+# CONFIG_CRYPTO_SERPENT is not set
-+# CONFIG_CRYPTO_TEA is not set
-+# CONFIG_CRYPTO_TWOFISH is not set
-+
-+#
-+# Compression
-+#
-+CONFIG_CRYPTO_DEFLATE=y
-+# CONFIG_CRYPTO_ZLIB is not set
-+CONFIG_CRYPTO_LZO=y
-+
-+#
-+# Random Number Generation
-+#
-+# CONFIG_CRYPTO_ANSI_CPRNG is not set
-+# CONFIG_CRYPTO_USER_API_HASH is not set
-+# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
-+CONFIG_CRYPTO_HW=y
-+# CONFIG_BINARY_PRINTF is not set
-+
-+#
-+# Library routines
-+#
-+CONFIG_BITREVERSE=y
-+CONFIG_RATIONAL=y
-+CONFIG_CRC_CCITT=m
-+CONFIG_CRC16=y
-+# CONFIG_CRC_T10DIF is not set
-+# CONFIG_CRC_ITU_T is not set
-+CONFIG_CRC32=y
-+# CONFIG_CRC7 is not set
-+# CONFIG_LIBCRC32C is not set
-+CONFIG_ZLIB_INFLATE=y
-+CONFIG_ZLIB_DEFLATE=y
-+CONFIG_LZO_COMPRESS=y
-+CONFIG_LZO_DECOMPRESS=y
-+# CONFIG_XZ_DEC is not set
-+# CONFIG_XZ_DEC_BCJ is not set
-+CONFIG_DECOMPRESS_GZIP=y
-+CONFIG_GENERIC_ALLOCATOR=y
-+CONFIG_HAS_IOMEM=y
-+CONFIG_HAS_IOPORT=y
-+CONFIG_HAS_DMA=y
-+CONFIG_CPU_RMAP=y
-+CONFIG_NLATTR=y
-+# CONFIG_AVERAGE is not set
-diff --git a/arch/arm/mach-mx6/Kconfig b/arch/arm/mach-mx6/Kconfig
-index 64ce4d4..e6c2fca 100644
---- a/arch/arm/mach-mx6/Kconfig
-+++ b/arch/arm/mach-mx6/Kconfig
-@@ -180,6 +180,41 @@ config MACH_MX6Q_SABRELITE
- Include support for i.MX 6Quad SABRE Lite platform. This includes specific
- configurations for the board and its peripherals.
-
-+config MACH_MX6Q_QMX6
-+ bool "Support Congatec i.MX 6Quad QMX6 platform"
-+ select ARCH_MX6Q
-+ select SOC_IMX6Q
-+ select IMX_HAVE_PLATFORM_IMX_UART
-+ select IMX_HAVE_PLATFORM_DMA
-+ select IMX_HAVE_PLATFORM_FEC
-+ select IMX_HAVE_PLATFORM_GPMI_NFC
-+ select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-+ select IMX_HAVE_PLATFORM_SPI_IMX
-+ select IMX_HAVE_PLATFORM_IMX_I2C
-+ select IMX_HAVE_PLATFORM_VIV_GPU
-+ select IMX_HAVE_PLATFORM_IMX_VPU
-+ select IMX_HAVE_PLATFORM_IMX_DVFS
-+ select IMX_HAVE_PLATFORM_IMX_SSI
-+ select IMX_HAVE_PLATFORM_IMX_ANATOP_THERMAL
-+ select IMX_HAVE_PLATFORM_FSL_USB2_UDC
-+ select IMX_HAVE_PLATFORM_MXC_EHCI
-+ select IMX_HAVE_PLATFORM_FSL_OTG
-+ select IMX_HAVE_PLATFORM_FSL_USB_WAKEUP
-+ select IMX_HAVE_PLATFORM_AHCI
-+ select IMX_HAVE_PLATFORM_IMX_OCOTP
-+ select IMX_HAVE_PLATFORM_IMX_VIIM
-+ select IMX_HAVE_PLATFORM_IMX2_WDT
-+ select IMX_HAVE_PLATFORM_IMX_SNVS_RTC
-+ select IMX_HAVE_PLATFORM_IMX_PM
-+ select IMX_HAVE_PLATFORM_MXC_HDMI
-+ select IMX_HAVE_PLATFORM_IMX_ASRC
-+ select IMX_HAVE_PLATFORM_FLEXCAN
-+ select IMX_HAVE_PLATFORM_IMX_MIPI_CSI2
-+ select IMX_HAVE_PLATFORM_IMX_PCIE
-+ help
-+ Include support for Congatec i.MX 6Quad QMX6 platform. This includes specific
-+ configurations for the board and its peripherals.
-+
- config MACH_MX6Q_SABRESD
- bool "Support i.MX 6Quad SABRESD platform"
- select ARCH_MX6Q
-diff --git a/arch/arm/mach-mx6/Makefile b/arch/arm/mach-mx6/Makefile
-index 8c1d754..b745797 100644
---- a/arch/arm/mach-mx6/Makefile
-+++ b/arch/arm/mach-mx6/Makefile
-@@ -1,6 +1,7 @@
- #
- # Makefile for the linux kernel.
- #
-+CFLAGS_mx6q_qmx6_pmic_pfuze100.o += -DPFUZE100_FIRST_VERSION
-
- # Object file lists.
- obj-y := cpu.o mm.o system.o devices.o dummy_gpio.o irq.o bus_freq.o usb_h2.o usb_h3.o\
-@@ -12,6 +13,7 @@ obj-$(CONFIG_MACH_MX6Q_ARM2) += board-mx6q_arm2.o
- obj-$(CONFIG_MACH_MX6SL_ARM2) += board-mx6sl_arm2.o mx6sl_arm2_pmic_pfuze100.o
- obj-$(CONFIG_MACH_MX6SL_EVK) += board-mx6sl_evk.o mx6sl_evk_pmic_pfuze100.o
- obj-$(CONFIG_MACH_MX6Q_SABRELITE) += board-mx6q_sabrelite.o
-+obj-$(CONFIG_MACH_MX6Q_QMX6) += board-mx6q_qmx6.o mx6q_qmx6_pmic_pfuze100.o
- obj-$(CONFIG_MACH_MX6Q_SABRESD) += board-mx6q_sabresd.o mx6q_sabresd_pmic_pfuze100.o
- obj-$(CONFIG_MACH_MX6Q_SABREAUTO) += board-mx6q_sabreauto.o mx6q_sabreauto_pmic_pfuze100.o
- obj-$(CONFIG_MACH_MX6Q_HDMIDONGLE) += board-mx6q_hdmidongle.o
-diff --git a/arch/arm/mach-mx6/board-mx6dl_qmx6.h b/arch/arm/mach-mx6/board-mx6dl_qmx6.h
-new file mode 100644
-index 0000000..b7f7e9a
---- /dev/null
-+++ b/arch/arm/mach-mx6/board-mx6dl_qmx6.h
-@@ -0,0 +1,199 @@
-+/*
-+ * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
-+ */
-+
-+#ifndef _BOARD_MX6DL_QMX6_H
-+#define _BOARD_MX6DL_QMX6_H
-+#include <mach/iomux-mx6dl.h>
-+
-+static iomux_v3_cfg_t mx6dl_qmx6_pads[] = {
-+ /* AUDMUX */
-+ MX6DL_PAD_DI0_PIN4__AUDMUX_AUD6_RXD,
-+ MX6DL_PAD_DI0_PIN15__AUDMUX_AUD6_TXC,
-+ MX6DL_PAD_DI0_PIN2__AUDMUX_AUD6_TXD,
-+ MX6DL_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS,
-+
-+ /* CAN1 */
-+ MX6DL_PAD_KEY_ROW2__CAN1_RXCAN,
-+ MX6DL_PAD_KEY_COL2__CAN1_TXCAN,
-+ MX6DL_PAD_GPIO_2__GPIO_1_2, /* PCIE_WAKE_B */
-+
-+ /* CCM */
-+ MX6DL_PAD_GPIO_0__GPIO_1_0, /* GPIO_0/Audio Ref. CLK */
-+
-+ /* ECSPI1 */
-+ MX6DL_PAD_EIM_D17__ECSPI1_MISO,
-+ MX6DL_PAD_EIM_D18__ECSPI1_MOSI,
-+ MX6DL_PAD_EIM_D16__ECSPI1_SCLK,
-+ MX6DL_PAD_EIM_D19__GPIO_3_19, /*SS1*/
-+
-+ /* ENET */
-+ MX6DL_PAD_ENET_MDIO__ENET_MDIO,
-+ MX6DL_PAD_ENET_MDC__ENET_MDC,
-+ MX6DL_PAD_RGMII_TXC__ENET_RGMII_TXC,
-+ MX6DL_PAD_RGMII_TD0__ENET_RGMII_TD0,
-+ MX6DL_PAD_RGMII_TD1__ENET_RGMII_TD1,
-+ MX6DL_PAD_RGMII_TD2__ENET_RGMII_TD2,
-+ MX6DL_PAD_RGMII_TD3__ENET_RGMII_TD3,
-+ MX6DL_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL,
-+ MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK,
-+ MX6DL_PAD_RGMII_RXC__ENET_RGMII_RXC,
-+ MX6DL_PAD_RGMII_RD0__ENET_RGMII_RD0,
-+ MX6DL_PAD_RGMII_RD1__ENET_RGMII_RD1,
-+ MX6DL_PAD_RGMII_RD2__ENET_RGMII_RD2,
-+ MX6DL_PAD_RGMII_RD3__ENET_RGMII_RD3,
-+ MX6DL_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL,
-+ MX6DL_PAD_ENET_TX_EN__GPIO_1_28, /* Micrel RGMII Phy Interrupt */
-+ MX6DL_PAD_EIM_D23__GPIO_3_23, /* RGMII reset */
-+
-+ /* GPIO1 */
-+ MX6DL_PAD_ENET_RX_ER__SPDIF_IN1, /* SPDIF_IN */
-+
-+ /* GPIO2 */
-+ MX6DL_PAD_NANDF_D1__GPIO_2_1, /* J14 - Menu Button */
-+ MX6DL_PAD_NANDF_D2__GPIO_2_2, /* J14 - Back Button */
-+ MX6DL_PAD_NANDF_D3__GPIO_2_3, /* J14 - Search Button */
-+ MX6DL_PAD_NANDF_D4__GPIO_2_4, /* J14 - Home Button */
-+ MX6DL_PAD_EIM_A22__GPIO_2_16, /* J12 - Boot Mode Select */
-+ MX6DL_PAD_EIM_A21__GPIO_2_17, /* J12 - Boot Mode Select */
-+ MX6DL_PAD_EIM_A20__GPIO_2_18, /* J12 - Boot Mode Select */
-+ MX6DL_PAD_EIM_A19__GPIO_2_19, /* J12 - Boot Mode Select */
-+ MX6DL_PAD_EIM_A18__GPIO_2_20, /* J12 - Boot Mode Select */
-+ MX6DL_PAD_EIM_A17__GPIO_2_21, /* J12 - Boot Mode Select */
-+ MX6DL_PAD_EIM_A16__GPIO_2_22, /* J12 - Boot Mode Select */
-+ MX6DL_PAD_EIM_RW__GPIO_2_26, /* J12 - Boot Mode Select */
-+ MX6DL_PAD_EIM_LBA__GPIO_2_27, /* J12 - Boot Mode Select */
-+ MX6DL_PAD_EIM_EB0__GPIO_2_28, /* J12 - Boot Mode Select */
-+ MX6DL_PAD_EIM_EB1__GPIO_2_29, /* J12 - Boot Mode Select */
-+ MX6DL_PAD_EIM_EB3__GPIO_2_31, /* J12 - Boot Mode Select */
-+
-+ /* GPIO3 */
-+ MX6DL_PAD_EIM_DA0__GPIO_3_0, /* J12 - Boot Mode Select */
-+ MX6DL_PAD_EIM_DA1__GPIO_3_1, /* J12 - Boot Mode Select */
-+ MX6DL_PAD_EIM_DA2__GPIO_3_2, /* J12 - Boot Mode Select */
-+ MX6DL_PAD_EIM_DA3__GPIO_3_3, /* J12 - Boot Mode Select */
-+ MX6DL_PAD_EIM_DA4__GPIO_3_4, /* J12 - Boot Mode Select */
-+ MX6DL_PAD_EIM_DA5__GPIO_3_5, /* J12 - Boot Mode Select */
-+ MX6DL_PAD_EIM_DA6__GPIO_3_6, /* J12 - Boot Mode Select */
-+ MX6DL_PAD_EIM_DA7__GPIO_3_7, /* J12 - Boot Mode Select */
-+ MX6DL_PAD_EIM_DA8__GPIO_3_8, /* J12 - Boot Mode Select */
-+ MX6DL_PAD_EIM_DA9__GPIO_3_9, /* J12 - Boot Mode Select */
-+ MX6DL_PAD_EIM_DA10__GPIO_3_10, /* J12 - Boot Mode Select */
-+ MX6DL_PAD_EIM_DA11__GPIO_3_11, /* J12 - Boot Mode Select */
-+ MX6DL_PAD_EIM_DA12__GPIO_3_12, /* J12 - Boot Mode Select */
-+ MX6DL_PAD_EIM_DA13__GPIO_3_13, /* J12 - Boot Mode Select */
-+ MX6DL_PAD_EIM_DA14__GPIO_3_14, /* J12 - Boot Mode Select */
-+ MX6DL_PAD_EIM_DA15__GPIO_3_15, /* J12 - Boot Mode Select */
-+
-+ /* GPIO4 */
-+ MX6DL_PAD_GPIO_19__GPIO_4_5, /* Volume Down */
-+
-+ /* GPIO5 */
-+ MX6DL_PAD_EIM_WAIT__GPIO_5_0, /* J12 - Boot Mode Select */
-+ MX6DL_PAD_EIM_A24__GPIO_5_4, /* J12 - Boot Mode Select */
-+
-+ /* GPIO6 */
-+ MX6DL_PAD_EIM_A23__GPIO_6_6, /* J12 - Boot Mode Select */
-+
-+ /* GPIO7 */
-+ MX6DL_PAD_GPIO_17__GPIO_7_12, /* USB Hub Reset */
-+ MX6DL_PAD_GPIO_18__GPIO_7_13, /* Volume Up */
-+
-+ /* I2C1 - PRIMARY */
-+ MX6DL_PAD_EIM_D21__I2C1_SCL, /* GPIO3[21] */
-+ MX6DL_PAD_EIM_D28__I2C1_SDA, /* GPIO3[28] */
-+
-+ /* I2C2 - PMIC SDVO */
-+ MX6DL_PAD_KEY_COL3__I2C2_SCL, /* GPIO4[12] */
-+ MX6DL_PAD_KEY_ROW3__I2C2_SDA, /* GPIO4[13] */
-+
-+ /* I2C3 - Unused */
-+ MX6DL_PAD_GPIO_3__I2C3_SCL,
-+ MX6DL_PAD_GPIO_6__I2C3_SDA,
-+
-+ /* SUS_S3 */
-+ MX6DL_PAD_GPIO_5__GPIO_1_5, /* GPIO1[5] */
-+
-+ MX6DL_PAD_GPIO_16__GPIO_7_11, /* GPIO7[11] */
-+
-+ MX6DL_PAD_GPIO_7__GPIO_1_7, /* Display Connector GP */
-+ MX6DL_PAD_GPIO_9__GPIO_1_9, /* Display Connector GP */
-+ MX6DL_PAD_NANDF_D0__GPIO_2_0, /* Unused */
-+
-+ /* PWM1 */
-+ MX6DL_PAD_SD1_DAT3__PWM1_PWMO, /* GPIO1[21] */
-+
-+ /* PCIe RESET */
-+ MX6DL_PAD_SD1_DAT2__GPIO_1_19, /* GPIO1[19] */
-+
-+ /* PWM4 */
-+ MX6DL_PAD_SD1_CMD__PWM4_PWMO, /* GPIO1[18] */
-+
-+ /* UART1 */
-+ MX6DL_PAD_CSI0_DAT10__UART1_TXD,
-+ MX6DL_PAD_CSI0_DAT11__UART1_RXD,
-+
-+ /* UART2 for debug */
-+ MX6DL_PAD_EIM_D26__UART2_TXD,
-+ MX6DL_PAD_EIM_D27__UART2_RXD,
-+
-+ /* USBOTG ID pin */
-+ MX6DL_PAD_GPIO_1__USBOTG_ID,
-+
-+ /* WATCHDOG */
-+ MX6DL_PAD_KEY_COL4__GPIO_4_14,
-+
-+ /* USB OC pin */
-+ /* MX6DL_PAD_EIM_D30__USBOH3_USBH1_OC, TODO: to be checked */
-+
-+ /* USDHC2 */
-+ MX6DL_PAD_SD2_CLK__USDHC2_CLK,
-+ MX6DL_PAD_SD2_CMD__USDHC2_CMD,
-+ MX6DL_PAD_SD2_DAT0__USDHC2_DAT0,
-+ MX6DL_PAD_SD2_DAT1__USDHC2_DAT1,
-+ MX6DL_PAD_SD2_DAT2__USDHC2_DAT2,
-+ MX6DL_PAD_SD2_DAT3__USDHC2_DAT3,
-+ MX6DL_PAD_GPIO_4__GPIO_1_4, /* Card Detect */
-+
-+ /* USDHC3 */
-+ MX6DL_PAD_SD3_CLK__USDHC3_CLK_50MHZ,
-+ MX6DL_PAD_SD3_CMD__USDHC3_CMD_50MHZ,
-+ MX6DL_PAD_SD3_DAT0__USDHC3_DAT0_50MHZ,
-+ MX6DL_PAD_SD3_DAT1__USDHC3_DAT1_50MHZ,
-+ MX6DL_PAD_SD3_DAT2__USDHC3_DAT2_50MHZ,
-+ MX6DL_PAD_SD3_DAT3__USDHC3_DAT3_50MHZ,
-+ MX6DL_PAD_SD3_DAT4__USDHC3_DAT4_50MHZ,
-+ MX6DL_PAD_SD3_DAT5__USDHC3_DAT5_50MHZ,
-+ MX6DL_PAD_SD3_DAT6__USDHC3_DAT6_50MHZ,
-+ MX6DL_PAD_SD3_DAT7__USDHC3_DAT7_50MHZ,
-+
-+ /* USDHC4 */
-+ MX6DL_PAD_SD4_CLK__USDHC4_CLK_50MHZ,
-+ MX6DL_PAD_SD4_CMD__USDHC4_CMD_50MHZ,
-+ MX6DL_PAD_SD4_DAT0__USDHC4_DAT0_50MHZ,
-+ MX6DL_PAD_SD4_DAT1__USDHC4_DAT1_50MHZ,
-+ MX6DL_PAD_SD4_DAT2__USDHC4_DAT2_50MHZ,
-+ MX6DL_PAD_SD4_DAT3__USDHC4_DAT3_50MHZ,
-+ MX6DL_PAD_SD4_DAT4__USDHC4_DAT4_50MHZ,
-+ MX6DL_PAD_SD4_DAT5__USDHC4_DAT5_50MHZ,
-+ MX6DL_PAD_SD4_DAT6__USDHC4_DAT6_50MHZ,
-+ MX6DL_PAD_SD4_DAT7__USDHC4_DAT7_50MHZ,
-+ MX6DL_PAD_NANDF_D6__GPIO_2_6, /* SD4_CD */
-+ MX6DL_PAD_NANDF_D7__GPIO_2_7, /* SD4_WP */
-+};
-+
-+#endif
-diff --git a/arch/arm/mach-mx6/board-mx6q_qmx6.c b/arch/arm/mach-mx6/board-mx6q_qmx6.c
-new file mode 100644
-index 0000000..720ca7f
---- /dev/null
-+++ b/arch/arm/mach-mx6/board-mx6q_qmx6.c
-@@ -0,0 +1,979 @@
-+/*
-+ * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
-+ */
-+
-+#include <linux/types.h>
-+#include <linux/sched.h>
-+#include <linux/delay.h>
-+#include <linux/pm.h>
-+#include <linux/interrupt.h>
-+#include <linux/irq.h>
-+#include <linux/init.h>
-+#include <linux/input.h>
-+#include <linux/nodemask.h>
-+#include <linux/clk.h>
-+#include <linux/platform_device.h>
-+#include <linux/fsl_devices.h>
-+#include <linux/spi/spi.h>
-+#include <linux/spi/flash.h>
-+#include <linux/i2c.h>
-+#include <linux/i2c/pca953x.h>
-+#include <linux/ata.h>
-+#include <linux/mtd/mtd.h>
-+#include <linux/mtd/map.h>
-+#include <linux/mtd/partitions.h>
-+#include <linux/regulator/consumer.h>
-+#include <linux/pmic_external.h>
-+#include <linux/pmic_status.h>
-+#include <linux/ipu.h>
-+#include <linux/mxcfb.h>
-+#include <linux/pwm_backlight.h>
-+#include <linux/fec.h>
-+#include <linux/memblock.h>
-+#include <linux/gpio.h>
-+#include <linux/etherdevice.h>
-+#include <linux/regulator/anatop-regulator.h>
-+#include <linux/regulator/consumer.h>
-+#include <linux/regulator/machine.h>
-+#include <linux/regulator/fixed.h>
-+
-+#include <mach/common.h>
-+#include <mach/hardware.h>
-+#include <mach/mxc_dvfs.h>
-+#include <mach/memory.h>
-+#include <mach/iomux-mx6q.h>
-+#include <mach/imx-uart.h>
-+#include <mach/viv_gpu.h>
-+#include <mach/ahci_sata.h>
-+#include <mach/ipu-v3.h>
-+#include <mach/mxc_hdmi.h>
-+#include <mach/mxc_asrc.h>
-+
-+#include <asm/irq.h>
-+#include <asm/setup.h>
-+#include <asm/mach-types.h>
-+#include <asm/mach/arch.h>
-+#include <asm/mach/time.h>
-+
-+#include "usb.h"
-+#include "devices-imx6q.h"
-+#include "crm_regs.h"
-+#include "cpu_op-mx6.h"
-+#include "board-mx6q_qmx6.h"
-+#include "board-mx6dl_qmx6.h"
-+
-+#define MX6Q_QMX6_VOLUME_UP_KEY IMX_GPIO_NR(7, 13)
-+#define MX6Q_QMX6_VOLUME_DOWN_KEY IMX_GPIO_NR(4, 5)
-+#define MX6Q_QMX6_MENU_KEY IMX_GPIO_NR(2, 1)
-+#define MX6Q_QMX6_BACK_KEY IMX_GPIO_NR(2, 2)
-+#define MX6Q_QMX6_SEARCH_KEY IMX_GPIO_NR(2, 3)
-+#define MX6Q_QMX6_HOME_KEY IMX_GPIO_NR(2, 4)
-+#define MX6Q_QMX6_ECSPI1_CS1 IMX_GPIO_NR(3, 19)
-+#define MX6Q_QMX6_USB_HUB_RESET IMX_GPIO_NR(7, 12)
-+
-+#define MX6Q_QMX6_SD4_CD IMX_GPIO_NR(2, 6)
-+#define MX6Q_QMX6_SD4_WP IMX_GPIO_NR(2, 7)
-+#define MX6Q_QMX6_SD2_CD IMX_GPIO_NR(1, 4)
-+#define MX6Q_QMX6_USB_OTG_PWR IMX_GPIO_NR(3, 22)
-+#define MX6Q_QMX6_POWER_OFF IMX_GPIO_NR(2, 3)
-+#define MX6Q_QMX6_PCIE_WAKE_B IMX_GPIO_NR(1, 2)
-+#define MX6Q_QMX6_BLT_EN IMX_GPIO_NR(1, 9)
-+
-+#define MX6Q_QMX6_TCH_INT1 IMX_GPIO_NR(7, 11)
-+#define MX6Q_QMX6_CSI0_RST IMX_GPIO_NR(1, 8)
-+#define MX6Q_QMX6_PCIE_RST_B IMX_GPIO_NR(1, 20)
-+#define MX6Q_QMX6_CSI0_PWN IMX_GPIO_NR(6, 10)
-+#define MX6Q_QMX6_PFUZE_INT IMX_GPIO_NR(5, 16)
-+
-+void __init early_console_setup(unsigned long base, struct clk *clk);
-+extern int mx6q_qmx6_init_pfuze100(u32 int_gpio);
-+
-+static struct clk *sata_clk;
-+static int disable_ldb;
-+
-+extern char *gp_reg_id;
-+extern void mx6_cpu_regulator_init(void);
-+
-+static const struct esdhc_platform_data mx6q_qmx6_sd2_data __initconst = {
-+ .cd_gpio = MX6Q_QMX6_SD2_CD,
-+
-+ .keep_power_at_suspend = 1,
-+ .support_8bit = 0,
-+ .delay_line = 0,
-+ .force_write_access = 1,
-+};
-+
-+static const struct esdhc_platform_data mx6q_qmx6_sd3_data __initconst = {
-+ .always_present = 1,
-+ .cd_gpio = -1,
-+ .keep_power_at_suspend = 1,
-+ .support_8bit = 1,
-+ .delay_line = 0,
-+};
-+
-+static const struct esdhc_platform_data mx6q_qmx6_sd4_data __initconst = {
-+ .cd_gpio = MX6Q_QMX6_SD4_CD,
-+ .wp_gpio = MX6Q_QMX6_SD4_WP,
-+ .keep_power_at_suspend = 1,
-+ .support_8bit = 1,
-+ .delay_line = 0,
-+};
-+
-+static const struct anatop_thermal_platform_data
-+ mx6q_qmx6_anatop_thermal_data __initconst = {
-+ .name = "anatop_thermal",
-+};
-+
-+static inline void mx6q_qmx6_init_uart(void)
-+{
-+ imx6q_add_imx_uart(0, NULL);
-+ imx6q_add_imx_uart(1, NULL);
-+}
-+
-+static int mx6q_qmx6_fec_phy_init(struct phy_device *phydev)
-+{
-+ /* adjust KSZ9031 ethernet phy */
-+
-+ phy_write(phydev, 0x0d, 0x2);
-+ phy_write(phydev, 0x0e, 0x4);
-+ phy_write(phydev, 0x0d, 0xc002);
-+ phy_write(phydev, 0x0e, 0x0000);
-+
-+ phy_write(phydev, 0x0d, 0x2);
-+ phy_write(phydev, 0x0e, 0x5);
-+ phy_write(phydev, 0x0d, 0xc002);
-+ phy_write(phydev, 0x0e, 0x0000);
-+
-+ phy_write(phydev, 0x0d, 0x2);
-+ phy_write(phydev, 0x0e, 0x6);
-+ phy_write(phydev, 0x0d, 0xc002);
-+ phy_write(phydev, 0x0e, 0xffff);
-+
-+ phy_write(phydev, 0x0d, 0x2);
-+ phy_write(phydev, 0x0e, 0x8);
-+ phy_write(phydev, 0x0d, 0xc002);
-+ phy_write(phydev, 0x0e, 0x3fff);
-+ phy_write(phydev, 0x0d, 0x0);
-+
-+ return 0;
-+}
-+
-+static struct fec_platform_data fec_data __initdata = {
-+ .init = mx6q_qmx6_fec_phy_init,
-+ .phy = PHY_INTERFACE_MODE_RGMII,
-+};
-+
-+static int mx6q_qmx6_spi_cs[] = {
-+ MX6Q_QMX6_ECSPI1_CS1,
-+};
-+
-+static const struct spi_imx_master mx6q_qmx6_spi_data __initconst = {
-+ .chipselect = mx6q_qmx6_spi_cs,
-+ .num_chipselect = ARRAY_SIZE(mx6q_qmx6_spi_cs),
-+};
-+
-+#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
-+static struct mtd_partition imx6_qmx6_spi_nor_partitions[] = {
-+ {
-+ .name = "bootloader",
-+ .offset = 0,
-+ .size = 0x00040000,
-+ },
-+ {
-+ .name = "user",
-+ .offset = MTDPART_OFS_APPEND,
-+ .size = 0x003BC000,
-+ },
-+ {
-+ /* this 16KB area is used for congatec manufacturing purposes */
-+ /* we strongly recommend not to modify or destroy this area */
-+ .name = "reserved",
-+ .offset = MTDPART_OFS_APPEND,
-+ .size = 0x00004000,
-+ .mask_flags = MTD_WRITEABLE,
-+ },
-+};
-+
-+static struct flash_platform_data imx6_qmx6__spi_flash_data = {
-+ .name = "m25p80",
-+ .parts = imx6_qmx6_spi_nor_partitions,
-+ .nr_parts = ARRAY_SIZE(imx6_qmx6_spi_nor_partitions),
-+ .type = "sst25vf032b",
-+};
-+#endif
-+
-+static struct spi_board_info imx6_qmx6_spi_nor_device[] __initdata = {
-+#if defined(CONFIG_MTD_M25P80)
-+ {
-+ .modalias = "m25p80",
-+ .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
-+ .bus_num = 0,
-+ .chip_select = 0,
-+ .platform_data = &imx6_qmx6__spi_flash_data,
-+ },
-+#endif
-+};
-+
-+static void spi_device_init(void)
-+{
-+ spi_register_board_info(imx6_qmx6_spi_nor_device,
-+ ARRAY_SIZE(imx6_qmx6_spi_nor_device));
-+}
-+
-+static struct imx_ssi_platform_data mx6_qmx6_ssi_pdata = {
-+ .flags = IMX_SSI_DMA | IMX_SSI_SYN,
-+};
-+
-+static struct platform_device mx6_qmx6_audio_device = {
-+ .name = "imx-sgtl5000",
-+};
-+
-+static struct mxc_audio_platform_data mx6_qmx6_audio_data = {
-+ .ssi_num = 1,
-+ .src_port = 2,
-+ .ext_port = 6,
-+ .hp_gpio = -1,
-+};
-+static int mx6_qmx6_sgtl5000_init(void)
-+{
-+ struct clk *clko;
-+ struct clk *new_parent;
-+ int rate;
-+
-+ clko = clk_get(NULL, "clko_clk");
-+ if (IS_ERR(clko)) {
-+ pr_err("can't get CLKO clock.\n");
-+ return PTR_ERR(clko);
-+ }
-+ new_parent = clk_get(NULL, "ahb");
-+ if (!IS_ERR(new_parent)) {
-+ clk_set_parent(clko, new_parent);
-+ clk_put(new_parent);
-+ }
-+ rate = clk_round_rate(clko, 16000000);
-+ if (rate < 8000000 || rate > 27000000) {
-+ pr_err("Error:SGTL5000 mclk freq %d out of range!\n", rate);
-+ clk_put(clko);
-+ return -1;
-+ }
-+
-+ mx6_qmx6_audio_data.sysclk = rate;
-+ clk_set_rate(clko, rate);
-+ clk_enable(clko);
-+ return 0;
-+}
-+static struct imxi2c_platform_data mx6q_qmx6_i2c_data = {
-+ .bitrate = 100000,
-+};
-+
-+static struct i2c_board_info mxc_i2c0_board_info[] __initdata = {
-+ {
-+ I2C_BOARD_INFO("sgtl5000", 0x0a),
-+ },
-+};
-+
-+
-+static struct i2c_board_info mxc_i2c1_board_info[] __initdata = {
-+ {
-+ I2C_BOARD_INFO("mxc_hdmi_i2c", 0x50),
-+ },
-+};
-+
-+static struct i2c_board_info mxc_i2c2_board_info[] __initdata = {
-+ {
-+ I2C_BOARD_INFO("mxc_ldb_i2c", 0x50),
-+ .platform_data = (void *)0,
-+ },
-+};
-+static void imx6q_qmx6_usbotg_vbus(bool on)
-+{
-+ if (on)
-+ gpio_set_value(MX6Q_QMX6_USB_OTG_PWR, 1);
-+ else
-+ gpio_set_value(MX6Q_QMX6_USB_OTG_PWR, 0);
-+}
-+
-+static void __init imx6q_qmx6_init_usb(void)
-+{
-+ int ret = 0;
-+
-+ imx_otg_base = MX6_IO_ADDRESS(MX6Q_USB_OTG_BASE_ADDR);
-+ /* disable external charger detect,
-+ * or it will affect signal quality at dp .
-+ */
-+ ret = gpio_request(MX6Q_QMX6_USB_OTG_PWR, "usb-pwr");
-+ if (ret) {
-+ pr_err("failed to get GPIO MX6Q_QMX6_USB_OTG_PWR: %d\n",
-+ ret);
-+ return;
-+ }
-+ gpio_direction_output(MX6Q_QMX6_USB_OTG_PWR, 0);
-+
-+ mx6_set_otghost_vbus_func(imx6q_qmx6_usbotg_vbus);
-+}
-+
-+/* HW Initialization, if return 0, initialization is successful. */
-+static int mx6q_qmx6_sata_init(struct device *dev, void __iomem *addr)
-+{
-+ u32 tmpdata;
-+ int ret = 0;
-+ struct clk *clk;
-+
-+ sata_clk = clk_get(dev, "imx_sata_clk");
-+ if (IS_ERR(sata_clk)) {
-+ dev_err(dev, "no sata clock.\n");
-+ return PTR_ERR(sata_clk);
-+ }
-+ ret = clk_enable(sata_clk);
-+ if (ret) {
-+ dev_err(dev, "can't enable sata clock.\n");
-+ goto put_sata_clk;
-+ }
-+
-+ /* Set PHY Paremeters, two steps to configure the GPR13,
-+ * one write for rest of parameters, mask of first write is 0x07FFFFFD,
-+ * and the other one write for setting the mpll_clk_off_b
-+ *.rx_eq_val_0(iomuxc_gpr13[26:24]),
-+ *.los_lvl(iomuxc_gpr13[23:19]),
-+ *.rx_dpll_mode_0(iomuxc_gpr13[18:16]),
-+ *.sata_speed(iomuxc_gpr13[15]),
-+ *.mpll_ss_en(iomuxc_gpr13[14]),
-+ *.tx_atten_0(iomuxc_gpr13[13:11]),
-+ *.tx_boost_0(iomuxc_gpr13[10:7]),
-+ *.tx_lvl(iomuxc_gpr13[6:2]),
-+ *.mpll_ck_off(iomuxc_gpr13[1]),
-+ *.tx_edgerate_0(iomuxc_gpr13[0]),
-+ */
-+ tmpdata = readl(IOMUXC_GPR13);
-+ writel(((tmpdata & ~0x07FFFFFD) | 0x0593A044), IOMUXC_GPR13);
-+
-+ /* enable SATA_PHY PLL */
-+ tmpdata = readl(IOMUXC_GPR13);
-+ writel(((tmpdata & ~0x2) | 0x2), IOMUXC_GPR13);
-+
-+ /* Get the AHB clock rate, and configure the TIMER1MS reg later */
-+ clk = clk_get(NULL, "ahb");
-+ if (IS_ERR(clk)) {
-+ dev_err(dev, "no ahb clock.\n");
-+ ret = PTR_ERR(clk);
-+ goto release_sata_clk;
-+ }
-+ tmpdata = clk_get_rate(clk) / 1000;
-+ clk_put(clk);
-+
-+ ret = sata_init(addr, tmpdata);
-+ if (ret == 0)
-+ return ret;
-+
-+release_sata_clk:
-+ clk_disable(sata_clk);
-+put_sata_clk:
-+ clk_put(sata_clk);
-+
-+ return ret;
-+}
-+
-+static void mx6q_qmx6_sata_exit(struct device *dev)
-+{
-+ clk_disable(sata_clk);
-+ clk_put(sata_clk);
-+}
-+
-+static struct ahci_platform_data mx6q_qmx6_sata_data = {
-+ .init = mx6q_qmx6_sata_init,
-+ .exit = mx6q_qmx6_sata_exit,
-+};
-+
-+static struct viv_gpu_platform_data imx6q_gpu_pdata __initdata = {
-+ .reserved_mem_size = SZ_128M,
-+};
-+
-+static struct imx_asrc_platform_data imx_asrc_data = {
-+ .channel_bits = 4,
-+ .clk_map_ver = 2,
-+};
-+
-+static struct ipuv3_fb_platform_data qmx6_fb_data[] = {
-+ { /*fb0*/
-+ .disp_dev = "ldb",
-+ .interface_pix_fmt = IPU_PIX_FMT_RGB666,
-+ .mode_str = "LDB-XGA",
-+ .default_bpp = 16,
-+ .int_clk = false,
-+ }, {
-+ .disp_dev = "lcd",
-+ .interface_pix_fmt = IPU_PIX_FMT_RGB565,
-+ .mode_str = "CLAA-WVGA",
-+ .default_bpp = 16,
-+ .int_clk = false,
-+ }, {
-+ .disp_dev = "ldb",
-+ .interface_pix_fmt = IPU_PIX_FMT_RGB666,
-+ .mode_str = "LDB-SVGA",
-+ .default_bpp = 16,
-+ .int_clk = false,
-+ }, {
-+ .disp_dev = "ldb",
-+ .interface_pix_fmt = IPU_PIX_FMT_RGB666,
-+ .mode_str = "LDB-VGA",
-+ .default_bpp = 16,
-+ .int_clk = false,
-+ },
-+};
-+
-+static void hdmi_init(int ipu_id, int disp_id)
-+{
-+ int hdmi_mux_setting;
-+
-+ if ((ipu_id > 1) || (ipu_id < 0)) {
-+ pr_err("Invalid IPU select for HDMI: %d. Set to 0\n", ipu_id);
-+ ipu_id = 0;
-+ }
-+
-+ if ((disp_id > 1) || (disp_id < 0)) {
-+ pr_err("Invalid DI select for HDMI: %d. Set to 0\n", disp_id);
-+ disp_id = 0;
-+ }
-+
-+ /* Configure the connection between IPU1/2 and HDMI */
-+ hdmi_mux_setting = 2*ipu_id + disp_id;
-+
-+ /* GPR3, bits 2-3 = HDMI_MUX_CTL */
-+ mxc_iomux_set_gpr_register(3, 2, 2, hdmi_mux_setting);
-+}
-+
-+static struct fsl_mxc_hdmi_platform_data hdmi_data = {
-+ .init = hdmi_init,
-+};
-+
-+static struct fsl_mxc_hdmi_core_platform_data hdmi_core_data = {
-+ .ipu_id = 0,
-+ .disp_id = 0,
-+};
-+
-+static struct fsl_mxc_lcd_platform_data lcdif_data = {
-+ .ipu_id = 0,
-+ .disp_id = 0,
-+ .default_ifmt = IPU_PIX_FMT_RGB565,
-+};
-+
-+static struct fsl_mxc_ldb_platform_data ldb_data = {
-+ .ipu_id = 1,
-+ .disp_id = 0,
-+ .ext_ref = 1,
-+ .mode = LDB_SEP0,
-+ .sec_ipu_id = 1,
-+ .sec_disp_id = 1,
-+};
-+
-+static struct imx_ipuv3_platform_data ipu_data[] = {
-+ {
-+ .rev = 4,
-+ .csi_clk[0] = "clko2_clk",
-+ }, {
-+ .rev = 4,
-+ .csi_clk[0] = "clko2_clk",
-+ },
-+};
-+
-+static struct fsl_mxc_capture_platform_data capture_data[] = {
-+ {
-+ .csi = 0,
-+ .ipu = 0,
-+ .mclk_source = 0,
-+ .is_mipi = 0,
-+ },
-+};
-+
-+static void qmx6_suspend_enter(void)
-+{
-+ /* suspend preparation */
-+ /* disable backlight */
-+ gpio_set_value(MX6Q_QMX6_BLT_EN, 0);
-+}
-+
-+static void qmx6_suspend_exit(void)
-+{
-+ /* resume restore */
-+ /* enable backlight */
-+ gpio_set_value(MX6Q_QMX6_BLT_EN, 1);
-+}
-+static const struct pm_platform_data mx6q_qmx6_pm_data __initconst = {
-+ .name = "imx_pm",
-+ .suspend_enter = qmx6_suspend_enter,
-+ .suspend_exit = qmx6_suspend_exit,
-+};
-+
-+static struct regulator_consumer_supply qmx6_vmmc_consumers[] = {
-+ REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.1"),
-+ REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.2"),
-+ REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.3"),
-+};
-+
-+static struct regulator_init_data qmx6_vmmc_init = {
-+ .num_consumer_supplies = ARRAY_SIZE(qmx6_vmmc_consumers),
-+ .consumer_supplies = qmx6_vmmc_consumers,
-+};
-+
-+static struct fixed_voltage_config qmx6_vmmc_reg_config = {
-+ .supply_name = "vmmc",
-+ .microvolts = 3300000,
-+ .gpio = -1,
-+ .init_data = &qmx6_vmmc_init,
-+};
-+
-+static struct platform_device qmx6_vmmc_reg_devices = {
-+ .name = "reg-fixed-voltage",
-+ .id = 3,
-+ .dev = {
-+ .platform_data = &qmx6_vmmc_reg_config,
-+ },
-+};
-+
-+#ifdef CONFIG_SND_SOC_SGTL5000
-+
-+static struct regulator_consumer_supply sgtl5000_qmx6_consumer_vdda = {
-+ .supply = "VDDA",
-+ .dev_name = "0-000a",
-+};
-+
-+static struct regulator_consumer_supply sgtl5000_qmx6_consumer_vddio = {
-+ .supply = "VDDIO",
-+ .dev_name = "0-000a",
-+};
-+
-+static struct regulator_consumer_supply sgtl5000_qmx6_consumer_vddd = {
-+ .supply = "VDDD",
-+ .dev_name = "0-000a",
-+};
-+
-+static struct regulator_init_data sgtl5000_qmx6_vdda_reg_initdata = {
-+ .num_consumer_supplies = 1,
-+ .consumer_supplies = &sgtl5000_qmx6_consumer_vdda,
-+};
-+
-+static struct regulator_init_data sgtl5000_qmx6_vddio_reg_initdata = {
-+ .num_consumer_supplies = 1,
-+ .consumer_supplies = &sgtl5000_qmx6_consumer_vddio,
-+};
-+
-+static struct regulator_init_data sgtl5000_qmx6_vddd_reg_initdata = {
-+ .num_consumer_supplies = 1,
-+ .consumer_supplies = &sgtl5000_qmx6_consumer_vddd,
-+};
-+
-+static struct fixed_voltage_config sgtl5000_qmx6_vdda_reg_config = {
-+ .supply_name = "VDDA",
-+ .microvolts = 2500000,
-+ .gpio = -1,
-+ .init_data = &sgtl5000_qmx6_vdda_reg_initdata,
-+};
-+
-+static struct fixed_voltage_config sgtl5000_qmx6_vddio_reg_config = {
-+ .supply_name = "VDDIO",
-+ .microvolts = 3300000,
-+ .gpio = -1,
-+ .init_data = &sgtl5000_qmx6_vddio_reg_initdata,
-+};
-+
-+static struct fixed_voltage_config sgtl5000_qmx6_vddd_reg_config = {
-+ .supply_name = "VDDD",
-+ .microvolts = 0,
-+ .gpio = -1,
-+ .init_data = &sgtl5000_qmx6_vddd_reg_initdata,
-+};
-+
-+static struct platform_device sgtl5000_qmx6_vdda_reg_devices = {
-+ .name = "reg-fixed-voltage",
-+ .id = 0,
-+ .dev = {
-+ .platform_data = &sgtl5000_qmx6_vdda_reg_config,
-+ },
-+};
-+
-+static struct platform_device sgtl5000_qmx6_vddio_reg_devices = {
-+ .name = "reg-fixed-voltage",
-+ .id = 1,
-+ .dev = {
-+ .platform_data = &sgtl5000_qmx6_vddio_reg_config,
-+ },
-+};
-+
-+static struct platform_device sgtl5000_qmx6_vddd_reg_devices = {
-+ .name = "reg-fixed-voltage",
-+ .id = 2,
-+ .dev = {
-+ .platform_data = &sgtl5000_qmx6_vddd_reg_config,
-+ },
-+};
-+
-+#endif /* CONFIG_SND_SOC_SGTL5000 */
-+
-+static int imx6q_init_audio(void)
-+{
-+ mxc_register_device(&mx6_qmx6_audio_device,
-+ &mx6_qmx6_audio_data);
-+ imx6q_add_imx_ssi(1, &mx6_qmx6_ssi_pdata);
-+#ifdef CONFIG_SND_SOC_SGTL5000
-+ platform_device_register(&sgtl5000_qmx6_vdda_reg_devices);
-+ platform_device_register(&sgtl5000_qmx6_vddio_reg_devices);
-+ platform_device_register(&sgtl5000_qmx6_vddd_reg_devices);
-+ mx6_qmx6_sgtl5000_init();
-+#endif
-+ return 0;
-+
-+}
-+
-+static void pcie_3v3_reset(void)
-+{
-+ /* reset miniPCIe */
-+ gpio_request(MX6Q_QMX6_PCIE_RST_B, "pcie_reset");
-+ gpio_direction_output(MX6Q_QMX6_PCIE_RST_B, 1);
-+
-+ gpio_set_value(MX6Q_QMX6_PCIE_RST_B, 0);
-+ /* The PCI Express Mini CEM specification states that PREST# is
-+ deasserted minimum 1ms after 3.3vVaux has been applied and stable*/
-+ msleep(1);
-+ gpio_set_value(MX6Q_QMX6_PCIE_RST_B, 1);
-+}
-+
-+#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
-+#define GPIO_BUTTON(gpio_num, ev_code, act_low, descr, wake) \
-+{ \
-+ .gpio = gpio_num, \
-+ .type = EV_KEY, \
-+ .code = ev_code, \
-+ .active_low = act_low, \
-+ .desc = "btn " descr, \
-+ .wakeup = wake, \
-+}
-+
-+static struct gpio_keys_button imx6q_buttons[] = {
-+ GPIO_BUTTON(MX6Q_QMX6_POWER_OFF, KEY_POWER, 1, "key-power", 1),
-+ GPIO_BUTTON(MX6Q_QMX6_MENU_KEY, KEY_MENU, 1, "key-memu", 0),
-+ GPIO_BUTTON(MX6Q_QMX6_HOME_KEY, KEY_HOME, 1, "key-home", 0),
-+ GPIO_BUTTON(MX6Q_QMX6_BACK_KEY, KEY_BACK, 1, "key-back", 0),
-+ GPIO_BUTTON(MX6Q_QMX6_VOLUME_UP_KEY, KEY_VOLUMEUP, 1, "volume-up", 0),
-+ GPIO_BUTTON(MX6Q_QMX6_VOLUME_DOWN_KEY, KEY_VOLUMEDOWN, 1, "volume-down", 0),
-+};
-+
-+static struct gpio_keys_platform_data imx6q_button_data = {
-+ .buttons = imx6q_buttons,
-+ .nbuttons = ARRAY_SIZE(imx6q_buttons),
-+};
-+
-+static struct platform_device imx6q_button_device = {
-+ .name = "gpio-keys",
-+ .id = -1,
-+ .num_resources = 0,
-+ .dev = {
-+ .platform_data = &imx6q_button_data,
-+ }
-+};
-+
-+static void __init imx6q_add_device_buttons(void)
-+{
-+ platform_device_register(&imx6q_button_device);
-+}
-+#else
-+static void __init imx6q_add_device_buttons(void) {}
-+#endif
-+
-+static struct platform_pwm_backlight_data mx6_qmx6_pwm_backlight_data = {
-+ .pwm_id = 3,
-+ .max_brightness = 255,
-+ .dft_brightness = 128,
-+ .pwm_period_ns = 50000,
-+};
-+
-+static struct mxc_dvfs_platform_data qmx6_dvfscore_data = {
-+ .reg_id = "cpu_vddgp",
-+ .clk1_id = "cpu_clk",
-+ .clk2_id = "gpc_dvfs_clk",
-+ .gpc_cntr_offset = MXC_GPC_CNTR_OFFSET,
-+ .ccm_cdcr_offset = MXC_CCM_CDCR_OFFSET,
-+ .ccm_cacrr_offset = MXC_CCM_CACRR_OFFSET,
-+ .ccm_cdhipr_offset = MXC_CCM_CDHIPR_OFFSET,
-+ .prediv_mask = 0x1F800,
-+ .prediv_offset = 11,
-+ .prediv_val = 3,
-+ .div3ck_mask = 0xE0000000,
-+ .div3ck_offset = 29,
-+ .div3ck_val = 2,
-+ .emac_val = 0x08,
-+ .upthr_val = 25,
-+ .dnthr_val = 9,
-+ .pncthr_val = 33,
-+ .upcnt_val = 10,
-+ .dncnt_val = 10,
-+ .delay_time = 80,
-+};
-+
-+static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags,
-+ char **cmdline, struct meminfo *mi)
-+{
-+ char *str;
-+ struct tag *t;
-+ int i = 0;
-+ struct ipuv3_fb_platform_data *pdata_fb = qmx6_fb_data;
-+
-+ for_each_tag(t, tags) {
-+ if (t->hdr.tag == ATAG_CMDLINE) {
-+ str = t->u.cmdline.cmdline;
-+ str = strstr(str, "fbmem=");
-+ if (str != NULL) {
-+ str += 6;
-+ pdata_fb[i++].res_size[0] = memparse(str, &str);
-+ while (*str == ',' &&
-+ i < ARRAY_SIZE(qmx6_fb_data)) {
-+ str++;
-+ pdata_fb[i++].res_size[0] = memparse(str, &str);
-+ }
-+ }
-+ break;
-+ }
-+ }
-+}
-+
-+#define SNVS_LPCR 0x38
-+static void mx6_snvs_poweroff(void)
-+{
-+
-+ void __iomem *mx6_snvs_base = MX6_IO_ADDRESS(MX6Q_SNVS_BASE_ADDR);
-+ u32 value;
-+ value = readl(mx6_snvs_base + SNVS_LPCR);
-+ /*set TOP and DP_EN bit*/
-+ writel(value | 0x60, mx6_snvs_base + SNVS_LPCR);
-+}
-+
-+static int __init early_disable_ldb(char *p)
-+{
-+ /*mipi dsi need pll3_pfd_540M as 540MHz, ldb will change to 454Mhz*/
-+ disable_ldb = 1;
-+ return 0;
-+}
-+
-+early_param("disable_ldb", early_disable_ldb);
-+
-+static const struct imx_pcie_platform_data mx6_qmx6_pcie_data __initconst = {
-+ .pcie_pwr_en = -1,
-+ .pcie_rst = MX6Q_QMX6_PCIE_RST_B,
-+ .pcie_wake_up = MX6Q_QMX6_PCIE_WAKE_B,
-+ .pcie_dis = -1,
-+};
-+
-+/*
-+ * Board specific initialization.
-+ */
-+static void __init mx6_qmx6_board_init(void)
-+{
-+ int i;
-+ int ret;
-+ struct clk *clko2;
-+ struct clk *new_parent;
-+ int rate;
-+
-+ if (cpu_is_mx6q())
-+ mxc_iomux_v3_setup_multiple_pads(mx6q_qmx6_pads,
-+ ARRAY_SIZE(mx6q_qmx6_pads));
-+ else if (cpu_is_mx6dl()) {
-+ mxc_iomux_v3_setup_multiple_pads(mx6dl_qmx6_pads,
-+ ARRAY_SIZE(mx6dl_qmx6_pads));
-+ }
-+
-+ gp_reg_id = qmx6_dvfscore_data.reg_id;
-+ mx6q_qmx6_init_uart();
-+
-+ /*
-+ * MX6DL/Solo only supports single IPU
-+ * The following codes are used to change ipu id
-+ * and display id information for MX6DL/Solo. Then
-+ * register 1 IPU device and up to 2 displays for
-+ * MX6DL/Solo
-+ */
-+ if (cpu_is_mx6dl()) {
-+ ldb_data.ipu_id = 0;
-+ ldb_data.disp_id = 0;
-+ ldb_data.sec_ipu_id = 0;
-+ ldb_data.sec_disp_id = 1;
-+ hdmi_core_data.disp_id = 1;
-+ }
-+ imx6q_add_mxc_hdmi_core(&hdmi_core_data);
-+
-+ imx6q_add_ipuv3(0, &ipu_data[0]);
-+ if (cpu_is_mx6q()) {
-+ imx6q_add_ipuv3(1, &ipu_data[1]);
-+ for (i = 0; i < ARRAY_SIZE(qmx6_fb_data); i++)
-+ imx6q_add_ipuv3fb(i, &qmx6_fb_data[i]);
-+ } else
-+ for (i = 0; i < (ARRAY_SIZE(qmx6_fb_data) + 1) / 2; i++)
-+ imx6q_add_ipuv3fb(i, &qmx6_fb_data[i]);
-+
-+ imx6q_add_vdoa();
-+ imx6q_add_lcdif(&lcdif_data);
-+ if (!disable_ldb)
-+ imx6q_add_ldb(&ldb_data);
-+ imx6q_add_v4l2_output(0);
-+ imx6q_add_v4l2_capture(0, &capture_data[0]);
-+ imx6q_add_imx_snvs_rtc();
-+
-+ imx6q_add_imx_i2c(0, &mx6q_qmx6_i2c_data);
-+ imx6q_add_imx_i2c(1, &mx6q_qmx6_i2c_data);
-+ imx6q_add_imx_i2c(2, &mx6q_qmx6_i2c_data);
-+ i2c_register_board_info(0, mxc_i2c0_board_info,
-+ ARRAY_SIZE(mxc_i2c0_board_info));
-+ i2c_register_board_info(1, mxc_i2c1_board_info,
-+ ARRAY_SIZE(mxc_i2c1_board_info));
-+ i2c_register_board_info(2, mxc_i2c2_board_info,
-+ ARRAY_SIZE(mxc_i2c2_board_info));
-+ ret = gpio_request(MX6Q_QMX6_PFUZE_INT, "pFUZE-int");
-+ if (ret) {
-+ printk(KERN_ERR"request pFUZE-int error!!\n");
-+ return;
-+ } else {
-+ gpio_direction_input(MX6Q_QMX6_PFUZE_INT);
-+ mx6q_qmx6_init_pfuze100(MX6Q_QMX6_PFUZE_INT);
-+ }
-+
-+ /* SPI */
-+ imx6q_add_ecspi(0, &mx6q_qmx6_spi_data);
-+ spi_device_init();
-+
-+ imx6q_add_mxc_hdmi(&hdmi_data);
-+
-+ imx6q_add_anatop_thermal_imx(1, &mx6q_qmx6_anatop_thermal_data);
-+ imx6_init_fec(fec_data);
-+ imx6q_add_pm_imx(0, &mx6q_qmx6_pm_data);
-+ /* Move sd3 to first because sd3 connect to emmc.
-+ Mfgtools want emmc is mmcblk0 and other sd card is mmcblk1.
-+ */
-+ imx6q_add_sdhci_usdhc_imx(1, &mx6q_qmx6_sd2_data);
-+ imx6q_add_sdhci_usdhc_imx(2, &mx6q_qmx6_sd3_data);
-+ imx6q_add_sdhci_usdhc_imx(3, &mx6q_qmx6_sd4_data);
-+
-+ imx_add_viv_gpu(&imx6_gpu_data, &imx6q_gpu_pdata);
-+ imx6q_qmx6_init_usb();
-+ /* SATA is not supported by MX6DL/Solo */
-+ if (cpu_is_mx6q())
-+ imx6q_add_ahci(0, &mx6q_qmx6_sata_data);
-+ imx6q_add_vpu();
-+ imx6q_init_audio();
-+ platform_device_register(&qmx6_vmmc_reg_devices);
-+
-+ imx_asrc_data.asrc_core_clk = clk_get(NULL, "asrc_clk");
-+ imx_asrc_data.asrc_audio_clk = clk_get(NULL, "asrc_serial_clk");
-+ imx6q_add_asrc(&imx_asrc_data);
-+
-+ /* release USB Hub reset */
-+ gpio_set_value(MX6Q_QMX6_USB_HUB_RESET, 1);
-+
-+ /* fan & backlight PWM */
-+ imx6q_add_mxc_pwm(0);
-+ imx6q_add_mxc_pwm(3);
-+ imx6q_add_mxc_pwm_backlight(3, &mx6_qmx6_pwm_backlight_data);
-+
-+ /* switch on backlight */
-+ gpio_request(MX6Q_QMX6_BLT_EN, "backlight");
-+ gpio_direction_output(MX6Q_QMX6_BLT_EN, 1);
-+ gpio_set_value(MX6Q_QMX6_BLT_EN, 1);
-+
-+ imx6q_add_otp();
-+ imx6q_add_viim();
-+ imx6q_add_imx2_wdt(0, NULL);
-+ imx6q_add_dma();
-+
-+ imx6q_add_dvfs_core(&qmx6_dvfscore_data);
-+
-+ imx6q_add_device_buttons();
-+
-+ imx6q_add_hdmi_soc();
-+ imx6q_add_hdmi_soc_dai();
-+
-+ clko2 = clk_get(NULL, "clko2_clk");
-+ if (IS_ERR(clko2))
-+ pr_err("can't get CLKO2 clock.\n");
-+
-+ new_parent = clk_get(NULL, "osc_clk");
-+ if (!IS_ERR(new_parent)) {
-+ clk_set_parent(clko2, new_parent);
-+ clk_put(new_parent);
-+ }
-+ rate = clk_round_rate(clko2, 24000000);
-+ clk_set_rate(clko2, rate);
-+ clk_enable(clko2);
-+
-+ pm_power_off = mx6_snvs_poweroff;
-+ imx6q_add_busfreq();
-+
-+ imx6q_add_pcie(&mx6_qmx6_pcie_data);
-+}
-+
-+extern void __iomem *twd_base;
-+static void __init mx6_qmx6_timer_init(void)
-+{
-+ struct clk *uart_clk;
-+#ifdef CONFIG_LOCAL_TIMERS
-+ twd_base = ioremap(LOCAL_TWD_ADDR, SZ_256);
-+ BUG_ON(!twd_base);
-+#endif
-+ mx6_clocks_init(32768, 24000000, 0, 0);
-+
-+ uart_clk = clk_get_sys("imx-uart.0", NULL);
-+ early_console_setup(UART2_BASE_ADDR, uart_clk);
-+}
-+
-+static struct sys_timer mx6_qmx6_timer = {
-+ .init = mx6_qmx6_timer_init,
-+};
-+
-+static void __init mx6q_qmx6_reserve(void)
-+{
-+ phys_addr_t phys;
-+ int i;
-+
-+ if (imx6q_gpu_pdata.reserved_mem_size) {
-+ phys = memblock_alloc_base(imx6q_gpu_pdata.reserved_mem_size,
-+ SZ_4K, SZ_1G);
-+ memblock_free(phys, imx6q_gpu_pdata.reserved_mem_size);
-+ memblock_remove(phys, imx6q_gpu_pdata.reserved_mem_size);
-+ imx6q_gpu_pdata.reserved_mem_base = phys;
-+ }
-+
-+ for (i = 0; i < ARRAY_SIZE(qmx6_fb_data); i++)
-+ if (qmx6_fb_data[i].res_size[0]) {
-+ /* reserve for background buffer */
-+ phys = memblock_alloc(qmx6_fb_data[i].res_size[0],
-+ SZ_4K);
-+ memblock_free(phys, qmx6_fb_data[i].res_size[0]);
-+ memblock_remove(phys, qmx6_fb_data[i].res_size[0]);
-+ qmx6_fb_data[i].res_base[0] = phys;
-+ }
-+}
-+
-+/*
-+ * initialize __mach_desc_MX6Q_QMX6 data structure.
-+ */
-+MACHINE_START(MX6Q_QMX6, "Congatec i.MX 6Quad QMX6 Board")
-+ /* Maintainer: congatec */
-+ .boot_params = MX6_PHYS_OFFSET + 0x100,
-+ .fixup = fixup_mxc_board,
-+ .map_io = mx6_map_io,
-+ .init_irq = mx6_init_irq,
-+ .init_machine = mx6_qmx6_board_init,
-+ .timer = &mx6_qmx6_timer,
-+ .reserve = mx6q_qmx6_reserve,
-+MACHINE_END
-diff --git a/arch/arm/mach-mx6/board-mx6q_qmx6.h b/arch/arm/mach-mx6/board-mx6q_qmx6.h
-new file mode 100644
-index 0000000..48829a3
---- /dev/null
-+++ b/arch/arm/mach-mx6/board-mx6q_qmx6.h
-@@ -0,0 +1,199 @@
-+/*
-+ * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
-+ */
-+
-+#ifndef _BOARD_MX6Q_QMX6_H
-+#define _BOARD_MX6Q_QMX6_H
-+#include <mach/iomux-mx6q.h>
-+
-+static iomux_v3_cfg_t mx6q_qmx6_pads[] = {
-+ /* AUDMUX */
-+ MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD,
-+ MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC,
-+ MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD,
-+ MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS,
-+
-+ /* CAN1 */
-+ MX6Q_PAD_KEY_ROW2__CAN1_RXCAN,
-+ MX6Q_PAD_KEY_COL2__CAN1_TXCAN,
-+ MX6Q_PAD_GPIO_2__GPIO_1_2, /* PCIE_WAKE_B */
-+
-+ /* CCM */
-+ MX6Q_PAD_GPIO_0__GPIO_1_0, /* GPIO_0/Audio Ref. CLK */
-+
-+ /* ECSPI1 */
-+ MX6Q_PAD_EIM_D17__ECSPI1_MISO,
-+ MX6Q_PAD_EIM_D18__ECSPI1_MOSI,
-+ MX6Q_PAD_EIM_D16__ECSPI1_SCLK,
-+ MX6Q_PAD_EIM_D19__GPIO_3_19, /*SS1*/
-+
-+ /* ENET */
-+ MX6Q_PAD_ENET_MDIO__ENET_MDIO,
-+ MX6Q_PAD_ENET_MDC__ENET_MDC,
-+ MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC,
-+ MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0,
-+ MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1,
-+ MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2,
-+ MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3,
-+ MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL,
-+ MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK,
-+ MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC,
-+ MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0,
-+ MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1,
-+ MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2,
-+ MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3,
-+ MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL,
-+ MX6Q_PAD_ENET_TX_EN__GPIO_1_28, /* Micrel RGMII Phy Interrupt */
-+ MX6Q_PAD_EIM_D23__GPIO_3_23, /* RGMII reset */
-+
-+ /* GPIO1 */
-+ MX6Q_PAD_ENET_RX_ER__SPDIF_IN1, /* SPDIF_IN */
-+
-+ /* GPIO2 */
-+ MX6Q_PAD_NANDF_D1__GPIO_2_1, /* J14 - Menu Button */
-+ MX6Q_PAD_NANDF_D2__GPIO_2_2, /* J14 - Back Button */
-+ MX6Q_PAD_NANDF_D3__GPIO_2_3, /* J14 - Search Button */
-+ MX6Q_PAD_NANDF_D4__GPIO_2_4, /* J14 - Home Button */
-+ MX6Q_PAD_EIM_A22__GPIO_2_16, /* J12 - Boot Mode Select */
-+ MX6Q_PAD_EIM_A21__GPIO_2_17, /* J12 - Boot Mode Select */
-+ MX6Q_PAD_EIM_A20__GPIO_2_18, /* J12 - Boot Mode Select */
-+ MX6Q_PAD_EIM_A19__GPIO_2_19, /* J12 - Boot Mode Select */
-+ MX6Q_PAD_EIM_A18__GPIO_2_20, /* J12 - Boot Mode Select */
-+ MX6Q_PAD_EIM_A17__GPIO_2_21, /* J12 - Boot Mode Select */
-+ MX6Q_PAD_EIM_A16__GPIO_2_22, /* J12 - Boot Mode Select */
-+ MX6Q_PAD_EIM_RW__GPIO_2_26, /* J12 - Boot Mode Select */
-+ MX6Q_PAD_EIM_LBA__GPIO_2_27, /* J12 - Boot Mode Select */
-+ MX6Q_PAD_EIM_EB0__GPIO_2_28, /* J12 - Boot Mode Select */
-+ MX6Q_PAD_EIM_EB1__GPIO_2_29, /* J12 - Boot Mode Select */
-+ MX6Q_PAD_EIM_EB3__GPIO_2_31, /* J12 - Boot Mode Select */
-+
-+ /* GPIO3 */
-+ MX6Q_PAD_EIM_DA0__GPIO_3_0, /* J12 - Boot Mode Select */
-+ MX6Q_PAD_EIM_DA1__GPIO_3_1, /* J12 - Boot Mode Select */
-+ MX6Q_PAD_EIM_DA2__GPIO_3_2, /* J12 - Boot Mode Select */
-+ MX6Q_PAD_EIM_DA3__GPIO_3_3, /* J12 - Boot Mode Select */
-+ MX6Q_PAD_EIM_DA4__GPIO_3_4, /* J12 - Boot Mode Select */
-+ MX6Q_PAD_EIM_DA5__GPIO_3_5, /* J12 - Boot Mode Select */
-+ MX6Q_PAD_EIM_DA6__GPIO_3_6, /* J12 - Boot Mode Select */
-+ MX6Q_PAD_EIM_DA7__GPIO_3_7, /* J12 - Boot Mode Select */
-+ MX6Q_PAD_EIM_DA8__GPIO_3_8, /* J12 - Boot Mode Select */
-+ MX6Q_PAD_EIM_DA9__GPIO_3_9, /* J12 - Boot Mode Select */
-+ MX6Q_PAD_EIM_DA10__GPIO_3_10, /* J12 - Boot Mode Select */
-+ MX6Q_PAD_EIM_DA11__GPIO_3_11, /* J12 - Boot Mode Select */
-+ MX6Q_PAD_EIM_DA12__GPIO_3_12, /* J12 - Boot Mode Select */
-+ MX6Q_PAD_EIM_DA13__GPIO_3_13, /* J12 - Boot Mode Select */
-+ MX6Q_PAD_EIM_DA14__GPIO_3_14, /* J12 - Boot Mode Select */
-+ MX6Q_PAD_EIM_DA15__GPIO_3_15, /* J12 - Boot Mode Select */
-+
-+ /* GPIO4 */
-+ MX6Q_PAD_GPIO_19__GPIO_4_5, /* Volume Down */
-+
-+ /* GPIO5 */
-+ MX6Q_PAD_EIM_WAIT__GPIO_5_0, /* J12 - Boot Mode Select */
-+ MX6Q_PAD_EIM_A24__GPIO_5_4, /* J12 - Boot Mode Select */
-+
-+ /* GPIO6 */
-+ MX6Q_PAD_EIM_A23__GPIO_6_6, /* J12 - Boot Mode Select */
-+
-+ /* GPIO7 */
-+ MX6Q_PAD_GPIO_17__GPIO_7_12, /* USB Hub Reset */
-+ MX6Q_PAD_GPIO_18__GPIO_7_13, /* Volume Up */
-+
-+ /* I2C1 - PRIMARY */
-+ MX6Q_PAD_EIM_D21__I2C1_SCL, /* GPIO3[21] */
-+ MX6Q_PAD_EIM_D28__I2C1_SDA, /* GPIO3[28] */
-+
-+ /* I2C2 - PMIC SDVO */
-+ MX6Q_PAD_KEY_COL3__I2C2_SCL, /* GPIO4[12] */
-+ MX6Q_PAD_KEY_ROW3__I2C2_SDA, /* GPIO4[13] */
-+
-+ /* I2C3 - Unused */
-+ MX6Q_PAD_GPIO_3__I2C3_SCL,
-+ MX6Q_PAD_GPIO_6__I2C3_SDA,
-+
-+ /* SUS_S3 */
-+ MX6Q_PAD_GPIO_5__GPIO_1_5, /* GPIO1[5] */
-+
-+ MX6Q_PAD_GPIO_16__GPIO_7_11, /* GPIO7[11] */
-+
-+ MX6Q_PAD_GPIO_7__GPIO_1_7, /* Display Connector GP */
-+ MX6Q_PAD_GPIO_9__GPIO_1_9, /* Display Connector GP */
-+ MX6Q_PAD_NANDF_D0__GPIO_2_0, /* Unused */
-+
-+ /* PWM1 */
-+ MX6Q_PAD_SD1_DAT3__PWM1_PWMO, /* GPIO1[21] */
-+
-+ /* PCIe RESET */
-+ MX6Q_PAD_SD1_DAT2__GPIO_1_19, /* GPIO1[19] */
-+
-+ /* PWM4 */
-+ MX6Q_PAD_SD1_CMD__PWM4_PWMO, /* GPIO1[18] */
-+
-+ /* UART1 */
-+ MX6Q_PAD_CSI0_DAT10__UART1_TXD,
-+ MX6Q_PAD_CSI0_DAT11__UART1_RXD,
-+
-+ /* UART2 for debug */
-+ MX6Q_PAD_EIM_D26__UART2_TXD,
-+ MX6Q_PAD_EIM_D27__UART2_RXD,
-+
-+ /* USBOTG ID pin */
-+ MX6Q_PAD_GPIO_1__USBOTG_ID,
-+
-+ /* WATCHDOG */
-+ MX6Q_PAD_KEY_COL4__GPIO_4_14,
-+
-+ /* USB OC pin */
-+ /* MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC, TODO: to be checked */
-+
-+ /* USDHC2 */
-+ MX6Q_PAD_SD2_CLK__USDHC2_CLK,
-+ MX6Q_PAD_SD2_CMD__USDHC2_CMD,
-+ MX6Q_PAD_SD2_DAT0__USDHC2_DAT0,
-+ MX6Q_PAD_SD2_DAT1__USDHC2_DAT1,
-+ MX6Q_PAD_SD2_DAT2__USDHC2_DAT2,
-+ MX6Q_PAD_SD2_DAT3__USDHC2_DAT3,
-+ MX6Q_PAD_GPIO_4__GPIO_1_4, /* Card Detect */
-+
-+ /* USDHC3 */
-+ MX6Q_PAD_SD3_CLK__USDHC3_CLK_50MHZ,
-+ MX6Q_PAD_SD3_CMD__USDHC3_CMD_50MHZ,
-+ MX6Q_PAD_SD3_DAT0__USDHC3_DAT0_50MHZ,
-+ MX6Q_PAD_SD3_DAT1__USDHC3_DAT1_50MHZ,
-+ MX6Q_PAD_SD3_DAT2__USDHC3_DAT2_50MHZ,
-+ MX6Q_PAD_SD3_DAT3__USDHC3_DAT3_50MHZ,
-+ MX6Q_PAD_SD3_DAT4__USDHC3_DAT4_50MHZ,
-+ MX6Q_PAD_SD3_DAT5__USDHC3_DAT5_50MHZ,
-+ MX6Q_PAD_SD3_DAT6__USDHC3_DAT6_50MHZ,
-+ MX6Q_PAD_SD3_DAT7__USDHC3_DAT7_50MHZ,
-+
-+ /* USDHC4 */
-+ MX6Q_PAD_SD4_CLK__USDHC4_CLK_50MHZ,
-+ MX6Q_PAD_SD4_CMD__USDHC4_CMD_50MHZ,
-+ MX6Q_PAD_SD4_DAT0__USDHC4_DAT0_50MHZ,
-+ MX6Q_PAD_SD4_DAT1__USDHC4_DAT1_50MHZ,
-+ MX6Q_PAD_SD4_DAT2__USDHC4_DAT2_50MHZ,
-+ MX6Q_PAD_SD4_DAT3__USDHC4_DAT3_50MHZ,
-+ MX6Q_PAD_SD4_DAT4__USDHC4_DAT4_50MHZ,
-+ MX6Q_PAD_SD4_DAT5__USDHC4_DAT5_50MHZ,
-+ MX6Q_PAD_SD4_DAT6__USDHC4_DAT6_50MHZ,
-+ MX6Q_PAD_SD4_DAT7__USDHC4_DAT7_50MHZ,
-+ MX6Q_PAD_NANDF_D6__GPIO_2_6, /* SD4_CD */
-+ MX6Q_PAD_NANDF_D7__GPIO_2_7, /* SD4_WP */
-+};
-+
-+#endif
-diff --git a/arch/arm/mach-mx6/mx6q_qmx6_pmic_pfuze100.c b/arch/arm/mach-mx6/mx6q_qmx6_pmic_pfuze100.c
-new file mode 100644
-index 0000000..1743ff8
---- /dev/null
-+++ b/arch/arm/mach-mx6/mx6q_qmx6_pmic_pfuze100.c
-@@ -0,0 +1,422 @@
-+/*
-+ * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/init.h>
-+#include <linux/platform_device.h>
-+#include <linux/err.h>
-+#include <linux/i2c.h>
-+#include <linux/gpio.h>
-+#include <linux/regulator/machine.h>
-+#include <linux/mfd/pfuze.h>
-+#include <mach/irqs.h>
-+
-+/*
-+ * Convenience conversion.
-+ * Here atm, maybe there is somewhere better for this.
-+ */
-+#define mV_to_uV(mV) (mV * 1000)
-+#define uV_to_mV(uV) (uV / 1000)
-+#define V_to_uV(V) (mV_to_uV(V * 1000))
-+#define uV_to_V(uV) (uV_to_mV(uV) / 1000)
-+
-+#define PFUZE100_I2C_DEVICE_NAME "pfuze100"
-+/* 7-bit I2C bus slave address */
-+#define PFUZE100_I2C_ADDR (0x08)
-+ /*SWBST*/
-+#define PFUZE100_SW1ASTANDBY 33
-+#define PFUZE100_SW1ASTANDBY_STBY_VAL (0x18)
-+#define PFUZE100_SW1ASTANDBY_STBY_M (0x3f<<0)
-+#define PFUZE100_SW1BSTANDBY 40
-+#define PFUZE100_SW1BSTANDBY_STBY_VAL (0x18)
-+#define PFUZE100_SW1BSTANDBY_STBY_M (0x3f<<0)
-+#define PFUZE100_SW1CSTANDBY 47
-+#define PFUZE100_SW1CSTANDBY_STBY_VAL (0x18)
-+#define PFUZE100_SW1CSTANDBY_STBY_M (0x3f<<0)
-+#define PFUZE100_SW2STANDBY 54
-+#define PFUZE100_SW2STANDBY_STBY_VAL 0x0
-+#define PFUZE100_SW2STANDBY_STBY_M (0x3f<<0)
-+#define PFUZE100_SW3ASTANDBY 61
-+#define PFUZE100_SW3ASTANDBY_STBY_VAL 0x0
-+#define PFUZE100_SW3ASTANDBY_STBY_M (0x3f<<0)
-+#define PFUZE100_SW3BSTANDBY 68
-+#define PFUZE100_SW3BSTANDBY_STBY_VAL 0x0
-+#define PFUZE100_SW3BSTANDBY_STBY_M (0x3f<<0)
-+#define PFUZE100_SW4STANDBY 75
-+#define PFUZE100_SW4STANDBY_STBY_VAL 0
-+#define PFUZE100_SW4STANDBY_STBY_M (0x3f<<0)
-+#define PFUZE100_SWBSTCON1 102
-+#define PFUZE100_SWBSTCON1_SWBSTMOD_VAL (0x1<<2)
-+#define PFUZE100_SWBSTCON1_SWBSTMOD_M (0x3<<2)
-+
-+
-+static struct regulator_consumer_supply sw2_consumers[] = {
-+ {
-+ .supply = "MICVDD",
-+ .dev_name = "0-001a",
-+ }
-+};
-+static struct regulator_consumer_supply sw4_consumers[] = {
-+ {
-+ .supply = "AUD_1V8",
-+ }
-+};
-+static struct regulator_consumer_supply swbst_consumers[] = {
-+ {
-+ .supply = "SWBST_5V",
-+ }
-+};
-+static struct regulator_consumer_supply vgen1_consumers[] = {
-+ {
-+ .supply = "VGEN1_1V5",
-+ }
-+};
-+static struct regulator_consumer_supply vgen2_consumers[] = {
-+ {
-+ .supply = "VGEN2_1V5",
-+ }
-+};
-+static struct regulator_consumer_supply vgen4_consumers[] = {
-+ {
-+ .supply = "DBVDD",
-+ .dev_name = "0-001a",
-+ },
-+ {
-+ .supply = "AVDD",
-+ .dev_name = "0-001a",
-+ },
-+ {
-+ .supply = "DCVDD",
-+ .dev_name = "0-001a",
-+ },
-+ {
-+ .supply = "CPVDD",
-+ .dev_name = "0-001a",
-+ },
-+ {
-+ .supply = "PLLVDD",
-+ .dev_name = "0-001a",
-+ }
-+};
-+static struct regulator_consumer_supply vgen5_consumers[] = {
-+ {
-+ .supply = "VGEN5_2V8",
-+ }
-+};
-+static struct regulator_consumer_supply vgen6_consumers[] = {
-+ {
-+ .supply = "VGEN6_3V3",
-+ }
-+};
-+
-+static struct regulator_init_data sw1a_init = {
-+ .constraints = {
-+ .name = "PFUZE100_SW1A",
-+#ifdef PFUZE100_FIRST_VERSION
-+ .min_uV = 650000,
-+ .max_uV = 1437500,
-+#else
-+ .min_uV = 300000,
-+ .max_uV = 1875000,
-+#endif
-+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-+ .valid_modes_mask = 0,
-+ .boot_on = 1,
-+ .always_on = 1,
-+ },
-+};
-+
-+static struct regulator_init_data sw1b_init = {
-+ .constraints = {
-+ .name = "PFUZE100_SW1B",
-+ .min_uV = 300000,
-+ .max_uV = 1875000,
-+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-+ .valid_modes_mask = 0,
-+ .always_on = 1,
-+ .boot_on = 1,
-+ },
-+};
-+
-+static struct regulator_init_data sw1c_init = {
-+ .constraints = {
-+ .name = "PFUZE100_SW1C",
-+ .min_uV = 300000,
-+ .max_uV = 1875000,
-+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-+ .valid_modes_mask = 0,
-+ .always_on = 1,
-+ .boot_on = 1,
-+ },
-+};
-+
-+static struct regulator_init_data sw2_init = {
-+ .constraints = {
-+ .name = "PFUZE100_SW2",
-+#if PFUZE100_SW2_VOL6
-+ .min_uV = 800000,
-+ .max_uV = 3950000,
-+#else
-+ .min_uV = 400000,
-+ .max_uV = 1975000,
-+#endif
-+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-+ .valid_modes_mask = 0,
-+ .always_on = 1,
-+ .boot_on = 1,
-+ },
-+ .num_consumer_supplies = ARRAY_SIZE(sw2_consumers),
-+ .consumer_supplies = sw2_consumers,
-+};
-+
-+static struct regulator_init_data sw3a_init = {
-+ .constraints = {
-+ .name = "PFUZE100_SW3A",
-+#if PFUZE100_SW3_VOL6
-+ .min_uV = 800000,
-+ .max_uV = 3950000,
-+#else
-+ .min_uV = 400000,
-+ .max_uV = 1975000,
-+#endif
-+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-+ .valid_modes_mask = 0,
-+ .always_on = 1,
-+ .boot_on = 1,
-+ },
-+};
-+
-+static struct regulator_init_data sw3b_init = {
-+ .constraints = {
-+ .name = "PFUZE100_SW3B",
-+#if PFUZE100_SW3_VOL6
-+ .min_uV = 800000,
-+ .max_uV = 3950000,
-+#else
-+ .min_uV = 400000,
-+ .max_uV = 1975000,
-+#endif
-+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-+ .valid_modes_mask = 0,
-+ .always_on = 1,
-+ .boot_on = 1,
-+ },
-+};
-+
-+static struct regulator_init_data sw4_init = {
-+ .constraints = {
-+ .name = "PFUZE100_SW4",
-+#if PFUZE100_SW4_VOL6
-+ .min_uV = 800000,
-+ .max_uV = 3950000,
-+#else
-+ .min_uV = 400000,
-+ .max_uV = 1975000,
-+#endif
-+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-+ .valid_modes_mask = 0,
-+ },
-+ .num_consumer_supplies = ARRAY_SIZE(sw4_consumers),
-+ .consumer_supplies = sw4_consumers,
-+};
-+
-+static struct regulator_init_data swbst_init = {
-+ .constraints = {
-+ .name = "PFUZE100_SWBST",
-+ .min_uV = 5000000,
-+ .max_uV = 5150000,
-+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-+ .valid_modes_mask = 0,
-+ .always_on = 1,
-+ .boot_on = 1,
-+ },
-+ .num_consumer_supplies = ARRAY_SIZE(swbst_consumers),
-+ .consumer_supplies = swbst_consumers,
-+};
-+
-+static struct regulator_init_data vsnvs_init = {
-+ .constraints = {
-+ .name = "PFUZE100_VSNVS",
-+ .min_uV = 1200000,
-+ .max_uV = 3000000,
-+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-+ .valid_modes_mask = 0,
-+ .always_on = 1,
-+ .boot_on = 1,
-+ },
-+};
-+
-+static struct regulator_init_data vrefddr_init = {
-+ .constraints = {
-+ .name = "PFUZE100_VREFDDR",
-+ .always_on = 1,
-+ .boot_on = 1,
-+ },
-+};
-+
-+static struct regulator_init_data vgen1_init = {
-+ .constraints = {
-+ .name = "PFUZE100_VGEN1",
-+#ifdef PFUZE100_FIRST_VERSION
-+ .min_uV = 1200000,
-+ .max_uV = 1550000,
-+#else
-+ .min_uV = 800000,
-+ .max_uV = 1550000,
-+#endif
-+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
-+ REGULATOR_CHANGE_STATUS,
-+ .valid_modes_mask = 0,
-+ },
-+ .num_consumer_supplies = ARRAY_SIZE(vgen1_consumers),
-+ .consumer_supplies = vgen1_consumers,
-+};
-+
-+static struct regulator_init_data vgen2_init = {
-+ .constraints = {
-+ .name = "PFUZE100_VGEN2",
-+#ifdef PFUZE100_FIRST_VERSION
-+ .min_uV = 1200000,
-+ .max_uV = 1550000,
-+#else
-+ .min_uV = 800000,
-+ .max_uV = 1550000,
-+#endif
-+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
-+ REGULATOR_CHANGE_STATUS,
-+ .valid_modes_mask = 0,
-+ },
-+ .num_consumer_supplies = ARRAY_SIZE(vgen2_consumers),
-+ .consumer_supplies = vgen2_consumers,
-+
-+};
-+
-+static struct regulator_init_data vgen3_init = {
-+ .constraints = {
-+ .name = "PFUZE100_VGEN3",
-+ .min_uV = 1800000,
-+ .max_uV = 3300000,
-+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
-+ REGULATOR_CHANGE_STATUS,
-+ .valid_modes_mask = 0,
-+ },
-+};
-+
-+static struct regulator_init_data vgen4_init = {
-+ .constraints = {
-+ .name = "PFUZE100_VGEN4",
-+ .min_uV = 1800000,
-+ .max_uV = 3300000,
-+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
-+ REGULATOR_CHANGE_STATUS,
-+ .valid_modes_mask = 0,
-+ .always_on = 1,
-+ .boot_on = 1,
-+ },
-+ .num_consumer_supplies = ARRAY_SIZE(vgen4_consumers),
-+ .consumer_supplies = vgen4_consumers,
-+};
-+
-+static struct regulator_init_data vgen5_init = {
-+ .constraints = {
-+ .name = "PFUZE100_VGEN5",
-+ .min_uV = 1800000,
-+ .max_uV = 3300000,
-+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
-+ REGULATOR_CHANGE_STATUS,
-+ .valid_modes_mask = 0,
-+ .always_on = 1,
-+ .boot_on = 1,
-+ },
-+ .num_consumer_supplies = ARRAY_SIZE(vgen5_consumers),
-+ .consumer_supplies = vgen5_consumers,
-+};
-+
-+static struct regulator_init_data vgen6_init = {
-+ .constraints = {
-+ .name = "PFUZE100_VGEN6",
-+ .min_uV = 1800000,
-+ .max_uV = 3300000,
-+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
-+ REGULATOR_CHANGE_STATUS,
-+ .valid_modes_mask = 0,
-+ },
-+ .num_consumer_supplies = ARRAY_SIZE(vgen6_consumers),
-+ .consumer_supplies = vgen6_consumers,
-+};
-+
-+static int pfuze100_init(struct mc_pfuze *pfuze)
-+{
-+ int ret;
-+ ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1ASTANDBY,
-+ PFUZE100_SW1ASTANDBY_STBY_M,
-+ PFUZE100_SW1ASTANDBY_STBY_VAL);
-+ if (ret)
-+ goto err;
-+ ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1BSTANDBY,
-+ PFUZE100_SW1BSTANDBY_STBY_M,
-+ PFUZE100_SW1BSTANDBY_STBY_VAL);
-+ if (ret)
-+ goto err;
-+ ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1CSTANDBY,
-+ PFUZE100_SW1CSTANDBY_STBY_M,
-+ PFUZE100_SW1CSTANDBY_STBY_VAL);
-+ if (ret)
-+ goto err;
-+ return 0;
-+err:
-+ printk(KERN_ERR "pfuze100 init error!\n");
-+ return -1;
-+}
-+
-+static struct pfuze_regulator_init_data mx6q_qmx6_pfuze100_regulators[] = {
-+ {.id = PFUZE100_SW1A, .init_data = &sw1a_init},
-+ {.id = PFUZE100_SW1B, .init_data = &sw1b_init},
-+ {.id = PFUZE100_SW1C, .init_data = &sw1c_init},
-+ {.id = PFUZE100_SW2, .init_data = &sw2_init},
-+ {.id = PFUZE100_SW3A, .init_data = &sw3a_init},
-+ {.id = PFUZE100_SW3B, .init_data = &sw3b_init},
-+ {.id = PFUZE100_SW4, .init_data = &sw4_init},
-+ {.id = PFUZE100_SWBST, .init_data = &swbst_init},
-+ {.id = PFUZE100_VSNVS, .init_data = &vsnvs_init},
-+ {.id = PFUZE100_VREFDDR, .init_data = &vrefddr_init},
-+ {.id = PFUZE100_VGEN1, .init_data = &vgen1_init},
-+ {.id = PFUZE100_VGEN2, .init_data = &vgen2_init},
-+ {.id = PFUZE100_VGEN3, .init_data = &vgen3_init},
-+ {.id = PFUZE100_VGEN4, .init_data = &vgen4_init},
-+ {.id = PFUZE100_VGEN5, .init_data = &vgen5_init},
-+ {.id = PFUZE100_VGEN6, .init_data = &vgen6_init},
-+};
-+
-+static struct pfuze_platform_data pfuze100_plat = {
-+ .flags = PFUZE_USE_REGULATOR,
-+ .num_regulators = ARRAY_SIZE(mx6q_qmx6_pfuze100_regulators),
-+ .regulators = mx6q_qmx6_pfuze100_regulators,
-+ .pfuze_init = pfuze100_init,
-+};
-+
-+static struct i2c_board_info __initdata pfuze100_i2c_device = {
-+ I2C_BOARD_INFO(PFUZE100_I2C_DEVICE_NAME, PFUZE100_I2C_ADDR),
-+ .platform_data = &pfuze100_plat,
-+};
-+
-+int __init mx6q_qmx6_init_pfuze100(u32 int_gpio)
-+{
-+ pfuze100_i2c_device.irq = gpio_to_irq(int_gpio); /*update INT gpio */
-+ return i2c_register_board_info(1, &pfuze100_i2c_device, 1);
-+}
-diff --git a/arch/arm/plat-mxc/include/mach/esdhc.h b/arch/arm/plat-mxc/include/mach/esdhc.h
-index bb15db1..dc5267d 100644
---- a/arch/arm/plat-mxc/include/mach/esdhc.h
-+++ b/arch/arm/plat-mxc/include/mach/esdhc.h
-@@ -36,5 +36,6 @@ struct esdhc_platform_data {
- unsigned int keep_power_at_suspend;
- unsigned int delay_line;
- int (*platform_pad_change)(unsigned int index, int clock);
-+ unsigned int force_write_access;
- };
- #endif /* __ASM_ARCH_IMX_ESDHC_H */
-diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
-index f6b5c0e..0b2d992 100644
---- a/arch/arm/tools/mach-types
-+++ b/arch/arm/tools/mach-types
-@@ -1118,6 +1118,7 @@ mx6q_sabrelite MACH_MX6Q_SABRELITE MX6Q_SABRELITE 3769
- mx6q_sabresd MACH_MX6Q_SABRESD MX6Q_SABRESD 3980
- mx6q_arm2 MACH_MX6Q_ARM2 MX6Q_ARM2 3837
- mx6sl_arm2 MACH_MX6SL_ARM2 MX6SL_ARM2 4091
-+mx6q_qmx6 MACH_MX6Q_QMX6 MX6Q_QMX6 4122
- mx6q_hdmidongle MACH_MX6Q_HDMIDONGLE MX6Q_HDMIDONGLE 4284
- mx6sl_evk MACH_MX6SL_EVK MX6SL_EVK 4307
-
-diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
-index 35fd825..44483dd 100644
---- a/drivers/mmc/host/sdhci-esdhc-imx.c
-+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
-@@ -563,7 +563,7 @@ static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
- case SDHCI_COMMAND:
- if ((host->cmd->opcode == MMC_STOP_TRANSMISSION ||
- host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
-- (imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
-+ (imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
- val |= SDHCI_CMD_ABORTCMD;
-
- writel(0x08800880, host->ioaddr + SDHCI_CAPABILITIES_1);
-@@ -719,6 +719,9 @@ static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
- {
- struct esdhc_platform_data *boarddata = host->mmc->parent->platform_data;
-
-+ if (boarddata->force_write_access)
-+ return 0;
-+
- if (boarddata && gpio_is_valid(boarddata->wp_gpio))
- return gpio_get_value(boarddata->wp_gpio);
- else
-diff --git a/drivers/net/fec.c b/drivers/net/fec.c
-index 71e0abc..d437fec 100755
---- a/drivers/net/fec.c
-+++ b/drivers/net/fec.c
-@@ -105,10 +105,10 @@ MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
- #define FEC_FLASHMAC 0xf0006000
- #elif defined(CONFIG_CANCam)
- #define FEC_FLASHMAC 0xf0020000
--#elif defined (CONFIG_M5272C3)
-+#elif defined(CONFIG_M5272C3)
- #define FEC_FLASHMAC (0xffe04000 + 4)
- #elif defined(CONFIG_MOD5272)
--#define FEC_FLASHMAC 0xffc0406b
-+#define FEC_FLASHMAC 0xffc0406b
- #else
- #define FEC_FLASHMAC 0
- #endif
-@@ -174,8 +174,8 @@ MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
- * account when setting it.
- */
- #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
-- defined(CONFIG_M520x) || defined(CONFIG_M532x) || \
-- defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28)
-+ defined(CONFIG_M520x) || defined(CONFIG_M532x) || \
-+ defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28)
- #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
- #else
- #define OPT_FRAME_SIZE 0
-@@ -200,8 +200,8 @@ struct fec_enet_private {
-
- /* The saved address of a sent-in-place packet/buffer, for skfree(). */
- unsigned char *tx_bounce[TX_RING_SIZE];
-- struct sk_buff* tx_skbuff[TX_RING_SIZE];
-- struct sk_buff* rx_skbuff[RX_RING_SIZE];
-+ struct sk_buff *tx_skbuff[TX_RING_SIZE];
-+ struct sk_buff *rx_skbuff[RX_RING_SIZE];
- ushort skb_cur;
- ushort skb_dirty;
-
-@@ -250,7 +250,7 @@ struct fec_enet_private {
- #define FEC_NAPI_ENABLE FALSE
- #endif
-
--static irqreturn_t fec_enet_interrupt(int irq, void * dev_id);
-+static irqreturn_t fec_enet_interrupt(int irq, void *dev_id);
- static void fec_enet_tx(struct net_device *dev);
- static int fec_rx_poll(struct napi_struct *napi, int budget);
- static void fec_enet_rx(struct net_device *dev);
-@@ -518,7 +518,7 @@ fec_enet_tx(struct net_device *ndev)
- }
-
- if (status & BD_ENET_TX_READY)
-- printk("HEY! Enet xmit interrupt and TX_READY.\n");
-+ printk(KERN_INFO "HEY! Enet xmit interrupt and TX_READY.\n");
-
- /* Deferred means some collisions occurred during transmit,
- * but we eventually sent the packet OK.
-@@ -768,7 +768,7 @@ fec_enet_rx(struct net_device *ndev)
- ndev->stats.rx_packets++;
- pkt_len = bdp->cbd_datlen;
- ndev->stats.rx_bytes += pkt_len;
-- data = (__u8*)__va(bdp->cbd_bufaddr);
-+ data = (__u8 *)__va(bdp->cbd_bufaddr);
-
- if (bdp->cbd_bufaddr)
- dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
-@@ -927,7 +927,7 @@ static void __inline__ fec_get_mac(struct net_device *ndev)
-
- /* Adjust MAC if using macaddr */
- if (iap == macaddr)
-- ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->pdev->id;
-+ ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->pdev->id;
- }
-
- /* ------------------------------------------------------------------------- */
-@@ -1112,6 +1112,7 @@ static int fec_enet_mii_init(struct platform_device *pdev)
- const struct platform_device_id *id_entry =
- platform_get_device_id(fep->pdev);
- int err = -ENXIO, i;
-+ struct clk *bus_clk;
-
- /*
- * The dual fec interfaces are not equivalent with enet-mac.
-@@ -1137,11 +1138,10 @@ static int fec_enet_mii_init(struct platform_device *pdev)
-
- fep->mii_timeout = 0;
-
-- /*
-- * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
-- */
-- fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->mdc_clk),
-- (FEC_ENET_MII_CLK << 2)) << 1;
-+ /* sml 2012-11-29: MII Speed derived from 66MHz ipg-clk */
-+ bus_clk = clk_get(NULL, "ipg_clk");
-+ fep->phy_speed = (DIV_ROUND_UP(clk_get_rate(bus_clk), FEC_ENET_MII_CLK)) - 1;
-+
- /* set hold time to 2 internal clock cycle */
- if (cpu_is_mx6q() || cpu_is_mx6dl())
- fep->phy_speed |= FEC_ENET_HOLD_TIME;
-@@ -1929,7 +1929,7 @@ fec_probe(struct platform_device *pdev)
-
- /* Carrier starts down, phylib will bring it up */
- netif_carrier_off(ndev);
-- clk_disable(fep->clk);
-+ clk_unprepare(fep->clk);
-
- INIT_DELAYED_WORK(&fep->fixup_trigger_tx, fixup_trigger_tx_func);
-
-diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
-index 80747d2..f158bc6 100644
---- a/drivers/net/phy/micrel.c
-+++ b/drivers/net/phy/micrel.c
-@@ -187,6 +187,21 @@ static struct phy_driver ksz9021_driver = {
- .driver = { .owner = THIS_MODULE, },
- };
-
-+static struct phy_driver ksz9031_driver = {
-+ .phy_id = PHY_ID_KSZ9031,
-+ .phy_id_mask = 0x00ffffff,
-+ .name = "Micrel KSZ9031 Gigabit PHY",
-+ .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause
-+ | SUPPORTED_Asym_Pause),
-+ .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
-+ .config_init = kszphy_config_init,
-+ .config_aneg = genphy_config_aneg,
-+ .read_status = genphy_read_status,
-+ .ack_interrupt = kszphy_ack_interrupt,
-+ .config_intr = ksz9021_config_intr,
-+ .driver = { .owner = THIS_MODULE, },
-+};
-+
- static int __init ksphy_init(void)
- {
- int ret;
-@@ -209,8 +224,14 @@ static int __init ksphy_init(void)
- if (ret)
- goto err5;
-
-+ ret = phy_driver_register(&ksz9031_driver);
-+ if (ret)
-+ goto err6;
-+
- return 0;
-
-+err6:
-+ phy_driver_unregister(&ksz9031_driver);
- err5:
- phy_driver_unregister(&ks8041_driver);
- err4:
-@@ -230,6 +251,7 @@ static void __exit ksphy_exit(void)
- phy_driver_unregister(&ksz9021_driver);
- phy_driver_unregister(&ks8041_driver);
- phy_driver_unregister(&ks8051_driver);
-+ phy_driver_unregister(&ksz9031_driver);
- }
-
- module_init(ksphy_init);
-@@ -241,6 +263,7 @@ MODULE_LICENSE("GPL");
-
- static struct mdio_device_id __maybe_unused micrel_tbl[] = {
- { PHY_ID_KSZ9021, 0x00ffffff },
-+ { PHY_ID_KSZ9031, 0x00ffffff },
- { PHY_ID_KS8001, 0x00ffffff },
- { PHY_ID_KS8737, 0x00ffffff },
- { PHY_ID_KS8041, 0x00ffffff },
-diff --git a/include/linux/micrel_phy.h b/include/linux/micrel_phy.h
-index dd8da34..3222193 100644
---- a/include/linux/micrel_phy.h
-+++ b/include/linux/micrel_phy.h
-@@ -4,6 +4,7 @@
- #define MICREL_PHY_ID_MASK 0x00fffff0
-
- #define PHY_ID_KSZ9021 0x00221611
-+#define PHY_ID_KSZ9031 0x00221621
- #define PHY_ID_KS8737 0x00221720
- #define PHY_ID_KS8041 0x00221510
- #define PHY_ID_KS8051 0x00221550
-diff --git a/sound/soc/imx/Kconfig b/sound/soc/imx/Kconfig
-index e30ebbe..3967a99 100644
---- a/sound/soc/imx/Kconfig
-+++ b/sound/soc/imx/Kconfig
-@@ -53,7 +53,7 @@ config SND_SOC_PHYCORE_AC97
- config SND_SOC_IMX_SGTL5000
- tristate "SoC Audio support for i.MX boards with sgtl5000"
- depends on I2C && (MACH_MX35_3DS || MACH_MX51_BABBAGE \
-- || MACH_MX6Q_SABRELITE || MACH_MX6Q_ARM2)
-+ || MACH_MX6Q_SABRELITE || MACH_MX6Q_ARM2 || MACH_MX6Q_QMX6)
- select SND_SOC_SGTL5000
- select SND_MXC_SOC_MX2
- help
-diff --git a/sound/soc/imx/imx-sgtl5000.c b/sound/soc/imx/imx-sgtl5000.c
-index 9325dc8..7c52545 100644
---- a/sound/soc/imx/imx-sgtl5000.c
-+++ b/sound/soc/imx/imx-sgtl5000.c
-@@ -363,7 +363,7 @@ static int __init imx_sgtl5000_init(void)
- if (ret)
- return -ENOMEM;
-
-- if (machine_is_mx35_3ds() || machine_is_mx6q_sabrelite())
-+ if (machine_is_mx35_3ds() || machine_is_mx6q_sabrelite() || machine_is_mx6q_qmx6())
- imx_sgtl5000_dai[0].codec_name = "sgtl5000.0-000a";
- else
- imx_sgtl5000_dai[0].codec_name = "sgtl5000.1-000a";
---
-1.8.5.3
-
diff --git a/recipes-kernel/linux/linux-congatec-3.0.35/0001-perf-tools-Fix-getrusage-related-build-failure-on-gl.patch b/recipes-kernel/linux/linux-congatec-3.0.35/0001-perf-tools-Fix-getrusage-related-build-failure-on-gl.patch
deleted file mode 100644
index abc02c9..0000000
--- a/recipes-kernel/linux/linux-congatec-3.0.35/0001-perf-tools-Fix-getrusage-related-build-failure-on-gl.patch
+++ /dev/null
@@ -1,43 +0,0 @@
-From 503daf4789dd23e4dc1e16c256de0c163fc2bf87 Mon Sep 17 00:00:00 2001
-From: Markus Trippelsdorf <markus at trippelsdorf.de>
-Date: Wed, 4 Apr 2012 10:45:27 +0200
-Subject: [PATCH] perf tools: Fix getrusage() related build failure on glibc
- trunk
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-Organization: O.S. Systems Software LTDA.
-
-On a system running glibc trunk perf doesn't build:
-
- CC builtin-sched.o
-builtin-sched.c: In function ‘get_cpu_usage_nsec_parent’: builtin-sched.c:399:16: error: storage size of ‘ru’ isn’t known builtin-sched.c:403:2: error: implicit declaration of function ‘getrusage’ [-Werror=implicit-function-declaration]
- [...]
-
-Fix it by including sys/resource.h.
-
-Upstream-Status: Pending
-
-Signed-off-by: Markus Trippelsdorf <markus at trippelsdorf.de>
-Cc: Peter Zijlstra <a.p.zijlstra at chello.nl>
-Link: http://lkml.kernel.org/r/20120404084527.GA294@x4
-Signed-off-by: Ingo Molnar <mingo at kernel.org>
----
- tools/perf/builtin-sched.c | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/tools/perf/builtin-sched.c b/tools/perf/builtin-sched.c
-index dcfe887..3632c2f 100644
---- a/tools/perf/builtin-sched.c
-+++ b/tools/perf/builtin-sched.c
-@@ -14,6 +14,7 @@
- #include "util/debug.h"
-
- #include <sys/prctl.h>
-+#include <sys/resource.h>
-
- #include <semaphore.h>
- #include <pthread.h>
---
-1.8.4.rc3
-
diff --git a/recipes-kernel/linux/linux-congatec-3.0.35/0002-ARM-7668-1-fix-memset-related-crashes-caused-by-rece.patch b/recipes-kernel/linux/linux-congatec-3.0.35/0002-ARM-7668-1-fix-memset-related-crashes-caused-by-rece.patch
deleted file mode 100644
index 4c31e74..0000000
--- a/recipes-kernel/linux/linux-congatec-3.0.35/0002-ARM-7668-1-fix-memset-related-crashes-caused-by-rece.patch
+++ /dev/null
@@ -1,259 +0,0 @@
-From 2235b85f1c76d98b5f1e160cbd0a61a84c15e125 Mon Sep 17 00:00:00 2001
-From: Ivan Djelic <ivan.djelic at parrot.com>
-Date: Wed, 6 Mar 2013 20:09:27 +0100
-Subject: [PATCH] ARM: 7668/1: fix memset-related crashes caused by recent GCC
- (4.7.2) optimizations
-Organization: O.S. Systems Software LTDA.
-
-Recent GCC versions (e.g. GCC-4.7.2) perform optimizations based on
-assumptions about the implementation of memset and similar functions.
-The current ARM optimized memset code does not return the value of
-its first argument, as is usually expected from standard implementations.
-
-For instance in the following function:
-
-void debug_mutex_lock_common(struct mutex *lock, struct mutex_waiter *waiter)
-{
- memset(waiter, MUTEX_DEBUG_INIT, sizeof(*waiter));
- waiter->magic = waiter;
- INIT_LIST_HEAD(&waiter->list);
-}
-
-compiled as:
-
-800554d0 <debug_mutex_lock_common>:
-800554d0: e92d4008 push {r3, lr}
-800554d4: e1a00001 mov r0, r1
-800554d8: e3a02010 mov r2, #16 ; 0x10
-800554dc: e3a01011 mov r1, #17 ; 0x11
-800554e0: eb04426e bl 80165ea0 <memset>
-800554e4: e1a03000 mov r3, r0
-800554e8: e583000c str r0, [r3, #12]
-800554ec: e5830000 str r0, [r3]
-800554f0: e5830004 str r0, [r3, #4]
-800554f4: e8bd8008 pop {r3, pc}
-
-GCC assumes memset returns the value of pointer 'waiter' in register r0; causing
-register/memory corruptions.
-
-This patch fixes the return value of the assembly version of memset.
-It adds a 'mov' instruction and merges an additional load+store into
-existing load/store instructions.
-For ease of review, here is a breakdown of the patch into 4 simple steps:
-
-Step 1
-======
-Perform the following substitutions:
-ip -> r8, then
-r0 -> ip,
-and insert 'mov ip, r0' as the first statement of the function.
-At this point, we have a memset() implementation returning the proper result,
-but corrupting r8 on some paths (the ones that were using ip).
-
-Step 2
-======
-Make sure r8 is saved and restored when (! CALGN(1)+0) == 1:
-
-save r8:
-- str lr, [sp, #-4]!
-+ stmfd sp!, {r8, lr}
-
-and restore r8 on both exit paths:
-- ldmeqfd sp!, {pc} @ Now <64 bytes to go.
-+ ldmeqfd sp!, {r8, pc} @ Now <64 bytes to go.
-(...)
- tst r2, #16
- stmneia ip!, {r1, r3, r8, lr}
-- ldr lr, [sp], #4
-+ ldmfd sp!, {r8, lr}
-
-Step 3
-======
-Make sure r8 is saved and restored when (! CALGN(1)+0) == 0:
-
-save r8:
-- stmfd sp!, {r4-r7, lr}
-+ stmfd sp!, {r4-r8, lr}
-
-and restore r8 on both exit paths:
- bgt 3b
-- ldmeqfd sp!, {r4-r7, pc}
-+ ldmeqfd sp!, {r4-r8, pc}
-(...)
- tst r2, #16
- stmneia ip!, {r4-r7}
-- ldmfd sp!, {r4-r7, lr}
-+ ldmfd sp!, {r4-r8, lr}
-
-Step 4
-======
-Rewrite register list "r4-r7, r8" as "r4-r8".
-
-Upstream-Status: Pending
-
-Signed-off-by: Ivan Djelic <ivan.djelic at parrot.com>
-Reviewed-by: Nicolas Pitre <nico at linaro.org>
-Signed-off-by: Dirk Behme <dirk.behme at gmail.com>
-Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
-(cherry picked from commit 455bd4c430b0c0a361f38e8658a0d6cb469942b5)
----
- arch/arm/lib/memset.S | 85 ++++++++++++++++++++++++++-------------------------
- 1 file changed, 44 insertions(+), 41 deletions(-)
-
-diff --git a/arch/arm/lib/memset.S b/arch/arm/lib/memset.S
-index 650d592..d912e73 100644
---- a/arch/arm/lib/memset.S
-+++ b/arch/arm/lib/memset.S
-@@ -19,9 +19,9 @@
- 1: subs r2, r2, #4 @ 1 do we have enough
- blt 5f @ 1 bytes to align with?
- cmp r3, #2 @ 1
-- strltb r1, [r0], #1 @ 1
-- strleb r1, [r0], #1 @ 1
-- strb r1, [r0], #1 @ 1
-+ strltb r1, [ip], #1 @ 1
-+ strleb r1, [ip], #1 @ 1
-+ strb r1, [ip], #1 @ 1
- add r2, r2, r3 @ 1 (r2 = r2 - (4 - r3))
- /*
- * The pointer is now aligned and the length is adjusted. Try doing the
-@@ -29,10 +29,14 @@
- */
-
- ENTRY(memset)
-- ands r3, r0, #3 @ 1 unaligned?
-+/*
-+ * Preserve the contents of r0 for the return value.
-+ */
-+ mov ip, r0
-+ ands r3, ip, #3 @ 1 unaligned?
- bne 1b @ 1
- /*
-- * we know that the pointer in r0 is aligned to a word boundary.
-+ * we know that the pointer in ip is aligned to a word boundary.
- */
- orr r1, r1, r1, lsl #8
- orr r1, r1, r1, lsl #16
-@@ -43,29 +47,28 @@ ENTRY(memset)
- #if ! CALGN(1)+0
-
- /*
-- * We need an extra register for this loop - save the return address and
-- * use the LR
-+ * We need 2 extra registers for this loop - use r8 and the LR
- */
-- str lr, [sp, #-4]!
-- mov ip, r1
-+ stmfd sp!, {r8, lr}
-+ mov r8, r1
- mov lr, r1
-
- 2: subs r2, r2, #64
-- stmgeia r0!, {r1, r3, ip, lr} @ 64 bytes at a time.
-- stmgeia r0!, {r1, r3, ip, lr}
-- stmgeia r0!, {r1, r3, ip, lr}
-- stmgeia r0!, {r1, r3, ip, lr}
-+ stmgeia ip!, {r1, r3, r8, lr} @ 64 bytes at a time.
-+ stmgeia ip!, {r1, r3, r8, lr}
-+ stmgeia ip!, {r1, r3, r8, lr}
-+ stmgeia ip!, {r1, r3, r8, lr}
- bgt 2b
-- ldmeqfd sp!, {pc} @ Now <64 bytes to go.
-+ ldmeqfd sp!, {r8, pc} @ Now <64 bytes to go.
- /*
- * No need to correct the count; we're only testing bits from now on
- */
- tst r2, #32
-- stmneia r0!, {r1, r3, ip, lr}
-- stmneia r0!, {r1, r3, ip, lr}
-+ stmneia ip!, {r1, r3, r8, lr}
-+ stmneia ip!, {r1, r3, r8, lr}
- tst r2, #16
-- stmneia r0!, {r1, r3, ip, lr}
-- ldr lr, [sp], #4
-+ stmneia ip!, {r1, r3, r8, lr}
-+ ldmfd sp!, {r8, lr}
-
- #else
-
-@@ -74,54 +77,54 @@ ENTRY(memset)
- * whole cache lines at once.
- */
-
-- stmfd sp!, {r4-r7, lr}
-+ stmfd sp!, {r4-r8, lr}
- mov r4, r1
- mov r5, r1
- mov r6, r1
- mov r7, r1
-- mov ip, r1
-+ mov r8, r1
- mov lr, r1
-
- cmp r2, #96
-- tstgt r0, #31
-+ tstgt ip, #31
- ble 3f
-
-- and ip, r0, #31
-- rsb ip, ip, #32
-- sub r2, r2, ip
-- movs ip, ip, lsl #(32 - 4)
-- stmcsia r0!, {r4, r5, r6, r7}
-- stmmiia r0!, {r4, r5}
-- tst ip, #(1 << 30)
-- mov ip, r1
-- strne r1, [r0], #4
-+ and r8, ip, #31
-+ rsb r8, r8, #32
-+ sub r2, r2, r8
-+ movs r8, r8, lsl #(32 - 4)
-+ stmcsia ip!, {r4, r5, r6, r7}
-+ stmmiia ip!, {r4, r5}
-+ tst r8, #(1 << 30)
-+ mov r8, r1
-+ strne r1, [ip], #4
-
- 3: subs r2, r2, #64
-- stmgeia r0!, {r1, r3-r7, ip, lr}
-- stmgeia r0!, {r1, r3-r7, ip, lr}
-+ stmgeia ip!, {r1, r3-r8, lr}
-+ stmgeia ip!, {r1, r3-r8, lr}
- bgt 3b
-- ldmeqfd sp!, {r4-r7, pc}
-+ ldmeqfd sp!, {r4-r8, pc}
-
- tst r2, #32
-- stmneia r0!, {r1, r3-r7, ip, lr}
-+ stmneia ip!, {r1, r3-r8, lr}
- tst r2, #16
-- stmneia r0!, {r4-r7}
-- ldmfd sp!, {r4-r7, lr}
-+ stmneia ip!, {r4-r7}
-+ ldmfd sp!, {r4-r8, lr}
-
- #endif
-
- 4: tst r2, #8
-- stmneia r0!, {r1, r3}
-+ stmneia ip!, {r1, r3}
- tst r2, #4
-- strne r1, [r0], #4
-+ strne r1, [ip], #4
- /*
- * When we get here, we've got less than 4 bytes to zero. We
- * may have an unaligned pointer as well.
- */
- 5: tst r2, #2
-- strneb r1, [r0], #1
-- strneb r1, [r0], #1
-+ strneb r1, [ip], #1
-+ strneb r1, [ip], #1
- tst r2, #1
-- strneb r1, [r0], #1
-+ strneb r1, [ip], #1
- mov pc, lr
- ENDPROC(memset)
---
-1.8.4.rc3
-
diff --git a/recipes-kernel/linux/linux-congatec-3.0.35/0003-ARM-7670-1-fix-the-memset-fix.patch b/recipes-kernel/linux/linux-congatec-3.0.35/0003-ARM-7670-1-fix-the-memset-fix.patch
deleted file mode 100644
index b8d6f53..0000000
--- a/recipes-kernel/linux/linux-congatec-3.0.35/0003-ARM-7670-1-fix-the-memset-fix.patch
+++ /dev/null
@@ -1,87 +0,0 @@
-From 2ba23fa6c4128febaaf57fe184420a7111caa237 Mon Sep 17 00:00:00 2001
-From: Nicolas Pitre <nicolas.pitre at linaro.org>
-Date: Tue, 12 Mar 2013 13:00:42 +0100
-Subject: [PATCH] ARM: 7670/1: fix the memset fix
-Organization: O.S. Systems Software LTDA.
-
-Commit 455bd4c430b0 ("ARM: 7668/1: fix memset-related crashes caused by
-recent GCC (4.7.2) optimizations") attempted to fix a compliance issue
-with the memset return value. However the memset itself became broken
-by that patch for misaligned pointers.
-
-This fixes the above by branching over the entry code from the
-misaligned fixup code to avoid reloading the original pointer.
-
-Also, because the function entry alignment is wrong in the Thumb mode
-compilation, that fixup code is moved to the end.
-
-While at it, the entry instructions are slightly reworked to help dual
-issue pipelines.
-
-Upstream-Status: Pending
-
-Signed-off-by: Nicolas Pitre <nico at linaro.org>
-Tested-by: Alexander Holler <holler at ahsoftware.de>
-Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
-(cherry picked from commit 418df63adac56841ef6b0f1fcf435bc64d4ed177)
----
- arch/arm/lib/memset.S | 33 +++++++++++++--------------------
- 1 file changed, 13 insertions(+), 20 deletions(-)
-
-diff --git a/arch/arm/lib/memset.S b/arch/arm/lib/memset.S
-index d912e73..94b0650 100644
---- a/arch/arm/lib/memset.S
-+++ b/arch/arm/lib/memset.S
-@@ -14,31 +14,15 @@
-
- .text
- .align 5
-- .word 0
--
--1: subs r2, r2, #4 @ 1 do we have enough
-- blt 5f @ 1 bytes to align with?
-- cmp r3, #2 @ 1
-- strltb r1, [ip], #1 @ 1
-- strleb r1, [ip], #1 @ 1
-- strb r1, [ip], #1 @ 1
-- add r2, r2, r3 @ 1 (r2 = r2 - (4 - r3))
--/*
-- * The pointer is now aligned and the length is adjusted. Try doing the
-- * memset again.
-- */
-
- ENTRY(memset)
--/*
-- * Preserve the contents of r0 for the return value.
-- */
-- mov ip, r0
-- ands r3, ip, #3 @ 1 unaligned?
-- bne 1b @ 1
-+ ands r3, r0, #3 @ 1 unaligned?
-+ mov ip, r0 @ preserve r0 as return value
-+ bne 6f @ 1
- /*
- * we know that the pointer in ip is aligned to a word boundary.
- */
-- orr r1, r1, r1, lsl #8
-+1: orr r1, r1, r1, lsl #8
- orr r1, r1, r1, lsl #16
- mov r3, r1
- cmp r2, #16
-@@ -127,4 +111,13 @@ ENTRY(memset)
- tst r2, #1
- strneb r1, [ip], #1
- mov pc, lr
-+
-+6: subs r2, r2, #4 @ 1 do we have enough
-+ blt 5b @ 1 bytes to align with?
-+ cmp r3, #2 @ 1
-+ strltb r1, [ip], #1 @ 1
-+ strleb r1, [ip], #1 @ 1
-+ strb r1, [ip], #1 @ 1
-+ add r2, r2, r3 @ 1 (r2 = r2 - (4 - r3))
-+ b 1b
- ENDPROC(memset)
---
-1.8.4.rc3
-
diff --git a/recipes-kernel/linux/linux-congatec-3.0.35/0004-ENGR00271136-Fix-build-break-when-CONFIG_CLK_DEBUG-i.patch b/recipes-kernel/linux/linux-congatec-3.0.35/0004-ENGR00271136-Fix-build-break-when-CONFIG_CLK_DEBUG-i.patch
deleted file mode 100644
index 7316351..0000000
--- a/recipes-kernel/linux/linux-congatec-3.0.35/0004-ENGR00271136-Fix-build-break-when-CONFIG_CLK_DEBUG-i.patch
+++ /dev/null
@@ -1,43 +0,0 @@
-From d8601292ae25e0af47aa4486055221ab44113f0e Mon Sep 17 00:00:00 2001
-From: Mahesh Mahadevan <Mahesh.Mahadevan at freescale.com>
-Date: Mon, 15 Jul 2013 15:34:54 -0500
-Subject: [PATCH] ENGR00271136 Fix build break when CONFIG_CLK_DEBUG is
- disabled
-Organization: O.S. Systems Software LTDA.
-
-clk structure member name is defined only when CONFIG_CLK_DEBUG is enabled.
-Hence need to encapsulate the code with this config.
-
-Patch received from imx community:
-https://community.freescale.com/thread/308482
-
-Upstream-Status: Pending
-
-Signed-off-by: xiongweihuang
-Signed-off-by: Mahesh Mahadevan <Mahesh.Mahadevan at freescale.com>
----
- arch/arm/plat-mxc/clock.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/arch/arm/plat-mxc/clock.c b/arch/arm/plat-mxc/clock.c
-index 93347eb..1aa2664 100755
---- a/arch/arm/plat-mxc/clock.c
-+++ b/arch/arm/plat-mxc/clock.c
-@@ -58,12 +58,12 @@ static void __clk_disable(struct clk *clk)
- {
- if (clk == NULL || IS_ERR(clk))
- return;
--
-+#ifdef CONFIG_CLK_DEBUG
- if (!clk->usecount) {
- WARN(1, "clock enable/disable mismatch! clk %s\n", clk->name);
- return;
- }
--
-+#endif
- if (!(--clk->usecount)) {
- if (clk->disable)
- clk->disable(clk);
---
-1.8.4.rc3
-
diff --git a/recipes-kernel/linux/linux-congatec-3.0.35/0005-ENGR00271359-Add-Multi-touch-support.patch b/recipes-kernel/linux/linux-congatec-3.0.35/0005-ENGR00271359-Add-Multi-touch-support.patch
deleted file mode 100644
index cb20198..0000000
--- a/recipes-kernel/linux/linux-congatec-3.0.35/0005-ENGR00271359-Add-Multi-touch-support.patch
+++ /dev/null
@@ -1,98 +0,0 @@
-From 538f4bb2f7a51f267395550a5be9f0ab2e426712 Mon Sep 17 00:00:00 2001
-From: Erik Boto <erik.boto at pelagicore.com>
-Date: Tue, 16 Jul 2013 12:06:05 -0500
-Subject: [PATCH] ENGR00271359 Add Multi-touch support
-Organization: O.S. Systems Software LTDA.
-
-The previous behavior of the driver did not work properly with Qt5
-QtQuick multi touch-point gestures, due to how touch-points are
-reported when removing a touch-point. My interpretation of the
-available documentation [1] was that the driver should report all
-touch-points between SYN_REPORTs, but it is not explicitly stated so.
-I've found another mail-thread [2] where the creator of the protocol
-states:
-
-"The protocol defines a generic way of sending a variable amount of
-contacts. The contact count is obtained by counting the number of
-non-empty finger packets between SYN_REPORT events."-Henrik Rydberg
-
-I think this verifies my assumption that all touch-points should be
-reported between SYN_REPORTs, otherwise it can not be used to obtain
-the count.
-
-[1] https://www.kernel.org/doc/Documentation/input/multi-touch-protocol.txt
-[2] http://lists.x.org/archives/xorg-devel/2010-March/006466.html
-
-Upstream-Status: Pending
-
-Signed-off-by: Erik Boto <erik.boto at pelagicore.com>
-Signed-off-by: Mahesh Mahadevan <Mahesh.Mahadevan at freescale.com>
-(cherry picked from commit 7cba001c5a502680f6dbf902821726779a9c9287)
----
- drivers/input/touchscreen/egalax_ts.c | 36 +++++++++++++++++------------------
- 1 file changed, 18 insertions(+), 18 deletions(-)
-
-diff --git a/drivers/input/touchscreen/egalax_ts.c b/drivers/input/touchscreen/egalax_ts.c
-index 0b6cde7..271f820 100644
---- a/drivers/input/touchscreen/egalax_ts.c
-+++ b/drivers/input/touchscreen/egalax_ts.c
-@@ -133,7 +133,6 @@ retry:
- }
-
- if (down) {
-- /* should also report old pointers */
- events[id].valid = valid;
- events[id].status = down;
- events[id].x = x;
-@@ -144,23 +143,6 @@ retry:
- input_report_abs(input_dev, ABS_Y, y);
- input_event(data->input_dev, EV_KEY, BTN_TOUCH, 1);
- input_report_abs(input_dev, ABS_PRESSURE, 1);
--#else
-- for (i = 0; i < MAX_SUPPORT_POINTS; i++) {
-- if (!events[i].valid)
-- continue;
-- dev_dbg(&client->dev, "report id:%d valid:%d x:%d y:%d",
-- i, valid, x, y);
--
-- input_report_abs(input_dev,
-- ABS_MT_TRACKING_ID, i);
-- input_report_abs(input_dev,
-- ABS_MT_TOUCH_MAJOR, 1);
-- input_report_abs(input_dev,
-- ABS_MT_POSITION_X, events[i].x);
-- input_report_abs(input_dev,
-- ABS_MT_POSITION_Y, events[i].y);
-- input_mt_sync(input_dev);
-- }
- #endif
- } else {
- dev_dbg(&client->dev, "release id:%d\n", id);
-@@ -176,6 +158,24 @@ retry:
- #endif
- }
-
-+#ifndef CONFIG_TOUCHSCREEN_EGALAX_SINGLE_TOUCH
-+ /* report all pointers */
-+ for (i = 0; i < MAX_SUPPORT_POINTS; i++) {
-+ if (!events[i].valid)
-+ continue;
-+ dev_dbg(&client->dev, "report id:%d valid:%d x:%d y:%d",
-+ i, valid, x, y);
-+ input_report_abs(input_dev,
-+ ABS_MT_TRACKING_ID, i);
-+ input_report_abs(input_dev,
-+ ABS_MT_TOUCH_MAJOR, 1);
-+ input_report_abs(input_dev,
-+ ABS_MT_POSITION_X, events[i].x);
-+ input_report_abs(input_dev,
-+ ABS_MT_POSITION_Y, events[i].y);
-+ input_mt_sync(input_dev);
-+ }
-+#endif
- input_sync(input_dev);
- return IRQ_HANDLED;
- }
---
-1.8.4.rc3
-
diff --git a/recipes-kernel/linux/linux-congatec-3.0.35/0006-Add-support-for-DVI-monitors.patch b/recipes-kernel/linux/linux-congatec-3.0.35/0006-Add-support-for-DVI-monitors.patch
deleted file mode 100644
index 00a6b5c..0000000
--- a/recipes-kernel/linux/linux-congatec-3.0.35/0006-Add-support-for-DVI-monitors.patch
+++ /dev/null
@@ -1,227 +0,0 @@
-From 3e6441d113f72b412081a2c87f39011e4c253a35 Mon Sep 17 00:00:00 2001
-From: Robert Winkler <robert.winkler at boundarydevices.com>
-Date: Fri, 19 Jul 2013 19:00:41 -0700
-Subject: [PATCH] Add support for DVI monitors
-Organization: O.S. Systems Software LTDA.
-
-Upstream-Status: Pending
-
-Signed-off-by: Robert Winkler <robert.winkler at boundarydevices.com>
----
- arch/arm/plat-mxc/include/mach/mxc_hdmi.h | 7 +++
- drivers/video/mxc_hdmi.c | 98 +++++++++++++------------------
- 2 files changed, 49 insertions(+), 56 deletions(-)
-
-diff --git a/arch/arm/plat-mxc/include/mach/mxc_hdmi.h b/arch/arm/plat-mxc/include/mach/mxc_hdmi.h
-index 94f7638..af59c62 100644
---- a/arch/arm/plat-mxc/include/mach/mxc_hdmi.h
-+++ b/arch/arm/plat-mxc/include/mach/mxc_hdmi.h
-@@ -605,6 +605,10 @@ enum {
- HDMI_IH_MUTE_PHY_STAT0_TX_PHY_LOCK = 0x2,
- HDMI_IH_MUTE_PHY_STAT0_HPD = 0x1,
-
-+/* IH and IH_MUTE convenience macro RX_SENSE | HPD*/
-+ HDMI_DVI_IH_STAT = 0x3D,
-+
-+
- /* IH_AHBDMAAUD_STAT0 field values */
- HDMI_IH_AHBDMAAUD_STAT0_ERROR = 0x20,
- HDMI_IH_AHBDMAAUD_STAT0_LOST = 0x10,
-@@ -903,6 +907,9 @@ enum {
- HDMI_PHY_HPD = 0x02,
- HDMI_PHY_TX_PHY_LOCK = 0x01,
-
-+/* HDMI STAT convenience RX_SENSE | HPD */
-+ HDMI_DVI_STAT = 0xF2,
-+
- /* PHY_I2CM_SLAVE_ADDR field values */
- HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69,
- HDMI_PHY_I2CM_SLAVE_ADDR_HEAC_PHY = 0x49,
-diff --git a/drivers/video/mxc_hdmi.c b/drivers/video/mxc_hdmi.c
-index c5069aa..544f352 100644
---- a/drivers/video/mxc_hdmi.c
-+++ b/drivers/video/mxc_hdmi.c
-@@ -180,7 +180,6 @@ struct mxc_hdmi {
- bool dft_mode_set;
- char *dft_mode_str;
- int default_bpp;
-- u8 latest_intr_stat;
- bool irq_enabled;
- spinlock_t irq_lock;
- bool phy_enabled;
-@@ -1996,58 +1995,48 @@ static void hotplug_worker(struct work_struct *work)
- struct delayed_work *delay_work = to_delayed_work(work);
- struct mxc_hdmi *hdmi =
- container_of(delay_work, struct mxc_hdmi, hotplug_work);
-- u32 phy_int_stat, phy_int_pol, phy_int_mask;
-- u8 val;
-+ u32 hdmi_phy_stat0, hdmi_phy_pol0, hdmi_phy_mask0;
- unsigned long flags;
- char event_string[32];
- char *envp[] = { event_string, NULL };
-
-- phy_int_stat = hdmi->latest_intr_stat;
-- phy_int_pol = hdmi_readb(HDMI_PHY_POL0);
-
-- dev_dbg(&hdmi->pdev->dev, "phy_int_stat=0x%x, phy_int_pol=0x%x\n",
-- phy_int_stat, phy_int_pol);
-+ hdmi_phy_stat0 = hdmi_readb(HDMI_PHY_STAT0);
-+ hdmi_phy_pol0 = hdmi_readb(HDMI_PHY_POL0);
-+
-+ dev_dbg(&hdmi->pdev->dev, "hdmi_phy_stat0=0x%x, hdmi_phy_pol0=0x%x\n",
-+ hdmi_phy_stat0, hdmi_phy_pol0);
-+
-+ /* Make HPD intr active low to capture unplug event or
-+ * active high to capture plugin event */
-+ hdmi_writeb((HDMI_DVI_STAT & ~hdmi_phy_stat0), HDMI_PHY_POL0);
-
- /* check cable status */
-- if (phy_int_stat & HDMI_IH_PHY_STAT0_HPD) {
-- /* cable connection changes */
-- if (phy_int_pol & HDMI_PHY_HPD) {
-- /* Plugin event */
-- dev_dbg(&hdmi->pdev->dev, "EVENT=plugin\n");
-- mxc_hdmi_cable_connected(hdmi);
--
-- /* Make HPD intr active low to capture unplug event */
-- val = hdmi_readb(HDMI_PHY_POL0);
-- val &= ~HDMI_PHY_HPD;
-- hdmi_writeb(val, HDMI_PHY_POL0);
--
-- sprintf(event_string, "EVENT=plugin");
-- kobject_uevent_env(&hdmi->pdev->dev.kobj, KOBJ_CHANGE, envp);
-+ if (hdmi_phy_stat0 & HDMI_DVI_STAT) {
-+ /* Plugin event */
-+ dev_dbg(&hdmi->pdev->dev, "EVENT=plugin\n");
-+ mxc_hdmi_cable_connected(hdmi);
-+
-+ sprintf(event_string, "EVENT=plugin");
-+ kobject_uevent_env(&hdmi->pdev->dev.kobj, KOBJ_CHANGE, envp);
- #ifdef CONFIG_MXC_HDMI_CEC
-- mxc_hdmi_cec_handle(0x80);
-+ mxc_hdmi_cec_handle(0x80);
- #endif
-- hdmi_set_cable_state(1);
--
-- } else if (!(phy_int_pol & HDMI_PHY_HPD)) {
-- /* Plugout event */
-- dev_dbg(&hdmi->pdev->dev, "EVENT=plugout\n");
-- hdmi_set_cable_state(0);
-- mxc_hdmi_abort_stream();
-- mxc_hdmi_cable_disconnected(hdmi);
-+ hdmi_set_cable_state(1);
-
-- /* Make HPD intr active high to capture plugin event */
-- val = hdmi_readb(HDMI_PHY_POL0);
-- val |= HDMI_PHY_HPD;
-- hdmi_writeb(val, HDMI_PHY_POL0);
-+ } else {
-+ /* Plugout event */
-+ dev_dbg(&hdmi->pdev->dev, "EVENT=plugout\n");
-+ hdmi_set_cable_state(0);
-+ mxc_hdmi_abort_stream();
-+ mxc_hdmi_cable_disconnected(hdmi);
-
-- sprintf(event_string, "EVENT=plugout");
-- kobject_uevent_env(&hdmi->pdev->dev.kobj, KOBJ_CHANGE, envp);
-+ sprintf(event_string, "EVENT=plugout");
-+ kobject_uevent_env(&hdmi->pdev->dev.kobj, KOBJ_CHANGE, envp);
- #ifdef CONFIG_MXC_HDMI_CEC
-- mxc_hdmi_cec_handle(0x100);
-+ mxc_hdmi_cec_handle(0x100);
- #endif
-
-- } else
-- dev_dbg(&hdmi->pdev->dev, "EVENT=none?\n");
- }
-
- /* Lock here to ensure full powerdown sequence
-@@ -2055,12 +2044,12 @@ static void hotplug_worker(struct work_struct *work)
- spin_lock_irqsave(&hdmi->irq_lock, flags);
-
- /* Re-enable HPD interrupts */
-- phy_int_mask = hdmi_readb(HDMI_PHY_MASK0);
-- phy_int_mask &= ~HDMI_PHY_HPD;
-- hdmi_writeb(phy_int_mask, HDMI_PHY_MASK0);
-+ hdmi_phy_mask0 = hdmi_readb(HDMI_PHY_MASK0);
-+ hdmi_phy_mask0 &= ~HDMI_DVI_STAT;
-+ hdmi_writeb(hdmi_phy_mask0, HDMI_PHY_MASK0);
-
- /* Unmute interrupts */
-- hdmi_writeb(~HDMI_IH_MUTE_PHY_STAT0_HPD, HDMI_IH_MUTE_PHY_STAT0);
-+ hdmi_writeb(~HDMI_DVI_IH_STAT, HDMI_IH_MUTE_PHY_STAT0);
-
- if (hdmi_readb(HDMI_IH_FC_STAT2) & HDMI_IH_FC_STAT2_OVERFLOW_MASK)
- mxc_hdmi_clear_overflow();
-@@ -2086,7 +2075,7 @@ static void hdcp_hdp_worker(struct work_struct *work)
- static irqreturn_t mxc_hdmi_hotplug(int irq, void *data)
- {
- struct mxc_hdmi *hdmi = data;
-- u8 val, intr_stat;
-+ u8 val;
- unsigned long flags;
-
- spin_lock_irqsave(&hdmi->irq_lock, flags);
-@@ -2108,25 +2097,22 @@ static irqreturn_t mxc_hdmi_hotplug(int irq, void *data)
- * HDMI registers.
- */
- /* Capture status - used in hotplug_worker ISR */
-- intr_stat = hdmi_readb(HDMI_IH_PHY_STAT0);
--
-- if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
-+ if (hdmi_readb(HDMI_IH_PHY_STAT0) & HDMI_DVI_IH_STAT) {
-
- dev_dbg(&hdmi->pdev->dev, "Hotplug interrupt received\n");
-- hdmi->latest_intr_stat = intr_stat;
-
- /* Mute interrupts until handled */
-
- val = hdmi_readb(HDMI_IH_MUTE_PHY_STAT0);
-- val |= HDMI_IH_MUTE_PHY_STAT0_HPD;
-+ val |= HDMI_DVI_IH_STAT;
- hdmi_writeb(val, HDMI_IH_MUTE_PHY_STAT0);
-
- val = hdmi_readb(HDMI_PHY_MASK0);
-- val |= HDMI_PHY_HPD;
-+ val |= HDMI_DVI_STAT;
- hdmi_writeb(val, HDMI_PHY_MASK0);
-
- /* Clear Hotplug interrupts */
-- hdmi_writeb(HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0);
-+ hdmi_writeb(HDMI_DVI_IH_STAT, HDMI_IH_PHY_STAT0);
-
- schedule_delayed_work(&(hdmi->hotplug_work), msecs_to_jiffies(20));
- }
-@@ -2282,13 +2268,13 @@ static void mxc_hdmi_fb_registered(struct mxc_hdmi *hdmi)
- HDMI_PHY_I2CM_CTLINT_ADDR);
-
- /* enable cable hot plug irq */
-- hdmi_writeb((u8)~HDMI_PHY_HPD, HDMI_PHY_MASK0);
-+ hdmi_writeb((u8)~HDMI_DVI_STAT, HDMI_PHY_MASK0);
-
- /* Clear Hotplug interrupts */
-- hdmi_writeb(HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0);
-+ hdmi_writeb(HDMI_DVI_IH_STAT, HDMI_IH_PHY_STAT0);
-
- /* Unmute interrupts */
-- hdmi_writeb(~HDMI_IH_MUTE_PHY_STAT0_HPD, HDMI_IH_MUTE_PHY_STAT0);
-+ hdmi_writeb(~HDMI_DVI_IH_STAT, HDMI_IH_MUTE_PHY_STAT0);
-
- hdmi->fb_reg = true;
-
-@@ -2522,10 +2508,10 @@ static int mxc_hdmi_disp_init(struct mxc_dispdrv_handle *disp,
-
- /* Configure registers related to HDMI interrupt
- * generation before registering IRQ. */
-- hdmi_writeb(HDMI_PHY_HPD, HDMI_PHY_POL0);
-+ hdmi_writeb(HDMI_DVI_STAT, HDMI_PHY_POL0);
-
- /* Clear Hotplug interrupts */
-- hdmi_writeb(HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0);
-+ hdmi_writeb(HDMI_DVI_IH_STAT, HDMI_IH_PHY_STAT0);
-
- hdmi->nb.notifier_call = mxc_hdmi_fb_event;
- ret = fb_register_client(&hdmi->nb);
---
-1.8.4.rc3
-
diff --git a/recipes-kernel/linux/linux-congatec-3.0.35/ENGR00278350-gpu-viante-4.6.9p13-kernel-part-integra.patch b/recipes-kernel/linux/linux-congatec-3.0.35/ENGR00278350-gpu-viante-4.6.9p13-kernel-part-integra.patch
deleted file mode 100644
index 1e039fd..0000000
--- a/recipes-kernel/linux/linux-congatec-3.0.35/ENGR00278350-gpu-viante-4.6.9p13-kernel-part-integra.patch
+++ /dev/null
@@ -1,6261 +0,0 @@
-From 2e575255b8c53d3cfe2af068411696fe3c40debb Mon Sep 17 00:00:00 2001
-From: Loren Huang <b02279 at freescale.com>
-Date: Mon, 2 Sep 2013 12:16:48 +0800
-Subject: [PATCH 01/16] ENGR00278350 gpu:viante 4.6.9p13 kernel part
- integration
-
-Integrated 4.6.9p13 kernel part change.
-This integration is mainly for android test.
-Linux test will be focused on 3.10 kernel.
-
-Signed-off-by: Loren HUANG <b02279 at freescale.com>
-Acked-by: Shawn Guo
----
- drivers/mxc/gpu-viv/Kbuild | 33 +-
- .../GC350/hal/kernel/gc_hal_kernel_hardware_vg.c | 177 ++--
- .../GC350/hal/kernel/gc_hal_kernel_hardware_vg.h | 9 +-
- .../arch/XAQ2/hal/kernel/gc_hal_kernel_context.c | 8 +-
- .../arch/XAQ2/hal/kernel/gc_hal_kernel_context.h | 13 +
- .../arch/XAQ2/hal/kernel/gc_hal_kernel_hardware.c | 736 ++++++++++++-
- .../arch/XAQ2/hal/kernel/gc_hal_kernel_hardware.h | 1 +
- drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel.c | 125 ++-
- drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel.h | 24 +-
- .../mxc/gpu-viv/hal/kernel/gc_hal_kernel_command.c | 57 ++
- .../gpu-viv/hal/kernel/gc_hal_kernel_command_vg.c | 45 +-
- drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_db.c | 12 +
- .../mxc/gpu-viv/hal/kernel/gc_hal_kernel_event.c | 29 +
- .../hal/kernel/gc_hal_kernel_interrupt_vg.c | 3 +
- drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_mmu.c | 8 +-
- .../hal/kernel/gc_hal_kernel_video_memory.c | 20 +-
- drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal.h | 84 +-
- drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_base.h | 172 +++-
- .../mxc/gpu-viv/hal/kernel/inc/gc_hal_compiler.h | 142 ++-
- drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_driver.h | 37 +
- drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_engine.h | 46 +-
- drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_enum.h | 125 ++-
- .../mxc/gpu-viv/hal/kernel/inc/gc_hal_options.h | 86 +-
- .../mxc/gpu-viv/hal/kernel/inc/gc_hal_profiler.h | 1078 +++-----------------
- drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_raster.h | 48 +
- drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_types.h | 79 +-
- .../mxc/gpu-viv/hal/kernel/inc/gc_hal_version.h | 2 +-
- .../hal/os/linux/kernel/gc_hal_kernel_device.c | 17 +-
- .../hal/os/linux/kernel/gc_hal_kernel_device.h | 16 +-
- .../hal/os/linux/kernel/gc_hal_kernel_driver.c | 99 +-
- .../gpu-viv/hal/os/linux/kernel/gc_hal_kernel_os.c | 655 ++++++++++--
- .../hal/os/linux/kernel/gc_hal_kernel_sync.c | 174 ++++
- .../hal/os/linux/kernel/gc_hal_kernel_sync.h | 71 ++
- 33 files changed, 2974 insertions(+), 1257 deletions(-)
- create mode 100644 drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_sync.c
- create mode 100644 drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_sync.h
-
-diff --git a/drivers/mxc/gpu-viv/Kbuild b/drivers/mxc/gpu-viv/Kbuild
-index 93b1259..2b277d6 100644
---- a/drivers/mxc/gpu-viv/Kbuild
-+++ b/drivers/mxc/gpu-viv/Kbuild
-@@ -45,8 +45,6 @@ OBJS := $(OS_KERNEL_DIR)/gc_hal_kernel_device.o \
- $(OS_KERNEL_DIR)/gc_hal_kernel_os.o \
- $(OS_KERNEL_DIR)/gc_hal_kernel_debugfs.o
-
--ifeq ($(USE_3D_VG), 1)
--
- OBJS += $(HAL_KERNEL_DIR)/gc_hal_kernel.o \
- $(HAL_KERNEL_DIR)/gc_hal_kernel_command.o \
- $(HAL_KERNEL_DIR)/gc_hal_kernel_db.o \
-@@ -69,19 +67,9 @@ OBJS +=\
- $(ARCH_VG_KERNEL_DIR)/gc_hal_kernel_hardware_command_vg.o\
- $(ARCH_VG_KERNEL_DIR)/gc_hal_kernel_hardware_vg.o
- endif
--else
--
--OBJS += $(HAL_KERNEL_DIR)/gc_hal_kernel.o \
-- $(HAL_KERNEL_DIR)/gc_hal_kernel_command.o \
-- $(HAL_KERNEL_DIR)/gc_hal_kernel_heap.o \
-- $(HAL_KERNEL_DIR)/gc_hal_kernel_interrupt.o \
-- $(HAL_KERNEL_DIR)/gc_hal_kernel_mmu.o \
-- $(HAL_KERNEL_DIR)/gc_hal_kernel_video_memory.o \
-- $(OS_KERNEL_DIR)/gc_hal_kernel_debug.o
--
--OBJS += $(ARCH_KERNEL_DIR)/gc_hal_kernel_hardware.o \
-- $(ARCH_KERNEL_DIR)/gc_hal_kernel_hardware_command.o
-
-+ifneq ($(CONFIG_SYNC),)
-+OBJS += $(OS_KERNEL_DIR)/gc_hal_kernel_sync.o
- endif
-
- ifeq ($(KERNELRELEASE), )
-@@ -129,23 +117,16 @@ ifeq ($(CONFIG_DOVE_GPU), 1)
- EXTRA_CFLAGS += -DCONFIG_DOVE_GPU=1
- endif
-
--ifeq ($(USE_POWER_MANAGEMENT), 1)
--EXTRA_CFLAGS += -DgcdPOWER_MANAGEMENT=1
--else
--EXTRA_CFLAGS += -DgcdPOWER_MANAGEMENT=0
--endif
--
- ifneq ($(USE_PLATFORM_DRIVER), 0)
- EXTRA_CFLAGS += -DUSE_PLATFORM_DRIVER=1
- else
- EXTRA_CFLAGS += -DUSE_PLATFORM_DRIVER=0
- endif
-
--ifeq ($(USE_PROFILER), 1)
-+
- EXTRA_CFLAGS += -DVIVANTE_PROFILER=1
--else
--EXTRA_CFLAGS += -DVIVANTE_PROFILER=0
--endif
-+EXTRA_CFLAGS += -DVIVANTE_PROFILER_CONTEXT=1
-+
-
- ifeq ($(ANDROID), 1)
- EXTRA_CFLAGS += -DANDROID=1
-@@ -235,6 +216,10 @@ ifeq ($(USE_BANK_ALIGNMENT), 1)
- endif
- endif
-
-+ifneq ($(CONFIG_SYNC),)
-+EXTRA_CFLAGS += -DgcdANDROID_NATIVE_FENCE_SYNC=1
-+endif
-+
- EXTRA_CFLAGS += -I$(AQROOT)/hal/kernel/inc
- EXTRA_CFLAGS += -I$(AQROOT)/hal/kernel
- EXTRA_CFLAGS += -I$(AQARCH)/hal/kernel
-diff --git a/drivers/mxc/gpu-viv/arch/GC350/hal/kernel/gc_hal_kernel_hardware_vg.c b/drivers/mxc/gpu-viv/arch/GC350/hal/kernel/gc_hal_kernel_hardware_vg.c
-index 70c2cd6..a17d2fd 100644
---- a/drivers/mxc/gpu-viv/arch/GC350/hal/kernel/gc_hal_kernel_hardware_vg.c
-+++ b/drivers/mxc/gpu-viv/arch/GC350/hal/kernel/gc_hal_kernel_hardware_vg.c
-@@ -217,50 +217,17 @@ _IdentifyHardware(
- return status;
- }
-
--static gctTHREADFUNCRESULT gctTHREADFUNCTYPE
--_TimeIdleThread(
-- gctTHREADFUNCPARAMETER ThreadParameter
-+#if gcdPOWEROFF_TIMEOUT
-+void
-+_VGPowerTimerFunction(
-+ gctPOINTER Data
- )
- {
-- gctUINT32 currentTime = 0;
-- gctBOOL isAfter = gcvFALSE;
-- gceCHIPPOWERSTATE state;
--
-- /* Cast the object. */
-- gckVGHARDWARE hardware = (gckVGHARDWARE) ThreadParameter;
--
-- while(gcvTRUE)
-- {
-- gcmkVERIFY_OK(gckOS_WaitSignal(hardware->os,
-- hardware->idleSignal, gcvINFINITE));
--
-- if (hardware->killThread)
-- {
-- break;
-- }
--
-- do
-- {
-- gcmkVERIFY_OK(gckOS_GetTicks(¤tTime));
--
-- gcmkVERIFY_OK(
-- gckOS_TicksAfter(currentTime, hardware->powerOffTime, &isAfter));
--
-- if (isAfter)
-- {
-- gcmkVERIFY_OK(gckVGHARDWARE_SetPowerManagementState(
-- hardware, gcvPOWER_OFF_BROADCAST));
-- }
--
-- gcmkVERIFY_OK(gckOS_Delay(hardware->os, 200));
--
-- gcmkVERIFY_OK(gckVGHARDWARE_QueryPowerManagementState(
-- hardware, &state));
--
-- } while (state == gcvPOWER_IDLE);
-- }
-- return 0;
-+ gckVGHARDWARE hardware = (gckVGHARDWARE)Data;
-+ gcmkVERIFY_OK(
-+ gckVGHARDWARE_SetPowerManagementState(hardware, gcvPOWER_OFF_TIMEOUT));
- }
-+#endif
-
- /******************************************************************************\
- ****************************** gckVGHARDWARE API code *****************************
-@@ -338,15 +305,21 @@ gckVGHARDWARE_Construct(
- hardware->chipMinorFeatures2 = chipMinorFeatures2;
-
- hardware->powerMutex = gcvNULL;
-- hardware->idleSignal = gcvNULL;
- hardware->chipPowerState = gcvPOWER_ON;
- hardware->chipPowerStateGlobal = gcvPOWER_ON;
- hardware->clockState = gcvTRUE;
- hardware->powerState = gcvTRUE;
-- hardware->powerOffTimeout = gcdPOWEROFF_TIMEOUT;
-+
- hardware->powerOffTime = 0;
-- hardware->timeIdleThread = gcvNULL;
-- hardware->killThread = gcvFALSE;
-+#if gcdPOWEROFF_TIMEOUT
-+ hardware->powerOffTimeout = gcdPOWEROFF_TIMEOUT;
-+
-+ gcmkVERIFY_OK(gckOS_CreateTimer(Os,
-+ _VGPowerTimerFunction,
-+ (gctPOINTER)hardware,
-+ &hardware->powerOffTimer));
-+#endif
-+
- /* Determine whether FE 2.0 is present. */
- hardware->fe20 = ((((gctUINT32) (hardware->chipFeatures)) >> (0 ? 28:28) & ((gctUINT32) ((((1 ? 28:28) - (0 ? 28:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 28:28) - (0 ? 28:28) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 28:28) - (0 ? 28:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 28:28) - (0 ? 28:28) + 1)))))));
-
-@@ -365,18 +338,10 @@ gckVGHARDWARE_Construct(
- gcmkVERIFY_OK(gckVGHARDWARE_SetFastClear(hardware, -1));
-
- gcmkERR_BREAK(gckOS_CreateMutex(Os, &hardware->powerMutex));
-- gcmkERR_BREAK(gckOS_CreateSignal(Os, gcvFALSE, &hardware->idleSignal));
-
- /* Enable power management by default. */
- hardware->powerManagement = gcvTRUE;
-
-- gcmkERR_BREAK(gckOS_StartThread(
-- hardware->os,
-- _TimeIdleThread,
-- hardware,
-- &hardware->timeIdleThread
-- ));
--
- /* Return pointer to the gckVGHARDWARE object. */
- *Hardware = hardware;
-
-@@ -386,6 +351,14 @@ gckVGHARDWARE_Construct(
- }
- while (gcvFALSE);
-
-+#if gcdPOWEROFF_TIMEOUT
-+ if (hardware->powerOffTimer != gcvNULL)
-+ {
-+ gcmkVERIFY_OK(gckOS_StopTimer(Os, hardware->powerOffTimer));
-+ gcmkVERIFY_OK(gckOS_DestroyTimer(Os, hardware->powerOffTimer));
-+ }
-+#endif
-+
- if (hardware->pageTableDirty != gcvNULL)
- {
- gcmkVERIFY_OK(gckOS_AtomDestroy(Os, hardware->pageTableDirty));
-@@ -428,10 +401,6 @@ gckVGHARDWARE_Destroy(
- /* Verify the arguments. */
- gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
-
-- Hardware->killThread = gcvTRUE;
-- gcmkVERIFY_OK(gckOS_Signal(Hardware->os, Hardware->idleSignal, gcvTRUE));
-- gcmkVERIFY_OK(gckOS_StopThread(Hardware->os, Hardware->timeIdleThread));
--
- /* Mark the object as unknown. */
- Hardware->object.type = gcvOBJ_UNKNOWN;
-
-@@ -441,11 +410,10 @@ gckVGHARDWARE_Destroy(
- Hardware->os, Hardware->powerMutex));
- }
-
-- if (Hardware->idleSignal != gcvNULL)
-- {
-- gcmkVERIFY_OK(gckOS_DestroySignal(
-- Hardware->os, Hardware->idleSignal));
-- }
-+#if gcdPOWEROFF_TIMEOUT
-+ gcmkVERIFY_OK(gckOS_StopTimer(Hardware->os, Hardware->powerOffTimer));
-+ gcmkVERIFY_OK(gckOS_DestroyTimer(Hardware->os, Hardware->powerOffTimer));
-+#endif
-
- if (Hardware->pageTableDirty != gcvNULL)
- {
-@@ -1510,11 +1478,15 @@ gckVGHARDWARE_SetPowerManagementState(
- gctBOOL commitMutex = gcvFALSE;
- gctBOOL mutexAcquired = gcvFALSE;
-
-+#if gcdPOWEROFF_TIMEOUT
-+ gctBOOL timeout = gcvFALSE;
-+ gctBOOL isAfter = gcvFALSE;
-+ gctUINT32 currentTime;
-+#endif
-+
- gctBOOL broadcast = gcvFALSE;
- gctUINT32 process, thread;
- gctBOOL global = gcvFALSE;
-- gctUINT32 currentTime;
--
-
- #if gcdENABLE_PROFILING
- gctUINT64 time, freq, mutexTime, onTime, stallTime, stopTime, delayTime,
-@@ -1661,6 +1633,16 @@ gckVGHARDWARE_SetPowerManagementState(
- global = gcvTRUE;
- break;
-
-+#if gcdPOWEROFF_TIMEOUT
-+ case gcvPOWER_OFF_TIMEOUT:
-+ /* Convert to OFF and note we are inside broadcast. */
-+ State = gcvPOWER_OFF;
-+ broadcast = gcvTRUE;
-+ /* Check time out */
-+ timeout = gcvTRUE;
-+ break;
-+#endif
-+
- default:
- break;
- }
-@@ -1719,6 +1701,31 @@ gckVGHARDWARE_SetPowerManagementState(
- flag = flags[Hardware->chipPowerState][State];
- /*clock = clocks[State];*/
-
-+#if gcdPOWEROFF_TIMEOUT
-+ if (timeout)
-+ {
-+ gcmkONERROR(gckOS_GetTicks(¤tTime));
-+
-+ gcmkONERROR(
-+ gckOS_TicksAfter(Hardware->powerOffTime, currentTime, &isAfter));
-+
-+ /* powerOffTime is pushed forward, give up.*/
-+ if (isAfter
-+ /* Expect a transition start from IDLE. */
-+ || (Hardware->chipPowerState == gcvPOWER_ON)
-+ || (Hardware->chipPowerState == gcvPOWER_OFF)
-+ )
-+ {
-+ /* Release the power mutex. */
-+ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex));
-+
-+ /* No need to do anything. */
-+ gcmkFOOTER_NO();
-+ return gcvSTATUS_OK;
-+ }
-+ }
-+#endif
-+
- if (flag == 0)
- {
- /* Release the power mutex. */
-@@ -1742,6 +1749,18 @@ gckVGHARDWARE_SetPowerManagementState(
- return gcvSTATUS_OK;
- }
- }
-+ else
-+ {
-+ if (flag & gcvPOWER_FLAG_ACQUIRE)
-+ {
-+ /* Acquire the power management semaphore. */
-+ gcmkONERROR(gckOS_AcquireSemaphore(os, command->powerSemaphore));
-+ acquired = gcvTRUE;
-+
-+ /* avoid acquiring again. */
-+ flag &= ~gcvPOWER_FLAG_ACQUIRE;
-+ }
-+ }
-
- if (flag & (gcvPOWER_FLAG_INITIALIZE | gcvPOWER_FLAG_CLOCK_ON))
- {
-@@ -1858,14 +1877,6 @@ gckVGHARDWARE_SetPowerManagementState(
- Hardware->chipPowerStateGlobal = State;
- }
-
-- if (State == gcvPOWER_IDLE)
-- {
-- gcmkVERIFY_OK(gckOS_Signal(os, Hardware->idleSignal, gcvTRUE));
-- }
-- /* Reset power off time */
-- gcmkVERIFY_OK(gckOS_GetTicks(¤tTime));
-- Hardware->powerOffTime = currentTime + Hardware->powerOffTimeout;
--
- if (commitMutex)
- {
- /* Acquire the mutex. */
-@@ -1875,6 +1886,28 @@ gckVGHARDWARE_SetPowerManagementState(
- ));
- }
-
-+#if gcdPOWEROFF_TIMEOUT
-+ /* Reset power off time */
-+ gcmkONERROR(gckOS_GetTicks(¤tTime));
-+
-+ Hardware->powerOffTime = currentTime + Hardware->powerOffTimeout;
-+
-+ if (State == gcvPOWER_IDLE)
-+ {
-+ /* Start a timer to power off GPU when GPU enters IDLE or SUSPEND. */
-+ gcmkVERIFY_OK(gckOS_StartTimer(os,
-+ Hardware->powerOffTimer,
-+ Hardware->powerOffTimeout));
-+ }
-+ else
-+ {
-+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, "Cancel powerOfftimer");
-+
-+ /* Cancel running timer when GPU enters ON or OFF. */
-+ gcmkVERIFY_OK(gckOS_StopTimer(os, Hardware->powerOffTimer));
-+ }
-+#endif
-+
- /* Release the power mutex. */
- gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex));
-
-diff --git a/drivers/mxc/gpu-viv/arch/GC350/hal/kernel/gc_hal_kernel_hardware_vg.h b/drivers/mxc/gpu-viv/arch/GC350/hal/kernel/gc_hal_kernel_hardware_vg.h
-index 16b81ae..73d4594 100644
---- a/drivers/mxc/gpu-viv/arch/GC350/hal/kernel/gc_hal_kernel_hardware_vg.h
-+++ b/drivers/mxc/gpu-viv/arch/GC350/hal/kernel/gc_hal_kernel_hardware_vg.h
-@@ -53,7 +53,6 @@ struct _gckVGHARDWARE
- gctBOOL clockState;
- gctBOOL powerState;
- gctPOINTER powerMutex;
-- gctSIGNAL idleSignal;
- gctUINT32 powerProcess;
- gctUINT32 powerThread;
- gceCHIPPOWERSTATE chipPowerState;
-@@ -61,11 +60,13 @@ struct _gckVGHARDWARE
- gctISRMANAGERFUNC startIsr;
- gctISRMANAGERFUNC stopIsr;
- gctPOINTER isrContext;
-+ gctPOINTER pageTableDirty;
-+
-+#if gcdPOWEROFF_TIMEOUT
- gctUINT32 powerOffTime;
- gctUINT32 powerOffTimeout;
-- gctTHREAD timeIdleThread;
-- gctBOOL killThread;
-- gctPOINTER pageTableDirty;
-+ gctPOINTER powerOffTimer;
-+#endif
-
- gctBOOL powerManagement;
- };
-diff --git a/drivers/mxc/gpu-viv/arch/XAQ2/hal/kernel/gc_hal_kernel_context.c b/drivers/mxc/gpu-viv/arch/XAQ2/hal/kernel/gc_hal_kernel_context.c
-index 24003e7..42e6915 100644
---- a/drivers/mxc/gpu-viv/arch/XAQ2/hal/kernel/gc_hal_kernel_context.c
-+++ b/drivers/mxc/gpu-viv/arch/XAQ2/hal/kernel/gc_hal_kernel_context.c
-@@ -181,7 +181,8 @@ _FlushPipe(
- ? ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3)))
- : ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)))
- | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1)))
-- | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2)));
-+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2)))
-+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4)));
-
- /* Semaphore from FE to PE. */
- *buffer++
-@@ -620,7 +621,10 @@ _InitializeContextBuffer(
- index += _State(Context, index, 0x10180 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE);
- index += _State(Context, index, 0x10200 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE);
- index += _State(Context, index, 0x10280 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE);
-- index += _State(Context, index, 0x02C00 >> 2, 0x00000000, 256, gcvFALSE, gcvFALSE);
-+ for (i = 0; i < 256 / 16; i += 1)
-+ {
-+ index += _State(Context, index, (0x02C00 >> 2) + i * 16, 0x00000000, 14, gcvFALSE, gcvFALSE);
-+ }
- index += _State(Context, index, 0x10300 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE);
- index += _State(Context, index, 0x10380 >> 2, 0x00321000, 32, gcvFALSE, gcvFALSE);
- index += _State(Context, index, 0x10400 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE);
-diff --git a/drivers/mxc/gpu-viv/arch/XAQ2/hal/kernel/gc_hal_kernel_context.h b/drivers/mxc/gpu-viv/arch/XAQ2/hal/kernel/gc_hal_kernel_context.h
-index 7554045..5d2c7c7 100644
---- a/drivers/mxc/gpu-viv/arch/XAQ2/hal/kernel/gc_hal_kernel_context.h
-+++ b/drivers/mxc/gpu-viv/arch/XAQ2/hal/kernel/gc_hal_kernel_context.h
-@@ -134,6 +134,19 @@ struct _gckCONTEXT
- #if gcdSECURE_USER
- gctBOOL_PTR hint;
- #endif
-+
-+#if VIVANTE_PROFILER_CONTEXT
-+ gcsPROFILER_COUNTERS latestProfiler;
-+ gcsPROFILER_COUNTERS histroyProfiler;
-+ gctUINT32 prevVSInstCount;
-+ gctUINT32 prevVSBranchInstCount;
-+ gctUINT32 prevVSTexInstCount;
-+ gctUINT32 prevVSVertexCount;
-+ gctUINT32 prevPSInstCount;
-+ gctUINT32 prevPSBranchInstCount;
-+ gctUINT32 prevPSTexInstCount;
-+ gctUINT32 prevPSPixelCount;
-+#endif
- };
-
- #ifdef __cplusplus
-diff --git a/drivers/mxc/gpu-viv/arch/XAQ2/hal/kernel/gc_hal_kernel_hardware.c b/drivers/mxc/gpu-viv/arch/XAQ2/hal/kernel/gc_hal_kernel_hardware.c
-index 00f3839..e02dc23 100644
---- a/drivers/mxc/gpu-viv/arch/XAQ2/hal/kernel/gc_hal_kernel_hardware.c
-+++ b/drivers/mxc/gpu-viv/arch/XAQ2/hal/kernel/gc_hal_kernel_hardware.c
-@@ -21,6 +21,9 @@
-
- #include "gc_hal.h"
- #include "gc_hal_kernel.h"
-+#if VIVANTE_PROFILER_CONTEXT
-+#include "gc_hal_kernel_context.h"
-+#endif
-
- #define _GC_OBJ_ZONE gcvZONE_HARDWARE
-
-@@ -69,6 +72,7 @@ _IdentifyHardware(
- gctUINT32 numConstants = 0;
- gctUINT32 bufferSize = 0;
- gctUINT32 varyingsCount = 0;
-+ gctBOOL useHZ;
-
- gcmkHEADER_ARG("Os=0x%x", Os);
-
-@@ -209,6 +213,15 @@ _IdentifyHardware(
- 0x00088,
- &Identity->chipMinorFeatures3));
-
-+ /*The BG2 chip has no compression supertiled, and the bit of GCMinorFeature3BugFixes15 is n/a*/
-+ if(Identity->chipModel == gcv1000 && Identity->chipRevision == 0x5036)
-+ {
-+ Identity->chipMinorFeatures3
-+ = ((((gctUINT32) (Identity->chipMinorFeatures3)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5)));
-+ Identity->chipMinorFeatures3
-+ = ((((gctUINT32) (Identity->chipMinorFeatures3)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 27:27) - (0 ? 27:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:27) - (0 ? 27:27) + 1))))))) << (0 ? 27:27))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 27:27) - (0 ? 27:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:27) - (0 ? 27:27) + 1))))))) << (0 ? 27:27)));
-+ }
-+
- /* Read chip minor featuress register #4. */
- gcmkONERROR(
- gckOS_ReadRegisterEx(Os, Core,
-@@ -244,14 +257,31 @@ _IdentifyHardware(
- if (((Identity->chipModel == gcv1000) && ((Identity->chipRevision == 0x5035)
- || (Identity->chipRevision == 0x5036)
- || (Identity->chipRevision == 0x5037)))
-- || ((Identity->chipModel == gcv800) && (Identity->chipRevision == 0x4612)))
-+ || ((Identity->chipModel == gcv800) && (Identity->chipRevision == 0x4612))
-+ || ((Identity->chipModel == gcv860) && (Identity->chipRevision == 0x4647)))
- {
- Identity->superTileMode = 1;
- }
-
-+ if (Identity->chipModel == gcv4000 && Identity->chipRevision == 0x5245)
-+ {
-+ useHZ = ((((gctUINT32) (Identity->chipMinorFeatures3)) >> (0 ? 26:26) & ((gctUINT32) ((((1 ? 26:26) - (0 ? 26:26) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:26) - (0 ? 26:26) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 26:26) - (0 ? 26:26) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:26) - (0 ? 26:26) + 1)))))))
-+ || ((((gctUINT32) (Identity->chipMinorFeatures3)) >> (0 ? 8:8) & ((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1)))))));
-+ }
-+ else
-+ {
-+ useHZ = gcvFALSE;
-+ }
-
-- /* Disable HZ when EZ is present for older chips. */
-- if (!((((gctUINT32) (Identity->chipFeatures)) >> (0 ? 16:16) & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))))
-+ if (useHZ)
-+ {
-+ /* Disable EZ. */
-+ Identity->chipFeatures
-+ = ((((gctUINT32) (Identity->chipFeatures)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16)));
-+ }
-+
-+ /* Disable HZ when EZ is present for older chips. */
-+ else if (!((((gctUINT32) (Identity->chipFeatures)) >> (0 ? 16:16) & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))))
- {
- /* Disable HIERARCHICAL_Z. */
- Identity->chipMinorFeatures
-@@ -470,6 +500,15 @@ _IdentifyHardware(
- Identity->varyingsCount = 8;
- }
-
-+ /* For some cores, it consumes two varying for position, so the max varying vectors should minus one. */
-+ if ((Identity->chipModel == gcv4000 && Identity->chipRevision == 0x5222) ||
-+ (Identity->chipModel == gcv4000 && Identity->chipRevision == 0x5208) ||
-+ ((Identity->chipModel == gcv2100 || Identity->chipModel == gcv2000) && Identity->chipRevision == 0x5108) ||
-+ (Identity->chipModel == gcv880 && (Identity->chipRevision == 0x5107 || Identity->chipRevision == 0x5106)))
-+ {
-+ Identity->varyingsCount -= 1;
-+ }
-+
- /* Success. */
- gcmkFOOTER();
- return gcvSTATUS_OK;
-@@ -535,9 +574,9 @@ _DumpDebugRegisters(
- IN gcsiDEBUG_REGISTERS_PTR Descriptor
- )
- {
-- gceSTATUS status;
-+ gceSTATUS status = gcvSTATUS_OK;
- gctUINT32 select;
-- gctUINT32 data;
-+ gctUINT32 data = 0;
- gctUINT i;
-
- gcmkHEADER_ARG("Os=0x%X Descriptor=0x%X", Os, Descriptor);
-@@ -643,6 +682,42 @@ OnError:
- return status;
- }
-
-+gceSTATUS
-+_FlushCache(
-+ gckHARDWARE Hardware,
-+ gckCOMMAND Command
-+ )
-+{
-+ gceSTATUS status;
-+ gctSIZE_T bytes, requested;
-+ gctPOINTER buffer;
-+
-+ /* Get the size of the flush command. */
-+ gcmkONERROR(gckHARDWARE_Flush(Hardware,
-+ gcvFLUSH_ALL,
-+ gcvNULL,
-+ &requested));
-+
-+ /* Reserve space in the command queue. */
-+ gcmkONERROR(gckCOMMAND_Reserve(Command,
-+ requested,
-+ &buffer,
-+ &bytes));
-+
-+ /* Append a flush. */
-+ gcmkONERROR(gckHARDWARE_Flush(
-+ Hardware, gcvFLUSH_ALL, buffer, &bytes
-+ ));
-+
-+ /* Execute the command queue. */
-+ gcmkONERROR(gckCOMMAND_Execute(Command, requested));
-+
-+ return gcvSTATUS_OK;
-+
-+OnError:
-+ return status;
-+}
-+
- /******************************************************************************\
- ****************************** gckHARDWARE API code *****************************
- \******************************************************************************/
-@@ -809,6 +884,9 @@ gckHARDWARE_Construct(
- /* Enable power management by default. */
- hardware->powerManagement = gcvTRUE;
-
-+ /* Disable profiler by default */
-+ hardware->gpuProfiler = gcvFALSE;
-+
- /* Return pointer to the gckHARDWARE object. */
- *Hardware = hardware;
-
-@@ -1113,6 +1191,31 @@ gckHARDWARE_InitializeHardware(
- ((((gctUINT32) (0x01590880)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:23) - (0 ? 23:23) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:23) - (0 ? 23:23) + 1))))))) << (0 ? 23:23))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 23:23) - (0 ? 23:23) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:23) - (0 ? 23:23) + 1))))))) << (0 ? 23:23)))));
- }
-
-+ if ((gckHARDWARE_IsFeatureAvailable(Hardware, gcvFEATURE_HALTI2) == gcvFALSE)
-+ || (gckHARDWARE_IsFeatureAvailable(Hardware, gcvFEATURE_HALTI2) && (Hardware->identity.chipRevision < 0x5422))
-+ )
-+ {
-+ gctUINT32 data;
-+
-+ gcmkONERROR(
-+ gckOS_ReadRegisterEx(Hardware->os,
-+ Hardware->core,
-+ Hardware->powerBaseAddress
-+ + 0x00104,
-+ &data));
-+
-+
-+ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:15) - (0 ? 15:15) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:15) - (0 ? 15:15) + 1))))))) << (0 ? 15:15))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 15:15) - (0 ? 15:15) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:15) - (0 ? 15:15) + 1))))))) << (0 ? 15:15)));
-+
-+
-+ gcmkONERROR(
-+ gckOS_WriteRegisterEx(Hardware->os,
-+ Hardware->core,
-+ Hardware->powerBaseAddress
-+ + 0x00104,
-+ data));
-+ }
-+
- /* Special workaround for this core
- ** Make sure FE and TX are on different buses */
- if ((Hardware->identity.chipModel == gcv2000)
-@@ -1152,7 +1255,9 @@ gckHARDWARE_InitializeHardware(
- }
-
- if (Hardware->identity.chipModel >= gcv400
-- && Hardware->identity.chipModel != gcv420)
-+ && Hardware->identity.chipModel != gcv420
-+ && (((((gctUINT32) (Hardware->identity.chipMinorFeatures3)) >> (0 ? 15:15) & ((gctUINT32) ((((1 ? 15:15) - (0 ? 15:15) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:15) - (0 ? 15:15) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 15:15) - (0 ? 15:15) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:15) - (0 ? 15:15) + 1))))))) != gcvTRUE)
-+ )
- {
- gctUINT32 data;
-
-@@ -2883,35 +2988,44 @@ gckHARDWARE_QueryShaderCaps(
- OUT gctUINT * Varyings
- )
- {
-+ gctUINT32 vsConstMax;
-+ gctUINT32 psConstMax;
-+
- gcmkHEADER_ARG("Hardware=0x%x VertexUniforms=0x%x "
- "FragmentUniforms=0x%x Varyings=0x%x",
- Hardware, VertexUniforms,
- FragmentUniforms, Varyings);
-
-+ if ((Hardware->identity.chipModel == gcv2000)
-+ && (Hardware->identity.chipRevision == 0x5118))
-+ {
-+ vsConstMax = 256;
-+ psConstMax = 64;
-+ }
-+ else if (Hardware->identity.numConstants > 256)
-+ {
-+ vsConstMax = 256;
-+ psConstMax = 256;
-+ }
-+ else if (Hardware->identity.numConstants == 256)
-+ {
-+ vsConstMax = 256;
-+ psConstMax = 256;
-+ }
-+ else
-+ {
-+ vsConstMax = 168;
-+ psConstMax = 64;
-+ }
-+
- if (VertexUniforms != gcvNULL)
- {
-- /* Return the vs shader const count. */
-- if (Hardware->identity.chipModel < gcv4000)
-- {
-- *VertexUniforms = 168;
-- }
-- else
-- {
-- *VertexUniforms = 256;
-- }
-+ *VertexUniforms = vsConstMax;
- }
-
- if (FragmentUniforms != gcvNULL)
- {
-- /* Return the ps shader const count. */
-- if (Hardware->identity.chipModel < gcv4000)
-- {
-- *FragmentUniforms = 64;
-- }
-- else
-- {
-- *FragmentUniforms = 256;
-- }
-+ *FragmentUniforms = psConstMax;
- }
-
- if (Varyings != gcvNULL)
-@@ -3229,12 +3343,28 @@ gckHARDWARE_SetMMUv2(
- gctBOOL commitEntered = gcvFALSE;
- gctPOINTER pointer = gcvNULL;
- gctBOOL acquired = gcvFALSE;
-+ gctBOOL config2D;
-+ gctSIZE_T configSize;
-
- gcmkHEADER_ARG("Hardware=0x%x Enable=%d", Hardware, Enable);
-
- /* Verify the arguments. */
- gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
-
-+ config2D = gckHARDWARE_IsFeatureAvailable(Hardware, gcvFEATURE_PIPE_3D)
-+ && gckHARDWARE_IsFeatureAvailable(Hardware, gcvFEATURE_PIPE_2D);
-+
-+ configSize = 4 * 4;
-+
-+ if (config2D)
-+ {
-+ configSize +=
-+ /* Pipe Select. */
-+ 4 * 4
-+ /* Configure MMU States. */
-+ + 4 * 4;
-+ }
-+
- /* Convert logical address into physical address. */
- gcmkONERROR(
- gckOS_GetPhysicalAddress(Hardware->os, MtlbAddress, &config));
-@@ -3281,7 +3411,7 @@ gckHARDWARE_SetMMUv2(
- commitEntered = gcvTRUE;
-
- gcmkONERROR(gckCOMMAND_Reserve(
-- command, 16, &pointer, &bufferSize
-+ command, configSize, &pointer, &bufferSize
- ));
-
- buffer = pointer;
-@@ -3300,10 +3430,43 @@ gckHARDWARE_SetMMUv2(
-
- buffer[3] = address;
-
-+ if (config2D)
-+ {
-+ /* LoadState(AQPipeSelect, 1), pipe. */
-+ buffer[4]
-+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
-+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E00) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
-+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
-+
-+ buffer[5] = 0x1;
-+
-+ buffer[6]
-+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
-+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0061) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
-+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
-+
-+ buffer[7] = config;
-+
-+ buffer[8]
-+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
-+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0060) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
-+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
-+
-+ buffer[9] = address;
-+
-+ /* LoadState(AQPipeSelect, 1), pipe. */
-+ buffer[10]
-+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
-+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E00) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
-+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
-+
-+ buffer[11] = 0x0;
-+ }
-+
- gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
- "Setup MMU: config=%08x, Safe Address=%08x\n.", config, address);
-
-- gcmkONERROR(gckCOMMAND_Execute(command, 16));
-+ gcmkONERROR(gckCOMMAND_Execute(command, configSize));
-
- if (FromPower == gcvFALSE)
- {
-@@ -3501,6 +3664,8 @@ gckHARDWARE_Flush(
- gctUINT32 flush = 0;
- gctUINT32_PTR logical = (gctUINT32_PTR) Logical;
- gceSTATUS status;
-+ gctBOOL fcFlushStall;
-+ gctUINT32 reserveBytes = 8;
-
- gcmkHEADER_ARG("Hardware=0x%x Flush=0x%x Logical=0x%x *Bytes=%lu",
- Hardware, Flush, Logical, gcmOPT_VALUE(Bytes));
-@@ -3511,6 +3676,16 @@ gckHARDWARE_Flush(
- /* Get current pipe. */
- pipe = Hardware->kernel->command->pipeSelect;
-
-+ fcFlushStall
-+ = ((((gctUINT32) (Hardware->identity.chipMinorFeatures1)) >> (0 ? 31:31) & ((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1)))))))
-+ && (Flush == gcvFLUSH_ALL)
-+ ;
-+
-+ if (fcFlushStall)
-+ {
-+ reserveBytes += 8;
-+ }
-+
- /* Flush 3D color cache. */
- if ((Flush & gcvFLUSH_COLOR) && (pipe == 0x0))
- {
-@@ -3527,6 +3702,7 @@ gckHARDWARE_Flush(
- if ((Flush & gcvFLUSH_TEXTURE) && (pipe == 0x0))
- {
- flush |= ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2)));
-+ flush |= ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4)));
- }
-
- /* Flush 2D cache. */
-@@ -3550,7 +3726,7 @@ gckHARDWARE_Flush(
- /* Copy to command queue. */
- if (Logical != gcvNULL)
- {
-- if (*Bytes < 8)
-+ if (*Bytes < reserveBytes)
- {
- /* Command queue too small. */
- gcmkONERROR(gcvSTATUS_BUFFER_TOO_SMALL);
-@@ -3565,12 +3741,26 @@ gckHARDWARE_Flush(
-
- gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
- "0x%x: FLUSH 0x%x", logical, flush);
-+
-+ if (fcFlushStall)
-+ {
-+ logical[2] = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
-+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0594) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
-+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
-+
-+ logical[3] = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
-+
-+
-+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
-+ "0x%x: FLUSH 0x%x", logical + 3, logical[3]);
-+ }
-+
- }
-
- if (Bytes != gcvNULL)
- {
-- /* 8 bytes required. */
-- *Bytes = 8;
-+ /* bytes required. */
-+ *Bytes = reserveBytes;
- }
- }
-
-@@ -4285,6 +4475,48 @@ gckHARDWARE_SetPowerManagementState(
- }
- }
-
-+ /* Flush Cache before Power Off. */
-+ if (flag & gcvPOWER_FLAG_POWER_OFF)
-+ {
-+ if (Hardware->clockState == gcvFALSE)
-+ {
-+ /* Turn off the GPU power. */
-+ gcmkONERROR(
-+ gckOS_SetGPUPower(os,
-+ Hardware->core,
-+ gcvTRUE,
-+ gcvTRUE));
-+
-+ Hardware->clockState = gcvTRUE;
-+
-+ if (gckHARDWARE_IsFeatureAvailable(Hardware, gcvFEATURE_DYNAMIC_FREQUENCY_SCALING) != gcvTRUE)
-+ {
-+ /* Write the clock control register. */
-+ gcmkONERROR(gckOS_WriteRegisterEx(os,
-+ Hardware->core,
-+ 0x00000,
-+ clocks[0]));
-+
-+ /* Done loading the frequency scaler. */
-+ gcmkONERROR(gckOS_WriteRegisterEx(os,
-+ Hardware->core,
-+ 0x00000,
-+ ((((gctUINT32) (clocks[0])) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9)))));
-+ }
-+ }
-+
-+ gcmkONERROR(gckCOMMAND_Start(command));
-+
-+ gcmkONERROR(_FlushCache(Hardware, command));
-+
-+ gckOS_Delay(gcvNULL, 1);
-+
-+ /* Stop the command parser. */
-+ gcmkONERROR(gckCOMMAND_Stop(command, gcvFALSE));
-+
-+ flag |= gcvPOWER_FLAG_CLOCK_OFF;
-+ }
-+
- /* Get time until stopped. */
- gcmkPROFILE_QUERY(time, stopTime);
-
-@@ -4582,6 +4814,40 @@ gckHARDWARE_SetPowerManagement(
- return gcvSTATUS_OK;
- }
-
-+/*******************************************************************************
-+**
-+** gckHARDWARE_SetGpuProfiler
-+**
-+** Configure GPU profiler function.
-+** Only used in driver initialization stage.
-+**
-+** INPUT:
-+**
-+** gckHARDWARE Harwdare
-+** Pointer to an gckHARDWARE object.
-+**
-+** gctBOOL GpuProfiler
-+** GOU Profiler State.
-+**
-+*/
-+gceSTATUS
-+gckHARDWARE_SetGpuProfiler(
-+ IN gckHARDWARE Hardware,
-+ IN gctBOOL GpuProfiler
-+ )
-+{
-+ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
-+
-+ /* Verify the arguments. */
-+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
-+
-+ Hardware->gpuProfiler = GpuProfiler;
-+
-+ /* Success. */
-+ gcmkFOOTER_NO();
-+ return gcvSTATUS_OK;
-+}
-+
- #if gcdENABLE_FSCALE_VAL_ADJUST
- gceSTATUS
- gckHARDWARE_SetFscaleValue(
-@@ -5141,6 +5407,402 @@ OnError:
- }
- #endif
-
-+#if VIVANTE_PROFILER_CONTEXT
-+#define gcmkUPDATE_PROFILE_DATA(data) \
-+ profilerHistroy->data += profiler->data
-+
-+gceSTATUS
-+gckHARDWARE_QueryContextProfile(
-+ IN gckHARDWARE Hardware,
-+ IN gctBOOL Reset,
-+ IN gckCONTEXT Context,
-+ OUT gcsPROFILER_COUNTERS * Counters
-+ )
-+{
-+ gceSTATUS status;
-+ gckCOMMAND command = Hardware->kernel->command;
-+ gcsPROFILER_COUNTERS * profiler = Counters;
-+
-+ gcmkHEADER_ARG("Hardware=0x%x Counters=0x%x", Hardware, Counters);
-+
-+ /* Verify the arguments. */
-+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
-+
-+ /* Acquire the context sequnence mutex. */
-+ gcmkONERROR(gckOS_AcquireMutex(
-+ command->os, command->mutexContextSeq, gcvINFINITE
-+ ));
-+
-+ /* Read the counters. */
-+ gcmkVERIFY_OK(gckOS_MemCopy(
-+ profiler, &Context->histroyProfiler, gcmSIZEOF(gcsPROFILER_COUNTERS)
-+ ));
-+
-+ if (Reset)
-+ {
-+ /* Reset counters. */
-+ gcmkVERIFY_OK(gckOS_ZeroMemory(
-+ &Context->histroyProfiler, gcmSIZEOF(gcsPROFILER_COUNTERS)
-+ ));
-+ }
-+
-+ gcmkVERIFY_OK(gckOS_ReleaseMutex(
-+ command->os, command->mutexContextSeq
-+ ));
-+
-+ /* Success. */
-+ gcmkFOOTER_NO();
-+ return gcvSTATUS_OK;
-+
-+OnError:
-+ /* Return the status. */
-+ gcmkFOOTER();
-+ return status;
-+}
-+
-+
-+gceSTATUS
-+gckHARDWARE_UpdateContextProfile(
-+ IN gckHARDWARE Hardware,
-+ IN gckCONTEXT Context
-+ )
-+{
-+ gceSTATUS status;
-+ gcsPROFILER_COUNTERS * profiler = &Context->latestProfiler;
-+ gcsPROFILER_COUNTERS * profilerHistroy = &Context->histroyProfiler;
-+ gctUINT i, clock;
-+ gctUINT32 colorKilled, colorDrawn, depthKilled, depthDrawn;
-+ gctUINT32 totalRead, totalWrite;
-+ gceCHIPMODEL chipModel;
-+ gctUINT32 chipRevision;
-+ gctUINT32 temp;
-+ gctBOOL needResetShader = gcvFALSE;
-+
-+ gcmkHEADER_ARG("Hardware=0x%x Context=0x%x", Hardware, Context);
-+
-+ /* Verify the arguments. */
-+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
-+ gcmkVERIFY_OBJECT(Context, gcvOBJ_CONTEXT);
-+
-+ chipModel = Hardware->identity.chipModel;
-+ chipRevision = Hardware->identity.chipRevision;
-+ if (chipModel == gcv2000 || (chipModel == gcv2100 && chipRevision == 0x5118))
-+ {
-+ needResetShader = gcvTRUE;
-+ }
-+
-+ /* Read the counters. */
-+ gcmkONERROR(
-+ gckOS_ReadRegisterEx(Hardware->os,
-+ Hardware->core,
-+ 0x00438,
-+ &profiler->gpuCyclesCounter));
-+ gcmkUPDATE_PROFILE_DATA(gpuCyclesCounter);
-+
-+ gcmkONERROR(
-+ gckOS_ReadRegisterEx(Hardware->os,
-+ Hardware->core,
-+ 0x00078,
-+ &profiler->gpuTotalCyclesCounter));
-+ gcmkUPDATE_PROFILE_DATA(gpuTotalCyclesCounter);
-+
-+ gcmkONERROR(
-+ gckOS_ReadRegisterEx(Hardware->os,
-+ Hardware->core,
-+ 0x0007C,
-+ &profiler->gpuIdleCyclesCounter));
-+ gcmkUPDATE_PROFILE_DATA(gpuIdleCyclesCounter);
-+
-+ /* Read clock control register. */
-+ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
-+ Hardware->core,
-+ 0x00000,
-+ &clock));
-+
-+ profiler->gpuTotalRead64BytesPerFrame = 0;
-+ profiler->gpuTotalWrite64BytesPerFrame = 0;
-+ profiler->pe_pixel_count_killed_by_color_pipe = 0;
-+ profiler->pe_pixel_count_killed_by_depth_pipe = 0;
-+ profiler->pe_pixel_count_drawn_by_color_pipe = 0;
-+ profiler->pe_pixel_count_drawn_by_depth_pipe = 0;
-+
-+ /* Walk through all avaiable pixel pipes. */
-+ for (i = 0; i < Hardware->identity.pixelPipes; ++i)
-+ {
-+ /* Select proper pipe. */
-+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
-+ Hardware->core,
-+ 0x00000,
-+ ((((gctUINT32) (clock)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:20) - (0 ? 23:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:20) - (0 ? 23:20) + 1))))))) << (0 ? 23:20))) | (((gctUINT32) ((gctUINT32) (i) & ((gctUINT32) ((((1 ? 23:20) - (0 ? 23:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:20) - (0 ? 23:20) + 1))))))) << (0 ? 23:20)))));
-+
-+ /* BW */
-+ gcmkONERROR(
-+ gckOS_ReadRegisterEx(Hardware->os,
-+ Hardware->core,
-+ 0x00040,
-+ &totalRead));
-+ gcmkONERROR(
-+ gckOS_ReadRegisterEx(Hardware->os,
-+ Hardware->core,
-+ 0x00044,
-+ &totalWrite));
-+
-+ profiler->gpuTotalRead64BytesPerFrame += totalRead;
-+ profiler->gpuTotalWrite64BytesPerFrame += totalWrite;
-+ gcmkUPDATE_PROFILE_DATA(gpuTotalRead64BytesPerFrame);
-+ gcmkUPDATE_PROFILE_DATA(gpuTotalWrite64BytesPerFrame);
-+
-+ /* PE */
-+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))));gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00454, &colorKilled));
-+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))));gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00454, &depthKilled));
-+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))));gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00454, &colorDrawn));
-+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))));gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00454, &depthDrawn));
-+
-+ profiler->pe_pixel_count_killed_by_color_pipe += colorKilled;
-+ profiler->pe_pixel_count_killed_by_depth_pipe += depthKilled;
-+ profiler->pe_pixel_count_drawn_by_color_pipe += colorDrawn;
-+ profiler->pe_pixel_count_drawn_by_depth_pipe += depthDrawn;
-+ gcmkUPDATE_PROFILE_DATA(pe_pixel_count_killed_by_color_pipe);
-+ gcmkUPDATE_PROFILE_DATA(pe_pixel_count_killed_by_depth_pipe);
-+ gcmkUPDATE_PROFILE_DATA(pe_pixel_count_drawn_by_color_pipe);
-+ gcmkUPDATE_PROFILE_DATA(pe_pixel_count_drawn_by_depth_pipe);
-+ }
-+
-+ /* Reset clock control register. */
-+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
-+ Hardware->core,
-+ 0x00000,
-+ clock));
-+
-+
-+
-+
-+ /* Reset counters. */
-+ gcmkONERROR(
-+ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x0003C, 1));
-+ gcmkONERROR(
-+ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x0003C, 0));
-+ gcmkONERROR(
-+ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00438, 0));
-+ gcmkONERROR(
-+ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00078, 0));
-+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
-+gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))
-+));
-+
-+ /* SH */
-+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (7) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
-+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->ps_inst_counter));
-+ if (needResetShader)
-+ {
-+ temp = profiler->ps_inst_counter;
-+ profiler->ps_inst_counter -= Context->prevPSInstCount;
-+ Context->prevPSInstCount = temp;
-+ }
-+ gcmkUPDATE_PROFILE_DATA(ps_inst_counter);
-+
-+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (8) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
-+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->rendered_pixel_counter));
-+ if (needResetShader)
-+ {
-+ temp = profiler->rendered_pixel_counter;
-+ profiler->rendered_pixel_counter -= Context->prevPSPixelCount;
-+ Context->prevPSPixelCount = temp;
-+ }
-+ gcmkUPDATE_PROFILE_DATA(rendered_pixel_counter);
-+
-+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (9) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
-+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->vs_inst_counter));
-+ if (needResetShader)
-+ {
-+ temp = profiler->vs_inst_counter;
-+ profiler->vs_inst_counter -= Context->prevVSInstCount;
-+ Context->prevVSInstCount = temp;
-+ }
-+ gcmkUPDATE_PROFILE_DATA(vs_inst_counter);
-+
-+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (10) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
-+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->rendered_vertice_counter));
-+ if (needResetShader)
-+ {
-+ temp = profiler->rendered_vertice_counter;
-+ profiler->rendered_vertice_counter -= Context->prevVSVertexCount;
-+ Context->prevVSVertexCount = temp;
-+ }
-+ gcmkUPDATE_PROFILE_DATA(rendered_vertice_counter);
-+
-+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (11) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
-+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->vtx_branch_inst_counter));
-+ if (needResetShader)
-+ {
-+ temp = profiler->vtx_branch_inst_counter;
-+ profiler->vtx_branch_inst_counter -= Context->prevVSBranchInstCount;
-+ Context->prevVSBranchInstCount = temp;
-+ }
-+ gcmkUPDATE_PROFILE_DATA(vtx_branch_inst_counter);
-+
-+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (12) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
-+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->vtx_texld_inst_counter));
-+ if (needResetShader)
-+ {
-+ temp = profiler->vtx_texld_inst_counter;
-+ profiler->vtx_texld_inst_counter -= Context->prevVSTexInstCount;
-+ Context->prevVSTexInstCount = temp;
-+ }
-+ gcmkUPDATE_PROFILE_DATA(vtx_texld_inst_counter);
-+
-+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (13) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
-+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->pxl_branch_inst_counter));
-+ if (needResetShader)
-+ {
-+ temp = profiler->pxl_branch_inst_counter;
-+ profiler->pxl_branch_inst_counter -= Context->prevPSBranchInstCount;
-+ Context->prevPSBranchInstCount = temp;
-+ }
-+ gcmkUPDATE_PROFILE_DATA(pxl_branch_inst_counter);
-+
-+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (14) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
-+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->pxl_texld_inst_counter));
-+ if (needResetShader)
-+ {
-+ temp = profiler->pxl_texld_inst_counter;
-+ profiler->pxl_texld_inst_counter -= Context->prevPSTexInstCount;
-+ Context->prevPSTexInstCount = temp;
-+ }
-+ gcmkUPDATE_PROFILE_DATA(pxl_texld_inst_counter);
-+
-+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
-+gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24)))
-+));
-+
-+ /* PA */
-+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
-+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_input_vtx_counter));
-+ gcmkUPDATE_PROFILE_DATA(pa_input_vtx_counter);
-+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (4) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
-+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_input_prim_counter));
-+ gcmkUPDATE_PROFILE_DATA(pa_input_prim_counter);
-+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (5) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
-+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_output_prim_counter));
-+ gcmkUPDATE_PROFILE_DATA(pa_output_prim_counter);
-+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (6) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
-+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_depth_clipped_counter));
-+ gcmkUPDATE_PROFILE_DATA(pa_depth_clipped_counter);
-+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (7) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
-+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_trivial_rejected_counter));
-+ gcmkUPDATE_PROFILE_DATA(pa_trivial_rejected_counter);
-+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (8) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
-+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_culled_counter));
-+ gcmkUPDATE_PROFILE_DATA(pa_culled_counter);
-+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
-+gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0)))
-+));
-+
-+ /* SE */
-+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
-+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00464, &profiler->se_culled_triangle_count));
-+ gcmkUPDATE_PROFILE_DATA(se_culled_triangle_count);
-+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
-+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00464, &profiler->se_culled_lines_count));
-+ gcmkUPDATE_PROFILE_DATA(se_culled_lines_count);
-+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
-+gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8)))
-+));
-+
-+ /* RA */
-+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
-+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_valid_pixel_count));
-+ gcmkUPDATE_PROFILE_DATA(ra_valid_pixel_count);
-+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
-+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_total_quad_count));
-+ gcmkUPDATE_PROFILE_DATA(ra_total_quad_count);
-+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
-+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_valid_quad_count_after_early_z));
-+ gcmkUPDATE_PROFILE_DATA(ra_valid_quad_count_after_early_z);
-+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
-+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_total_primitive_count));
-+ gcmkUPDATE_PROFILE_DATA(ra_total_primitive_count);
-+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (9) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
-+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_pipe_cache_miss_counter));
-+ gcmkUPDATE_PROFILE_DATA(ra_pipe_cache_miss_counter);
-+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (10) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
-+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_prefetch_cache_miss_counter));
-+ gcmkUPDATE_PROFILE_DATA(ra_prefetch_cache_miss_counter);
-+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
-+gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))
-+));
-+
-+ /* TX */
-+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
-+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_total_bilinear_requests));
-+ gcmkUPDATE_PROFILE_DATA(tx_total_bilinear_requests);
-+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
-+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_total_trilinear_requests));
-+ gcmkUPDATE_PROFILE_DATA(tx_total_trilinear_requests);
-+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
-+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_total_discarded_texture_requests));
-+ gcmkUPDATE_PROFILE_DATA(tx_total_discarded_texture_requests);
-+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
-+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_total_texture_requests));
-+ gcmkUPDATE_PROFILE_DATA(tx_total_texture_requests);
-+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (5) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
-+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_mem_read_count));
-+ gcmkUPDATE_PROFILE_DATA(tx_mem_read_count);
-+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (6) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
-+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_mem_read_in_8B_count));
-+ gcmkUPDATE_PROFILE_DATA(tx_mem_read_in_8B_count);
-+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (7) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
-+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_cache_miss_count));
-+ gcmkUPDATE_PROFILE_DATA(tx_cache_miss_count);
-+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (8) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
-+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_cache_hit_texel_count));
-+ gcmkUPDATE_PROFILE_DATA(tx_cache_hit_texel_count);
-+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (9) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
-+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_cache_miss_texel_count));
-+ gcmkUPDATE_PROFILE_DATA(tx_cache_miss_texel_count);
-+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
-+gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24)))
-+));
-+
-+ /* MC */
-+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
-+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00468, &profiler->mc_total_read_req_8B_from_pipeline));
-+ gcmkUPDATE_PROFILE_DATA(mc_total_read_req_8B_from_pipeline);
-+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
-+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00468, &profiler->mc_total_read_req_8B_from_IP));
-+ gcmkUPDATE_PROFILE_DATA(mc_total_read_req_8B_from_IP);
-+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
-+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00468, &profiler->mc_total_write_req_8B_from_pipeline));
-+ gcmkUPDATE_PROFILE_DATA(mc_total_write_req_8B_from_pipeline);
-+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
-+gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0)))
-+));
-+
-+ /* HI */
-+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
-+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0046C, &profiler->hi_axi_cycles_read_request_stalled));
-+ gcmkUPDATE_PROFILE_DATA(hi_axi_cycles_read_request_stalled);
-+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
-+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0046C, &profiler->hi_axi_cycles_write_request_stalled));
-+ gcmkUPDATE_PROFILE_DATA(hi_axi_cycles_write_request_stalled);
-+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
-+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0046C, &profiler->hi_axi_cycles_write_data_stalled));
-+ gcmkUPDATE_PROFILE_DATA(hi_axi_cycles_write_data_stalled);
-+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
-+gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8)))
-+));
-+
-+ /* Success. */
-+ gcmkFOOTER_NO();
-+ return gcvSTATUS_OK;
-+
-+OnError:
-+ /* Return the status. */
-+ gcmkFOOTER();
-+ return status;
-+}
-+#endif
-+
- static gceSTATUS
- _ResetGPU(
- IN gckHARDWARE Hardware,
-@@ -5602,6 +6264,22 @@ gckHARDWARE_IsFeatureAvailable(
- && ((((gctUINT32) (Hardware->identity.chipFeatures)) >> (0 ? 2:2) & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1)))))));
- break;
-
-+ case gcvFEATURE_PIPE_2D:
-+ available = ((((gctUINT32) (Hardware->identity.chipFeatures)) >> (0 ? 9:9) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1)))))));
-+ break;
-+
-+ case gcvFEATURE_PIPE_3D:
-+#ifndef VIVANTE_NO_3D
-+ available = ((((gctUINT32) (Hardware->identity.chipFeatures)) >> (0 ? 2:2) & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1)))))));
-+#else
-+ available = gcvFALSE;
-+#endif
-+ break;
-+
-+ case gcvFEATURE_HALTI2:
-+ available = ((((gctUINT32) (Hardware->identity.chipMinorFeatures4)) >> (0 ? 16:16) & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1)))))));
-+ break;
-+
- default:
- gcmkFATAL("Invalid feature has been requested.");
- available = gcvFALSE;
-diff --git a/drivers/mxc/gpu-viv/arch/XAQ2/hal/kernel/gc_hal_kernel_hardware.h b/drivers/mxc/gpu-viv/arch/XAQ2/hal/kernel/gc_hal_kernel_hardware.h
-index 37226b7..287ea60 100644
---- a/drivers/mxc/gpu-viv/arch/XAQ2/hal/kernel/gc_hal_kernel_hardware.h
-+++ b/drivers/mxc/gpu-viv/arch/XAQ2/hal/kernel/gc_hal_kernel_hardware.h
-@@ -92,6 +92,7 @@ struct _gckHARDWARE
- #endif
-
- gctBOOL powerManagement;
-+ gctBOOL gpuProfiler;
- };
-
- gceSTATUS
-diff --git a/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel.c b/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel.c
-index b7b0d28..12a5340 100644
---- a/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel.c
-+++ b/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel.c
-@@ -128,19 +128,6 @@ _ResetFinishFunction(
- ** Pointer to a variable that will hold the pointer to the gckKERNEL
- ** object.
- */
--#ifdef ANDROID
--#if gcdNEW_PROFILER_FILE
--#define DEFAULT_PROFILE_FILE_NAME "/sdcard/vprofiler.vpd"
--#else
--#define DEFAULT_PROFILE_FILE_NAME "/sdcard/vprofiler.xml"
--#endif
--#else
--#if gcdNEW_PROFILER_FILE
--#define DEFAULT_PROFILE_FILE_NAME "vprofiler.vpd"
--#else
--#define DEFAULT_PROFILE_FILE_NAME "vprofiler.xml"
--#endif
--#endif
-
- gceSTATUS
- gckKERNEL_Construct(
-@@ -302,17 +289,12 @@ gckKERNEL_Construct(
-
- #if VIVANTE_PROFILER
- /* Initialize profile setting */
--#if defined ANDROID
- kernel->profileEnable = gcvFALSE;
--#else
-- kernel->profileEnable = gcvTRUE;
--#endif
- kernel->profileCleanRegister = gcvTRUE;
-+#endif
-
-- gcmkVERIFY_OK(
-- gckOS_MemCopy(kernel->profileFileName,
-- DEFAULT_PROFILE_FILE_NAME,
-- gcmSIZEOF(DEFAULT_PROFILE_FILE_NAME) + 1));
-+#if gcdANDROID_NATIVE_FENCE_SYNC
-+ gcmkONERROR(gckOS_CreateSyncTimeline(Os, &kernel->timeline));
- #endif
-
- /* Return pointer to the gckKERNEL object. */
-@@ -395,6 +377,13 @@ OnError:
- }
- #endif
-
-+#if gcdANDROID_NATIVE_FENCE_SYNC
-+ if (kernel->timeline)
-+ {
-+ gcmkVERIFY_OK(gckOS_DestroySyncTimeline(Os, kernel->timeline));
-+ }
-+#endif
-+
- gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Os, kernel));
- }
-
-@@ -525,6 +514,10 @@ gckKERNEL_Destroy(
- }
- #endif
-
-+#if gcdANDROID_NATIVE_FENCE_SYNC
-+ gcmkVERIFY_OK(gckOS_DestroySyncTimeline(Kernel->os, Kernel->timeline));
-+#endif
-+
- /* Mark the gckKERNEL object as unknown. */
- Kernel->object.type = gcvOBJ_UNKNOWN;
-
-@@ -1310,7 +1303,8 @@ gckKERNEL_Dispatch(
- /* Commit a command and context buffer. */
- gcmkONERROR(
- gckCOMMAND_Commit(Kernel->command,
-- gcmNAME_TO_PTR(Interface->u.Commit.context),
-+ Interface->u.Commit.context ?
-+ gcmNAME_TO_PTR(Interface->u.Commit.context) : gcvNULL,
- gcmUINT64_TO_PTR(Interface->u.Commit.commandBuffer),
- gcmUINT64_TO_PTR(Interface->u.Commit.delta),
- gcmUINT64_TO_PTR(Interface->u.Commit.queue),
-@@ -1600,7 +1594,15 @@ gckKERNEL_Dispatch(
- break;
-
- case gcvHAL_READ_ALL_PROFILE_REGISTERS:
--#if VIVANTE_PROFILER
-+#if VIVANTE_PROFILER && VIVANTE_PROFILER_CONTEXT
-+ /* Read profile data according to the context. */
-+ gcmkONERROR(
-+ gckHARDWARE_QueryContextProfile(
-+ Kernel->hardware,
-+ Kernel->profileCleanRegister,
-+ gcmNAME_TO_PTR(Interface->u.RegisterProfileData.context),
-+ &Interface->u.RegisterProfileData.counters));
-+#elif VIVANTE_PROFILER
- /* Read all 3D profile registers. */
- gcmkONERROR(
- gckHARDWARE_QueryProfileRegisters(
-@@ -1628,11 +1630,6 @@ gckKERNEL_Dispatch(
- #if VIVANTE_PROFILER
- /* Get profile setting */
- Interface->u.GetProfileSetting.enable = Kernel->profileEnable;
--
-- gcmkVERIFY_OK(
-- gckOS_MemCopy(Interface->u.GetProfileSetting.fileName,
-- Kernel->profileFileName,
-- gcdMAX_PROFILE_FILE_NAME));
- #endif
-
- status = gcvSTATUS_OK;
-@@ -1640,12 +1637,13 @@ gckKERNEL_Dispatch(
- case gcvHAL_SET_PROFILE_SETTING:
- #if VIVANTE_PROFILER
- /* Set profile setting */
-- Kernel->profileEnable = Interface->u.SetProfileSetting.enable;
--
-- gcmkVERIFY_OK(
-- gckOS_MemCopy(Kernel->profileFileName,
-- Interface->u.SetProfileSetting.fileName,
-- gcdMAX_PROFILE_FILE_NAME));
-+ if(Kernel->hardware->gpuProfiler)
-+ Kernel->profileEnable = Interface->u.SetProfileSetting.enable;
-+ else
-+ {
-+ status = gcvSTATUS_NOT_SUPPORTED;
-+ break;
-+ }
- #endif
-
- status = gcvSTATUS_OK;
-@@ -2093,6 +2091,61 @@ gckKERNEL_Dispatch(
- #endif
- break;
-
-+#if gcdANDROID_NATIVE_FENCE_SYNC
-+ case gcvHAL_SYNC_POINT:
-+ {
-+ gctSYNC_POINT syncPoint;
-+
-+ switch (Interface->u.SyncPoint.command)
-+ {
-+ case gcvSYNC_POINT_CREATE:
-+ gcmkONERROR(gckOS_CreateSyncPoint(Kernel->os, &syncPoint));
-+
-+ Interface->u.SyncPoint.syncPoint = gcmPTR_TO_UINT64(syncPoint);
-+
-+ gcmkVERIFY_OK(
-+ gckKERNEL_AddProcessDB(Kernel,
-+ processID, gcvDB_SYNC_POINT,
-+ syncPoint,
-+ gcvNULL,
-+ 0));
-+ break;
-+
-+ case gcvSYNC_POINT_DESTROY:
-+ syncPoint = gcmUINT64_TO_PTR(Interface->u.SyncPoint.syncPoint);
-+
-+ gcmkONERROR(gckOS_DestroySyncPoint(Kernel->os, syncPoint));
-+
-+ gcmkVERIFY_OK(
-+ gckKERNEL_RemoveProcessDB(Kernel,
-+ processID, gcvDB_SYNC_POINT,
-+ syncPoint));
-+ break;
-+
-+ default:
-+ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
-+ break;
-+ }
-+ }
-+ break;
-+
-+ case gcvHAL_CREATE_NATIVE_FENCE:
-+ {
-+ gctINT fenceFD;
-+ gctSYNC_POINT syncPoint =
-+ gcmUINT64_TO_PTR(Interface->u.CreateNativeFence.syncPoint);
-+
-+ gcmkONERROR(
-+ gckOS_CreateNativeFence(Kernel->os,
-+ Kernel->timeline,
-+ syncPoint,
-+ &fenceFD));
-+
-+ Interface->u.CreateNativeFence.fenceFD = fenceFD;
-+ }
-+ break;
-+#endif
-+
- default:
- /* Invalid command. */
- gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
-@@ -2856,6 +2909,8 @@ gckKERNEL_Recovery(
- return gcvSTATUS_OK;
- }
-
-+ gcmkPRINT("[galcore]: GPU[%d] hang, automatic recovery.", Kernel->core);
-+
- /* Start a timer to clear reset flag, before timer is expired,
- ** other recovery request is ignored. */
- gcmkVERIFY_OK(
-@@ -3382,7 +3437,7 @@ gckLINKQUEUE_Dequeue(
- IN gckLINKQUEUE LinkQueue
- )
- {
-- gcmASSERT(LinkQueue->count == gcdLINK_QUEUE_SIZE);
-+ gcmkASSERT(LinkQueue->count == gcdLINK_QUEUE_SIZE);
-
- LinkQueue->count--;
- LinkQueue->front = (LinkQueue->front + 1) % gcdLINK_QUEUE_SIZE;
-diff --git a/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel.h b/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel.h
-index 5896e93..1c40df2 100644
---- a/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel.h
-+++ b/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel.h
-@@ -140,8 +140,9 @@ typedef enum _gceDATABASE_TYPE
- gcvDB_CONTEXT, /* Context */
- gcvDB_IDLE, /* GPU idle. */
- gcvDB_MAP_MEMORY, /* Map memory */
-- gcvDB_SHARED_INFO, /* Private data */
-- gcvDB_MAP_USER_MEMORY /* Map user memory */
-+ gcvDB_SHARED_INFO, /* Private data */
-+ gcvDB_MAP_USER_MEMORY, /* Map user memory */
-+ gcvDB_SYNC_POINT, /* Sync point. */
- }
- gceDATABASE_TYPE;
-
-@@ -406,9 +407,6 @@ struct _gckKERNEL
- /* Enable profiling */
- gctBOOL profileEnable;
-
-- /* The profile file name */
-- gctCHAR profileFileName[gcdMAX_PROFILE_FILE_NAME];
--
- /* Clear profile register or not*/
- gctBOOL profileCleanRegister;
-
-@@ -445,6 +443,10 @@ struct _gckKERNEL
- #if gcdDVFS
- gckDVFS dvfs;
- #endif
-+
-+#if gcdANDROID_NATIVE_FENCE_SYNC
-+ gctHANDLE timeline;
-+#endif
- };
-
- struct _FrequencyHistory
-@@ -496,6 +498,11 @@ struct _gckCOMMAND
- /* Context switching mutex. */
- gctPOINTER mutexContext;
-
-+#if VIVANTE_PROFILER_CONTEXT
-+ /* Context sequence mutex. */
-+ gctPOINTER mutexContextSeq;
-+#endif
-+
- /* Command queue power semaphore. */
- gctPOINTER powerSemaphore;
-
-@@ -649,6 +656,8 @@ struct _gckEVENT
- gctPOINTER eventListMutex;
-
- gctPOINTER submitTimer;
-+
-+ volatile gctBOOL inNotify;
- };
-
- /* Free all events belonging to a process. */
-@@ -668,6 +677,11 @@ gckEVENT_Stop(
- IN OUT gctSIZE_T * waitSize
- );
-
-+gceSTATUS
-+gckEVENT_WaitEmpty(
-+ IN gckEVENT Event
-+ );
-+
- /* gcuVIDMEM_NODE structure. */
- typedef union _gcuVIDMEM_NODE
- {
-diff --git a/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_command.c b/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_command.c
-index 9ee9ea1..73dab81 100644
---- a/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_command.c
-+++ b/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_command.c
-@@ -494,6 +494,11 @@ gckCOMMAND_Construct(
- /* Create the context switching mutex. */
- gcmkONERROR(gckOS_CreateMutex(os, &command->mutexContext));
-
-+#if VIVANTE_PROFILER_CONTEXT
-+ /* Create the context switching mutex. */
-+ gcmkONERROR(gckOS_CreateMutex(os, &command->mutexContextSeq));
-+#endif
-+
- /* Create the power management semaphore. */
- gcmkONERROR(gckOS_CreateSemaphore(os, &command->powerSemaphore));
-
-@@ -572,6 +577,13 @@ OnError:
- gcmkVERIFY_OK(gckOS_DeleteMutex(os, command->mutexContext));
- }
-
-+#if VIVANTE_PROFILER_CONTEXT
-+ if (command->mutexContextSeq != gcvNULL)
-+ {
-+ gcmkVERIFY_OK(gckOS_DeleteMutex(os, command->mutexContextSeq));
-+ }
-+#endif
-+
- if (command->mutexQueue != gcvNULL)
- {
- gcmkVERIFY_OK(gckOS_DeleteMutex(os, command->mutexQueue));
-@@ -662,6 +674,11 @@ gckCOMMAND_Destroy(
- /* Delete the context switching mutex. */
- gcmkVERIFY_OK(gckOS_DeleteMutex(Command->os, Command->mutexContext));
-
-+#if VIVANTE_PROFILER_CONTEXT
-+ if (Command->mutexContextSeq != gcvNULL)
-+ gcmkVERIFY_OK(gckOS_DeleteMutex(Command->os, Command->mutexContextSeq));
-+#endif
-+
- /* Delete the command queue mutex. */
- gcmkVERIFY_OK(gckOS_DeleteMutex(Command->os, Command->mutexQueue));
-
-@@ -1127,6 +1144,10 @@ gckCOMMAND_Commit(
- # endif
- #endif
-
-+#if VIVANTE_PROFILER_CONTEXT
-+ gctBOOL sequenceAcquired = gcvFALSE;
-+#endif
-+
- gctPOINTER pointer = gcvNULL;
-
- gcmkHEADER_ARG(
-@@ -1145,6 +1166,17 @@ gckCOMMAND_Commit(
-
- gcmkONERROR(_FlushMMU(Command));
-
-+#if VIVANTE_PROFILER_CONTEXT
-+ if((Command->kernel->hardware->gpuProfiler) && (Command->kernel->profileEnable))
-+ {
-+ /* Acquire the context sequnence mutex. */
-+ gcmkONERROR(gckOS_AcquireMutex(
-+ Command->os, Command->mutexContextSeq, gcvINFINITE
-+ ));
-+ sequenceAcquired = gcvTRUE;
-+ }
-+#endif
-+
- /* Acquire the command queue. */
- gcmkONERROR(gckCOMMAND_EnterCommit(Command, gcvFALSE));
- commitEntered = gcvTRUE;
-@@ -2002,6 +2034,23 @@ gckCOMMAND_Commit(
- gcmkONERROR(gckCOMMAND_ExitCommit(Command, gcvFALSE));
- commitEntered = gcvFALSE;
-
-+#if VIVANTE_PROFILER_CONTEXT
-+ if(sequenceAcquired)
-+ {
-+ gcmkONERROR(gckCOMMAND_Stall(Command, gcvTRUE));
-+ if (Command->currContext)
-+ {
-+ gcmkONERROR(gckHARDWARE_UpdateContextProfile(
-+ hardware,
-+ Command->currContext));
-+ }
-+
-+ /* Release the context switching mutex. */
-+ gcmkONERROR(gckOS_ReleaseMutex(Command->os, Command->mutexContextSeq));
-+ sequenceAcquired = gcvFALSE;
-+ }
-+#endif
-+
- /* Loop while there are records in the queue. */
- while (EventQueue != gcvNULL)
- {
-@@ -2114,6 +2163,14 @@ OnError:
- gcmkVERIFY_OK(gckCOMMAND_ExitCommit(Command, gcvFALSE));
- }
-
-+#if VIVANTE_PROFILER_CONTEXT
-+ if (sequenceAcquired)
-+ {
-+ /* Release the context sequence mutex. */
-+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Command->os, Command->mutexContextSeq));
-+ }
-+#endif
-+
- /* Unmap the command buffer pointer. */
- if (commandBufferMapped)
- {
-diff --git a/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_command_vg.c b/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_command_vg.c
-index 76c1c10..1a7c340 100644
---- a/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_command_vg.c
-+++ b/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_command_vg.c
-@@ -2819,6 +2819,7 @@ gckVGCOMMAND_Construct(
- ** Enable TS overflow interrupt.
- */
-
-+ command->info.tsOverflowInt = 0;
- gcmkERR_BREAK(gckVGINTERRUPT_Enable(
- Kernel->interrupt,
- &command->info.tsOverflowInt,
-@@ -3406,38 +3407,26 @@ gckVGCOMMAND_Commit(
- gctBOOL previousExecuted;
- gctUINT controlIndex;
-
-+ gcmkERR_BREAK(gckVGHARDWARE_SetPowerManagementState(
-+ Command->hardware, gcvPOWER_ON_AUTO
-+ ));
-+
-+ /* Acquire the power semaphore. */
-+ gcmkERR_BREAK(gckOS_AcquireSemaphore(
-+ Command->os, Command->powerSemaphore
-+ ));
-+
- /* Acquire the mutex. */
-- gcmkERR_BREAK(gckOS_AcquireMutex(
-+ status = gckOS_AcquireMutex(
- Command->os,
- Command->commitMutex,
- gcvINFINITE
-- ));
--
-- status = gckVGHARDWARE_SetPowerManagementState(
-- Command->hardware, gcvPOWER_ON_AUTO);
--
-- if (gcmIS_ERROR(status))
-- {
-- /* Acquire the mutex. */
-- gcmkVERIFY_OK(gckOS_ReleaseMutex(
-- Command->os,
-- Command->commitMutex
-- ));
--
-- break;
-- }
-- /* Acquire the power semaphore. */
-- status = gckOS_AcquireSemaphore(
-- Command->os, Command->powerSemaphore);
-+ );
-
- if (gcmIS_ERROR(status))
- {
-- /* Acquire the mutex. */
-- gcmkVERIFY_OK(gckOS_ReleaseMutex(
-- Command->os,
-- Command->commitMutex
-- ));
--
-+ gcmkVERIFY_OK(gckOS_ReleaseSemaphore(
-+ Command->os, Command->powerSemaphore));
- break;
- }
-
-@@ -3669,14 +3658,14 @@ gckVGCOMMAND_Commit(
- }
- while (gcvFALSE);
-
-- gcmkVERIFY_OK(gckOS_ReleaseSemaphore(
-- Command->os, Command->powerSemaphore));
--
- /* Release the mutex. */
- gcmkCHECK_STATUS(gckOS_ReleaseMutex(
- Command->os,
- Command->commitMutex
- ));
-+
-+ gcmkVERIFY_OK(gckOS_ReleaseSemaphore(
-+ Command->os, Command->powerSemaphore));
- }
- while (gcvFALSE);
-
-diff --git a/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_db.c b/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_db.c
-index 673d4f7..134351a 100644
---- a/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_db.c
-+++ b/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_db.c
-@@ -1307,6 +1307,18 @@ gckKERNEL_DestroyProcessDB(
- status = gckOS_FreeMemory(Kernel->os, record->physical);
- break;
-
-+#if gcdANDROID_NATIVE_FENCE_SYNC
-+ case gcvDB_SYNC_POINT:
-+ /* Free the user signal. */
-+ status = gckOS_DestroySyncPoint(Kernel->os,
-+ (gctSYNC_POINT) record->data);
-+
-+ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DATABASE,
-+ "DB: SYNC POINT %d (status=%d)",
-+ (gctINT)(gctUINTPTR_T)record->data, status);
-+ break;
-+#endif
-+
- default:
- gcmkTRACE_ZONE(gcvLEVEL_ERROR, gcvZONE_DATABASE,
- "DB: Correcupted record=0x%08x type=%d",
-diff --git a/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_event.c b/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_event.c
-index 217f7f1..2d81a56 100644
---- a/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_event.c
-+++ b/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_event.c
-@@ -931,6 +931,7 @@ gckEVENT_AddList(
- || (Interface->command == gcvHAL_TIMESTAMP)
- || (Interface->command == gcvHAL_COMMIT_DONE)
- || (Interface->command == gcvHAL_FREE_VIRTUAL_COMMAND_BUFFER)
-+ || (Interface->command == gcvHAL_SYNC_POINT)
- );
-
- /* Validate the source. */
-@@ -2131,6 +2132,9 @@ gckEVENT_Notify(
- gcvINFINITE));
- acquired = gcvTRUE;
-
-+ /* We are in the notify loop. */
-+ Event->inNotify = gcvTRUE;
-+
- /* Grab the event head. */
- record = queue->head;
-
-@@ -2463,6 +2467,17 @@ gckEVENT_Notify(
- break;
- #endif
-
-+#if gcdANDROID_NATIVE_FENCE_SYNC
-+ case gcvHAL_SYNC_POINT:
-+ {
-+ gctSYNC_POINT syncPoint;
-+
-+ syncPoint = gcmUINT64_TO_PTR(record->info.u.SyncPoint.syncPoint);
-+ status = gckOS_SignalSyncPoint(Event->os, syncPoint);
-+ }
-+ break;
-+#endif
-+
- case gcvHAL_COMMIT_DONE:
- break;
-
-@@ -2505,6 +2520,9 @@ gckEVENT_Notify(
- gcmkONERROR(_TryToIdleGPU(Event));
- }
-
-+ /* We are out the notify loop. */
-+ Event->inNotify = gcvFALSE;
-+
- /* Success. */
- gcmkFOOTER_NO();
- return gcvSTATUS_OK;
-@@ -2524,6 +2542,9 @@ OnError:
- }
- #endif
-
-+ /* We are out the notify loop. */
-+ Event->inNotify = gcvFALSE;
-+
- /* Return the status. */
- gcmkFOOTER();
- return status;
-@@ -2871,3 +2892,11 @@ gckEVENT_Dump(
- return gcvSTATUS_OK;
- }
-
-+gceSTATUS gckEVENT_WaitEmpty(gckEVENT Event)
-+{
-+ gctBOOL isEmpty;
-+
-+ while (Event->inNotify || (gcmIS_SUCCESS(gckEVENT_IsEmpty(Event, &isEmpty)) && !isEmpty)) ;
-+
-+ return gcvSTATUS_OK;
-+}
-diff --git a/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_interrupt_vg.c b/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_interrupt_vg.c
-index 8ac187b..50bc63e 100644
---- a/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_interrupt_vg.c
-+++ b/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_interrupt_vg.c
-@@ -794,6 +794,9 @@ gckVGINTERRUPT_Enque(
- Interrupt->kernel->hardware, &triggered
- ));
-
-+ /* Mask out TS overflow interrupt */
-+ triggered &= 0xfffffffe;
-+
- /* No interrupts to process? */
- if (triggered == 0)
- {
-diff --git a/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_mmu.c b/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_mmu.c
-index c7f67c7..e4ca497 100644
---- a/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_mmu.c
-+++ b/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_mmu.c
-@@ -1436,7 +1436,7 @@ gckMMU_AllocatePages(
- acquired = gcvTRUE;
-
- /* Allocate page table for current MMU. */
-- for (i = 0; i < mirrorPageTable->reference; i++)
-+ for (i = 0; i < (gctINT)mirrorPageTable->reference; i++)
- {
- if (Mmu == mirrorPageTable->mmus[i])
- {
-@@ -1446,7 +1446,7 @@ gckMMU_AllocatePages(
- }
-
- /* Allocate page table for other MMUs. */
-- for (i = 0; i < mirrorPageTable->reference; i++)
-+ for (i = 0; i < (gctINT)mirrorPageTable->reference; i++)
- {
- mmu = mirrorPageTable->mmus[i];
-
-@@ -1500,7 +1500,7 @@ gckMMU_FreePages(
-
- offset = (gctUINT32)PageTable - (gctUINT32)Mmu->pageTableLogical;
-
-- for (i = 0; i < mirrorPageTable->reference; i++)
-+ for (i = 0; i < (gctINT)mirrorPageTable->reference; i++)
- {
- mmu = mirrorPageTable->mmus[i];
-
-@@ -1639,7 +1639,7 @@ gckMMU_SetPage(
- _WritePageEntry(PageEntry, data);
-
- #if gcdMIRROR_PAGETABLE
-- for (i = 0; i < mirrorPageTable->reference; i++)
-+ for (i = 0; i < (gctINT)mirrorPageTable->reference; i++)
- {
- mmu = mirrorPageTable->mmus[i];
-
-diff --git a/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_video_memory.c b/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_video_memory.c
-index 8b8bbdc..3b5dd82 100644
---- a/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_video_memory.c
-+++ b/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_video_memory.c
-@@ -1582,6 +1582,7 @@ _NeedVirtualMapping(
- gctUINT32 end;
- gcePOOL pool;
- gctUINT32 offset;
-+ gctUINT32 baseAddress;
-
- gcmkHEADER_ARG("Node=0x%X", Node);
-
-@@ -1601,10 +1602,16 @@ _NeedVirtualMapping(
- else
- #endif
- {
-- /* For cores which can't access all physical address. */
-- gcmkONERROR(gckHARDWARE_ConvertLogical(Kernel->hardware,
-- Node->Virtual.logical,
-- &phys));
-+ /* Convert logical address into a physical address. */
-+ gcmkONERROR(
-+ gckOS_GetPhysicalAddress(Kernel->os, Node->Virtual.logical, &phys));
-+
-+ gcmkONERROR(gckOS_GetBaseAddress(Kernel->os, &baseAddress));
-+
-+ gcmkASSERT(phys >= baseAddress);
-+
-+ /* Subtract baseAddress to get a GPU address used for programming. */
-+ phys -= baseAddress;
-
- /* If part of region is belong to gcvPOOL_VIRTUAL,
- ** whole region has to be mapped. */
-@@ -1734,6 +1741,11 @@ gckVIDMEM_Lock(
- gcmkONERROR(gckOS_AcquireMutex(os, Node->Virtual.mutex, gcvINFINITE));
- acquired = gcvTRUE;
-
-+#if gcdPAGED_MEMORY_CACHEABLE
-+ /* Force video memory cacheable. */
-+ Cacheable = gcvTRUE;
-+#endif
-+
- gcmkONERROR(
- gckOS_LockPages(os,
- Node->Virtual.physical,
-diff --git a/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal.h b/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal.h
-index 4406d7e..7312cc2 100644
---- a/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal.h
-+++ b/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal.h
-@@ -123,6 +123,12 @@ extern "C" {
-
- #define gcvINVALID_ADDRESS ~0U
-
-+#define gcmGET_PRE_ROTATION(rotate) \
-+ ((rotate) & (~(gcvSURF_POST_FLIP_X | gcvSURF_POST_FLIP_Y)))
-+
-+#define gcmGET_POST_ROTATION(rotate) \
-+ ((rotate) & (gcvSURF_POST_FLIP_X | gcvSURF_POST_FLIP_Y))
-+
- /******************************************************************************\
- ******************************** gcsOBJECT Object *******************************
- \******************************************************************************/
-@@ -1124,6 +1130,60 @@ gckOS_UnmapUserMemory(
- IN gctUINT32 Address
- );
-
-+/******************************************************************************\
-+************************** Android Native Fence Sync ***************************
-+\******************************************************************************/
-+gceSTATUS
-+gckOS_CreateSyncTimeline(
-+ IN gckOS Os,
-+ OUT gctHANDLE * Timeline
-+ );
-+
-+gceSTATUS
-+gckOS_DestroySyncTimeline(
-+ IN gckOS Os,
-+ IN gctHANDLE Timeline
-+ );
-+
-+gceSTATUS
-+gckOS_CreateSyncPoint(
-+ IN gckOS Os,
-+ OUT gctSYNC_POINT * SyncPoint
-+ );
-+
-+gceSTATUS
-+gckOS_ReferenceSyncPoint(
-+ IN gckOS Os,
-+ IN gctSYNC_POINT SyncPoint
-+ );
-+
-+gceSTATUS
-+gckOS_DestroySyncPoint(
-+ IN gckOS Os,
-+ IN gctSYNC_POINT SyncPoint
-+ );
-+
-+gceSTATUS
-+gckOS_SignalSyncPoint(
-+ IN gckOS Os,
-+ IN gctSYNC_POINT SyncPoint
-+ );
-+
-+gceSTATUS
-+gckOS_QuerySyncPoint(
-+ IN gckOS Os,
-+ IN gctSYNC_POINT SyncPoint,
-+ OUT gctBOOL_PTR State
-+ );
-+
-+gceSTATUS
-+gckOS_CreateNativeFence(
-+ IN gckOS Os,
-+ IN gctHANDLE Timeline,
-+ IN gctSYNC_POINT SyncPoint,
-+ OUT gctINT * FenceFD
-+ );
-+
- #if !USE_NEW_LINUX_SIGNAL
- /* Create signal to be used in the user space. */
- gceSTATUS
-@@ -1758,7 +1818,7 @@ gckKERNEL_Recovery(
- void
- gckKERNEL_SetTimeOut(
- IN gckKERNEL Kernel,
-- IN gctUINT32 timeOut
-+ IN gctUINT32 timeOut
- );
-
- /* Get access to the user data. */
-@@ -2078,6 +2138,12 @@ gckHARDWARE_SetPowerManagement(
- IN gctBOOL PowerManagement
- );
-
-+gceSTATUS
-+gckHARDWARE_SetGpuProfiler(
-+ IN gckHARDWARE Hardware,
-+ IN gctBOOL GpuProfiler
-+ );
-+
- #if gcdENABLE_FSCALE_VAL_ADJUST
- gceSTATUS
- gckHARDWARE_SetFscaleValue(
-@@ -2554,6 +2620,22 @@ gckHARDWARE_QueryProfileRegisters(
- );
- #endif
-
-+#if VIVANTE_PROFILER_CONTEXT
-+gceSTATUS
-+gckHARDWARE_QueryContextProfile(
-+ IN gckHARDWARE Hardware,
-+ IN gctBOOL Clear,
-+ IN gckCONTEXT Context,
-+ OUT gcsPROFILER_COUNTERS * Counters
-+ );
-+
-+gceSTATUS
-+gckHARDWARE_UpdateContextProfile(
-+ IN gckHARDWARE Hardware,
-+ IN gckCONTEXT Context
-+ );
-+#endif
-+
- gceSTATUS
- gckOS_SignalQueryHardware(
- IN gckOS Os,
-diff --git a/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_base.h b/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_base.h
-index 44689b0..9c17114 100644
---- a/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_base.h
-+++ b/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_base.h
-@@ -71,10 +71,17 @@ typedef struct _gcoFENCE * gcoFENCE;
- typedef struct _gcsSYNC_CONTEXT * gcsSYNC_CONTEXT_PTR;
- #endif
-
-+typedef struct _gcoOS_SymbolsList gcoOS_SymbolsList;
-+
- /******************************************************************************\
- ******************************* Process local storage *************************
- \******************************************************************************/
- typedef struct _gcsPLS * gcsPLS_PTR;
-+
-+typedef void (* gctPLS_DESTRUCTOR) (
-+ gcsPLS_PTR
-+ );
-+
- typedef struct _gcsPLS
- {
- /* Global objects. */
-@@ -103,6 +110,12 @@ typedef struct _gcsPLS
-
- /* PorcessID of the constrcutor process */
- gctUINT32 processID;
-+#if gcdFORCE_GAL_LOAD_TWICE
-+ /* ThreadID of the constrcutor process. */
-+ gctSIZE_T threadID;
-+ /* Flag for calling module destructor. */
-+ gctBOOL exiting;
-+#endif
-
- /* Reference count for destructor. */
- gcsATOM_PTR reference;
-@@ -111,6 +124,8 @@ typedef struct _gcsPLS
- gctBOOL bNeedSupportNP2Texture;
- #endif
-
-+ /* Destructor for eglDisplayInfo. */
-+ gctPLS_DESTRUCTOR destructor;
- }
- gcsPLS;
-
-@@ -148,6 +163,11 @@ typedef struct _gcsTLS
- #endif
- gco2D engine2D;
- gctBOOL copied;
-+
-+#if gcdFORCE_GAL_LOAD_TWICE
-+ /* libGAL.so handle */
-+ gctHANDLE handle;
-+#endif
- }
- gcsTLS;
-
-@@ -160,6 +180,7 @@ typedef enum _gcePLS_VALUE
- gcePLS_VALUE_EGL_DISPLAY_INFO,
- gcePLS_VALUE_EGL_SURFACE_INFO,
- gcePLS_VALUE_EGL_CONFIG_FORMAT_INFO,
-+ gcePLS_VALUE_EGL_DESTRUCTOR_INFO,
- }
- gcePLS_VALUE;
-
-@@ -577,6 +598,12 @@ gcoHAL_Call(
- IN OUT gcsHAL_INTERFACE_PTR Interface
- );
-
-+gceSTATUS
-+gcoHAL_GetPatchID(
-+ IN gcoHAL Hal,
-+ OUT gcePATCH_ID * PatchID
-+ );
-+
- /* Schedule an event. */
- gceSTATUS
- gcoHAL_ScheduleEvent(
-@@ -637,6 +664,16 @@ gcoHAL_QuerySeparated3D2D(
- IN gcoHAL Hal
- );
-
-+gceSTATUS
-+gcoHAL_QuerySpecialHint(
-+ IN gceSPECIAL_HINT Hint
-+ );
-+
-+gceSTATUS
-+gcoHAL_SetSpecialHintData(
-+ IN gcoHARDWARE Hardware
-+ );
-+
- /* Get pointer to gcoVG object. */
- gceSTATUS
- gcoHAL_GetVGEngine(
-@@ -786,7 +823,6 @@ gcoOS_FreeVideoMemory(
- IN gctPOINTER Handle
- );
-
--#if gcdENABLE_BANK_ALIGNMENT
- gceSTATUS
- gcoSURF_GetBankOffsetBytes(
- IN gcoSURF Surfce,
-@@ -794,7 +830,6 @@ gcoSURF_GetBankOffsetBytes(
- IN gctUINT32 Stride,
- IN gctUINT32_PTR Bytes
- );
--#endif
-
- /* Map user memory. */
- gceSTATUS
-@@ -918,6 +953,21 @@ gcoOS_Flush(
- IN gctFILE File
- );
-
-+/* Close a file descriptor. */
-+gceSTATUS
-+gcoOS_CloseFD(
-+ IN gcoOS Os,
-+ IN gctINT FD
-+ );
-+
-+/* Dup file descriptor to another. */
-+gceSTATUS
-+gcoOS_DupFD(
-+ IN gcoOS Os,
-+ IN gctINT FD,
-+ OUT gctINT * FD2
-+ );
-+
- /* Create an endpoint for communication. */
- gceSTATUS
- gcoOS_Socket(
-@@ -977,6 +1027,14 @@ gcoOS_GetEnv(
- OUT gctSTRING * Value
- );
-
-+/* Set environment variable value. */
-+gceSTATUS
-+gcoOS_SetEnv(
-+ IN gcoOS Os,
-+ IN gctCONST_STRING VarName,
-+ IN gctSTRING Value
-+ );
-+
- /* Get current working directory. */
- gceSTATUS
- gcoOS_GetCwd(
-@@ -1210,6 +1268,13 @@ gcoOS_DetectProcessByEncryptedName(
- IN gctCONST_STRING Name
- );
-
-+#if defined(ANDROID)
-+gceSTATUS
-+gcoOS_DetectProgrameByEncryptedSymbols(
-+ IN gcoOS_SymbolsList Symbols
-+ );
-+#endif
-+
- /*----------------------------------------------------------------------------*/
- /*----- Atoms ----------------------------------------------------------------*/
-
-@@ -1403,6 +1468,42 @@ gcoOS_UnmapSignal(
- IN gctSIGNAL Signal
- );
-
-+/*----------------------------------------------------------------------------*/
-+/*----- Android Native Fence -------------------------------------------------*/
-+
-+/* Create sync point. */
-+gceSTATUS
-+gcoOS_CreateSyncPoint(
-+ IN gcoOS Os,
-+ OUT gctSYNC_POINT * SyncPoint
-+ );
-+
-+/* Destroy sync point. */
-+gceSTATUS
-+gcoOS_DestroySyncPoint(
-+ IN gcoOS Os,
-+ IN gctSYNC_POINT SyncPoint
-+ );
-+
-+/* Create native fence. */
-+gceSTATUS
-+gcoOS_CreateNativeFence(
-+ IN gcoOS Os,
-+ IN gctSYNC_POINT SyncPoint,
-+ OUT gctINT * FenceFD
-+ );
-+
-+/* Wait on native fence. */
-+gceSTATUS
-+gcoOS_WaitNativeFence(
-+ IN gcoOS Os,
-+ IN gctINT FenceFD,
-+ IN gctUINT32 Timeout
-+ );
-+
-+/*----------------------------------------------------------------------------*/
-+/*----- Memory Access and Cache ----------------------------------------------*/
-+
- /* Write a register. */
- gceSTATUS
- gcoOS_WriteRegister(
-@@ -1507,7 +1608,7 @@ gcoOS_QueryProfileTickRate(
- # define gcmPROFILE_QUERY(start, ticks) do { } while (gcvFALSE)
- # define gcmPROFILE_ONLY(x) do { } while (gcvFALSE)
- # define gcmPROFILE_ELSE(x) x
--# define gcmPROFILE_DECLARE_ONLY(x) typedef x
-+# define gcmPROFILE_DECLARE_ONLY(x) do { } while (gcvFALSE)
- # define gcmPROFILE_DECLARE_ELSE(x) x
- #endif
-
-@@ -1579,6 +1680,28 @@ typedef struct _gcsRECT
- }
- gcsRECT;
-
-+typedef union _gcsPIXEL
-+{
-+ struct
-+ {
-+ gctFLOAT r, g, b, a;
-+ gctFLOAT d, s;
-+ } pf;
-+
-+ struct
-+ {
-+ gctINT32 r, g, b, a;
-+ gctINT32 d, s;
-+ } pi;
-+
-+ struct
-+ {
-+ gctUINT32 r, g, b, a;
-+ gctUINT32 d, s;
-+ } pui;
-+
-+} gcsPIXEL;
-+
-
- /******************************************************************************\
- ********************************* gcoSURF Object ********************************
-@@ -1795,6 +1918,18 @@ gcoSURF_SetRotation(
- );
-
- gceSTATUS
-+gcoSURF_SetPreRotation(
-+ IN gcoSURF Surface,
-+ IN gceSURF_ROTATION Rotation
-+ );
-+
-+gceSTATUS
-+gcoSURF_GetPreRotation(
-+ IN gcoSURF Surface,
-+ IN gceSURF_ROTATION *Rotation
-+ );
-+
-+gceSTATUS
- gcoSURF_IsValid(
- IN gcoSURF Surface
- );
-@@ -1824,6 +1959,15 @@ gcoSURF_DisableTileStatus(
- IN gcoSURF Surface,
- IN gctBOOL Decompress
- );
-+
-+gceSTATUS
-+gcoSURF_AlignResolveRect(
-+ IN gcoSURF Surf,
-+ IN gcsPOINT_PTR RectOrigin,
-+ IN gcsPOINT_PTR RectSize,
-+ OUT gcsPOINT_PTR AlignedOrigin,
-+ OUT gcsPOINT_PTR AlignedSize
-+ );
- #endif /* VIVANTE_NO_3D */
-
- /* Get surface size. */
-@@ -1910,6 +2054,9 @@ gcoSURF_FillFromTile(
- IN gcoSURF Surface
- );
-
-+/* Check if surface needs a filler. */
-+gceSTATUS gcoSURF_NeedFiller(IN gcoSURF Surface);
-+
- /* Fill surface with a value. */
- gceSTATUS
- gcoSURF_Fill(
-@@ -1949,6 +2096,19 @@ gcoSURF_SetBuffer(
- IN gctUINT32 Physical
- );
-
-+/* Set the underlying video buffer for the surface wrapper. */
-+gceSTATUS
-+gcoSURF_SetVideoBuffer(
-+ IN gcoSURF Surface,
-+ IN gceSURF_TYPE Type,
-+ IN gceSURF_FORMAT Format,
-+ IN gctUINT Width,
-+ IN gctUINT Height,
-+ IN gctUINT Stride,
-+ IN gctPOINTER *LogicalPlane1,
-+ IN gctUINT32 *PhysicalPlane1
-+ );
-+
- /* Set the size of the surface in pixels and map the underlying buffer. */
- gceSTATUS
- gcoSURF_SetWindow(
-@@ -3705,6 +3865,12 @@ gcGetUserDebugOption(
- void
- );
-
-+struct _gcoOS_SymbolsList
-+{
-+ gcePATCH_ID patchId;
-+ const char * symList[10];
-+};
-+
- #if gcdHAS_ELLIPSES
- #define gcmUSER_DEBUG_MSG(level, ...) \
- do \
-diff --git a/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_compiler.h b/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_compiler.h
-index 8693c37..062224c 100644
---- a/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_compiler.h
-+++ b/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_compiler.h
-@@ -39,12 +39,10 @@ extern "C" {
- #define GC_ENABLE_LOADTIME_OPT 1
- #endif
-
--#define TEMP_OPT_CONSTANT_TEXLD_COORD 1
-+#define TEMP_OPT_CONSTANT_TEXLD_COORD 0
-
- #define TEMP_SHADER_PATCH 1
-
--#define ADD_PRE_ROTATION_TO_VS 0
--
- #define TEMP_INLINE_ALL_EXPANSION 1
- /******************************* IR VERSION ******************/
- #define gcdSL_IR_VERSION gcmCC('\0','\0','\0','\1')
-@@ -271,6 +269,7 @@ typedef enum _gcSL_OPCODE
- gcSL_ADDSAT, /* 0x5C */ /* Integer only. */
- gcSL_SUBSAT, /* 0x5D */ /* Integer only. */
- gcSL_MULSAT, /* 0x5E */ /* Integer only. */
-+ gcSL_DP2, /* 0x5F */
- gcSL_MAXOPCODE
- }
- gcSL_OPCODE;
-@@ -474,6 +473,9 @@ struct _gcsHINT
-
- gctBOOL clipW;
-
-+ /* Flag whether or not the shader has a KILL instruction. */
-+ gctBOOL hasKill;
-+
- /* Element count. */
- gctUINT32 elementCount;
-
-@@ -495,12 +497,18 @@ struct _gcsHINT
- /* Balance maximum. */
- gctUINT32 balanceMax;
-
-+ /* Auto-shift balancing. */
-+ gctBOOL autoShift;
-+
- /* Flag whether the PS outputs the depth value or not. */
- gctBOOL psHasFragDepthOut;
-
- /* Flag whether the ThreadWalker is in PS. */
- gctBOOL threadWalkerInPS;
-
-+ /* HW reg number for position of VS */
-+ gctUINT32 hwRegNoOfSIVPos;
-+
- #if gcdALPHA_KILL_IN_SHADER
- /* States to set when alpha kill is enabled. */
- gctUINT32 killStateAddress;
-@@ -687,12 +695,12 @@ typedef enum _gceSHADER_FLAGS
- gcvSHADER_USE_ALPHA_KILL = 0x100,
- #endif
-
--#if ADD_PRE_ROTATION_TO_VS
-+#if gcdPRE_ROTATION && (ANDROID_SDK_VERSION >= 14)
- gcvSHADER_VS_PRE_ROTATION = 0x200,
- #endif
-
- #if TEMP_INLINE_ALL_EXPANSION
-- gcvSHADER_INLINE_ALL_EXPANSION = 0x200,
-+ gcvSHADER_INLINE_ALL_EXPANSION = 0x400,
- #endif
- }
- gceSHADER_FLAGS;
-@@ -827,6 +835,7 @@ typedef struct _gcOPTIMIZER_OPTION
- gctBOOL dumpOptimizerVerbose; /* dump result IR in each optimization phase */
- gctBOOL dumpBEGenertedCode; /* dump generated machine code */
- gctBOOL dumpBEVerbose; /* dump BE tree and optimization detail */
-+ gctBOOL dumpBEFinalIR; /* dump BE final IR */
-
- /* Code generation */
-
-@@ -945,6 +954,8 @@ extern gcOPTIMIZER_OPTION theOptimizerOption;
- gcmOPT_DUMP_CODEGEN_VERBOSE() )
- #define gcmOPT_DUMP_CODEGEN_VERBOSE() \
- (gcmGetOptimizerOption()->dumpBEVerbose != 0)
-+#define gcmOPT_DUMP_FINAL_IR() \
-+ (gcmGetOptimizerOption()->dumpBEFinalIR != 0)
-
- #define gcmOPT_SET_DUMP_SHADER_SRC(v) \
- gcmGetOptimizerOption()->dumpShaderSource = (v)
-@@ -1064,6 +1075,13 @@ typedef struct _gcNPOT_PATCH_PARAM
- gctINT texDimension; /* 2 or 3 */
- }gcNPOT_PATCH_PARAM, *gcNPOT_PATCH_PARAM_PTR;
-
-+typedef struct _gcZBIAS_PATCH_PARAM
-+{
-+ /* Driver uses this to program uniform that designating zbias */
-+ gctINT uniformAddr;
-+ gctINT channel;
-+}gcZBIAS_PATCH_PARAM, *gcZBIAS_PATCH_PARAM_PTR;
-+
- void
- gcGetOptionFromEnv(
- IN OUT gcOPTIMIZER_OPTION * Option
-@@ -1556,6 +1574,43 @@ gcSHADER_AddUniform(
- OUT gcUNIFORM * Uniform
- );
-
-+/*******************************************************************************
-+** gcSHADER_AddPreRotationUniform
-+********************************************************************************
-+**
-+** Add an uniform to a gcSHADER object.
-+**
-+** INPUT:
-+**
-+** gcSHADER Shader
-+** Pointer to a gcSHADER object.
-+**
-+** gctCONST_STRING Name
-+** Name of the uniform to add.
-+**
-+** gcSHADER_TYPE Type
-+** Type of the uniform to add.
-+**
-+** gctSIZE_T Length
-+** Array length of the uniform to add. 'Length' must be at least 1.
-+**
-+** gctINT col
-+** Which uniform.
-+**
-+** OUTPUT:
-+**
-+** gcUNIFORM * Uniform
-+** Pointer to a variable receiving the gcUNIFORM object pointer.
-+*/
-+gceSTATUS
-+gcSHADER_AddPreRotationUniform(
-+ IN gcSHADER Shader,
-+ IN gctCONST_STRING Name,
-+ IN gcSHADER_TYPE Type,
-+ IN gctSIZE_T Length,
-+ IN gctINT col,
-+ OUT gcUNIFORM * Uniform
-+ );
-
- /*******************************************************************************
- ** gcSHADER_AddUniformEx
-@@ -1677,6 +1732,28 @@ gcSHADER_GetUniformCount(
- );
-
- /*******************************************************************************
-+** gcSHADER_GetPreRotationUniform
-+********************************************************************************
-+**
-+** Get the preRotate Uniform.
-+**
-+** INPUT:
-+**
-+** gcSHADER Shader
-+** Pointer to a gcSHADER object.
-+**
-+** OUTPUT:
-+**
-+** gcUNIFORM ** pUniform
-+** Pointer to a preRotation uniforms array.
-+*/
-+gceSTATUS
-+gcSHADER_GetPreRotationUniform(
-+ IN gcSHADER Shader,
-+ OUT gcUNIFORM ** pUniform
-+ );
-+
-+/*******************************************************************************
- ** gcSHADER_GetUniform
- ********************************************************************************
- **
-@@ -3438,6 +3515,34 @@ gcUNIFORM_SetValueF(
- );
-
- /*******************************************************************************
-+** gcUNIFORM_ProgramF
-+**
-+** Set the value of a uniform in floating point.
-+**
-+** INPUT:
-+**
-+** gctUINT32 Address
-+** Address of Uniform.
-+**
-+** gctSIZE_T Row/Col
-+**
-+** const gctFLOAT * Value
-+** Pointer to a buffer holding the floating point values for the
-+** uniform.
-+**
-+** OUTPUT:
-+**
-+** Nothing.
-+*/
-+gceSTATUS
-+gcUNIFORM_ProgramF(
-+ IN gctUINT32 Address,
-+ IN gctSIZE_T Row,
-+ IN gctSIZE_T Col,
-+ IN const gctFLOAT * Value
-+ );
-+
-+/*******************************************************************************
- ** gcUNIFORM_GetModelViewProjMatrix
- ********************************************************************************
- **
-@@ -3912,6 +4017,23 @@ gcRecompileShaders(
- IN gctUINT32 *SamplerWrapS,
- IN gctUINT32 *SamplerWrapT
- );
-+
-+gceSTATUS
-+gcRecompileDepthBias(
-+ IN gcoHAL Hal,
-+ IN gcMACHINECODE_PTR pVsMachineCode,
-+ /*Recompile variables*/
-+ IN OUT gctPOINTER *ppRecompileStateBuffer,
-+ IN OUT gctSIZE_T *pRecompileStateBufferSize,
-+ IN OUT gcsHINT_PTR *ppRecompileHints,
-+ /* natvie state*/
-+ IN gctPOINTER pNativeStateBuffer,
-+ IN gctSIZE_T nativeStateBufferSize,
-+ IN gcsHINT_PTR pNativeHints,
-+ OUT gctINT * uniformAddr,
-+ OUT gctINT * uniformChannel
-+ );
-+
- /*******************************************************************************
- ** gcSaveProgram
- ********************************************************************************
-@@ -4138,6 +4260,16 @@ gcSHADER_PatchNPOTForMachineCode(
- IN OUT gcsHINT_PTR pHints /* User needs copy original hints to this one, then passed this one in */
- );
-
-+gceSTATUS
-+gcSHADER_PatchZBiasForMachineCodeVS(
-+ IN gcMACHINECODE_PTR pMachineCode,
-+ IN OUT gcZBIAS_PATCH_PARAM_PTR pPatchParam,
-+ IN gctUINT hwSupportedInstCount,
-+ OUT gctPOINTER* ppCmdBuffer,
-+ OUT gctUINT32* pByteSizeOfCmdBuffer,
-+ IN OUT gcsHINT_PTR pHints /* User needs copy original hints to this one, then passed this one in */
-+ );
-+
- #ifdef __cplusplus
- }
- #endif
-diff --git a/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_driver.h b/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_driver.h
-index b056c52..fc8c395 100644
---- a/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_driver.h
-+++ b/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_driver.h
-@@ -166,6 +166,12 @@ typedef enum _gceHAL_COMMAND_CODES
-
- /* Reset time stamp. */
- gcvHAL_QUERY_RESET_TIME_STAMP,
-+
-+ /* Sync point operations. */
-+ gcvHAL_SYNC_POINT,
-+
-+ /* Create native fence and return its fd. */
-+ gcvHAL_CREATE_NATIVE_FENCE,
- }
- gceHAL_COMMAND_CODES;
-
-@@ -723,6 +729,10 @@ typedef struct _gcsHAL_INTERFACE
- /* gcvHAL_READ_ALL_PROFILE_REGISTERS */
- struct _gcsHAL_READ_ALL_PROFILE_REGISTERS
- {
-+#if VIVANTE_PROFILER_CONTEXT
-+ /* Context buffer object gckCONTEXT. Just a name. */
-+ IN gctUINT32 context;
-+#endif
- /* Data read. */
- OUT gcsPROFILER_COUNTERS counters;
- }
-@@ -978,6 +988,33 @@ typedef struct _gcsHAL_INTERFACE
- OUT gctUINT64 timeStamp;
- }
- QueryResetTimeStamp;
-+
-+ struct _gcsHAL_SYNC_POINT
-+ {
-+ /* Command. */
-+ gceSYNC_POINT_COMMAND_CODES command;
-+
-+ /* Sync point. */
-+ IN OUT gctUINT64 syncPoint;
-+
-+ /* From where. */
-+ IN gceKERNEL_WHERE fromWhere;
-+
-+ /* Signaled state. */
-+ OUT gctBOOL state;
-+ }
-+ SyncPoint;
-+
-+ struct _gcsHAL_CREATE_NATIVE_FENCE
-+ {
-+ /* Signal id to dup. */
-+ IN gctUINT64 syncPoint;
-+
-+ /* Native fence file descriptor. */
-+ OUT gctINT fenceFD;
-+
-+ }
-+ CreateNativeFence;
- }
- u;
- }
-diff --git a/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_engine.h b/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_engine.h
-index 8481375..3fb2fe4 100644
---- a/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_engine.h
-+++ b/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_engine.h
-@@ -323,6 +323,15 @@ gcoSURF_Resolve(
- IN gcoSURF DestSurface
- );
-
-+gceSTATUS
-+gcoSURF_IsHWResolveable(
-+ IN gcoSURF SrcSurface,
-+ IN gcoSURF DestSurface,
-+ IN gcsPOINT_PTR SrcOrigin,
-+ IN gcsPOINT_PTR DestOrigin,
-+ IN gcsPOINT_PTR RectSize
-+ );
-+
- /* Resolve rectangular area of a surface. */
- gceSTATUS
- gcoSURF_ResolveRect(
-@@ -345,6 +354,11 @@ gcoSURF_IsRenderable(
- IN gcoSURF Surface
- );
-
-+gceSTATUS
-+gcoSURF_IsFormatRenderableAsRT(
-+ IN gcoSURF Surface
-+ );
-+
- #if gcdSYNC
- gceSTATUS
- gcoSURF_GetFence(
-@@ -1006,6 +1020,7 @@ typedef struct _gcsALPHA_INFO
- gctBOOL test;
- gceCOMPARE compare;
- gctUINT8 reference;
-+ gctFLOAT floatReference;
-
- /* Alpha blending states. */
- gctBOOL blend;
-@@ -1040,7 +1055,8 @@ gco3D_SetAlphaCompare(
- gceSTATUS
- gco3D_SetAlphaReference(
- IN gco3D Engine,
-- IN gctUINT8 Reference
-+ IN gctUINT8 Reference,
-+ IN gctFLOAT FloatReference
- );
-
- /* Set alpha test reference in fixed point. */
-@@ -1504,6 +1520,19 @@ gcoTEXTURE_UploadSub(
- IN gceSURF_FORMAT Format
- );
-
-+/* Upload YUV data to an gcoTEXTURE object. */
-+gceSTATUS
-+gcoTEXTURE_UploadYUV(
-+ IN gcoTEXTURE Texture,
-+ IN gceTEXTURE_FACE Face,
-+ IN gctUINT Width,
-+ IN gctUINT Height,
-+ IN gctUINT Slice,
-+ IN gctPOINTER Memory[3],
-+ IN gctINT Stride[3],
-+ IN gceSURF_FORMAT Format
-+ );
-+
- /* Upload compressed data to an gcoTEXTURE object. */
- gceSTATUS
- gcoTEXTURE_UploadCompressed(
-@@ -1621,6 +1650,13 @@ gcoTEXTURE_QueryCaps(
- );
-
- gceSTATUS
-+gcoTEXTURE_GetTiling(
-+ IN gcoTEXTURE Texture,
-+ IN gctINT preferLevel,
-+ OUT gceTILING * Tiling
-+ );
-+
-+gceSTATUS
- gcoTEXTURE_GetClosestFormat(
- IN gcoHAL Hal,
- IN gceSURF_FORMAT InFormat,
-@@ -2001,6 +2037,14 @@ gcoHAL_SetSharedInfo(
- IN gctSIZE_T Bytes
- );
-
-+#if VIVANTE_PROFILER_CONTEXT
-+gceSTATUS
-+gcoHARDWARE_GetContext(
-+ IN gcoHARDWARE Hardware,
-+ OUT gctUINT32 * Context
-+ );
-+#endif
-+
- #ifdef __cplusplus
- }
- #endif
-diff --git a/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_enum.h b/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_enum.h
-index a1d9ae5..8e3c2f8 100644
---- a/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_enum.h
-+++ b/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_enum.h
-@@ -146,10 +146,26 @@ typedef enum _gceFEATURE
- gcvFEATURE_FRUSTUM_CLIP_FIX,
- gcvFEATURE_TEXTURE_LINEAR,
- gcvFEATURE_TEXTURE_YUV_ASSEMBLER,
-+ gcvFEATURE_SHADER_HAS_INSTRUCTION_CACHE,
- gcvFEATURE_DYNAMIC_FREQUENCY_SCALING,
- gcvFEATURE_BUGFIX15,
-+ gcvFEATURE_2D_GAMMA,
-+ gcvFEATURE_2D_COLOR_SPACE_CONVERSION,
-+ gcvFEATURE_2D_SUPER_TILE_VERSION,
- gcvFEATURE_2D_MIRROR_EXTENSION,
-+ gcvFEATURE_2D_SUPER_TILE_V1,
-+ gcvFEATURE_2D_SUPER_TILE_V2,
-+ gcvFEATURE_2D_SUPER_TILE_V3,
-+ gcvFEATURE_2D_MULTI_SOURCE_BLT_EX2,
- gcvFEATURE_ELEMENT_INDEX_UINT,
-+ gcvFEATURE_2D_COMPRESSION,
-+ gcvFEATURE_2D_OPF_YUV_OUTPUT,
-+ gcvFEATURE_2D_MULTI_SRC_BLT_TO_UNIFIED_DST_RECT,
-+ gcvFEATURE_2D_YUV_MODE,
-+ gcvFEATURE_DECOMPRESS_Z16,
-+ gcvFEATURE_LINEAR_RENDER_TARGET,
-+ gcvFEATURE_BUG_FIXES8,
-+ gcvFEATURE_HALTI2,
- }
- gceFEATURE;
-
-@@ -203,11 +219,14 @@ typedef enum _gceSURF_TYPE
- gcvSURF_NO_VIDMEM = 0x200, /* Used to allocate surfaces with no underlying vidmem node.
- In Android, vidmem node is allocated by another process. */
- gcvSURF_CACHEABLE = 0x400, /* Used to allocate a cacheable surface */
--#if gcdANDROID_UNALIGNED_LINEAR_COMPOSITION_ADJUST
- gcvSURF_FLIP = 0x800, /* The Resolve Target the will been flip resolve from RT */
--#endif
- gcvSURF_TILE_STATUS_DIRTY = 0x1000, /* Init tile status to all dirty */
-
-+ gcvSURF_LINEAR = 0x2000,
-+
-+ gcvSURF_TEXTURE_LINEAR = gcvSURF_TEXTURE
-+ | gcvSURF_LINEAR,
-+
- gcvSURF_RENDER_TARGET_NO_TILE_STATUS = gcvSURF_RENDER_TARGET
- | gcvSURF_NO_TILE_STATUS,
-
-@@ -217,6 +236,9 @@ typedef enum _gceSURF_TYPE
- gcvSURF_DEPTH_NO_TILE_STATUS = gcvSURF_DEPTH
- | gcvSURF_NO_TILE_STATUS,
-
-+ gcvSURF_DEPTH_TS_DIRTY = gcvSURF_DEPTH
-+ | gcvSURF_TILE_STATUS_DIRTY,
-+
- /* Supported surface types with no vidmem node. */
- gcvSURF_BITMAP_NO_VIDMEM = gcvSURF_BITMAP
- | gcvSURF_NO_VIDMEM,
-@@ -231,10 +253,8 @@ typedef enum _gceSURF_TYPE
- gcvSURF_CACHEABLE_BITMAP = gcvSURF_BITMAP
- | gcvSURF_CACHEABLE,
-
--#if gcdANDROID_UNALIGNED_LINEAR_COMPOSITION_ADJUST
- gcvSURF_FLIP_BITMAP = gcvSURF_BITMAP
- | gcvSURF_FLIP,
--#endif
- }
- gceSURF_TYPE;
-
-@@ -263,6 +283,9 @@ typedef enum _gceSURF_ROTATION
- gcvSURF_270_DEGREE,
- gcvSURF_FLIP_X,
- gcvSURF_FLIP_Y,
-+
-+ gcvSURF_POST_FLIP_X = 0x40000000,
-+ gcvSURF_POST_FLIP_Y = 0x80000000,
- }
- gceSURF_ROTATION;
-
-@@ -622,21 +645,16 @@ gce2D_PORTER_DUFF_RULE;
- typedef enum _gce2D_YUV_COLOR_MODE
- {
- gcv2D_YUV_601= 0,
-- gcv2D_YUV_709
--}
--gce2D_YUV_COLOR_MODE;
-+ gcv2D_YUV_709,
-+ gcv2D_YUV_USER_DEFINED,
-+ gcv2D_YUV_USER_DEFINED_CLAMP,
-
--/* 2D Rotation and flipping. */
--typedef enum _gce2D_ORIENTATION
--{
-- gcv2D_0_DEGREE = 0,
-- gcv2D_90_DEGREE,
-- gcv2D_180_DEGREE,
-- gcv2D_270_DEGREE,
-- gcv2D_X_FLIP,
-- gcv2D_Y_FLIP
-+ /* Default setting is for src. gcv2D_YUV_DST
-+ can be ORed to set dst.
-+ */
-+ gcv2D_YUV_DST = 0x80000000,
- }
--gce2D_ORIENTATION;
-+gce2D_YUV_COLOR_MODE;
-
- typedef enum _gce2D_COMMAND
- {
-@@ -656,21 +674,39 @@ typedef enum _gce2D_TILE_STATUS_CONFIG
- gcv2D_TSC_ENABLE = 0x00000001,
- gcv2D_TSC_COMPRESSED = 0x00000002,
- gcv2D_TSC_DOWN_SAMPLER = 0x00000004,
-+ gcv2D_TSC_2D_COMPRESSED = 0x00000008,
- }
- gce2D_TILE_STATUS_CONFIG;
-
- typedef enum _gce2D_QUERY
- {
-- gcv2D_QUERY_RGB_ADDRESS_MAX_ALIGN = 0,
-- gcv2D_QUERY_RGB_STRIDE_MAX_ALIGN,
-- gcv2D_QUERY_YUV_ADDRESS_MAX_ALIGN,
-- gcv2D_QUERY_YUV_STRIDE_MAX_ALIGN,
-+ gcv2D_QUERY_RGB_ADDRESS_MIN_ALIGN = 0,
-+ gcv2D_QUERY_RGB_STRIDE_MIN_ALIGN,
-+ gcv2D_QUERY_YUV_ADDRESS_MIN_ALIGN,
-+ gcv2D_QUERY_YUV_STRIDE_MIN_ALIGN,
- }
- gce2D_QUERY;
-
-+typedef enum _gce2D_SUPER_TILE_VERSION
-+{
-+ gcv2D_SUPER_TILE_VERSION_V1 = 1,
-+ gcv2D_SUPER_TILE_VERSION_V2 = 2,
-+ gcv2D_SUPER_TILE_VERSION_V3 = 3,
-+}
-+gce2D_SUPER_TILE_VERSION;
-+
- typedef enum _gce2D_STATE
- {
- gcv2D_STATE_SPECIAL_FILTER_MIRROR_MODE = 1,
-+ gcv2D_STATE_SUPER_TILE_VERSION,
-+ gcv2D_STATE_EN_GAMMA,
-+ gcv2D_STATE_DE_GAMMA,
-+ gcv2D_STATE_MULTI_SRC_BLIT_UNIFIED_DST_RECT,
-+
-+ gcv2D_STATE_ARRAY_EN_GAMMA = 0x10001,
-+ gcv2D_STATE_ARRAY_DE_GAMMA,
-+ gcv2D_STATE_ARRAY_CSC_YUV_TO_RGB,
-+ gcv2D_STATE_ARRAY_CSC_RGB_TO_YUV,
- }
- gce2D_STATE;
-
-@@ -809,6 +845,15 @@ typedef enum _gceUSER_SIGNAL_COMMAND_CODES
- }
- gceUSER_SIGNAL_COMMAND_CODES;
-
-+/* Sync point command codes. */
-+typedef enum _gceSYNC_POINT_COMMAND_CODES
-+{
-+ gcvSYNC_POINT_CREATE,
-+ gcvSYNC_POINT_DESTROY,
-+ gcvSYNC_POINT_SIGNAL,
-+}
-+gceSYNC_POINT_COMMAND_CODES;
-+
- /* Event locations. */
- typedef enum _gceKERNEL_WHERE
- {
-@@ -848,6 +893,44 @@ typedef enum _gceDEBUG_MESSAGE_TYPE
- }
- gceDEBUG_MESSAGE_TYPE;
-
-+typedef enum _gceSPECIAL_HINT
-+{
-+ gceSPECIAL_HINT0,
-+ gceSPECIAL_HINT1,
-+ gceSPECIAL_HINT2,
-+ gceSPECIAL_HINT3,
-+ /* For disable dynamic stream/index */
-+ gceSPECIAL_HINT4
-+}
-+gceSPECIAL_HINT;
-+
-+typedef enum _gceMACHINECODE
-+{
-+ gcvMACHINECODE_HOVERJET0 = 0x0,
-+ gcvMACHINECODE_HOVERJET1 ,
-+
-+ gcvMACHINECODE_TAIJI0 ,
-+ gcvMACHINECODE_TAIJI1 ,
-+ gcvMACHINECODE_TAIJI2 ,
-+
-+ gcvMACHINECODE_ANTUTU0 ,
-+
-+ gcvMACHINECODE_GLB27_RELEASE_0,
-+ gcvMACHINECODE_GLB27_RELEASE_1,
-+
-+ gcvMACHINECODE_WAVESCAPE0 ,
-+ gcvMACHINECODE_WAVESCAPE1 ,
-+
-+ gcvMACHINECODE_NENAMARKV2_4_0 ,
-+ gcvMACHINECODE_NENAMARKV2_4_1 ,
-+
-+ gcvMACHINECODE_GLB25_RELEASE_0,
-+ gcvMACHINECODE_GLB25_RELEASE_1,
-+ gcvMACHINECODE_GLB25_RELEASE_2,
-+}
-+gceMACHINECODE;
-+
-+
- /******************************************************************************\
- ****************************** Object Declarations *****************************
- \******************************************************************************/
-diff --git a/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_options.h b/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_options.h
-index 9e2a8db..b53b618 100644
---- a/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_options.h
-+++ b/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_options.h
-@@ -46,7 +46,7 @@
- This define enables the profiler.
- */
- #ifndef VIVANTE_PROFILER
--# define VIVANTE_PROFILER 0
-+# define VIVANTE_PROFILER 1
- #endif
-
- #ifndef VIVANTE_PROFILER_PERDRAW
-@@ -54,6 +54,15 @@
- #endif
-
- /*
-+ VIVANTE_PROFILER_CONTEXT
-+
-+ This define enables the profiler according to each hw context.
-+*/
-+#ifndef VIVANTE_PROFILER_CONTEXT
-+# define VIVANTE_PROFILER_CONTEXT 1
-+#endif
-+
-+/*
- gcdUSE_VG
-
- Enable VG HAL layer (only for GC350).
-@@ -729,7 +738,24 @@
- Use linear buffer for GPU apps so HWC can do 2D composition.
- */
- #ifndef gcdGPU_LINEAR_BUFFER_ENABLED
--# define gcdGPU_LINEAR_BUFFER_ENABLED 0
-+# define gcdGPU_LINEAR_BUFFER_ENABLED 1
-+#endif
-+
-+/*
-+ gcdENABLE_RENDER_INTO_WINDOW
-+
-+ Enable Render-Into-Window (ie, No-Resolve) feature on android.
-+ NOTE that even if enabled, it still depends on hardware feature and
-+ android application behavior. When hardware feature or application
-+ behavior can not support render into window mode, it will fail back
-+ to normal mode.
-+ When Render-Into-Window is finally used, window back buffer of android
-+ applications will be allocated matching render target tiling format.
-+ Otherwise buffer tiling is decided by the above option
-+ 'gcdGPU_LINEAR_BUFFER_ENABLED'.
-+*/
-+#ifndef gcdENABLE_RENDER_INTO_WINDOW
-+# define gcdENABLE_RENDER_INTO_WINDOW 1
- #endif
-
- /*
-@@ -758,7 +784,11 @@
- #endif
-
- #ifndef gcdANDROID_UNALIGNED_LINEAR_COMPOSITION_ADJUST
--# define gcdANDROID_UNALIGNED_LINEAR_COMPOSITION_ADJUST 0
-+# ifdef ANDROID
-+# define gcdANDROID_UNALIGNED_LINEAR_COMPOSITION_ADJUST 1
-+# else
-+# define gcdANDROID_UNALIGNED_LINEAR_COMPOSITION_ADJUST 0
-+# endif
- #endif
-
- #ifndef gcdENABLE_PE_DITHER_FIX
-@@ -800,6 +830,10 @@
- # define gcdDISALBE_EARLY_EARLY_Z 1
- #endif
-
-+#ifndef gcdSHADER_SRC_BY_MACHINECODE
-+# define gcdSHADER_SRC_BY_MACHINECODE 1
-+#endif
-+
- /*
- gcdLINK_QUEUE_SIZE
-
-@@ -849,11 +883,20 @@
- #define gcdUSE_NPOT_PATCH 1
- #endif
-
--
- #ifndef gcdSYNC
- # define gcdSYNC 1
- #endif
-
-+#ifndef gcdENABLE_SPECIAL_HINT3
-+# define gcdENABLE_SPECIAL_HINT3 1
-+#endif
-+
-+#if defined(ANDROID)
-+#ifndef gcdPRE_ROTATION
-+# define gcdPRE_ROTATION 1
-+#endif
-+#endif
-+
- /*
- gcdDVFS
-
-@@ -866,4 +909,39 @@
- # define gcdDVFS_POLLING_TIME (gcdDVFS_ANAYLSE_WINDOW * 4)
- #endif
-
-+/*
-+ gcdANDROID_NATIVE_FENCE_SYNC
-+
-+ Enable android native fence sync. It is introduced since jellybean-4.2.
-+ Depends on linux kernel option: CONFIG_SYNC.
-+
-+ 0: Disabled
-+ 1: Build framework for native fence sync feature, and EGL extension
-+ 2: Enable async swap buffers for client
-+ * Native fence sync for client 'queueBuffer' in EGL, which is
-+ 'acquireFenceFd' for layer in compositor side.
-+ 3. Enable async hwcomposer composition.
-+ * 'releaseFenceFd' for layer in compositor side, which is native
-+ fence sync when client 'dequeueBuffer'
-+ * Native fence sync for compositor 'queueBuffer' in EGL, which is
-+ 'acquireFenceFd' for framebuffer target for DC
-+ */
-+#ifndef gcdANDROID_NATIVE_FENCE_SYNC
-+# define gcdANDROID_NATIVE_FENCE_SYNC 0
-+#endif
-+
-+#ifndef gcdFORCE_MIPMAP
-+# define gcdFORCE_MIPMAP 0
-+#endif
-+
-+/*
-+ gcdFORCE_GAL_LOAD_TWICE
-+
-+ When non-zero, each thread except the main one will load libGAL.so twice to avoid potential segmetantion fault when app using dlopen/dlclose.
-+ If threads exit arbitrarily, libGAL.so may not unload until the process quit.
-+ */
-+#ifndef gcdFORCE_GAL_LOAD_TWICE
-+# define gcdFORCE_GAL_LOAD_TWICE 0
-+#endif
-+
- #endif /* __gc_hal_options_h_ */
-diff --git a/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_profiler.h b/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_profiler.h
-index 3e450ba..aed73aa 100644
---- a/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_profiler.h
-+++ b/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_profiler.h
-@@ -45,509 +45,115 @@ extern "C" {
- #define gcdNEW_PROFILER_FILE 1
- #endif
-
--/* OpenGL ES11 API IDs. */
--#define ES11_ACTIVETEXTURE 1
--#define ES11_ALPHAFUNC (ES11_ACTIVETEXTURE + 1)
--#define ES11_ALPHAFUNCX (ES11_ALPHAFUNC + 1)
--#define ES11_BINDBUFFER (ES11_ALPHAFUNCX + 1)
--#define ES11_BINDTEXTURE (ES11_BINDBUFFER + 1)
--#define ES11_BLENDFUNC (ES11_BINDTEXTURE + 1)
--#define ES11_BUFFERDATA (ES11_BLENDFUNC + 1)
--#define ES11_BUFFERSUBDATA (ES11_BUFFERDATA + 1)
--#define ES11_CLEAR (ES11_BUFFERSUBDATA + 1)
--#define ES11_CLEARCOLOR (ES11_CLEAR + 1)
--#define ES11_CLEARCOLORX (ES11_CLEARCOLOR + 1)
--#define ES11_CLEARDEPTHF (ES11_CLEARCOLORX + 1)
--#define ES11_CLEARDEPTHX (ES11_CLEARDEPTHF + 1)
--#define ES11_CLEARSTENCIL (ES11_CLEARDEPTHX + 1)
--#define ES11_CLIENTACTIVETEXTURE (ES11_CLEARSTENCIL + 1)
--#define ES11_CLIPPLANEF (ES11_CLIENTACTIVETEXTURE + 1)
--#define ES11_CLIPPLANEX (ES11_CLIPPLANEF + 1)
--#define ES11_COLOR4F (ES11_CLIPPLANEX + 1)
--#define ES11_COLOR4UB (ES11_COLOR4F + 1)
--#define ES11_COLOR4X (ES11_COLOR4UB + 1)
--#define ES11_COLORMASK (ES11_COLOR4X + 1)
--#define ES11_COLORPOINTER (ES11_COLORMASK + 1)
--#define ES11_COMPRESSEDTEXIMAGE2D (ES11_COLORPOINTER + 1)
--#define ES11_COMPRESSEDTEXSUBIMAGE2D (ES11_COMPRESSEDTEXIMAGE2D + 1)
--#define ES11_COPYTEXIMAGE2D (ES11_COMPRESSEDTEXSUBIMAGE2D + 1)
--#define ES11_COPYTEXSUBIMAGE2D (ES11_COPYTEXIMAGE2D + 1)
--#define ES11_CULLFACE (ES11_COPYTEXSUBIMAGE2D + 1)
--#define ES11_DELETEBUFFERS (ES11_CULLFACE + 1)
--#define ES11_DELETETEXTURES (ES11_DELETEBUFFERS + 1)
--#define ES11_DEPTHFUNC (ES11_DELETETEXTURES + 1)
--#define ES11_DEPTHMASK (ES11_DEPTHFUNC + 1)
--#define ES11_DEPTHRANGEF (ES11_DEPTHMASK + 1)
--#define ES11_DEPTHRANGEX (ES11_DEPTHRANGEF + 1)
--#define ES11_DISABLE (ES11_DEPTHRANGEX + 1)
--#define ES11_DISABLECLIENTSTATE (ES11_DISABLE + 1)
--#define ES11_DRAWARRAYS (ES11_DISABLECLIENTSTATE + 1)
--#define ES11_DRAWELEMENTS (ES11_DRAWARRAYS + 1)
--#define ES11_ENABLE (ES11_DRAWELEMENTS + 1)
--#define ES11_ENABLECLIENTSTATE (ES11_ENABLE + 1)
--#define ES11_FINISH (ES11_ENABLECLIENTSTATE + 1)
--#define ES11_FLUSH (ES11_FINISH + 1)
--#define ES11_FOGF (ES11_FLUSH + 1)
--#define ES11_FOGFV (ES11_FOGF + 1)
--#define ES11_FOGX (ES11_FOGFV + 1)
--#define ES11_FOGXV (ES11_FOGX + 1)
--#define ES11_FRONTFACE (ES11_FOGXV + 1)
--#define ES11_FRUSTUMF (ES11_FRONTFACE + 1)
--#define ES11_FRUSTUMX (ES11_FRUSTUMF + 1)
--#define ES11_GENBUFFERS (ES11_FRUSTUMX + 1)
--#define ES11_GENTEXTURES (ES11_GENBUFFERS + 1)
--#define ES11_GETBOOLEANV (ES11_GENTEXTURES + 1)
--#define ES11_GETBUFFERPARAMETERIV (ES11_GETBOOLEANV + 1)
--#define ES11_GETCLIPPLANEF (ES11_GETBUFFERPARAMETERIV + 1)
--#define ES11_GETCLIPPLANEX (ES11_GETCLIPPLANEF + 1)
--#define ES11_GETERROR (ES11_GETCLIPPLANEX + 1)
--#define ES11_GETFIXEDV (ES11_GETERROR + 1)
--#define ES11_GETFLOATV (ES11_GETFIXEDV + 1)
--#define ES11_GETINTEGERV (ES11_GETFLOATV + 1)
--#define ES11_GETLIGHTFV (ES11_GETINTEGERV + 1)
--#define ES11_GETLIGHTXV (ES11_GETLIGHTFV + 1)
--#define ES11_GETMATERIALFV (ES11_GETLIGHTXV + 1)
--#define ES11_GETMATERIALXV (ES11_GETMATERIALFV + 1)
--#define ES11_GETPOINTERV (ES11_GETMATERIALXV + 1)
--#define ES11_GETSTRING (ES11_GETPOINTERV + 1)
--#define ES11_GETTEXENVFV (ES11_GETSTRING + 1)
--#define ES11_GETTEXENVIV (ES11_GETTEXENVFV + 1)
--#define ES11_GETTEXENVXV (ES11_GETTEXENVIV + 1)
--#define ES11_GETTEXPARAMETERFV (ES11_GETTEXENVXV + 1)
--#define ES11_GETTEXPARAMETERIV (ES11_GETTEXPARAMETERFV + 1)
--#define ES11_GETTEXPARAMETERXV (ES11_GETTEXPARAMETERIV + 1)
--#define ES11_HINT (ES11_GETTEXPARAMETERXV + 1)
--#define ES11_ISBUFFER (ES11_HINT + 1)
--#define ES11_ISENABLED (ES11_ISBUFFER + 1)
--#define ES11_ISTEXTURE (ES11_ISENABLED + 1)
--#define ES11_LIGHTF (ES11_ISTEXTURE + 1)
--#define ES11_LIGHTFV (ES11_LIGHTF + 1)
--#define ES11_LIGHTMODELF (ES11_LIGHTFV + 1)
--#define ES11_LIGHTMODELFV (ES11_LIGHTMODELF + 1)
--#define ES11_LIGHTMODELX (ES11_LIGHTMODELFV + 1)
--#define ES11_LIGHTMODELXV (ES11_LIGHTMODELX + 1)
--#define ES11_LIGHTX (ES11_LIGHTMODELXV + 1)
--#define ES11_LIGHTXV (ES11_LIGHTX + 1)
--#define ES11_LINEWIDTH (ES11_LIGHTXV + 1)
--#define ES11_LINEWIDTHX (ES11_LINEWIDTH + 1)
--#define ES11_LOADIDENTITY (ES11_LINEWIDTHX + 1)
--#define ES11_LOADMATRIXF (ES11_LOADIDENTITY + 1)
--#define ES11_LOADMATRIXX (ES11_LOADMATRIXF + 1)
--#define ES11_LOGICOP (ES11_LOADMATRIXX + 1)
--#define ES11_MATERIALF (ES11_LOGICOP + 1)
--#define ES11_MATERIALFV (ES11_MATERIALF + 1)
--#define ES11_MATERIALX (ES11_MATERIALFV + 1)
--#define ES11_MATERIALXV (ES11_MATERIALX + 1)
--#define ES11_MATRIXMODE (ES11_MATERIALXV + 1)
--#define ES11_MULTITEXCOORD4F (ES11_MATRIXMODE + 1)
--#define ES11_MULTITEXCOORD4X (ES11_MULTITEXCOORD4F + 1)
--#define ES11_MULTMATRIXF (ES11_MULTITEXCOORD4X + 1)
--#define ES11_MULTMATRIXX (ES11_MULTMATRIXF + 1)
--#define ES11_NORMAL3F (ES11_MULTMATRIXX + 1)
--#define ES11_NORMAL3X (ES11_NORMAL3F + 1)
--#define ES11_NORMALPOINTER (ES11_NORMAL3X + 1)
--#define ES11_ORTHOF (ES11_NORMALPOINTER + 1)
--#define ES11_ORTHOX (ES11_ORTHOF + 1)
--#define ES11_PIXELSTOREI (ES11_ORTHOX + 1)
--#define ES11_POINTPARAMETERF (ES11_PIXELSTOREI + 1)
--#define ES11_POINTPARAMETERFV (ES11_POINTPARAMETERF + 1)
--#define ES11_POINTPARAMETERX (ES11_POINTPARAMETERFV + 1)
--#define ES11_POINTPARAMETERXV (ES11_POINTPARAMETERX + 1)
--#define ES11_POINTSIZE (ES11_POINTPARAMETERXV + 1)
--#define ES11_POINTSIZEX (ES11_POINTSIZE + 1)
--#define ES11_POLYGONOFFSET (ES11_POINTSIZEX + 1)
--#define ES11_POLYGONOFFSETX (ES11_POLYGONOFFSET + 1)
--#define ES11_POPMATRIX (ES11_POLYGONOFFSETX + 1)
--#define ES11_PUSHMATRIX (ES11_POPMATRIX + 1)
--#define ES11_READPIXELS (ES11_PUSHMATRIX + 1)
--#define ES11_ROTATEF (ES11_READPIXELS + 1)
--#define ES11_ROTATEX (ES11_ROTATEF + 1)
--#define ES11_SAMPLECOVERAGE (ES11_ROTATEX + 1)
--#define ES11_SAMPLECOVERAGEX (ES11_SAMPLECOVERAGE + 1)
--#define ES11_SCALEF (ES11_SAMPLECOVERAGEX + 1)
--#define ES11_SCALEX (ES11_SCALEF + 1)
--#define ES11_SCISSOR (ES11_SCALEX + 1)
--#define ES11_SHADEMODEL (ES11_SCISSOR + 1)
--#define ES11_STENCILFUNC (ES11_SHADEMODEL + 1)
--#define ES11_STENCILMASK (ES11_STENCILFUNC + 1)
--#define ES11_STENCILOP (ES11_STENCILMASK + 1)
--#define ES11_TEXCOORDPOINTER (ES11_STENCILOP + 1)
--#define ES11_TEXENVF (ES11_TEXCOORDPOINTER + 1)
--#define ES11_TEXENVFV (ES11_TEXENVF + 1)
--#define ES11_TEXENVI (ES11_TEXENVFV + 1)
--#define ES11_TEXENVIV (ES11_TEXENVI + 1)
--#define ES11_TEXENVX (ES11_TEXENVIV + 1)
--#define ES11_TEXENVXV (ES11_TEXENVX + 1)
--#define ES11_TEXIMAGE2D (ES11_TEXENVXV + 1)
--#define ES11_TEXPARAMETERF (ES11_TEXIMAGE2D + 1)
--#define ES11_TEXPARAMETERFV (ES11_TEXPARAMETERF + 1)
--#define ES11_TEXPARAMETERI (ES11_TEXPARAMETERFV + 1)
--#define ES11_TEXPARAMETERIV (ES11_TEXPARAMETERI + 1)
--#define ES11_TEXPARAMETERX (ES11_TEXPARAMETERIV + 1)
--#define ES11_TEXPARAMETERXV (ES11_TEXPARAMETERX + 1)
--#define ES11_TEXSUBIMAGE2D (ES11_TEXPARAMETERXV + 1)
--#define ES11_TRANSLATEF (ES11_TEXSUBIMAGE2D + 1)
--#define ES11_TRANSLATEX (ES11_TRANSLATEF + 1)
--#define ES11_VERTEXPOINTER (ES11_TRANSLATEX + 1)
--#define ES11_VIEWPORT (ES11_VERTEXPOINTER + 1)
--#define ES11_BLENDEQUATIONOES (ES11_VIEWPORT + 1)
--#define ES11_BLENDFUNCSEPERATEOES (ES11_BLENDEQUATIONOES + 1)
--#define ES11_BLENDEQUATIONSEPARATEOES (ES11_BLENDFUNCSEPERATEOES + 1)
--#define ES11_GLMAPBUFFEROES (ES11_BLENDEQUATIONSEPARATEOES + 1)
--#define ES11_GLUNMAPBUFFEROES (ES11_GLMAPBUFFEROES + 1)
--#define ES11_GLGETBUFFERPOINTERVOES (ES11_GLUNMAPBUFFEROES + 1)
--#define ES11_CALLS (ES11_GLGETBUFFERPOINTERVOES + 1)
--#define ES11_DRAWCALLS (ES11_CALLS + 1)
--#define ES11_STATECHANGECALLS (ES11_DRAWCALLS + 1)
--#define ES11_POINTCOUNT (ES11_STATECHANGECALLS + 1)
--#define ES11_LINECOUNT (ES11_POINTCOUNT + 1)
--#define ES11_TRIANGLECOUNT (ES11_LINECOUNT + 1)
--
--/* OpenGL ES2X API IDs. */
--#define ES20_ACTIVETEXTURE 1
--#define ES20_ATTACHSHADER (ES20_ACTIVETEXTURE + 1)
--#define ES20_BINDATTRIBLOCATION (ES20_ATTACHSHADER + 1)
--#define ES20_BINDBUFFER (ES20_BINDATTRIBLOCATION + 1)
--#define ES20_BINDFRAMEBUFFER (ES20_BINDBUFFER + 1)
--#define ES20_BINDRENDERBUFFER (ES20_BINDFRAMEBUFFER + 1)
--#define ES20_BINDTEXTURE (ES20_BINDRENDERBUFFER + 1)
--#define ES20_BLENDCOLOR (ES20_BINDTEXTURE + 1)
--#define ES20_BLENDEQUATION (ES20_BLENDCOLOR + 1)
--#define ES20_BLENDEQUATIONSEPARATE (ES20_BLENDEQUATION + 1)
--#define ES20_BLENDFUNC (ES20_BLENDEQUATIONSEPARATE + 1)
--#define ES20_BLENDFUNCSEPARATE (ES20_BLENDFUNC + 1)
--#define ES20_BUFFERDATA (ES20_BLENDFUNCSEPARATE + 1)
--#define ES20_BUFFERSUBDATA (ES20_BUFFERDATA + 1)
--#define ES20_CHECKFRAMEBUFFERSTATUS (ES20_BUFFERSUBDATA + 1)
--#define ES20_CLEAR (ES20_CHECKFRAMEBUFFERSTATUS + 1)
--#define ES20_CLEARCOLOR (ES20_CLEAR + 1)
--#define ES20_CLEARDEPTHF (ES20_CLEARCOLOR + 1)
--#define ES20_CLEARSTENCIL (ES20_CLEARDEPTHF + 1)
--#define ES20_COLORMASK (ES20_CLEARSTENCIL + 1)
--#define ES20_COMPILESHADER (ES20_COLORMASK + 1)
--#define ES20_COMPRESSEDTEXIMAGE2D (ES20_COMPILESHADER + 1)
--#define ES20_COMPRESSEDTEXSUBIMAGE2D (ES20_COMPRESSEDTEXIMAGE2D + 1)
--#define ES20_COPYTEXIMAGE2D (ES20_COMPRESSEDTEXSUBIMAGE2D + 1)
--#define ES20_COPYTEXSUBIMAGE2D (ES20_COPYTEXIMAGE2D + 1)
--#define ES20_CREATEPROGRAM (ES20_COPYTEXSUBIMAGE2D + 1)
--#define ES20_CREATESHADER (ES20_CREATEPROGRAM + 1)
--#define ES20_CULLFACE (ES20_CREATESHADER + 1)
--#define ES20_DELETEBUFFERS (ES20_CULLFACE + 1)
--#define ES20_DELETEFRAMEBUFFERS (ES20_DELETEBUFFERS + 1)
--#define ES20_DELETEPROGRAM (ES20_DELETEFRAMEBUFFERS + 1)
--#define ES20_DELETERENDERBUFFERS (ES20_DELETEPROGRAM + 1)
--#define ES20_DELETESHADER (ES20_DELETERENDERBUFFERS + 1)
--#define ES20_DELETETEXTURES (ES20_DELETESHADER + 1)
--#define ES20_DEPTHFUNC (ES20_DELETETEXTURES + 1)
--#define ES20_DEPTHMASK (ES20_DEPTHFUNC + 1)
--#define ES20_DEPTHRANGEF (ES20_DEPTHMASK + 1)
--#define ES20_DETACHSHADER (ES20_DEPTHRANGEF + 1)
--#define ES20_DISABLE (ES20_DETACHSHADER + 1)
--#define ES20_DISABLEVERTEXATTRIBARRAY (ES20_DISABLE + 1)
--#define ES20_DRAWARRAYS (ES20_DISABLEVERTEXATTRIBARRAY + 1)
--#define ES20_DRAWELEMENTS (ES20_DRAWARRAYS + 1)
--#define ES20_ENABLE (ES20_DRAWELEMENTS + 1)
--#define ES20_ENABLEVERTEXATTRIBARRAY (ES20_ENABLE + 1)
--#define ES20_FINISH (ES20_ENABLEVERTEXATTRIBARRAY + 1)
--#define ES20_FLUSH (ES20_FINISH + 1)
--#define ES20_FRAMEBUFFERRENDERBUFFER (ES20_FLUSH + 1)
--#define ES20_FRAMEBUFFERTEXTURE2D (ES20_FRAMEBUFFERRENDERBUFFER + 1)
--#define ES20_FRONTFACE (ES20_FRAMEBUFFERTEXTURE2D + 1)
--#define ES20_GENBUFFERS (ES20_FRONTFACE + 1)
--#define ES20_GENERATEMIPMAP (ES20_GENBUFFERS + 1)
--#define ES20_GENFRAMEBUFFERS (ES20_GENERATEMIPMAP + 1)
--#define ES20_GENRENDERBUFFERS (ES20_GENFRAMEBUFFERS + 1)
--#define ES20_GENTEXTURES (ES20_GENRENDERBUFFERS + 1)
--#define ES20_GETACTIVEATTRIB (ES20_GENTEXTURES + 1)
--#define ES20_GETACTIVEUNIFORM (ES20_GETACTIVEATTRIB + 1)
--#define ES20_GETATTACHEDSHADERS (ES20_GETACTIVEUNIFORM + 1)
--#define ES20_GETATTRIBLOCATION (ES20_GETATTACHEDSHADERS + 1)
--#define ES20_GETBOOLEANV (ES20_GETATTRIBLOCATION + 1)
--#define ES20_GETBUFFERPARAMETERIV (ES20_GETBOOLEANV + 1)
--#define ES20_GETERROR (ES20_GETBUFFERPARAMETERIV + 1)
--#define ES20_GETFLOATV (ES20_GETERROR + 1)
--#define ES20_GETFRAMEBUFFERATTACHMENTPARAMETERIV (ES20_GETFLOATV + 1)
--#define ES20_GETINTEGERV (ES20_GETFRAMEBUFFERATTACHMENTPARAMETERIV + 1)
--#define ES20_GETPROGRAMIV (ES20_GETINTEGERV + 1)
--#define ES20_GETPROGRAMINFOLOG (ES20_GETPROGRAMIV + 1)
--#define ES20_GETRENDERBUFFERPARAMETERIV (ES20_GETPROGRAMINFOLOG + 1)
--#define ES20_GETSHADERIV (ES20_GETRENDERBUFFERPARAMETERIV + 1)
--#define ES20_GETSHADERINFOLOG (ES20_GETSHADERIV + 1)
--#define ES20_GETSHADERPRECISIONFORMAT (ES20_GETSHADERINFOLOG + 1)
--#define ES20_GETSHADERSOURCE (ES20_GETSHADERPRECISIONFORMAT + 1)
--#define ES20_GETSTRING (ES20_GETSHADERSOURCE + 1)
--#define ES20_GETTEXPARAMETERFV (ES20_GETSTRING + 1)
--#define ES20_GETTEXPARAMETERIV (ES20_GETTEXPARAMETERFV + 1)
--#define ES20_GETUNIFORMFV (ES20_GETTEXPARAMETERIV + 1)
--#define ES20_GETUNIFORMIV (ES20_GETUNIFORMFV + 1)
--#define ES20_GETUNIFORMLOCATION (ES20_GETUNIFORMIV + 1)
--#define ES20_GETVERTEXATTRIBFV (ES20_GETUNIFORMLOCATION + 1)
--#define ES20_GETVERTEXATTRIBIV (ES20_GETVERTEXATTRIBFV + 1)
--#define ES20_GETVERTEXATTRIBPOINTERV (ES20_GETVERTEXATTRIBIV + 1)
--#define ES20_HINT (ES20_GETVERTEXATTRIBPOINTERV + 1)
--#define ES20_ISBUFFER (ES20_HINT + 1)
--#define ES20_ISENABLED (ES20_ISBUFFER + 1)
--#define ES20_ISFRAMEBUFFER (ES20_ISENABLED + 1)
--#define ES20_ISPROGRAM (ES20_ISFRAMEBUFFER + 1)
--#define ES20_ISRENDERBUFFER (ES20_ISPROGRAM + 1)
--#define ES20_ISSHADER (ES20_ISRENDERBUFFER + 1)
--#define ES20_ISTEXTURE (ES20_ISSHADER + 1)
--#define ES20_LINEWIDTH (ES20_ISTEXTURE + 1)
--#define ES20_LINKPROGRAM (ES20_LINEWIDTH + 1)
--#define ES20_PIXELSTOREI (ES20_LINKPROGRAM + 1)
--#define ES20_POLYGONOFFSET (ES20_PIXELSTOREI + 1)
--#define ES20_READPIXELS (ES20_POLYGONOFFSET + 1)
--#define ES20_RELEASESHADERCOMPILER (ES20_READPIXELS + 1)
--#define ES20_RENDERBUFFERSTORAGE (ES20_RELEASESHADERCOMPILER + 1)
--#define ES20_SAMPLECOVERAGE (ES20_RENDERBUFFERSTORAGE + 1)
--#define ES20_SCISSOR (ES20_SAMPLECOVERAGE + 1)
--#define ES20_SHADERBINARY (ES20_SCISSOR + 1)
--#define ES20_SHADERSOURCE (ES20_SHADERBINARY + 1)
--#define ES20_STENCILFUNC (ES20_SHADERSOURCE + 1)
--#define ES20_STENCILFUNCSEPARATE (ES20_STENCILFUNC + 1)
--#define ES20_STENCILMASK (ES20_STENCILFUNCSEPARATE + 1)
--#define ES20_STENCILMASKSEPARATE (ES20_STENCILMASK + 1)
--#define ES20_STENCILOP (ES20_STENCILMASKSEPARATE + 1)
--#define ES20_STENCILOPSEPARATE (ES20_STENCILOP + 1)
--#define ES20_TEXIMAGE2D (ES20_STENCILOPSEPARATE + 1)
--#define ES20_TEXPARAMETERF (ES20_TEXIMAGE2D + 1)
--#define ES20_TEXPARAMETERFV (ES20_TEXPARAMETERF + 1)
--#define ES20_TEXPARAMETERI (ES20_TEXPARAMETERFV + 1)
--#define ES20_TEXPARAMETERIV (ES20_TEXPARAMETERI + 1)
--#define ES20_TEXSUBIMAGE2D (ES20_TEXPARAMETERIV + 1)
--#define ES20_UNIFORM1F (ES20_TEXSUBIMAGE2D + 1)
--#define ES20_UNIFORM1FV (ES20_UNIFORM1F + 1)
--#define ES20_UNIFORM1I (ES20_UNIFORM1FV + 1)
--#define ES20_UNIFORM1IV (ES20_UNIFORM1I + 1)
--#define ES20_UNIFORM2F (ES20_UNIFORM1IV + 1)
--#define ES20_UNIFORM2FV (ES20_UNIFORM2F + 1)
--#define ES20_UNIFORM2I (ES20_UNIFORM2FV + 1)
--#define ES20_UNIFORM2IV (ES20_UNIFORM2I + 1)
--#define ES20_UNIFORM3F (ES20_UNIFORM2IV + 1)
--#define ES20_UNIFORM3FV (ES20_UNIFORM3F + 1)
--#define ES20_UNIFORM3I (ES20_UNIFORM3FV + 1)
--#define ES20_UNIFORM3IV (ES20_UNIFORM3I + 1)
--#define ES20_UNIFORM4F (ES20_UNIFORM3IV + 1)
--#define ES20_UNIFORM4FV (ES20_UNIFORM4F + 1)
--#define ES20_UNIFORM4I (ES20_UNIFORM4FV + 1)
--#define ES20_UNIFORM4IV (ES20_UNIFORM4I + 1)
--#define ES20_UNIFORMMATRIX2FV (ES20_UNIFORM4IV + 1)
--#define ES20_UNIFORMMATRIX3FV (ES20_UNIFORMMATRIX2FV + 1)
--#define ES20_UNIFORMMATRIX4FV (ES20_UNIFORMMATRIX3FV + 1)
--#define ES20_USEPROGRAM (ES20_UNIFORMMATRIX4FV + 1)
--#define ES20_VALIDATEPROGRAM (ES20_USEPROGRAM + 1)
--#define ES20_VERTEXATTRIB1F (ES20_VALIDATEPROGRAM + 1)
--#define ES20_VERTEXATTRIB1FV (ES20_VERTEXATTRIB1F + 1)
--#define ES20_VERTEXATTRIB2F (ES20_VERTEXATTRIB1FV + 1)
--#define ES20_VERTEXATTRIB2FV (ES20_VERTEXATTRIB2F + 1)
--#define ES20_VERTEXATTRIB3F (ES20_VERTEXATTRIB2FV + 1)
--#define ES20_VERTEXATTRIB3FV (ES20_VERTEXATTRIB3F + 1)
--#define ES20_VERTEXATTRIB4F (ES20_VERTEXATTRIB3FV + 1)
--#define ES20_VERTEXATTRIB4FV (ES20_VERTEXATTRIB4F + 1)
--#define ES20_VERTEXATTRIBPOINTER (ES20_VERTEXATTRIB4FV + 1)
--#define ES20_VIEWPORT (ES20_VERTEXATTRIBPOINTER + 1)
--#define ES20_GETPROGRAMBINARYOES (ES20_VIEWPORT + 1)
--#define ES20_PROGRAMBINARYOES (ES20_GETPROGRAMBINARYOES + 1)
--#define ES20_TEXIMAGE3DOES (ES20_PROGRAMBINARYOES + 1)
--#define ES20_TEXSUBIMAGE3DOES (ES20_TEXIMAGE3DOES + 1)
--#define ES20_COPYSUBIMAGE3DOES (ES20_TEXSUBIMAGE3DOES + 1)
--#define ES20_COMPRESSEDTEXIMAGE3DOES (ES20_COPYSUBIMAGE3DOES + 1)
--#define ES20_COMPRESSEDTEXSUBIMAGE3DOES (ES20_COMPRESSEDTEXIMAGE3DOES + 1)
--#define ES20_FRAMEBUFFERTEXTURE3DOES (ES20_COMPRESSEDTEXSUBIMAGE3DOES + 1)
--#define ES20_BINDVERTEXARRAYOES (ES20_FRAMEBUFFERTEXTURE3DOES + 1)
--#define ES20_GENVERTEXARRAYOES (ES20_BINDVERTEXARRAYOES + 1)
--#define ES20_ISVERTEXARRAYOES (ES20_GENVERTEXARRAYOES + 1)
--#define ES20_DELETEVERTEXARRAYOES (ES20_ISVERTEXARRAYOES + 1)
--#define ES20_GLMAPBUFFEROES (ES20_DELETEVERTEXARRAYOES + 1)
--#define ES20_GLUNMAPBUFFEROES (ES20_GLMAPBUFFEROES + 1)
--#define ES20_GLGETBUFFERPOINTERVOES (ES20_GLUNMAPBUFFEROES + 1)
--#define ES20_DISCARDFRAMEBUFFEREXT (ES20_GLGETBUFFERPOINTERVOES + 1)
--#define ES20_CALLS (ES20_DISCARDFRAMEBUFFEREXT + 1)
--#define ES20_DRAWCALLS (ES20_CALLS + 1)
--#define ES20_STATECHANGECALLS (ES20_DRAWCALLS + 1)
--#define ES20_POINTCOUNT (ES20_STATECHANGECALLS + 1)
--#define ES20_LINECOUNT (ES20_POINTCOUNT + 1)
--#define ES20_TRIANGLECOUNT (ES20_LINECOUNT + 1)
--
--/* OpenVG API IDs. */
--#define VG11_APPENDPATH 1
--#define VG11_APPENDPATHDATA (VG11_APPENDPATH + 1)
--#define VG11_CHILDIMAGE (VG11_APPENDPATHDATA + 1)
--#define VG11_CLEAR (VG11_CHILDIMAGE + 1)
--#define VG11_CLEARGLYPH (VG11_CLEAR + 1)
--#define VG11_CLEARIMAGE (VG11_CLEARGLYPH + 1)
--#define VG11_CLEARPATH (VG11_CLEARIMAGE + 1)
--#define VG11_COLORMATRIX (VG11_CLEARPATH + 1)
--#define VG11_CONVOLVE (VG11_COLORMATRIX + 1)
--#define VG11_COPYIMAGE (VG11_CONVOLVE + 1)
--#define VG11_COPYMASK (VG11_COPYIMAGE + 1)
--#define VG11_COPYPIXELS (VG11_COPYMASK + 1)
--#define VG11_CREATEFONT (VG11_COPYPIXELS + 1)
--#define VG11_CREATEIMAGE (VG11_CREATEFONT + 1)
--#define VG11_CREATEMASKLAYER (VG11_CREATEIMAGE + 1)
--#define VG11_CREATEPAINT (VG11_CREATEMASKLAYER + 1)
--#define VG11_CREATEPATH (VG11_CREATEPAINT + 1)
--#define VG11_DESTROYFONT (VG11_CREATEPATH + 1)
--#define VG11_DESTROYIMAGE (VG11_DESTROYFONT + 1)
--#define VG11_DESTROYMASKLAYER (VG11_DESTROYIMAGE + 1)
--#define VG11_DESTROYPAINT (VG11_DESTROYMASKLAYER + 1)
--#define VG11_DESTROYPATH (VG11_DESTROYPAINT + 1)
--#define VG11_DRAWGLYPH (VG11_DESTROYPATH + 1)
--#define VG11_DRAWGLYPHS (VG11_DRAWGLYPH + 1)
--#define VG11_DRAWIMAGE (VG11_DRAWGLYPHS + 1)
--#define VG11_DRAWPATH (VG11_DRAWIMAGE + 1)
--#define VG11_FILLMASKLAYER (VG11_DRAWPATH + 1)
--#define VG11_FINISH (VG11_FILLMASKLAYER + 1)
--#define VG11_FLUSH (VG11_FINISH + 1)
--#define VG11_GAUSSIANBLUR (VG11_FLUSH + 1)
--#define VG11_GETCOLOR (VG11_GAUSSIANBLUR + 1)
--#define VG11_GETERROR (VG11_GETCOLOR + 1)
--#define VG11_GETF (VG11_GETERROR + 1)
--#define VG11_GETFV (VG11_GETF + 1)
--#define VG11_GETI (VG11_GETFV + 1)
--#define VG11_GETIMAGESUBDATA (VG11_GETI + 1)
--#define VG11_GETIV (VG11_GETIMAGESUBDATA + 1)
--#define VG11_GETMATRIX (VG11_GETIV + 1)
--#define VG11_GETPAINT (VG11_GETMATRIX + 1)
--#define VG11_GETPARAMETERF (VG11_GETPAINT + 1)
--#define VG11_GETPARAMETERFV (VG11_GETPARAMETERF + 1)
--#define VG11_GETPARAMETERI (VG11_GETPARAMETERFV + 1)
--#define VG11_GETPARAMETERIV (VG11_GETPARAMETERI + 1)
--#define VG11_GETPARAMETERVECTORSIZE (VG11_GETPARAMETERIV + 1)
--#define VG11_GETPARENT (VG11_GETPARAMETERVECTORSIZE + 1)
--#define VG11_GETPATHCAPABILITIES (VG11_GETPARENT + 1)
--#define VG11_GETPIXELS (VG11_GETPATHCAPABILITIES + 1)
--#define VG11_GETSTRING (VG11_GETPIXELS + 1)
--#define VG11_GETVECTORSIZE (VG11_GETSTRING + 1)
--#define VG11_HARDWAREQUERY (VG11_GETVECTORSIZE + 1)
--#define VG11_IMAGESUBDATA (VG11_HARDWAREQUERY + 1)
--#define VG11_INTERPOLATEPATH (VG11_IMAGESUBDATA + 1)
--#define VG11_LOADIDENTITY (VG11_INTERPOLATEPATH + 1)
--#define VG11_LOADMATRIX (VG11_LOADIDENTITY + 1)
--#define VG11_LOOKUP (VG11_LOADMATRIX + 1)
--#define VG11_LOOKUPSINGLE (VG11_LOOKUP + 1)
--#define VG11_MASK (VG11_LOOKUPSINGLE + 1)
--#define VG11_MODIFYPATHCOORDS (VG11_MASK + 1)
--#define VG11_MULTMATRIX (VG11_MODIFYPATHCOORDS + 1)
--#define VG11_PAINTPATTERN (VG11_MULTMATRIX + 1)
--#define VG11_PATHBOUNDS (VG11_PAINTPATTERN + 1)
--#define VG11_PATHLENGTH (VG11_PATHBOUNDS + 1)
--#define VG11_PATHTRANSFORMEDBOUNDS (VG11_PATHLENGTH + 1)
--#define VG11_POINTALONGPATH (VG11_PATHTRANSFORMEDBOUNDS + 1)
--#define VG11_READPIXELS (VG11_POINTALONGPATH + 1)
--#define VG11_REMOVEPATHCAPABILITIES (VG11_READPIXELS + 1)
--#define VG11_RENDERTOMASK (VG11_REMOVEPATHCAPABILITIES + 1)
--#define VG11_ROTATE (VG11_RENDERTOMASK + 1)
--#define VG11_SCALE (VG11_ROTATE + 1)
--#define VG11_SEPARABLECONVOLVE (VG11_SCALE + 1)
--#define VG11_SETCOLOR (VG11_SEPARABLECONVOLVE + 1)
--#define VG11_SETF (VG11_SETCOLOR + 1)
--#define VG11_SETFV (VG11_SETF + 1)
--#define VG11_SETGLYPHTOIMAGE (VG11_SETFV + 1)
--#define VG11_SETGLYPHTOPATH (VG11_SETGLYPHTOIMAGE + 1)
--#define VG11_SETI (VG11_SETGLYPHTOPATH + 1)
--#define VG11_SETIV (VG11_SETI + 1)
--#define VG11_SETPAINT (VG11_SETIV + 1)
--#define VG11_SETPARAMETERF (VG11_SETPAINT + 1)
--#define VG11_SETPARAMETERFV (VG11_SETPARAMETERF + 1)
--#define VG11_SETPARAMETERI (VG11_SETPARAMETERFV + 1)
--#define VG11_SETPARAMETERIV (VG11_SETPARAMETERI + 1)
--#define VG11_SETPIXELS (VG11_SETPARAMETERIV + 1)
--#define VG11_SHEAR (VG11_SETPIXELS + 1)
--#define VG11_TRANSFORMPATH (VG11_SHEAR + 1)
--#define VG11_TRANSLATE (VG11_TRANSFORMPATH + 1)
--#define VG11_WRITEPIXELS (VG11_TRANSLATE + 1)
--#define VG11_CALLS (VG11_WRITEPIXELS + 1)
--#define VG11_DRAWCALLS (VG11_CALLS + 1)
--#define VG11_STATECHANGECALLS (VG11_DRAWCALLS + 1)
--#define VG11_FILLCOUNT (VG11_STATECHANGECALLS + 1)
--#define VG11_STROKECOUNT (VG11_FILLCOUNT + 1)
-+#define ES11_CALLS 151
-+#define ES11_DRAWCALLS (ES11_CALLS + 1)
-+#define ES11_STATECHANGECALLS (ES11_DRAWCALLS + 1)
-+#define ES11_POINTCOUNT (ES11_STATECHANGECALLS + 1)
-+#define ES11_LINECOUNT (ES11_POINTCOUNT + 1)
-+#define ES11_TRIANGLECOUNT (ES11_LINECOUNT + 1)
-+
-+#define ES20_CALLS 159
-+#define ES20_DRAWCALLS (ES20_CALLS + 1)
-+#define ES20_STATECHANGECALLS (ES20_DRAWCALLS + 1)
-+#define ES20_POINTCOUNT (ES20_STATECHANGECALLS + 1)
-+#define ES20_LINECOUNT (ES20_POINTCOUNT + 1)
-+#define ES20_TRIANGLECOUNT (ES20_LINECOUNT + 1)
-+
-+#define VG11_CALLS 88
-+#define VG11_DRAWCALLS (VG11_CALLS + 1)
-+#define VG11_STATECHANGECALLS (VG11_DRAWCALLS + 1)
-+#define VG11_FILLCOUNT (VG11_STATECHANGECALLS + 1)
-+#define VG11_STROKECOUNT (VG11_FILLCOUNT + 1)
- /* End of Driver API ID Definitions. */
-
- /* HAL & MISC IDs. */
--#define HAL_VERTBUFNEWBYTEALLOC 1
--#define HAL_VERTBUFTOTALBYTEALLOC (HAL_VERTBUFNEWBYTEALLOC + 1)
--#define HAL_VERTBUFNEWOBJALLOC (HAL_VERTBUFTOTALBYTEALLOC + 1)
--#define HAL_VERTBUFTOTALOBJALLOC (HAL_VERTBUFNEWOBJALLOC + 1)
--#define HAL_INDBUFNEWBYTEALLOC (HAL_VERTBUFTOTALOBJALLOC + 1)
--#define HAL_INDBUFTOTALBYTEALLOC (HAL_INDBUFNEWBYTEALLOC + 1)
--#define HAL_INDBUFNEWOBJALLOC (HAL_INDBUFTOTALBYTEALLOC + 1)
--#define HAL_INDBUFTOTALOBJALLOC (HAL_INDBUFNEWOBJALLOC + 1)
--#define HAL_TEXBUFNEWBYTEALLOC (HAL_INDBUFTOTALOBJALLOC + 1)
--#define HAL_TEXBUFTOTALBYTEALLOC (HAL_TEXBUFNEWBYTEALLOC + 1)
--#define HAL_TEXBUFNEWOBJALLOC (HAL_TEXBUFTOTALBYTEALLOC + 1)
--#define HAL_TEXBUFTOTALOBJALLOC (HAL_TEXBUFNEWOBJALLOC + 1)
--
--#define GPU_CYCLES 1
--#define GPU_READ64BYTE (GPU_CYCLES + 1)
--#define GPU_WRITE64BYTE (GPU_READ64BYTE + 1)
--#define GPU_TOTALCYCLES (GPU_WRITE64BYTE + 1)
--#define GPU_IDLECYCLES (GPU_TOTALCYCLES + 1)
--
--#define VS_INSTCOUNT 1
--#define VS_BRANCHINSTCOUNT (VS_INSTCOUNT + 1)
--#define VS_TEXLDINSTCOUNT (VS_BRANCHINSTCOUNT + 1)
--#define VS_RENDEREDVERTCOUNT (VS_TEXLDINSTCOUNT + 1)
--
--#define PS_INSTCOUNT 1
--#define PS_BRANCHINSTCOUNT (PS_INSTCOUNT + 1)
--#define PS_TEXLDINSTCOUNT (PS_BRANCHINSTCOUNT + 1)
--#define PS_RENDEREDPIXCOUNT (PS_TEXLDINSTCOUNT + 1)
--
--#define PA_INVERTCOUNT 1
--#define PA_INPRIMCOUNT (PA_INVERTCOUNT + 1)
--#define PA_OUTPRIMCOUNT (PA_INPRIMCOUNT + 1)
--#define PA_DEPTHCLIPCOUNT (PA_OUTPRIMCOUNT + 1)
--#define PA_TRIVIALREJCOUNT (PA_DEPTHCLIPCOUNT + 1)
--#define PA_CULLCOUNT (PA_TRIVIALREJCOUNT + 1)
--
--#define SE_TRIANGLECOUNT 1
--#define SE_LINECOUNT (SE_TRIANGLECOUNT + 1)
--
--#define RA_VALIDPIXCOUNT 1
--#define RA_TOTALQUADCOUNT (RA_VALIDPIXCOUNT + 1)
--#define RA_VALIDQUADCOUNTEZ (RA_TOTALQUADCOUNT + 1)
--#define RA_TOTALPRIMCOUNT (RA_VALIDQUADCOUNTEZ + 1)
--#define RA_PIPECACHEMISSCOUNT (RA_TOTALPRIMCOUNT + 1)
--#define RA_PREFCACHEMISSCOUNT (RA_PIPECACHEMISSCOUNT + 1)
--#define RA_EEZCULLCOUNT (RA_PREFCACHEMISSCOUNT + 1)
--
--#define TX_TOTBILINEARREQ 1
--#define TX_TOTTRILINEARREQ (TX_TOTBILINEARREQ + 1)
--#define TX_TOTDISCARDTEXREQ (TX_TOTTRILINEARREQ + 1)
--#define TX_TOTTEXREQ (TX_TOTDISCARDTEXREQ + 1)
--#define TX_MEMREADCOUNT (TX_TOTTEXREQ + 1)
--#define TX_MEMREADIN8BCOUNT (TX_MEMREADCOUNT + 1)
--#define TX_CACHEMISSCOUNT (TX_MEMREADIN8BCOUNT + 1)
--#define TX_CACHEHITTEXELCOUNT (TX_CACHEMISSCOUNT + 1)
--#define TX_CACHEMISSTEXELCOUNT (TX_CACHEHITTEXELCOUNT + 1)
--
--#define PE_KILLEDBYCOLOR 1
--#define PE_KILLEDBYDEPTH (PE_KILLEDBYCOLOR + 1)
--#define PE_DRAWNBYCOLOR (PE_KILLEDBYDEPTH + 1)
--#define PE_DRAWNBYDEPTH (PE_DRAWNBYCOLOR + 1)
--
--#define MC_READREQ8BPIPE 1
--#define MC_READREQ8BIP (MC_READREQ8BPIPE + 1)
--#define MC_WRITEREQ8BPIPE (MC_READREQ8BIP + 1)
--
--#define AXI_READREQSTALLED 1
--#define AXI_WRITEREQSTALLED (AXI_READREQSTALLED + 1)
--#define AXI_WRITEDATASTALLED (AXI_WRITEREQSTALLED + 1)
--
--#define PVS_INSTRCOUNT 1
--#define PVS_ALUINSTRCOUNT (PVS_INSTRCOUNT + 1)
--#define PVS_TEXINSTRCOUNT (PVS_ALUINSTRCOUNT + 1)
--#define PVS_ATTRIBCOUNT (PVS_TEXINSTRCOUNT + 1)
--#define PVS_UNIFORMCOUNT (PVS_ATTRIBCOUNT + 1)
--#define PVS_FUNCTIONCOUNT (PVS_UNIFORMCOUNT + 1)
--
--#define PPS_INSTRCOUNT 1
--#define PPS_ALUINSTRCOUNT (PPS_INSTRCOUNT + 1)
--#define PPS_TEXINSTRCOUNT (PPS_ALUINSTRCOUNT + 1)
--#define PPS_ATTRIBCOUNT (PPS_TEXINSTRCOUNT + 1)
--#define PPS_UNIFORMCOUNT (PPS_ATTRIBCOUNT + 1)
--#define PPS_FUNCTIONCOUNT (PPS_UNIFORMCOUNT + 1)
-+#define HAL_VERTBUFNEWBYTEALLOC 1
-+#define HAL_VERTBUFTOTALBYTEALLOC (HAL_VERTBUFNEWBYTEALLOC + 1)
-+#define HAL_VERTBUFNEWOBJALLOC (HAL_VERTBUFTOTALBYTEALLOC + 1)
-+#define HAL_VERTBUFTOTALOBJALLOC (HAL_VERTBUFNEWOBJALLOC + 1)
-+#define HAL_INDBUFNEWBYTEALLOC (HAL_VERTBUFTOTALOBJALLOC + 1)
-+#define HAL_INDBUFTOTALBYTEALLOC (HAL_INDBUFNEWBYTEALLOC + 1)
-+#define HAL_INDBUFNEWOBJALLOC (HAL_INDBUFTOTALBYTEALLOC + 1)
-+#define HAL_INDBUFTOTALOBJALLOC (HAL_INDBUFNEWOBJALLOC + 1)
-+#define HAL_TEXBUFNEWBYTEALLOC (HAL_INDBUFTOTALOBJALLOC + 1)
-+#define HAL_TEXBUFTOTALBYTEALLOC (HAL_TEXBUFNEWBYTEALLOC + 1)
-+#define HAL_TEXBUFNEWOBJALLOC (HAL_TEXBUFTOTALBYTEALLOC + 1)
-+#define HAL_TEXBUFTOTALOBJALLOC (HAL_TEXBUFNEWOBJALLOC + 1)
-+
-+#define GPU_CYCLES 1
-+#define GPU_READ64BYTE (GPU_CYCLES + 1)
-+#define GPU_WRITE64BYTE (GPU_READ64BYTE + 1)
-+#define GPU_TOTALCYCLES (GPU_WRITE64BYTE + 1)
-+#define GPU_IDLECYCLES (GPU_TOTALCYCLES + 1)
-+
-+#define VS_INSTCOUNT 1
-+#define VS_BRANCHINSTCOUNT (VS_INSTCOUNT + 1)
-+#define VS_TEXLDINSTCOUNT (VS_BRANCHINSTCOUNT + 1)
-+#define VS_RENDEREDVERTCOUNT (VS_TEXLDINSTCOUNT + 1)
-+#define VS_SOURCE (VS_RENDEREDVERTCOUNT + 1)
-+
-+#define PS_INSTCOUNT 1
-+#define PS_BRANCHINSTCOUNT (PS_INSTCOUNT + 1)
-+#define PS_TEXLDINSTCOUNT (PS_BRANCHINSTCOUNT + 1)
-+#define PS_RENDEREDPIXCOUNT (PS_TEXLDINSTCOUNT + 1)
-+#define PS_SOURCE (PS_RENDEREDPIXCOUNT + 1)
-+
-+#define PA_INVERTCOUNT 1
-+#define PA_INPRIMCOUNT (PA_INVERTCOUNT + 1)
-+#define PA_OUTPRIMCOUNT (PA_INPRIMCOUNT + 1)
-+#define PA_DEPTHCLIPCOUNT (PA_OUTPRIMCOUNT + 1)
-+#define PA_TRIVIALREJCOUNT (PA_DEPTHCLIPCOUNT + 1)
-+#define PA_CULLCOUNT (PA_TRIVIALREJCOUNT + 1)
-+
-+#define SE_TRIANGLECOUNT 1
-+#define SE_LINECOUNT (SE_TRIANGLECOUNT + 1)
-+
-+#define RA_VALIDPIXCOUNT 1
-+#define RA_TOTALQUADCOUNT (RA_VALIDPIXCOUNT + 1)
-+#define RA_VALIDQUADCOUNTEZ (RA_TOTALQUADCOUNT + 1)
-+#define RA_TOTALPRIMCOUNT (RA_VALIDQUADCOUNTEZ + 1)
-+#define RA_PIPECACHEMISSCOUNT (RA_TOTALPRIMCOUNT + 1)
-+#define RA_PREFCACHEMISSCOUNT (RA_PIPECACHEMISSCOUNT + 1)
-+#define RA_EEZCULLCOUNT (RA_PREFCACHEMISSCOUNT + 1)
-+
-+#define TX_TOTBILINEARREQ 1
-+#define TX_TOTTRILINEARREQ (TX_TOTBILINEARREQ + 1)
-+#define TX_TOTDISCARDTEXREQ (TX_TOTTRILINEARREQ + 1)
-+#define TX_TOTTEXREQ (TX_TOTDISCARDTEXREQ + 1)
-+#define TX_MEMREADCOUNT (TX_TOTTEXREQ + 1)
-+#define TX_MEMREADIN8BCOUNT (TX_MEMREADCOUNT + 1)
-+#define TX_CACHEMISSCOUNT (TX_MEMREADIN8BCOUNT + 1)
-+#define TX_CACHEHITTEXELCOUNT (TX_CACHEMISSCOUNT + 1)
-+#define TX_CACHEMISSTEXELCOUNT (TX_CACHEHITTEXELCOUNT + 1)
-+
-+#define PE_KILLEDBYCOLOR 1
-+#define PE_KILLEDBYDEPTH (PE_KILLEDBYCOLOR + 1)
-+#define PE_DRAWNBYCOLOR (PE_KILLEDBYDEPTH + 1)
-+#define PE_DRAWNBYDEPTH (PE_DRAWNBYCOLOR + 1)
-+
-+#define MC_READREQ8BPIPE 1
-+#define MC_READREQ8BIP (MC_READREQ8BPIPE + 1)
-+#define MC_WRITEREQ8BPIPE (MC_READREQ8BIP + 1)
-+
-+#define AXI_READREQSTALLED 1
-+#define AXI_WRITEREQSTALLED (AXI_READREQSTALLED + 1)
-+#define AXI_WRITEDATASTALLED (AXI_WRITEREQSTALLED + 1)
-+
-+#define PVS_INSTRCOUNT 1
-+#define PVS_ALUINSTRCOUNT (PVS_INSTRCOUNT + 1)
-+#define PVS_TEXINSTRCOUNT (PVS_ALUINSTRCOUNT + 1)
-+#define PVS_ATTRIBCOUNT (PVS_TEXINSTRCOUNT + 1)
-+#define PVS_UNIFORMCOUNT (PVS_ATTRIBCOUNT + 1)
-+#define PVS_FUNCTIONCOUNT (PVS_UNIFORMCOUNT + 1)
-+#define PVS_SOURCE (PVS_FUNCTIONCOUNT + 1)
-+
-+#define PPS_INSTRCOUNT 1
-+#define PPS_ALUINSTRCOUNT (PPS_INSTRCOUNT + 1)
-+#define PPS_TEXINSTRCOUNT (PPS_ALUINSTRCOUNT + 1)
-+#define PPS_ATTRIBCOUNT (PPS_TEXINSTRCOUNT + 1)
-+#define PPS_UNIFORMCOUNT (PPS_ATTRIBCOUNT + 1)
-+#define PPS_FUNCTIONCOUNT (PPS_UNIFORMCOUNT + 1)
-+#define PPS_SOURCE (PPS_FUNCTIONCOUNT + 1)
- /* End of MISC Counter IDs. */
-
- #ifdef gcdNEW_PROFILER_FILE
-@@ -578,8 +184,8 @@ extern "C" {
- #define VPG_ES11_TIME 0x170000
- #define VPG_ES20_TIME 0x180000
- #define VPG_FRAME 0x190000
--#define VPG_ES11_DRAW 0x200000
--#define VPG_ES20_DRAW 0x210000
-+#define VPG_ES11_DRAW 0x200000
-+#define VPG_ES20_DRAW 0x210000
- #define VPG_END 0xff0000
-
- /* Info. */
-@@ -592,7 +198,7 @@ extern "C" {
- #define VPC_INFOSCREENSIZE (VPC_INFODRIVERMODE + 1)
-
- /* Counter Constants. */
--#define VPC_ELAPSETIME (VPG_TIME + 1)
-+#define VPC_ELAPSETIME (VPG_TIME + 1)
- #define VPC_CPUTIME (VPC_ELAPSETIME + 1)
-
- #define VPC_MEMMAXRES (VPG_MEM + 1)
-@@ -600,404 +206,28 @@ extern "C" {
- #define VPC_MEMUNSHAREDDATA (VPC_MEMSHARED + 1)
- #define VPC_MEMUNSHAREDSTACK (VPC_MEMUNSHAREDDATA + 1)
-
--/* OpenGL ES11 Counters. */
--#define VPC_ES11ACTIVETEXTURE (VPG_ES11 + ES11_ACTIVETEXTURE)
--#define VPC_ES11ALPHAFUNC (VPG_ES11 + ES11_ALPHAFUNC)
--#define VPC_ES11ALPHAFUNCX (VPG_ES11 + ES11_ALPHAFUNCX)
--#define VPC_ES11BINDBUFFER (VPG_ES11 + ES11_BINDBUFFER)
--#define VPC_ES11BINDTEXTURE (VPG_ES11 + ES11_BINDTEXTURE)
--#define VPC_ES11BLENDFUNC (VPG_ES11 + ES11_BLENDFUNC)
--#define VPC_ES11BUFFERDATA (VPG_ES11 + ES11_BUFFERDATA)
--#define VPC_ES11BUFFERSUBDATA (VPG_ES11 + ES11_BUFFERSUBDATA)
--#define VPC_ES11CLEAR (VPG_ES11 + ES11_CLEAR)
--#define VPC_ES11CLEARCOLOR (VPG_ES11 + ES11_CLEARCOLOR)
--#define VPC_ES11CLEARCOLORX (VPG_ES11 + ES11_CLEARCOLORX)
--#define VPC_ES11CLEARDEPTHF (VPG_ES11 + ES11_CLEARDEPTHF)
--#define VPC_ES11CLEARDEPTHX (VPG_ES11 + ES11_CLEARDEPTHX)
--#define VPC_ES11CLEARSTENCIL (VPG_ES11 + ES11_CLEARSTENCIL)
--#define VPC_ES11CLIENTACTIVETEXTURE (VPG_ES11 + ES11_CLIENTACTIVETEXTURE)
--#define VPC_ES11CLIPPLANEF (VPG_ES11 + ES11_CLIPPLANEF)
--#define VPC_ES11CLIPPLANEX (VPG_ES11 + ES11_CLIPPLANEX)
--#define VPC_ES11COLOR4F (VPG_ES11 + ES11_COLOR4F)
--#define VPC_ES11COLOR4UB (VPG_ES11 + ES11_COLOR4UB)
--#define VPC_ES11COLOR4X (VPG_ES11 + ES11_COLOR4X)
--#define VPC_ES11COLORMASK (VPG_ES11 + ES11_COLORMASK)
--#define VPC_ES11COLORPOINTER (VPG_ES11 + ES11_COLORPOINTER)
--#define VPC_ES11COMPRESSEDTEXIMAGE2D (VPG_ES11 + ES11_COMPRESSEDTEXIMAGE2D)
--#define VPC_ES11COMPRESSEDTEXSUBIMAGE2D (VPG_ES11 + ES11_COMPRESSEDTEXSUBIMAGE2D)
--#define VPC_ES11COPYTEXIMAGE2D (VPG_ES11 + ES11_COPYTEXIMAGE2D)
--#define VPC_ES11COPYTEXSUBIMAGE2D (VPG_ES11 + ES11_COPYTEXSUBIMAGE2D)
--#define VPC_ES11CULLFACE (VPG_ES11 + ES11_CULLFACE)
--#define VPC_ES11DELETEBUFFERS (VPG_ES11 + ES11_DELETEBUFFERS)
--#define VPC_ES11DELETETEXTURES (VPG_ES11 + ES11_DELETETEXTURES)
--#define VPC_ES11DEPTHFUNC (VPG_ES11 + ES11_DEPTHFUNC)
--#define VPC_ES11DEPTHMASK (VPG_ES11 + ES11_DEPTHMASK)
--#define VPC_ES11DEPTHRANGEF (VPG_ES11 + ES11_DEPTHRANGEF)
--#define VPC_ES11DEPTHRANGEX (VPG_ES11 + ES11_DEPTHRANGEX)
--#define VPC_ES11DISABLE (VPG_ES11 + ES11_DISABLE)
--#define VPC_ES11DISABLECLIENTSTATE (VPG_ES11 + ES11_DISABLECLIENTSTATE)
--#define VPC_ES11DRAWARRAYS (VPG_ES11 + ES11_DRAWARRAYS)
--#define VPC_ES11DRAWELEMENTS (VPG_ES11 + ES11_DRAWELEMENTS)
--#define VPC_ES11ENABLE (VPG_ES11 + ES11_ENABLE)
--#define VPC_ES11ENABLECLIENTSTATE (VPG_ES11 + ES11_ENABLECLIENTSTATE)
--#define VPC_ES11FINISH (VPG_ES11 + ES11_FINISH)
--#define VPC_ES11FLUSH (VPG_ES11 + ES11_FLUSH)
--#define VPC_ES11FOGF (VPG_ES11 + ES11_FOGF)
--#define VPC_ES11FOGFV (VPG_ES11 + ES11_FOGFV)
--#define VPC_ES11FOGX (VPG_ES11 + ES11_FOGX)
--#define VPC_ES11FOGXV (VPG_ES11 + ES11_FOGXV)
--#define VPC_ES11FRONTFACE (VPG_ES11 + ES11_FRONTFACE)
--#define VPC_ES11FRUSTUMF (VPG_ES11 + ES11_FRUSTUMF)
--#define VPC_ES11FRUSTUMX (VPG_ES11 + ES11_FRUSTUMX)
--#define VPC_ES11GENBUFFERS (VPG_ES11 + ES11_GENBUFFERS)
--#define VPC_ES11GENTEXTURES (VPG_ES11 + ES11_GENTEXTURES)
--#define VPC_ES11GETBOOLEANV (VPG_ES11 + ES11_GETBOOLEANV)
--#define VPC_ES11GETBUFFERPARAMETERIV (VPG_ES11 + ES11_GETBUFFERPARAMETERIV)
--#define VPC_ES11GETCLIPPLANEF (VPG_ES11 + ES11_GETCLIPPLANEF)
--#define VPC_ES11GETCLIPPLANEX (VPG_ES11 + ES11_GETCLIPPLANEX)
--#define VPC_ES11GETERROR (VPG_ES11 + ES11_GETERROR)
--#define VPC_ES11GETFIXEDV (VPG_ES11 + ES11_GETFIXEDV)
--#define VPC_ES11GETFLOATV (VPG_ES11 + ES11_GETFLOATV)
--#define VPC_ES11GETINTEGERV (VPG_ES11 + ES11_GETINTEGERV)
--#define VPC_ES11GETLIGHTFV (VPG_ES11 + ES11_GETLIGHTFV)
--#define VPC_ES11GETLIGHTXV (VPG_ES11 + ES11_GETLIGHTXV)
--#define VPC_ES11GETMATERIALFV (VPG_ES11 + ES11_GETMATERIALFV)
--#define VPC_ES11GETMATERIALXV (VPG_ES11 + ES11_GETMATERIALXV)
--#define VPC_ES11GETPOINTERV (VPG_ES11 + ES11_GETPOINTERV)
--#define VPC_ES11GETSTRING (VPG_ES11 + ES11_GETSTRING)
--#define VPC_ES11GETTEXENVFV (VPG_ES11 + ES11_GETTEXENVFV)
--#define VPC_ES11GETTEXENVIV (VPG_ES11 + ES11_GETTEXENVIV)
--#define VPC_ES11GETTEXENVXV (VPG_ES11 + ES11_GETTEXENVXV)
--#define VPC_ES11GETTEXPARAMETERFV (VPG_ES11 + ES11_GETTEXPARAMETERFV)
--#define VPC_ES11GETTEXPARAMETERIV (VPG_ES11 + ES11_GETTEXPARAMETERIV)
--#define VPC_ES11GETTEXPARAMETERXV (VPG_ES11 + ES11_GETTEXPARAMETERXV)
--#define VPC_ES11HINT (VPG_ES11 + ES11_HINT)
--#define VPC_ES11ISBUFFER (VPG_ES11 + ES11_ISBUFFER)
--#define VPC_ES11ISENABLED (VPG_ES11 + ES11_ISENABLED)
--#define VPC_ES11ISTEXTURE (VPG_ES11 + ES11_ISTEXTURE)
--#define VPC_ES11LIGHTF (VPG_ES11 + ES11_LIGHTF)
--#define VPC_ES11LIGHTFV (VPG_ES11 + ES11_LIGHTFV)
--#define VPC_ES11LIGHTMODELF (VPG_ES11 + ES11_LIGHTMODELF)
--#define VPC_ES11LIGHTMODELFV (VPG_ES11 + ES11_LIGHTMODELFV)
--#define VPC_ES11LIGHTMODELX (VPG_ES11 + ES11_LIGHTMODELX)
--#define VPC_ES11LIGHTMODELXV (VPG_ES11 + ES11_LIGHTMODELXV)
--#define VPC_ES11LIGHTX (VPG_ES11 + ES11_LIGHTX)
--#define VPC_ES11LIGHTXV (VPG_ES11 + ES11_LIGHTXV)
--#define VPC_ES11LINEWIDTH (VPG_ES11 + ES11_LINEWIDTH)
--#define VPC_ES11LINEWIDTHX (VPG_ES11 + ES11_LINEWIDTHX)
--#define VPC_ES11LOADIDENTITY (VPG_ES11 + ES11_LOADIDENTITY)
--#define VPC_ES11LOADMATRIXF (VPG_ES11 + ES11_LOADMATRIXF)
--#define VPC_ES11LOADMATRIXX (VPG_ES11 + ES11_LOADMATRIXX)
--#define VPC_ES11LOGICOP (VPG_ES11 + ES11_LOGICOP)
--#define VPC_ES11MATERIALF (VPG_ES11 + ES11_MATERIALF)
--#define VPC_ES11MATERIALFV (VPG_ES11 + ES11_MATERIALFV)
--#define VPC_ES11MATERIALX (VPG_ES11 + ES11_MATERIALX)
--#define VPC_ES11MATERIALXV (VPG_ES11 + ES11_MATERIALXV)
--#define VPC_ES11MATRIXMODE (VPG_ES11 + ES11_MATRIXMODE)
--#define VPC_ES11MULTITEXCOORD4F (VPG_ES11 + ES11_MULTITEXCOORD4F)
--#define VPC_ES11MULTITEXCOORD4X (VPG_ES11 + ES11_MULTITEXCOORD4X)
--#define VPC_ES11MULTMATRIXF (VPG_ES11 + ES11_MULTMATRIXF)
--#define VPC_ES11MULTMATRIXX (VPG_ES11 + ES11_MULTMATRIXX)
--#define VPC_ES11NORMAL3F (VPG_ES11 + ES11_NORMAL3F)
--#define VPC_ES11NORMAL3X (VPG_ES11 + ES11_NORMAL3X)
--#define VPC_ES11NORMALPOINTER (VPG_ES11 + ES11_NORMALPOINTER)
--#define VPC_ES11ORTHOF (VPG_ES11 + ES11_ORTHOF)
--#define VPC_ES11ORTHOX (VPG_ES11 + ES11_ORTHOX)
--#define VPC_ES11PIXELSTOREI (VPG_ES11 + ES11_PIXELSTOREI)
--#define VPC_ES11POINTPARAMETERF (VPG_ES11 + ES11_POINTPARAMETERF)
--#define VPC_ES11POINTPARAMETERFV (VPG_ES11 + ES11_POINTPARAMETERFV)
--#define VPC_ES11POINTPARAMETERX (VPG_ES11 + ES11_POINTPARAMETERX)
--#define VPC_ES11POINTPARAMETERXV (VPG_ES11 + ES11_POINTPARAMETERXV)
--#define VPC_ES11POINTSIZE (VPG_ES11 + ES11_POINTSIZE)
--#define VPC_ES11POINTSIZEX (VPG_ES11 + ES11_POINTSIZEX)
--#define VPC_ES11POLYGONOFFSET (VPG_ES11 + ES11_POLYGONOFFSET)
--#define VPC_ES11POLYGONOFFSETX (VPG_ES11 + ES11_POLYGONOFFSETX)
--#define VPC_ES11POPMATRIX (VPG_ES11 + ES11_POPMATRIX)
--#define VPC_ES11PUSHMATRIX (VPG_ES11 + ES11_PUSHMATRIX)
--#define VPC_ES11READPIXELS (VPG_ES11 + ES11_READPIXELS)
--#define VPC_ES11ROTATEF (VPG_ES11 + ES11_ROTATEF)
--#define VPC_ES11ROTATEX (VPG_ES11 + ES11_ROTATEX)
--#define VPC_ES11SAMPLECOVERAGE (VPG_ES11 + ES11_SAMPLECOVERAGE)
--#define VPC_ES11SAMPLECOVERAGEX (VPG_ES11 + ES11_SAMPLECOVERAGEX)
--#define VPC_ES11SCALEF (VPG_ES11 + ES11_SCALEF)
--#define VPC_ES11SCALEX (VPG_ES11 + ES11_SCALEX)
--#define VPC_ES11SCISSOR (VPG_ES11 + ES11_SCISSOR)
--#define VPC_ES11SHADEMODEL (VPG_ES11 + ES11_SHADEMODEL)
--#define VPC_ES11STENCILFUNC (VPG_ES11 + ES11_STENCILFUNC)
--#define VPC_ES11STENCILMASK (VPG_ES11 + ES11_STENCILMASK)
--#define VPC_ES11STENCILOP (VPG_ES11 + ES11_STENCILOP)
--#define VPC_ES11TEXCOORDPOINTER (VPG_ES11 + ES11_TEXCOORDPOINTER)
--#define VPC_ES11TEXENVF (VPG_ES11 + ES11_TEXENVF)
--#define VPC_ES11TEXENVFV (VPG_ES11 + ES11_TEXENVFV)
--#define VPC_ES11TEXENVI (VPG_ES11 + ES11_TEXENVI)
--#define VPC_ES11TEXENVIV (VPG_ES11 + ES11_TEXENVIV)
--#define VPC_ES11TEXENVX (VPG_ES11 + ES11_TEXENVX)
--#define VPC_ES11TEXENVXV (VPG_ES11 + ES11_TEXENVXV)
--#define VPC_ES11TEXIMAGE2D (VPG_ES11 + ES11_TEXIMAGE2D)
--#define VPC_ES11TEXPARAMETERF (VPG_ES11 + ES11_TEXPARAMETERF)
--#define VPC_ES11TEXPARAMETERFV (VPG_ES11 + ES11_TEXPARAMETERFV)
--#define VPC_ES11TEXPARAMETERI (VPG_ES11 + ES11_TEXPARAMETERI)
--#define VPC_ES11TEXPARAMETERIV (VPG_ES11 + ES11_TEXPARAMETERIV)
--#define VPC_ES11TEXPARAMETERX (VPG_ES11 + ES11_TEXPARAMETERX)
--#define VPC_ES11TEXPARAMETERXV (VPG_ES11 + ES11_TEXPARAMETERXV)
--#define VPC_ES11TEXSUBIMAGE2D (VPG_ES11 + ES11_TEXSUBIMAGE2D)
--#define VPC_ES11TRANSLATEF (VPG_ES11 + ES11_TRANSLATEF)
--#define VPC_ES11TRANSLATEX (VPG_ES11 + ES11_TRANSLATEX)
--#define VPC_ES11VERTEXPOINTER (VPG_ES11 + ES11_VERTEXPOINTER)
--#define VPC_ES11VIEWPORT (VPG_ES11 + ES11_VIEWPORT)
- /* OpenGL ES11 Statics Counter IDs. */
--#define VPC_ES11CALLS (VPG_ES11 + ES11_CALLS)
--#define VPC_ES11DRAWCALLS (VPG_ES11 + ES11_DRAWCALLS)
--#define VPC_ES11STATECHANGECALLS (VPG_ES11 + ES11_STATECHANGECALLS)
--#define VPC_ES11POINTCOUNT (VPG_ES11 + ES11_POINTCOUNT)
--#define VPC_ES11LINECOUNT (VPG_ES11 + ES11_LINECOUNT)
--#define VPC_ES11TRIANGLECOUNT (VPG_ES11 + ES11_TRIANGLECOUNT)
--
--/* OpenGLES 2.x */
--#define VPC_ES20ACTIVETEXTURE (VPG_ES20 + ES20_ACTIVETEXTURE)
--#define VPC_ES20ATTACHSHADER (VPG_ES20 + ES20_ATTACHSHADER)
--#define VPC_ES20BINDATTRIBLOCATION (VPG_ES20 + ES20_BINDATTRIBLOCATION)
--#define VPC_ES20BINDBUFFER (VPG_ES20 + ES20_BINDBUFFER)
--#define VPC_ES20BINDFRAMEBUFFER (VPG_ES20 + ES20_BINDFRAMEBUFFER)
--#define VPC_ES20BINDRENDERBUFFER (VPG_ES20 + ES20_BINDRENDERBUFFER)
--#define VPC_ES20BINDTEXTURE (VPG_ES20 + ES20_BINDTEXTURE)
--#define VPC_ES20BLENDCOLOR (VPG_ES20 + ES20_BLENDCOLOR)
--#define VPC_ES20BLENDEQUATION (VPG_ES20 + ES20_BLENDEQUATION)
--#define VPC_ES20BLENDEQUATIONSEPARATE (VPG_ES20 + ES20_BLENDEQUATIONSEPARATE)
--#define VPC_ES20BLENDFUNC (VPG_ES20 + ES20_BLENDFUNC)
--#define VPC_ES20BLENDFUNCSEPARATE (VPG_ES20 + ES20_BLENDFUNCSEPARATE)
--#define VPC_ES20BUFFERDATA (VPG_ES20 + ES20_BUFFERDATA)
--#define VPC_ES20BUFFERSUBDATA (VPG_ES20 + ES20_BUFFERSUBDATA)
--#define VPC_ES20CHECKFRAMEBUFFERSTATUS (VPG_ES20 + ES20_CHECKFRAMEBUFFERSTATUS)
--#define VPC_ES20CLEAR (VPG_ES20 + ES20_CLEAR)
--#define VPC_ES20CLEARCOLOR (VPG_ES20 + ES20_CLEARCOLOR)
--#define VPC_ES20CLEARDEPTHF (VPG_ES20 + ES20_CLEARDEPTHF)
--#define VPC_ES20CLEARSTENCIL (VPG_ES20 + ES20_CLEARSTENCIL)
--#define VPC_ES20COLORMASK (VPG_ES20 + ES20_COLORMASK)
--#define VPC_ES20COMPILESHADER (VPG_ES20 + ES20_COMPILESHADER)
--#define VPC_ES20COMPRESSEDTEXIMAGE2D (VPG_ES20 + ES20_COMPRESSEDTEXIMAGE2D)
--#define VPC_ES20COMPRESSEDTEXSUBIMAGE2D (VPG_ES20 + ES20_COMPRESSEDTEXSUBIMAGE2D)
--#define VPC_ES20COPYTEXIMAGE2D (VPG_ES20 + ES20_COPYTEXIMAGE2D)
--#define VPC_ES20COPYTEXSUBIMAGE2D (VPG_ES20 + ES20_COPYTEXSUBIMAGE2D)
--#define VPC_ES20CREATEPROGRAM (VPG_ES20 + ES20_CREATEPROGRAM)
--#define VPC_ES20CREATESHADER (VPG_ES20 + ES20_CREATESHADER)
--#define VPC_ES20CULLFACE (VPG_ES20 + ES20_CULLFACE)
--#define VPC_ES20DELETEBUFFERS (VPG_ES20 + ES20_DELETEBUFFERS)
--#define VPC_ES20DELETEFRAMEBUFFERS (VPG_ES20 + ES20_DELETEFRAMEBUFFERS)
--#define VPC_ES20DELETEPROGRAM (VPG_ES20 + ES20_DELETEPROGRAM)
--#define VPC_ES20DELETERENDERBUFFERS (VPG_ES20 + ES20_DELETERENDERBUFFERS)
--#define VPC_ES20DELETESHADER (VPG_ES20 + ES20_DELETESHADER)
--#define VPC_ES20DELETETEXTURES (VPG_ES20 + ES20_DELETETEXTURES)
--#define VPC_ES20DEPTHFUNC (VPG_ES20 + ES20_DEPTHFUNC)
--#define VPC_ES20DEPTHMASK (VPG_ES20 + ES20_DEPTHMASK)
--#define VPC_ES20DEPTHRANGEF (VPG_ES20 + ES20_DEPTHRANGEF)
--#define VPC_ES20DETACHSHADER (VPG_ES20 + ES20_DETACHSHADER)
--#define VPC_ES20DISABLE (VPG_ES20 + ES20_DISABLE)
--#define VPC_ES20DISABLEVERTEXATTRIBARRAY (VPG_ES20 + ES20_DISABLEVERTEXATTRIBARRAY)
--#define VPC_ES20DRAWARRAYS (VPG_ES20 + ES20_DRAWARRAYS)
--#define VPC_ES20DRAWELEMENTS (VPG_ES20 + ES20_DRAWELEMENTS)
--#define VPC_ES20ENABLE (VPG_ES20 + ES20_ENABLE)
--#define VPC_ES20ENABLEVERTEXATTRIBARRAY (VPG_ES20 + ES20_ENABLEVERTEXATTRIBARRAY)
--#define VPC_ES20FINISH (VPG_ES20 + ES20_FINISH)
--#define VPC_ES20FLUSH (VPG_ES20 + ES20_FLUSH)
--#define VPC_ES20FRAMEBUFFERRENDERBUFFER (VPG_ES20 + ES20_FRAMEBUFFERRENDERBUFFER)
--#define VPC_ES20FRAMEBUFFERTEXTURE2D (VPG_ES20 + ES20_FRAMEBUFFERTEXTURE2D)
--#define VPC_ES20FRONTFACE (VPG_ES20 + ES20_FRONTFACE)
--#define VPC_ES20GENBUFFERS (VPG_ES20 + ES20_GENBUFFERS)
--#define VPC_ES20GENERATEMIPMAP (VPG_ES20 + ES20_GENERATEMIPMAP)
--#define VPC_ES20GENFRAMEBUFFERS (VPG_ES20 + ES20_GENFRAMEBUFFERS)
--#define VPC_ES20GENRENDERBUFFERS (VPG_ES20 + ES20_GENRENDERBUFFERS)
--#define VPC_ES20GENTEXTURES (VPG_ES20 + ES20_GENTEXTURES)
--#define VPC_ES20GETACTIVEATTRIB (VPG_ES20 + ES20_GETACTIVEATTRIB)
--#define VPC_ES20GETACTIVEUNIFORM (VPG_ES20 + ES20_GETACTIVEUNIFORM)
--#define VPC_ES20GETATTACHEDSHADERS (VPG_ES20 + ES20_GETATTACHEDSHADERS)
--#define VPC_ES20GETATTRIBLOCATION (VPG_ES20 + ES20_GETATTRIBLOCATION)
--#define VPC_ES20GETBOOLEANV (VPG_ES20 + ES20_GETBOOLEANV)
--#define VPC_ES20GETBUFFERPARAMETERIV (VPG_ES20 + ES20_GETBUFFERPARAMETERIV)
--#define VPC_ES20GETERROR (VPG_ES20 + ES20_GETERROR)
--#define VPC_ES20GETFLOATV (VPG_ES20 + ES20_GETFLOATV)
--#define VPC_ES20GETFRAMEBUFFERATTACHMENTPARAMETERIV (VPG_ES20 + ES20_GETFRAMEBUFFERATTACHMENTPARAMETERIV)
--#define VPC_ES20GETINTEGERV (VPG_ES20 + ES20_GETINTEGERV)
--#define VPC_ES20GETPROGRAMIV (VPG_ES20 + ES20_GETPROGRAMIV)
--#define VPC_ES20GETPROGRAMINFOLOG (VPG_ES20 + ES20_GETPROGRAMINFOLOG)
--#define VPC_ES20GETRENDERBUFFERPARAMETERIV (VPG_ES20 + ES20_GETRENDERBUFFERPARAMETERIV)
--#define VPC_ES20GETSHADERIV (VPG_ES20 + ES20_GETSHADERIV)
--#define VPC_ES20GETSHADERINFOLOG (VPG_ES20 + ES20_GETSHADERINFOLOG)
--#define VPC_ES20GETSHADERPRECISIONFORMAT (VPG_ES20 + ES20_GETSHADERPRECISIONFORMAT)
--#define VPC_ES20GETSHADERSOURCE (VPG_ES20 + ES20_GETSHADERSOURCE)
--#define VPC_ES20GETSTRING (VPG_ES20 + ES20_GETSTRING)
--#define VPC_ES20GETTEXPARAMETERFV (VPG_ES20 + ES20_GETTEXPARAMETERFV)
--#define VPC_ES20GETTEXPARAMETERIV (VPG_ES20 + ES20_GETTEXPARAMETERIV)
--#define VPC_ES20GETUNIFORMFV (VPG_ES20 + ES20_GETUNIFORMFV)
--#define VPC_ES20GETUNIFORMIV (VPG_ES20 + ES20_GETUNIFORMIV)
--#define VPC_ES20GETUNIFORMLOCATION (VPG_ES20 + ES20_GETUNIFORMLOCATION)
--#define VPC_ES20GETVERTEXATTRIBFV (VPG_ES20 + ES20_GETVERTEXATTRIBFV)
--#define VPC_ES20GETVERTEXATTRIBIV (VPG_ES20 + ES20_GETVERTEXATTRIBIV)
--#define VPC_ES20GETVERTEXATTRIBPOINTERV (VPG_ES20 + ES20_GETVERTEXATTRIBPOINTERV)
--#define VPC_ES20HINT (VPG_ES20 + ES20_HINT)
--#define VPC_ES20ISBUFFER (VPG_ES20 + ES20_ISBUFFER)
--#define VPC_ES20ISENABLED (VPG_ES20 + ES20_ISENABLED)
--#define VPC_ES20ISFRAMEBUFFER (VPG_ES20 + ES20_ISFRAMEBUFFER)
--#define VPC_ES20ISPROGRAM (VPG_ES20 + ES20_ISPROGRAM)
--#define VPC_ES20ISRENDERBUFFER (VPG_ES20 + ES20_ISRENDERBUFFER)
--#define VPC_ES20ISSHADER (VPG_ES20 + ES20_ISSHADER)
--#define VPC_ES20ISTEXTURE (VPG_ES20 + ES20_ISTEXTURE)
--#define VPC_ES20LINEWIDTH (VPG_ES20 + ES20_LINEWIDTH)
--#define VPC_ES20LINKPROGRAM (VPG_ES20 + ES20_LINKPROGRAM)
--#define VPC_ES20PIXELSTOREI (VPG_ES20 + ES20_PIXELSTOREI)
--#define VPC_ES20POLYGONOFFSET (VPG_ES20 + ES20_POLYGONOFFSET)
--#define VPC_ES20READPIXELS (VPG_ES20 + ES20_READPIXELS)
--#define VPC_ES20RELEASESHADERCOMPILER (VPG_ES20 + ES20_RELEASESHADERCOMPILER)
--#define VPC_ES20RENDERBUFFERSTORAGE (VPG_ES20 + ES20_RENDERBUFFERSTORAGE)
--#define VPC_ES20SAMPLECOVERAGE (VPG_ES20 + ES20_SAMPLECOVERAGE)
--#define VPC_ES20SCISSOR (VPG_ES20 + ES20_SCISSOR)
--#define VPC_ES20SHADERBINARY (VPG_ES20 + ES20_SHADERBINARY)
--#define VPC_ES20SHADERSOURCE (VPG_ES20 + ES20_SHADERSOURCE)
--#define VPC_ES20STENCILFUNC (VPG_ES20 + ES20_STENCILFUNC)
--#define VPC_ES20STENCILFUNCSEPARATE (VPG_ES20 + ES20_STENCILFUNCSEPARATE)
--#define VPC_ES20STENCILMASK (VPG_ES20 + ES20_STENCILMASK)
--#define VPC_ES20STENCILMASKSEPARATE (VPG_ES20 + ES20_STENCILMASKSEPARATE)
--#define VPC_ES20STENCILOP (VPG_ES20 + ES20_STENCILOP)
--#define VPC_ES20STENCILOPSEPARATE (VPG_ES20 + ES20_STENCILOPSEPARATE)
--#define VPC_ES20TEXIMAGE2D (VPG_ES20 + ES20_TEXIMAGE2D)
--#define VPC_ES20TEXPARAMETERF (VPG_ES20 + ES20_TEXPARAMETERF)
--#define VPC_ES20TEXPARAMETERFV (VPG_ES20 + ES20_TEXPARAMETERFV)
--#define VPC_ES20TEXPARAMETERI (VPG_ES20 + ES20_TEXPARAMETERI)
--#define VPC_ES20TEXPARAMETERIV (VPG_ES20 + ES20_TEXPARAMETERIV)
--#define VPC_ES20TEXSUBIMAGE2D (VPG_ES20 + ES20_TEXSUBIMAGE2D)
--#define VPC_ES20UNIFORM1F (VPG_ES20 + ES20_UNIFORM1F)
--#define VPC_ES20UNIFORM1FV (VPG_ES20 + ES20_UNIFORM1FV)
--#define VPC_ES20UNIFORM1I (VPG_ES20 + ES20_UNIFORM1I)
--#define VPC_ES20UNIFORM1IV (VPG_ES20 + ES20_UNIFORM1IV)
--#define VPC_ES20UNIFORM2F (VPG_ES20 + ES20_UNIFORM2F)
--#define VPC_ES20UNIFORM2FV (VPG_ES20 + ES20_UNIFORM2FV)
--#define VPC_ES20UNIFORM2I (VPG_ES20 + ES20_UNIFORM2I)
--#define VPC_ES20UNIFORM2IV (VPG_ES20 + ES20_UNIFORM2IV)
--#define VPC_ES20UNIFORM3F (VPG_ES20 + ES20_UNIFORM3F)
--#define VPC_ES20UNIFORM3FV (VPG_ES20 + ES20_UNIFORM3FV)
--#define VPC_ES20UNIFORM3I (VPG_ES20 + ES20_UNIFORM3I)
--#define VPC_ES20UNIFORM3IV (VPG_ES20 + ES20_UNIFORM3IV)
--#define VPC_ES20UNIFORM4F (VPG_ES20 + ES20_UNIFORM4F)
--#define VPC_ES20UNIFORM4FV (VPG_ES20 + ES20_UNIFORM4FV)
--#define VPC_ES20UNIFORM4I (VPG_ES20 + ES20_UNIFORM4I)
--#define VPC_ES20UNIFORM4IV (VPG_ES20 + ES20_UNIFORM4IV)
--#define VPC_ES20UNIFORMMATRIX2FV (VPG_ES20 + ES20_UNIFORMMATRIX2FV)
--#define VPC_ES20UNIFORMMATRIX3FV (VPG_ES20 + ES20_UNIFORMMATRIX3FV)
--#define VPC_ES20UNIFORMMATRIX4FV (VPG_ES20 + ES20_UNIFORMMATRIX4FV)
--#define VPC_ES20USEPROGRAM (VPG_ES20 + ES20_USEPROGRAM)
--#define VPC_ES20VALIDATEPROGRAM (VPG_ES20 + ES20_VALIDATEPROGRAM)
--#define VPC_ES20VERTEXATTRIB1F (VPG_ES20 + ES20_VERTEXATTRIB1F)
--#define VPC_ES20VERTEXATTRIB1FV (VPG_ES20 + ES20_VERTEXATTRIB1FV)
--#define VPC_ES20VERTEXATTRIB2F (VPG_ES20 + ES20_VERTEXATTRIB2F)
--#define VPC_ES20VERTEXATTRIB2FV (VPG_ES20 + ES20_VERTEXATTRIB2FV)
--#define VPC_ES20VERTEXATTRIB3F (VPG_ES20 + ES20_VERTEXATTRIB3F)
--#define VPC_ES20VERTEXATTRIB3FV (VPG_ES20 + ES20_VERTEXATTRIB3FV)
--#define VPC_ES20VERTEXATTRIB4F (VPG_ES20 + ES20_VERTEXATTRIB4F)
--#define VPC_ES20VERTEXATTRIB4FV (VPG_ES20 + ES20_VERTEXATTRIB4FV)
--#define VPC_ES20VERTEXATTRIBPOINTER (VPG_ES20 + ES20_VERTEXATTRIBPOINTER)
--#define VPC_ES20VIEWPORT (VPG_ES20 + ES20_VIEWPORT)
-+#define VPC_ES11CALLS (VPG_ES11 + ES11_CALLS)
-+#define VPC_ES11DRAWCALLS (VPG_ES11 + ES11_DRAWCALLS)
-+#define VPC_ES11STATECHANGECALLS (VPG_ES11 + ES11_STATECHANGECALLS)
-+#define VPC_ES11POINTCOUNT (VPG_ES11 + ES11_POINTCOUNT)
-+#define VPC_ES11LINECOUNT (VPG_ES11 + ES11_LINECOUNT)
-+#define VPC_ES11TRIANGLECOUNT (VPG_ES11 + ES11_TRIANGLECOUNT)
-+
- /* OpenGL ES20 Statistics Counter IDs. */
--#define VPC_ES20CALLS (VPG_ES20 + ES20_CALLS)
--#define VPC_ES20DRAWCALLS (VPG_ES20 + ES20_DRAWCALLS)
--#define VPC_ES20STATECHANGECALLS (VPG_ES20 + ES20_STATECHANGECALLS)
--#define VPC_ES20POINTCOUNT (VPG_ES20 + ES20_POINTCOUNT)
--#define VPC_ES20LINECOUNT (VPG_ES20 + ES20_LINECOUNT)
--#define VPC_ES20TRIANGLECOUNT (VPG_ES20 + ES20_TRIANGLECOUNT)
--
--/* VG11 Counters. */
--#define VPC_VG11APPENDPATH (VPG_VG11 + VG11_APPENDPATH)
--#define VPC_VG11APPENDPATHDATA (VPG_VG11 + VG11_APPENDPATHDATA)
--#define VPC_VG11CHILDIMAGE (VPG_VG11 + VG11_CHILDIMAGE)
--#define VPC_VG11CLEAR (VPG_VG11 + VG11_CLEAR)
--#define VPC_VG11CLEARGLYPH (VPG_VG11 + VG11_CLEARGLYPH)
--#define VPC_VG11CLEARIMAGE (VPG_VG11 + VG11_CLEARIMAGE)
--#define VPC_VG11CLEARPATH (VPG_VG11 + VG11_CLEARPATH)
--#define VPC_VG11COLORMATRIX (VPG_VG11 + VG11_COLORMATRIX)
--#define VPC_VG11CONVOLVE (VPG_VG11 + VG11_CONVOLVE)
--#define VPC_VG11COPYIMAGE (VPG_VG11 + VG11_COPYIMAGE)
--#define VPC_VG11COPYMASK (VPG_VG11 + VG11_COPYMASK)
--#define VPC_VG11COPYPIXELS (VPG_VG11 + VG11_COPYPIXELS)
--#define VPC_VG11CREATEFONT (VPG_VG11 + VG11_CREATEFONT)
--#define VPC_VG11CREATEIMAGE (VPG_VG11 + VG11_CREATEIMAGE)
--#define VPC_VG11CREATEMASKLAYER (VPG_VG11 + VG11_CREATEMASKLAYER)
--#define VPC_VG11CREATEPAINT (VPG_VG11 + VG11_CREATEPAINT)
--#define VPC_VG11CREATEPATH (VPG_VG11 + VG11_CREATEPATH)
--#define VPC_VG11DESTROYFONT (VPG_VG11 + VG11_DESTROYFONT)
--#define VPC_VG11DESTROYIMAGE (VPG_VG11 + VG11_DESTROYIMAGE)
--#define VPC_VG11DESTROYMASKLAYER (VPG_VG11 + VG11_DESTROYMASKLAYER)
--#define VPC_VG11DESTROYPAINT (VPG_VG11 + VG11_DESTROYPAINT)
--#define VPC_VG11DESTROYPATH (VPG_VG11 + VG11_DESTROYPATH)
--#define VPC_VG11DRAWGLYPH (VPG_VG11 + VG11_DRAWGLYPH)
--#define VPC_VG11DRAWGLYPHS (VPG_VG11 + VG11_DRAWGLYPHS)
--#define VPC_VG11DRAWIMAGE (VPG_VG11 + VG11_DRAWIMAGE)
--#define VPC_VG11DRAWPATH (VPG_VG11 + VG11_DRAWPATH)
--#define VPC_VG11FILLMASKLAYER (VPG_VG11 + VG11_FILLMASKLAYER)
--#define VPC_VG11FINISH (VPG_VG11 + VG11_FINISH)
--#define VPC_VG11FLUSH (VPG_VG11 + VG11_FLUSH)
--#define VPC_VG11GAUSSIANBLUR (VPG_VG11 + VG11_GAUSSIANBLUR)
--#define VPC_VG11GETCOLOR (VPG_VG11 + VG11_GETCOLOR)
--#define VPC_VG11GETERROR (VPG_VG11 + VG11_GETERROR)
--#define VPC_VG11GETF (VPG_VG11 + VG11_GETF)
--#define VPC_VG11GETFV (VPG_VG11 + VG11_GETFV)
--#define VPC_VG11GETI (VPG_VG11 + VG11_GETI)
--#define VPC_VG11GETIMAGESUBDATA (VPG_VG11 + VG11_GETIMAGESUBDATA)
--#define VPC_VG11GETIV (VPG_VG11 + VG11_GETIV)
--#define VPC_VG11GETMATRIX (VPG_VG11 + VG11_GETMATRIX)
--#define VPC_VG11GETPAINT (VPG_VG11 + VG11_GETPAINT)
--#define VPC_VG11GETPARAMETERF (VPG_VG11 + VG11_GETPARAMETERF)
--#define VPC_VG11GETPARAMETERFV (VPG_VG11 + VG11_GETPARAMETERFV)
--#define VPC_VG11GETPARAMETERI (VPG_VG11 + VG11_GETPARAMETERI)
--#define VPC_VG11GETPARAMETERIV (VPG_VG11 + VG11_GETPARAMETERIV)
--#define VPC_VG11GETPARAMETERVECTORSIZE (VPG_VG11 + VG11_GETPARAMETERVECTORSIZE)
--#define VPC_VG11GETPARENT (VPG_VG11 + VG11_GETPARENT)
--#define VPC_VG11GETPATHCAPABILITIES (VPG_VG11 + VG11_GETPATHCAPABILITIES)
--#define VPC_VG11GETPIXELS (VPG_VG11 + VG11_GETPIXELS)
--#define VPC_VG11GETSTRING (VPG_VG11 + VG11_GETSTRING)
--#define VPC_VG11GETVECTORSIZE (VPG_VG11 + VG11_GETVECTORSIZE)
--#define VPC_VG11HARDWAREQUERY (VPG_VG11 + VG11_HARDWAREQUERY)
--#define VPC_VG11IMAGESUBDATA (VPG_VG11 + VG11_IMAGESUBDATA)
--#define VPC_VG11INTERPOLATEPATH (VPG_VG11 + VG11_INTERPOLATEPATH)
--#define VPC_VG11LOADIDENTITY (VPG_VG11 + VG11_LOADIDENTITY)
--#define VPC_VG11LOADMATRIX (VPG_VG11 + VG11_LOADMATRIX)
--#define VPC_VG11LOOKUP (VPG_VG11 + VG11_LOOKUP)
--#define VPC_VG11LOOKUPSINGLE (VPG_VG11 + VG11_LOOKUPSINGLE)
--#define VPC_VG11MASK (VPG_VG11 + VG11_MASK)
--#define VPC_VG11MODIFYPATHCOORDS (VPG_VG11 + VG11_MODIFYPATHCOORDS)
--#define VPC_VG11MULTMATRIX (VPG_VG11 + VG11_MULTMATRIX)
--#define VPC_VG11PAINTPATTERN (VPG_VG11 + VG11_PAINTPATTERN)
--#define VPC_VG11PATHBOUNDS (VPG_VG11 + VG11_PATHBOUNDS)
--#define VPC_VG11PATHLENGTH (VPG_VG11 + VG11_PATHLENGTH)
--#define VPC_VG11PATHTRANSFORMEDBOUNDS (VPG_VG11 + VG11_PATHTRANSFORMEDBOUNDS)
--#define VPC_VG11POINTALONGPATH (VPG_VG11 + VG11_POINTALONGPATH)
--#define VPC_VG11READPIXELS (VPG_VG11 + VG11_READPIXELS)
--#define VPC_VG11REMOVEPATHCAPABILITIES (VPG_VG11 + VG11_REMOVEPATHCAPABILITIES)
--#define VPC_VG11RENDERTOMASK (VPG_VG11 + VG11_RENDERTOMASK)
--#define VPC_VG11ROTATE (VPG_VG11 + VG11_ROTATE)
--#define VPC_VG11SCALE (VPG_VG11 + VG11_SCALE)
--#define VPC_VG11SEPARABLECONVOLVE (VPG_VG11 + VG11_SEPARABLECONVOLVE)
--#define VPC_VG11SETCOLOR (VPG_VG11 + VG11_SETCOLOR)
--#define VPC_VG11SETF (VPG_VG11 + VG11_SETF)
--#define VPC_VG11SETFV (VPG_VG11 + VG11_SETFV)
--#define VPC_VG11SETGLYPHTOIMAGE (VPG_VG11 + VG11_SETGLYPHTOIMAGE)
--#define VPC_VG11SETGLYPHTOPATH (VPG_VG11 + VG11_SETGLYPHTOPATH)
--#define VPC_VG11SETI (VPG_VG11 + VG11_SETI)
--#define VPC_VG11SETIV (VPG_VG11 + VG11_SETIV)
--#define VPC_VG11SETPAINT (VPG_VG11 + VG11_SETPAINT)
--#define VPC_VG11SETPARAMETERF (VPG_VG11 + VG11_SETPARAMETERF)
--#define VPC_VG11SETPARAMETERFV (VPG_VG11 + VG11_SETPARAMETERFV)
--#define VPC_VG11SETPARAMETERI (VPG_VG11 + VG11_SETPARAMETERI)
--#define VPC_VG11SETPARAMETERIV (VPG_VG11 + VG11_SETPARAMETERIV)
--#define VPC_VG11SETPIXELS (VPG_VG11 + VG11_SETPIXELS)
--#define VPC_VG11SHEAR (VPG_VG11 + VG11_SHEAR)
--#define VPC_VG11TRANSFORMPATH (VPG_VG11 + VG11_TRANSFORMPATH)
--#define VPC_VG11TRANSLATE (VPG_VG11 + VG11_TRANSLATE)
--#define VPC_VG11WRITEPIXELS (VPG_VG11 + VG11_WRITEPIXELS)
-+#define VPC_ES20CALLS (VPG_ES20 + ES20_CALLS)
-+#define VPC_ES20DRAWCALLS (VPG_ES20 + ES20_DRAWCALLS)
-+#define VPC_ES20STATECHANGECALLS (VPG_ES20 + ES20_STATECHANGECALLS)
-+#define VPC_ES20POINTCOUNT (VPG_ES20 + ES20_POINTCOUNT)
-+#define VPC_ES20LINECOUNT (VPG_ES20 + ES20_LINECOUNT)
-+#define VPC_ES20TRIANGLECOUNT (VPG_ES20 + ES20_TRIANGLECOUNT)
-+
- /* OpenVG Statistics Counter IDs. */
--#define VPC_VG11CALLS (VPG_VG11 + VG11_CALLS)
--#define VPC_VG11DRAWCALLS (VPG_VG11 + VG11_DRAWCALLS)
--#define VPC_VG11STATECHANGECALLS (VPG_VG11 + VG11_STATECHANGECALLS)
--#define VPC_VG11FILLCOUNT (VPG_VG11 + VG11_FILLCOUNT)
--#define VPC_VG11STROKECOUNT (VPG_VG11 + VG11_STROKECOUNT)
-+#define VPC_VG11CALLS (VPG_VG11 + VG11_CALLS)
-+#define VPC_VG11DRAWCALLS (VPG_VG11 + VG11_DRAWCALLS)
-+#define VPC_VG11STATECHANGECALLS (VPG_VG11 + VG11_STATECHANGECALLS)
-+#define VPC_VG11FILLCOUNT (VPG_VG11 + VG11_FILLCOUNT)
-+#define VPC_VG11STROKECOUNT (VPG_VG11 + VG11_STROKECOUNT)
-
- /* HAL Counters. */
- #define VPC_HALVERTBUFNEWBYTEALLOC (VPG_HAL + HAL_VERTBUFNEWBYTEALLOC)
-@@ -1018,7 +248,7 @@ extern "C" {
- #define VPC_GPUREAD64BYTE (VPG_GPU + GPU_READ64BYTE)
- #define VPC_GPUWRITE64BYTE (VPG_GPU + GPU_WRITE64BYTE)
- #define VPC_GPUTOTALCYCLES (VPG_GPU + GPU_TOTALCYCLES)
--#define VPC_GPUIDLECYCLES (VPG_GPU + GPU_IDLECYCLES)
-+#define VPC_GPUIDLECYCLES (VPG_GPU + GPU_IDLECYCLES)
-
- /* HW: Shader Counters. */
- #define VPC_VSINSTCOUNT (VPG_VS + VS_INSTCOUNT)
-@@ -1026,9 +256,9 @@ extern "C" {
- #define VPC_VSTEXLDINSTCOUNT (VPG_VS + VS_TEXLDINSTCOUNT)
- #define VPC_VSRENDEREDVERTCOUNT (VPG_VS + VS_RENDEREDVERTCOUNT)
- /* HW: PS Count. */
--#define VPC_PSINSTCOUNT (VPG_PS + PS_INSTCOUNT)
--#define VPC_PSBRANCHINSTCOUNT (VPG_PS + PS_BRANCHINSTCOUNT)
--#define VPC_PSTEXLDINSTCOUNT (VPG_PS + PS_TEXLDINSTCOUNT)
-+#define VPC_PSINSTCOUNT (VPG_PS + PS_INSTCOUNT)
-+#define VPC_PSBRANCHINSTCOUNT (VPG_PS + PS_BRANCHINSTCOUNT)
-+#define VPC_PSTEXLDINSTCOUNT (VPG_PS + PS_TEXLDINSTCOUNT)
- #define VPC_PSRENDEREDPIXCOUNT (VPG_PS + PS_RENDEREDPIXCOUNT)
-
-
-@@ -1071,7 +301,7 @@ extern "C" {
- #define VPC_PEDRAWNBYDEPTH (VPG_PE + PE_DRAWNBYDEPTH)
-
- /* HW: MC Counters. */
--#define VPC_MCREADREQ8BPIPE (VPG_MC + MC_READREQ8BPIPE)
-+#define VPC_MCREADREQ8BPIPE (VPG_MC + MC_READREQ8BPIPE)
- #define VPC_MCREADREQ8BIP (VPG_MC + MC_READREQ8BIP)
- #define VPC_MCWRITEREQ8BPIPE (VPG_MC + MC_WRITEREQ8BPIPE)
-
-@@ -1087,6 +317,7 @@ extern "C" {
- #define VPC_PVSATTRIBCOUNT (VPG_PVS + PVS_ATTRIBCOUNT)
- #define VPC_PVSUNIFORMCOUNT (VPG_PVS + PVS_UNIFORMCOUNT)
- #define VPC_PVSFUNCTIONCOUNT (VPG_PVS + PVS_FUNCTIONCOUNT)
-+#define VPC_PVSSOURCE (VPG_PVS + PVS_SOURCE)
-
- #define VPC_PPSINSTRCOUNT (VPG_PPS + PPS_INSTRCOUNT)
- #define VPC_PPSALUINSTRCOUNT (VPG_PPS + PPS_ALUINSTRCOUNT)
-@@ -1094,7 +325,9 @@ extern "C" {
- #define VPC_PPSATTRIBCOUNT (VPG_PPS + PPS_ATTRIBCOUNT)
- #define VPC_PPSUNIFORMCOUNT (VPG_PPS + PPS_UNIFORMCOUNT)
- #define VPC_PPSFUNCTIONCOUNT (VPG_PPS + PPS_FUNCTIONCOUNT)
-+#define VPC_PPSSOURCE (VPG_PPS + PPS_SOURCE)
-
-+#define VPC_PROGRAMHANDLE (VPG_PROG + 1)
-
- #define VPG_ES20_DRAW_NO (VPG_ES20_DRAW + 1)
- #define VPG_ES11_DRAW_NO (VPG_ES11_DRAW + 1)
-@@ -1118,8 +351,8 @@ typedef struct _gcsPROFILER_COUNTERS
-
- /* HW vairable counters. */
- gctUINT32 gpuCyclesCounter;
-- gctUINT32 gpuTotalCyclesCounter;
-- gctUINT32 gpuIdleCyclesCounter;
-+ gctUINT32 gpuTotalCyclesCounter;
-+ gctUINT32 gpuIdleCyclesCounter;
- gctUINT32 gpuTotalRead64BytesPerFrame;
- gctUINT32 gpuTotalWrite64BytesPerFrame;
-
-@@ -1158,7 +391,7 @@ typedef struct _gcsPROFILER_COUNTERS
- gctUINT32 ra_total_primitive_count;
- gctUINT32 ra_pipe_cache_miss_counter;
- gctUINT32 ra_prefetch_cache_miss_counter;
-- gctUINT32 ra_eez_culled_counter;
-+ gctUINT32 ra_eez_culled_counter;
-
- /* TX */
- gctUINT32 tx_total_bilinear_requests;
-@@ -1190,7 +423,7 @@ typedef struct _gcsPROFILER
- gctBOOL enableHal;
- gctBOOL enableHW;
- gctBOOL enableSH;
-- gctBOOL isSyncMode;
-+ gctBOOL isSyncMode;
-
- gctBOOL useSocket;
- gctINT sockFd;
-@@ -1234,14 +467,17 @@ typedef struct _gcsPROFILER
- gctUINT32 redundantStateChangeCalls;
- #endif
-
-- gctUINT32 prevVSInstCount;
-- gctUINT32 prevVSBranchInstCount;
-- gctUINT32 prevVSTexInstCount;
-- gctUINT32 prevVSVertexCount;
-- gctUINT32 prevPSInstCount;
-- gctUINT32 prevPSBranchInstCount;
-- gctUINT32 prevPSTexInstCount;
-- gctUINT32 prevPSPixelCount;
-+ gctUINT32 prevVSInstCount;
-+ gctUINT32 prevVSBranchInstCount;
-+ gctUINT32 prevVSTexInstCount;
-+ gctUINT32 prevVSVertexCount;
-+ gctUINT32 prevPSInstCount;
-+ gctUINT32 prevPSBranchInstCount;
-+ gctUINT32 prevPSTexInstCount;
-+ gctUINT32 prevPSPixelCount;
-+
-+ char* psSource;
-+ char* vsSource;
-
- }
- gcsPROFILER;
-@@ -1315,6 +551,18 @@ gcoPROFILER_Count(
- IN gctINT Value
- );
-
-+gceSTATUS
-+gcoPROFILER_ShaderSourceFS(
-+ IN gcoHAL Hal,
-+ IN char* source
-+ );
-+
-+gceSTATUS
-+gcoPROFILER_ShaderSourceVS(
-+ IN gcoHAL Hal,
-+ IN char* source
-+ );
-+
- /* Profile input vertex shader. */
- gceSTATUS
- gcoPROFILER_ShaderVS(
-diff --git a/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_raster.h b/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_raster.h
-index bc4171e..6e4d830 100644
---- a/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_raster.h
-+++ b/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_raster.h
-@@ -568,6 +568,23 @@ gco2D_MonoBlit(
- IN gceSURF_FORMAT DestFormat
- );
-
-+gceSTATUS
-+gco2D_MonoBlitEx(
-+ IN gco2D Engine,
-+ IN gctPOINTER StreamBits,
-+ IN gctINT32 StreamStride,
-+ IN gctINT32 StreamWidth,
-+ IN gctINT32 StreamHeight,
-+ IN gctINT32 StreamX,
-+ IN gctINT32 StreamY,
-+ IN gctUINT32 FgColor,
-+ IN gctUINT32 BgColor,
-+ IN gcsRECT_PTR SrcRect,
-+ IN gcsRECT_PTR DstRect,
-+ IN gctUINT8 FgRop,
-+ IN gctUINT8 BgRop
-+ );
-+
- /* Set kernel size. */
- gceSTATUS
- gco2D_SetKernelSize(
-@@ -942,6 +959,15 @@ gco2D_SetSourceTileStatus(
- );
-
- gceSTATUS
-+gco2D_SetTargetTileStatus(
-+ IN gco2D Engine,
-+ IN gce2D_TILE_STATUS_CONFIG TileStatusConfig,
-+ IN gceSURF_FORMAT CompressedFormat,
-+ IN gctUINT32 ClearValue,
-+ IN gctUINT32 GpuAddress
-+ );
-+
-+gceSTATUS
- gco2D_QueryU32(
- IN gco2D Engine,
- IN gce2D_QUERY Item,
-@@ -955,6 +981,28 @@ gco2D_SetStateU32(
- IN gctUINT32 Value
- );
-
-+gceSTATUS
-+gco2D_SetStateArrayI32(
-+ IN gco2D Engine,
-+ IN gce2D_STATE State,
-+ IN gctINT32_PTR Array,
-+ IN gctINT32 ArraySize
-+ );
-+
-+gceSTATUS
-+gco2D_SetStateArrayU32(
-+ IN gco2D Engine,
-+ IN gce2D_STATE State,
-+ IN gctUINT32_PTR Array,
-+ IN gctINT32 ArraySize
-+ );
-+
-+gceSTATUS
-+gco2D_SetTargetRect(
-+ IN gco2D Engine,
-+ IN gcsRECT_PTR Rect
-+ );
-+
- #ifdef __cplusplus
- }
- #endif
-diff --git a/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_types.h b/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_types.h
-index 5c0877d..14801aa 100644
---- a/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_types.h
-+++ b/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_types.h
-@@ -128,6 +128,7 @@ typedef int gctBOOL;
- typedef gctBOOL * gctBOOL_PTR;
-
- typedef int gctINT;
-+typedef long gctLONG;
- typedef signed char gctINT8;
- typedef signed short gctINT16;
- typedef signed int gctINT32;
-@@ -171,6 +172,7 @@ typedef void * gctFILE;
- typedef void * gctSIGNAL;
- typedef void * gctWINDOW;
- typedef void * gctIMAGE;
-+typedef void * gctSYNC_POINT;
-
- typedef void * gctSEMAPHORE;
-
-@@ -941,12 +943,19 @@ typedef struct _gcsHAL_FRAME_INFO
- OUT gctUINT readRequests[8];
- OUT gctUINT writeRequests[8];
-
-+ /* FE counters. */
-+ OUT gctUINT drawCount;
-+ OUT gctUINT vertexOutCount;
-+ OUT gctUINT vertexMissCount;
-+
- /* 3D counters. */
- OUT gctUINT vertexCount;
- OUT gctUINT primitiveCount;
- OUT gctUINT rejectedPrimitives;
- OUT gctUINT culledPrimitives;
- OUT gctUINT clippedPrimitives;
-+ OUT gctUINT droppedPrimitives;
-+ OUT gctUINT frustumClippedPrimitives;
- OUT gctUINT outPrimitives;
- OUT gctUINT inPrimitives;
- OUT gctUINT culledQuadCount;
-@@ -964,18 +973,86 @@ typedef struct _gcsHAL_FRAME_INFO
- OUT gctUINT shaderCycles;
- OUT gctUINT vsInstructionCount;
- OUT gctUINT vsTextureCount;
-+ OUT gctUINT vsBranchCount;
-+ OUT gctUINT vsVertices;
- OUT gctUINT psInstructionCount;
- OUT gctUINT psTextureCount;
-+ OUT gctUINT psBranchCount;
-+ OUT gctUINT psPixels;
-
- /* Texture counters. */
- OUT gctUINT bilinearRequests;
- OUT gctUINT trilinearRequests;
-- OUT gctUINT txBytes8;
-+ OUT gctUINT txBytes8[2];
- OUT gctUINT txHitCount;
- OUT gctUINT txMissCount;
- }
- gcsHAL_FRAME_INFO;
-
-+typedef enum _gcePATCH_ID
-+{
-+ gcePATCH_UNKNOWN = 0xFFFFFFFF,
-+
-+ /* Benchmark list*/
-+ gcePATCH_GLB11 = 0x0,
-+ gcePATCH_GLB21,
-+ gcePATCH_GLB25,
-+ gcePATCH_GLB27,
-+
-+ gcePATCH_BM21,
-+ gcePATCH_MM,
-+ gcePATCH_MM06,
-+ gcePATCH_MM07,
-+ gcePATCH_QUADRANT,
-+ gcePATCH_ANTUTU,
-+ gcePATCH_SMARTBENCH,
-+ gcePATCH_JPCT,
-+ gcePATCH_NENAMARK,
-+ gcePATCH_NENAMARK2,
-+ gcePATCH_NEOCORE,
-+ gcePATCH_GLB,
-+ gcePATCH_GB,
-+ gcePATCH_RTESTVA,
-+ gcePATCH_BMX,
-+ gcePATCH_BMGUI,
-+
-+ /* Game list */
-+ gcePATCH_NBA2013,
-+ gcePATCH_BARDTALE,
-+ gcePATCH_BUSPARKING3D,
-+ gcePATCH_FISHBOODLE,
-+ gcePATCH_SUBWAYSURFER,
-+ gcePATCH_HIGHWAYDRIVER,
-+ gcePATCH_PREMIUM,
-+ gcePATCH_RACEILLEGAL,
-+ gcePATCH_BLABLA,
-+ gcePATCH_MEGARUN,
-+ gcePATCH_GALAXYONFIRE2,
-+ gcePATCH_GLOFTR3HM,
-+ gcePATCH_GLOFTSXHM,
-+ gcePATCH_GLOFTF3HM,
-+ gcePATCH_GLOFTGANG,
-+ gcePATCH_XRUNNER,
-+ gcePATCH_WP,
-+ gcePATCH_DEVIL,
-+ gcePATCH_HOLYARCH,
-+ gcePATCH_MUSE,
-+ gcePATCH_SG,
-+ gcePATCH_SIEGECRAFT,
-+ gcePATCH_CARCHALLENGE,
-+ gcePATCH_HEROESCALL,
-+ gcePATCH_MONOPOLY,
-+ gcePATCH_CTGL20,
-+ gcePATCH_FIREFOX,
-+ gcePATCH_CHORME,
-+ gcePATCH_DUOKANTV,
-+ gcePATCH_TESTAPP,
-+
-+ /* Count enum*/
-+ gcePATCH_COUNT,
-+}
-+gcePATCH_ID;
-+
- #if gcdLINK_QUEUE_SIZE
- typedef struct _gckLINKDATA * gckLINKDATA;
- struct _gckLINKDATA
-diff --git a/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_version.h b/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_version.h
-index 03cb4d6..2eab666 100644
---- a/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_version.h
-+++ b/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_version.h
-@@ -28,7 +28,7 @@
-
- #define gcvVERSION_PATCH 9
-
--#define gcvVERSION_BUILD 6622
-+#define gcvVERSION_BUILD 9754
-
- #define gcvVERSION_DATE __DATE__
-
-diff --git a/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_device.c b/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_device.c
-index 4d48bd5..b029428 100644
---- a/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_device.c
-+++ b/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_device.c
-@@ -25,7 +25,9 @@
- #include <linux/mm.h>
- #include <linux/mman.h>
- #include <linux/slab.h>
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,10,0)
- #include <mach/hardware.h>
-+#endif
- #include <linux/pm_runtime.h>
-
- #define _GC_OBJ_ZONE gcvZONE_DEVICE
-@@ -305,6 +307,7 @@ gckGALDEVICE_Construct(
- IN gctUINT LogFileSize,
- IN struct device *pdev,
- IN gctINT PowerManagement,
-+ IN gctINT GpuProfiler,
- OUT gckGALDEVICE *Device
- )
- {
-@@ -369,6 +372,10 @@ gckGALDEVICE_Construct(
- #if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0)
- /*get gpu regulator*/
- device->gpu_regulator = regulator_get(pdev, "cpu_vddgpu");
-+#elif LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
-+ device->gpu_regulator = regulator_get(pdev, "vddpu");
-+#endif
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0) || LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
- if (IS_ERR(device->gpu_regulator)) {
- gcmkTRACE_ZONE(gcvLEVEL_ERROR, gcvZONE_DRIVER,
- "%s(%d): Failed to get gpu regulator %s/%s \n",
-@@ -541,6 +548,10 @@ gckGALDEVICE_Construct(
- device->kernels[gcvCORE_MAJOR]->hardware, PowerManagement
- ));
-
-+ gcmkONERROR(gckHARDWARE_SetGpuProfiler(
-+ device->kernels[gcvCORE_MAJOR]->hardware, GpuProfiler
-+ ));
-+
- #if COMMAND_PROCESSOR_VERSION == 1
- /* Start the command queue. */
- gcmkONERROR(gckCOMMAND_Start(device->kernels[gcvCORE_MAJOR]->command));
-@@ -599,6 +610,7 @@ gckGALDEVICE_Construct(
- device->kernels[gcvCORE_2D]->hardware, PowerManagement
- ));
-
-+
- #if COMMAND_PROCESSOR_VERSION == 1
- /* Start the command queue. */
- gcmkONERROR(gckCOMMAND_Start(device->kernels[gcvCORE_2D]->command));
-@@ -635,6 +647,7 @@ gckGALDEVICE_Construct(
- device->kernels[gcvCORE_VG]->vg->hardware,
- PowerManagement
- ));
-+
- #endif
- }
- else
-@@ -849,6 +862,7 @@ gckGALDEVICE_Construct(
- }
- else
- {
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,10,0)
- mem_region = request_mem_region(
- ContiguousBase, ContiguousSize, "galcore managed memory"
- );
-@@ -864,6 +878,7 @@ gckGALDEVICE_Construct(
-
- gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
- }
-+#endif
-
- device->requestedContiguousBase = ContiguousBase;
- device->requestedContiguousSize = ContiguousSize;
-@@ -1107,7 +1122,7 @@ gckGALDEVICE_Destroy(
- pm_runtime_disable(Device->pmdev);
- #endif
-
--#if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0)
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0) || LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
- if (Device->gpu_regulator) {
- regulator_put(Device->gpu_regulator);
- Device->gpu_regulator = NULL;
-diff --git a/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_device.h b/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_device.h
-index dde4f03..c51432f 100644
---- a/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_device.h
-+++ b/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_device.h
-@@ -26,6 +26,15 @@
- ******************************* gckGALDEVICE Structure *******************************
- \******************************************************************************/
-
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
-+struct contiguous_mem_pool {
-+ struct dma_attrs attrs;
-+ dma_addr_t phys;
-+ void *virt;
-+ size_t size;
-+};
-+#endif
-+
- typedef struct _gckGALDEVICE
- {
- /* Objects. */
-@@ -91,12 +100,16 @@ typedef struct _gckGALDEVICE
- struct clk *clk_2d_axi;
- struct clk *clk_vg_axi;
-
--#if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0)
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0) || LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
- /*Power management.*/
- struct regulator *gpu_regulator;
- #endif
- /*Run time pm*/
- struct device *pmdev;
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
-+ struct contiguous_mem_pool *pool;
-+ struct reset_control *rstc[gcdMAX_GPU_COUNT];
-+#endif
- }
- * gckGALDEVICE;
-
-@@ -171,6 +184,7 @@ gceSTATUS gckGALDEVICE_Construct(
- IN gctUINT LogFileSize,
- IN struct device *pdev,
- IN gctINT PowerManagement,
-+ IN gctINT GpuProfiler,
- OUT gckGALDEVICE *Device
- );
-
-diff --git a/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_driver.c b/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_driver.c
-index bacd531..88a7e4e6 100644
---- a/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_driver.c
-+++ b/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_driver.c
-@@ -1,7 +1,7 @@
- /****************************************************************************
- *
- * Copyright (C) 2005 - 2013 by Vivante Corp.
--* Copyright (C) 2011-2012 Freescale Semiconductor, Inc.
-+* Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
-@@ -69,14 +69,26 @@ task_notify_func(struct notifier_block *self, unsigned long val, void *data)
- #include <mach/viv_gpu.h>
- #else
- #include <linux/pm_runtime.h>
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,10,0)
- #include <mach/busfreq.h>
-+#else
-+#include <linux/reset.h>
-+#endif
- #endif
- /* Zone used for header/footer. */
- #define _GC_OBJ_ZONE gcvZONE_DRIVER
-
- #if gcdENABLE_FSCALE_VAL_ADJUST
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
-+#include <linux/device_cooling.h>
-+#define REG_THERMAL_NOTIFIER(a) register_devfreq_cooling_notifier(a);
-+#define UNREG_THERMAL_NOTIFIER(a) unregister_devfreq_cooling_notifier(a);
-+#else
- extern int register_thermal_notifier(struct notifier_block *nb);
- extern int unregister_thermal_notifier(struct notifier_block *nb);
-+#define REG_THERMAL_NOTIFIER(a) register_thermal_notifier(a);
-+#define UNREG_THERMAL_NOTIFIER(a) unregister_thermal_notifier(a);
-+#endif
- #endif
-
- MODULE_DESCRIPTION("Vivante Graphics Driver");
-@@ -116,7 +128,11 @@ module_param(registerMemBaseVG, ulong, 0644);
- static ulong registerMemSizeVG = 2 << 10;
- module_param(registerMemSizeVG, ulong, 0644);
-
-+#if gcdENABLE_FSCALE_VAL_ADJUST
-+static ulong contiguousSize = 128 << 20;
-+#else
- static ulong contiguousSize = 4 << 20;
-+#endif
- module_param(contiguousSize, ulong, 0644);
-
- static ulong contiguousBase = 0;
-@@ -134,6 +150,9 @@ module_param(compression, int, 0644);
- static int powerManagement = 1;
- module_param(powerManagement, int, 0644);
-
-+static int gpuProfiler = 0;
-+module_param(gpuProfiler, int, 0644);
-+
- static int signal = 48;
- module_param(signal, int, 0644);
-
-@@ -786,7 +805,9 @@ static int drv_init(struct device *pdev)
-
- printk(KERN_INFO "Galcore version %d.%d.%d.%d\n",
- gcvVERSION_MAJOR, gcvVERSION_MINOR, gcvVERSION_PATCH, gcvVERSION_BUILD);
--
-+ /* when enable gpu profiler, we need to turn off gpu powerMangement */
-+ if(gpuProfiler)
-+ powerManagement = 0;
- if (showArgs)
- {
- printk("galcore options:\n");
-@@ -818,6 +839,7 @@ static int drv_init(struct device *pdev)
- printk(" physSize = 0x%08lX\n", physSize);
- printk(" logFileSize = %d KB \n", logFileSize);
- printk(" powerManagement = %d\n", powerManagement);
-+ printk(" gpuProfiler = %d\n", gpuProfiler);
- #if ENABLE_GPU_CLOCK_BY_DRIVER
- printk(" coreClock = %lu\n", coreClock);
- #endif
-@@ -841,9 +863,14 @@ static int drv_init(struct device *pdev)
- logFileSize,
- pdev,
- powerManagement,
-+ gpuProfiler,
- &device
- ));
-
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
-+ device->pool = dev_get_drvdata(pdev);
-+#endif
-+
- /* Start the GAL device. */
- gcmkONERROR(gckGALDEVICE_Start(device));
-
-@@ -1028,11 +1055,18 @@ static struct notifier_block thermal_hot_pm_notifier = {
-
-
-
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)
-+static int gpu_probe(struct platform_device *pdev)
-+#else
- static int __devinit gpu_probe(struct platform_device *pdev)
-+#endif
- {
- int ret = -ENODEV;
- struct resource* res;
--#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,5,0)
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
-+ struct contiguous_mem_pool *pool;
-+ struct reset_control *rstc;
-+#elif LINUX_VERSION_CODE >= KERNEL_VERSION(3,5,0)
- struct device_node *dn =pdev->dev.of_node;
- const u32 *prop;
- #else
-@@ -1077,7 +1111,22 @@ static int __devinit gpu_probe(struct platform_device *pdev)
- registerMemSizeVG = res->end - res->start + 1;
- }
-
--#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,5,0)
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
-+ pool = devm_kzalloc(&pdev->dev, sizeof(*pool), GFP_KERNEL);
-+ if (!pool)
-+ return -ENOMEM;
-+ pool->size = contiguousSize;
-+ init_dma_attrs(&pool->attrs);
-+ dma_set_attr(DMA_ATTR_WRITE_COMBINE, &pool->attrs);
-+ pool->virt = dma_alloc_attrs(&pdev->dev, pool->size, &pool->phys,
-+ GFP_KERNEL, &pool->attrs);
-+ if (!pool->virt) {
-+ dev_err(&pdev->dev, "Failed to allocate contiguous memory\n");
-+ return -ENOMEM;
-+ }
-+ contiguousBase = pool->phys;
-+ dev_set_drvdata(&pdev->dev, pool);
-+#elif LINUX_VERSION_CODE >= KERNEL_VERSION(3,5,0)
- prop = of_get_property(dn, "contiguousbase", NULL);
- if(prop)
- contiguousBase = *prop;
-@@ -1095,30 +1144,56 @@ static int __devinit gpu_probe(struct platform_device *pdev)
-
- if (!ret)
- {
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
-+ rstc = devm_reset_control_get(&pdev->dev, "gpu3d");
-+ galDevice->rstc[gcvCORE_MAJOR] = IS_ERR(rstc) ? NULL : rstc;
-+
-+ rstc = devm_reset_control_get(&pdev->dev, "gpu2d");
-+ galDevice->rstc[gcvCORE_2D] = IS_ERR(rstc) ? NULL : rstc;
-+
-+ rstc = devm_reset_control_get(&pdev->dev, "gpuvg");
-+ galDevice->rstc[gcvCORE_VG] = IS_ERR(rstc) ? NULL : rstc;
-+#endif
- platform_set_drvdata(pdev, galDevice);
-
- #if gcdENABLE_FSCALE_VAL_ADJUST
-- if(galDevice->kernels[gcvCORE_MAJOR])
-- register_thermal_notifier(&thermal_hot_pm_notifier);
-+ if (galDevice->kernels[gcvCORE_MAJOR])
-+ REG_THERMAL_NOTIFIER(&thermal_hot_pm_notifier);
- #endif
- gcmkFOOTER_NO();
- return ret;
- }
- #if gcdENABLE_FSCALE_VAL_ADJUST
-- unregister_thermal_notifier(&thermal_hot_pm_notifier);
-+ UNREG_THERMAL_NOTIFIER(&thermal_hot_pm_notifier);
-+#endif
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
-+ dma_free_attrs(&pdev->dev, pool->size, pool->virt, pool->phys,
-+ &pool->attrs);
- #endif
- gcmkFOOTER_ARG(KERN_INFO "Failed to register gpu driver: %d\n", ret);
- return ret;
- }
-
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)
-+static int gpu_remove(struct platform_device *pdev)
-+#else
- static int __devexit gpu_remove(struct platform_device *pdev)
-+#endif
- {
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
-+ gckGALDEVICE device = platform_get_drvdata(pdev);
-+ struct contiguous_mem_pool *pool = device->pool;
-+#endif
- gcmkHEADER();
- #if gcdENABLE_FSCALE_VAL_ADJUST
- if(galDevice->kernels[gcvCORE_MAJOR])
-- unregister_thermal_notifier(&thermal_hot_pm_notifier);
-+ UNREG_THERMAL_NOTIFIER(&thermal_hot_pm_notifier);
- #endif
- drv_exit();
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
-+ dma_free_attrs(&pdev->dev, pool->size, pool->virt, pool->phys,
-+ &pool->attrs);
-+#endif
- gcmkFOOTER_NO();
- return 0;
- }
-@@ -1254,13 +1329,17 @@ MODULE_DEVICE_TABLE(of, mxs_gpu_dt_ids);
- #ifdef CONFIG_PM
- static int gpu_runtime_suspend(struct device *dev)
- {
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,10,0)
- release_bus_freq(BUS_FREQ_HIGH);
-+#endif
- return 0;
- }
-
- static int gpu_runtime_resume(struct device *dev)
- {
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,10,0)
- request_bus_freq(BUS_FREQ_HIGH);
-+#endif
- return 0;
- }
-
-@@ -1284,7 +1363,11 @@ static const struct dev_pm_ops gpu_pm_ops = {
-
- static struct platform_driver gpu_driver = {
- .probe = gpu_probe,
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)
-+ .remove = gpu_remove,
-+#else
- .remove = __devexit_p(gpu_remove),
-+#endif
-
- .suspend = gpu_suspend,
- .resume = gpu_resume,
-diff --git a/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_os.c b/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_os.c
-index e7edc39..331c73f 100644
---- a/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_os.c
-+++ b/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_os.c
-@@ -30,19 +30,30 @@
- #include <linux/dma-mapping.h>
- #include <linux/slab.h>
- #include <linux/idr.h>
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,10,0)
- #include <mach/hardware.h>
-+#endif
- #include <linux/workqueue.h>
- #include <linux/idr.h>
- #if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,23)
- #include <linux/math64.h>
- #endif
--#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,5,0)
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
-+#include <linux/reset.h>
-+static inline void imx_gpc_power_up_pu(bool flag) {}
-+#elif LINUX_VERSION_CODE >= KERNEL_VERSION(3,5,0)
- #include <mach/common.h>
- #endif
- #include <linux/delay.h>
- #include <linux/pm_runtime.h>
-
-
-+#if gcdANDROID_NATIVE_FENCE_SYNC
-+#include <linux/file.h>
-+#include "gc_hal_kernel_sync.h"
-+#endif
-+
-+
- #define _GC_OBJ_ZONE gcvZONE_OS
-
- /*******************************************************************************
-@@ -148,6 +159,7 @@ typedef struct _gcsINTEGER_DB
- {
- struct idr idr;
- spinlock_t lock;
-+ gctINT curr;
- }
- gcsINTEGER_DB;
-
-@@ -180,6 +192,14 @@ struct _gckOS
- /* signal id database. */
- gcsINTEGER_DB signalDB;
-
-+#if gcdANDROID_NATIVE_FENCE_SYNC
-+ /* Lock. */
-+ gctPOINTER syncPointMutex;
-+
-+ /* sync point id database. */
-+ gcsINTEGER_DB syncPointDB;
-+#endif
-+
- gcsUSER_MAPPING_PTR userMap;
- gctPOINTER debugLock;
-
-@@ -215,6 +235,25 @@ typedef struct _gcsSIGNAL
- }
- gcsSIGNAL;
-
-+#if gcdANDROID_NATIVE_FENCE_SYNC
-+typedef struct _gcsSYNC_POINT * gcsSYNC_POINT_PTR;
-+typedef struct _gcsSYNC_POINT
-+{
-+ /* The reference counter. */
-+ atomic_t ref;
-+
-+ /* State. */
-+ atomic_t state;
-+
-+ /* timeline. */
-+ struct sync_timeline * timeline;
-+
-+ /* ID. */
-+ gctUINT32 id;
-+}
-+gcsSYNC_POINT;
-+#endif
-+
- typedef struct _gcsPageInfo * gcsPageInfo_PTR;
- typedef struct _gcsPageInfo
- {
-@@ -767,7 +806,32 @@ _AllocateIntegerId(
- )
- {
- int result;
-+ gctINT next;
-+
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)
-+ idr_preload(GFP_KERNEL | gcdNOWARN);
-
-+ spin_lock(&Database->lock);
-+
-+ next = (Database->curr + 1 <= 0) ? 1 : Database->curr + 1;
-+ result = idr_alloc(&Database->idr, KernelPointer, next, 0, GFP_ATOMIC);
-+
-+ if (!result)
-+ {
-+ Database->curr = *Id;
-+ }
-+
-+ spin_unlock(&Database->lock);
-+
-+ idr_preload_end();
-+
-+ if (result < 0)
-+ {
-+ return gcvSTATUS_OUT_OF_RESOURCES;
-+ }
-+
-+ *Id = result;
-+#else
- again:
- if (idr_pre_get(&Database->idr, GFP_KERNEL | gcdNOWARN) == 0)
- {
-@@ -776,8 +840,15 @@ again:
-
- spin_lock(&Database->lock);
-
-- /* Try to get a id greater than 0. */
-- result = idr_get_new_above(&Database->idr, KernelPointer, 1, Id);
-+ next = (Database->curr + 1 <= 0) ? 1 : Database->curr + 1;
-+
-+ /* Try to get a id greater than current id. */
-+ result = idr_get_new_above(&Database->idr, KernelPointer, next, Id);
-+
-+ if (!result)
-+ {
-+ Database->curr = *Id;
-+ }
-
- spin_unlock(&Database->lock);
-
-@@ -790,6 +861,7 @@ again:
- {
- return gcvSTATUS_OUT_OF_RESOURCES;
- }
-+#endif
-
- return gcvSTATUS_OK;
- }
-@@ -1008,6 +1080,21 @@ gckOS_Construct(
- /* Initialize signal id database. */
- idr_init(&os->signalDB.idr);
-
-+#if gcdANDROID_NATIVE_FENCE_SYNC
-+ /*
-+ * Initialize the sync point manager.
-+ */
-+
-+ /* Initialize mutex. */
-+ gcmkONERROR(gckOS_CreateMutex(os, &os->syncPointMutex));
-+
-+ /* Initialize sync point id database lock. */
-+ spin_lock_init(&os->syncPointDB.lock);
-+
-+ /* Initialize sync point id database. */
-+ idr_init(&os->syncPointDB.idr);
-+#endif
-+
- #if gcdUSE_NON_PAGED_MEMORY_CACHE
- os->cacheSize = 0;
- os->cacheHead = gcvNULL;
-@@ -1031,6 +1118,15 @@ gckOS_Construct(
- return gcvSTATUS_OK;
-
- OnError:
-+
-+#if gcdANDROID_NATIVE_FENCE_SYNC
-+ if (os->syncPointMutex != gcvNULL)
-+ {
-+ gcmkVERIFY_OK(
-+ gckOS_DeleteMutex(os, os->syncPointMutex));
-+ }
-+#endif
-+
- if (os->signalMutex != gcvNULL)
- {
- gcmkVERIFY_OK(
-@@ -1104,6 +1200,15 @@ gckOS_Destroy(
- _FreeAllNonPagedMemoryCache(Os);
- #endif
-
-+#if gcdANDROID_NATIVE_FENCE_SYNC
-+ /*
-+ * Destroy the sync point manager.
-+ */
-+
-+ /* Destroy the mutex. */
-+ gcmkVERIFY_OK(gckOS_DeleteMutex(Os, Os->syncPointMutex));
-+#endif
-+
- /*
- * Destroy the signal manager.
- */
-@@ -1961,12 +2066,6 @@ gckOS_AllocateNonPagedMemory(
- gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
- }
-
-- if ((Os->device->baseAddress & 0x80000000) != (mdl->dmaHandle & 0x80000000))
-- {
-- mdl->dmaHandle = (mdl->dmaHandle & ~0x80000000)
-- | (Os->device->baseAddress & 0x80000000);
-- }
--
- mdl->addr = addr;
-
- /* Return allocated memory. */
-@@ -2307,6 +2406,7 @@ gckOS_ReadRegisterEx(
-
- /* Verify the arguments. */
- gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
-+ gcmkVERIFY_ARGUMENT(Address < Os->device->requestedRegisterMemSizes[Core]);
- gcmkVERIFY_ARGUMENT(Data != gcvNULL);
-
- *Data = readl((gctUINT8 *)Os->device->registerBases[Core] + Address);
-@@ -2357,6 +2457,8 @@ gckOS_WriteRegisterEx(
- {
- gcmkHEADER_ARG("Os=0x%X Core=%d Address=0x%X Data=0x%08x", Os, Core, Address, Data);
-
-+ gcmkVERIFY_ARGUMENT(Address < Os->device->requestedRegisterMemSizes[Core]);
-+
- writel(Data, (gctUINT8 *)Os->device->registerBases[Core] + Address);
-
- /* Success. */
-@@ -2799,16 +2901,25 @@ gckOS_MapPhysical(
-
- if (mdl == gcvNULL)
- {
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
-+ struct contiguous_mem_pool *pool = Os->device->pool;
-+
-+ if (Physical >= pool->phys && Physical < pool->phys + pool->size)
-+ logical = (gctPOINTER)(Physical - pool->phys + pool->virt);
-+ else
-+ logical = gcvNULL;
-+#else
- /* Map memory as cached memory. */
- request_mem_region(physical, Bytes, "MapRegion");
- logical = (gctPOINTER) ioremap_nocache(physical, Bytes);
-+#endif
-
- if (logical == gcvNULL)
- {
- gcmkTRACE_ZONE(
- gcvLEVEL_INFO, gcvZONE_OS,
-- "%s(%d): Failed to ioremap",
-- __FUNCTION__, __LINE__
-+ "%s(%d): Failed to map physical address 0x%08x",
-+ __FUNCTION__, __LINE__, Physical
- );
-
- MEMORY_UNLOCK(Os);
-@@ -3621,7 +3732,7 @@ gckOS_Delay(
- if (Delay > 0)
- {
- #if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 28)
-- ktime_t delay = ktime_set(0, Delay * NSEC_PER_MSEC);
-+ ktime_t delay = ktime_set(Delay/1000, (Delay%1000) * NSEC_PER_MSEC);
- __set_current_state(TASK_UNINTERRUPTIBLE);
- schedule_hrtimeout(&delay, HRTIMER_MODE_REL);
- #else
-@@ -3881,8 +3992,13 @@ gckOS_AllocatePagedMemoryEx(
-
- if (Contiguous)
- {
-- /* Get contiguous pages, and suppress warning (stack dump) from kernel when
-- we run out of memory. */
-+ gctUINT32 order = get_order(bytes);
-+
-+ if (order >= MAX_ORDER)
-+ {
-+ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
-+ }
-+
- #if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)
- addr =
- alloc_pages_exact(numPages * PAGE_SIZE, GFP_KERNEL | gcdNOWARN | __GFP_NORETRY);
-@@ -3894,12 +4010,12 @@ gckOS_AllocatePagedMemoryEx(
- mdl->exact = gcvTRUE;
- #else
- mdl->u.contiguousPages =
-- alloc_pages(GFP_KERNEL | gcdNOWARN | __GFP_NORETRY, GetOrder(numPages));
-+ alloc_pages(GFP_KERNEL | gcdNOWARN | __GFP_NORETRY, order);
- #endif
- if (mdl->u.contiguousPages == gcvNULL)
- {
- mdl->u.contiguousPages =
-- alloc_pages(GFP_KERNEL | __GFP_HIGHMEM | gcdNOWARN, GetOrder(numPages));
-+ alloc_pages(GFP_KERNEL | __GFP_HIGHMEM | gcdNOWARN, order);
-
- #if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)
- mdl->exact = gcvFALSE;
-@@ -4239,13 +4355,13 @@ gckOS_LockPages(
- }
-
- mdlMap->vma->vm_flags |= gcdVM_FLAGS;
--#if !gcdPAGED_MEMORY_CACHEABLE
-+
- if (Cacheable == gcvFALSE)
- {
- /* Make this mapping non-cached. */
- mdlMap->vma->vm_page_prot = gcmkPAGED_MEMROY_PROT(mdlMap->vma->vm_page_prot);
- }
--#endif
-+
- addr = mdl->addr;
-
- /* Now map all the vmalloc pages to this user address. */
-@@ -5336,6 +5452,7 @@ OnError:
- {
- /* Get the user pages. */
- down_read(¤t->mm->mmap_sem);
-+
- result = get_user_pages(current,
- current->mm,
- memory & PAGE_MASK,
-@@ -5345,105 +5462,127 @@ OnError:
- pages,
- gcvNULL
- );
-+
- up_read(¤t->mm->mmap_sem);
-
- if (result <=0 || result < pageCount)
- {
- struct vm_area_struct *vma;
-
-- /* Free the page table. */
-- if (pages != gcvNULL)
-+ /* Release the pages if any. */
-+ if (result > 0)
- {
-- /* Release the pages if any. */
-- if (result > 0)
-+ for (i = 0; i < result; i++)
- {
-- for (i = 0; i < result; i++)
-+ if (pages[i] == gcvNULL)
- {
-- if (pages[i] == gcvNULL)
-- {
-- break;
-- }
--
-- page_cache_release(pages[i]);
-+ break;
- }
-+
-+ page_cache_release(pages[i]);
-+ pages[i] = gcvNULL;
- }
-
-- kfree(pages);
-- pages = gcvNULL;
-+ result = 0;
- }
-
- vma = find_vma(current->mm, memory);
-
-- if (vma && (vma->vm_flags & VM_PFNMAP) )
-+ if (vma && (vma->vm_flags & VM_PFNMAP))
- {
- pte_t * pte;
- spinlock_t * ptl;
-- unsigned long pfn;
-+ gctUINTPTR_T logical = memory;
-
-- pgd_t * pgd = pgd_offset(current->mm, memory);
-- pud_t * pud = pud_offset(pgd, memory);
-- if (pud)
-+ for (i = 0; i < pageCount; i++)
- {
-- pmd_t * pmd = pmd_offset(pud, memory);
-- pte = pte_offset_map_lock(current->mm, pmd, memory, &ptl);
-- if (!pte)
-+ pgd_t * pgd = pgd_offset(current->mm, logical);
-+ pud_t * pud = pud_offset(pgd, logical);
-+
-+ if (pud)
-+ {
-+ pmd_t * pmd = pmd_offset(pud, logical);
-+ pte = pte_offset_map_lock(current->mm, pmd, logical, &ptl);
-+ if (!pte)
-+ {
-+ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
-+ }
-+ }
-+ else
- {
- gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
- }
-+
-+ pages[i] = pte_page(*pte);
-+ pte_unmap_unlock(pte, ptl);
-+
-+ /* Advance to next. */
-+ logical += PAGE_SIZE;
- }
-- else
-+ }
-+ else
-+ {
-+ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
-+ }
-+
-+ /* Check if this memory is contiguous for old mmu. */
-+ if (Os->device->kernels[Core]->hardware->mmuVersion == 0)
-+ {
-+ for (i = 1; i < pageCount; i++)
- {
-- gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
-+ if (pages[i] != nth_page(pages[0], i))
-+ {
-+ /* Non-contiguous. */
-+ break;
-+ }
- }
-
-- pfn = pte_pfn(*pte);
--
-- physical = (pfn << PAGE_SHIFT) | (memory & ~PAGE_MASK);
-+ if (i == pageCount)
-+ {
-+ /* Contiguous memory. */
-+ physical = page_to_phys(pages[0]) | (memory & ~PAGE_MASK);
-
-- pte_unmap_unlock(pte, ptl);
-+ if (!((physical - Os->device->baseAddress) & 0x80000000))
-+ {
-+ kfree(pages);
-+ pages = gcvNULL;
-
-- if ((Os->device->kernels[Core]->hardware->mmuVersion == 0)
-- && !((physical - Os->device->baseAddress) & 0x80000000))
-- {
-- info->pages = gcvNULL;
-- info->pageTable = gcvNULL;
-+ info->pages = gcvNULL;
-+ info->pageTable = gcvNULL;
-
-- MEMORY_MAP_UNLOCK(Os);
-+ MEMORY_MAP_UNLOCK(Os);
-
-- *Address = physical - Os->device->baseAddress;
-- *Info = info;
-+ *Address = physical - Os->device->baseAddress;
-+ *Info = info;
-
-- gcmkFOOTER_ARG("*Info=0x%X *Address=0x%08x",
-- *Info, *Address);
-+ gcmkFOOTER_ARG("*Info=0x%X *Address=0x%08x",
-+ *Info, *Address);
-
-- return gcvSTATUS_OK;
-+ return gcvSTATUS_OK;
-+ }
- }
- }
-- else
-+
-+ /* Reference pages. */
-+ for (i = 0; i < pageCount; i++)
- {
-- gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
-+ get_page(pages[i]);
- }
- }
- }
-
-- if (pages)
-- {
-- for (i = 0; i < pageCount; i++)
-- {
-- /* Flush(clean) the data cache. */
-- gcmkONERROR(gckOS_CacheFlush(Os, _GetProcessID(), gcvNULL,
-- (gctPOINTER)(gctUINTPTR_T)page_to_phys(pages[i]),
-- (gctPOINTER)(memory & PAGE_MASK) + i*PAGE_SIZE,
-- PAGE_SIZE));
-- }
-- }
-- else
-+ for (i = 0; i < pageCount; i++)
- {
-+#ifdef CONFIG_ARM
-+ gctUINT32 data;
-+ get_user(data, (gctUINT32*)((memory & PAGE_MASK) + i * PAGE_SIZE));
-+#endif
-+
- /* Flush(clean) the data cache. */
- gcmkONERROR(gckOS_CacheFlush(Os, _GetProcessID(), gcvNULL,
-- (gctPOINTER)(gctUINTPTR_T)(physical & PAGE_MASK),
-- (gctPOINTER)(memory & PAGE_MASK),
-- PAGE_SIZE * pageCount));
-+ (gctPOINTER)(gctUINTPTR_T)page_to_phys(pages[i]),
-+ (gctPOINTER)(memory & PAGE_MASK) + i*PAGE_SIZE,
-+ PAGE_SIZE));
- }
-
- #if gcdENABLE_VG
-@@ -5464,20 +5603,14 @@ OnError:
- (gctPOINTER *) &pageTable,
- &address));
- }
-+
- /* Fill the page table. */
- for (i = 0; i < pageCount; i++)
- {
- gctUINT32 phys;
- gctUINT32_PTR tab = pageTable + i * (PAGE_SIZE/4096);
-
-- if (pages)
-- {
-- phys = page_to_phys(pages[i]);
-- }
-- else
-- {
-- phys = (physical & PAGE_MASK) + i * PAGE_SIZE;
-- }
-+ phys = page_to_phys(pages[i]);
-
- #if gcdENABLE_VG
- if (Core == gcvCORE_VG)
-@@ -6126,7 +6259,7 @@ gckOS_CacheClean(
- #else
- dma_sync_single_for_device(
- gcvNULL,
-- Physical,
-+ (dma_addr_t)Physical,
- Bytes,
- DMA_TO_DEVICE);
- #endif
-@@ -6205,7 +6338,7 @@ gckOS_CacheInvalidate(
- #else
- dma_sync_single_for_device(
- gcvNULL,
-- Physical,
-+ (dma_addr_t)Physical,
- Bytes,
- DMA_FROM_DEVICE);
- #endif
-@@ -6279,7 +6412,7 @@ gckOS_CacheFlush(
- #else
- dma_sync_single_for_device(
- gcvNULL,
-- Physical,
-+ (dma_addr_t)Physical,
- Bytes,
- DMA_BIDIRECTIONAL);
- #endif
-@@ -6827,6 +6960,9 @@ gckOS_SetGPUPower(
- struct clk *clk_2dcore = Os->device->clk_2d_core;
- struct clk *clk_2d_axi = Os->device->clk_2d_axi;
- struct clk *clk_vg_axi = Os->device->clk_vg_axi;
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0) || LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
-+ int ret;
-+#endif
-
- gctBOOL oldClockState = gcvFALSE;
- gctBOOL oldPowerState = gcvFALSE;
-@@ -6852,9 +6988,13 @@ gckOS_SetGPUPower(
- }
- if((Power == gcvTRUE) && (oldPowerState == gcvFALSE))
- {
--#if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0)
-- if(!IS_ERR(Os->device->gpu_regulator))
-- regulator_enable(Os->device->gpu_regulator);
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0) || LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
-+ if(!IS_ERR(Os->device->gpu_regulator)) {
-+ ret = regulator_enable(Os->device->gpu_regulator);
-+ if (ret != 0)
-+ gckOS_Print("%s(%d): fail to enable pu regulator %d!\n",
-+ __FUNCTION__, __LINE__, ret);
-+ }
- #else
- imx_gpc_power_up_pu(true);
- #endif
-@@ -6969,7 +7109,7 @@ gckOS_SetGPUPower(
- pm_runtime_put_sync(Os->device->pmdev);
- #endif
-
--#if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0)
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0) || LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
- if(!IS_ERR(Os->device->gpu_regulator))
- regulator_disable(Os->device->gpu_regulator);
- #else
-@@ -7033,6 +7173,10 @@ gckOS_ResetGPU(
- }
-
- gcmkFOOTER_NO();
-+#elif LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
-+ struct reset_control *rstc = Os->device->rstc[Core];
-+ if (rstc)
-+ reset_control_reset(rstc);
- #else
- imx_src_reset_gpu((int)Core);
- #endif
-@@ -8529,3 +8673,338 @@ gckOS_GetProcessNameByPid(
- return gcvSTATUS_OK;
- }
-
-+#if gcdANDROID_NATIVE_FENCE_SYNC
-+
-+gceSTATUS
-+gckOS_CreateSyncPoint(
-+ IN gckOS Os,
-+ OUT gctSYNC_POINT * SyncPoint
-+ )
-+{
-+ gceSTATUS status;
-+ gcsSYNC_POINT_PTR syncPoint;
-+
-+ gcmkHEADER_ARG("Os=0x%X", Os);
-+
-+ /* Verify the arguments. */
-+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
-+
-+ /* Create an sync point structure. */
-+ syncPoint = (gcsSYNC_POINT_PTR) kmalloc(
-+ sizeof(gcsSYNC_POINT), GFP_KERNEL | gcdNOWARN);
-+
-+ if (syncPoint == gcvNULL)
-+ {
-+ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
-+ }
-+
-+ /* Initialize the sync point. */
-+ atomic_set(&syncPoint->ref, 1);
-+ atomic_set(&syncPoint->state, 0);
-+
-+ gcmkONERROR(_AllocateIntegerId(&Os->syncPointDB, syncPoint, &syncPoint->id));
-+
-+ *SyncPoint = (gctSYNC_POINT)(gctUINTPTR_T)syncPoint->id;
-+
-+ gcmkFOOTER_ARG("*SyncPonint=%d", syncPoint->id);
-+ return gcvSTATUS_OK;
-+
-+OnError:
-+ if (syncPoint != gcvNULL)
-+ {
-+ kfree(syncPoint);
-+ }
-+
-+ gcmkFOOTER();
-+ return status;
-+}
-+
-+gceSTATUS
-+gckOS_ReferenceSyncPoint(
-+ IN gckOS Os,
-+ IN gctSYNC_POINT SyncPoint
-+ )
-+{
-+ gceSTATUS status;
-+ gcsSYNC_POINT_PTR syncPoint;
-+
-+ gcmkHEADER_ARG("Os=0x%X", Os);
-+
-+ /* Verify the arguments. */
-+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
-+ gcmkVERIFY_ARGUMENT(SyncPoint != gcvNULL);
-+
-+ gcmkONERROR(
-+ _QueryIntegerId(&Os->syncPointDB,
-+ (gctUINT32)(gctUINTPTR_T)SyncPoint,
-+ (gctPOINTER)&syncPoint));
-+
-+ /* Initialize the sync point. */
-+ atomic_inc(&syncPoint->ref);
-+
-+ gcmkFOOTER_NO();
-+ return gcvSTATUS_OK;
-+
-+OnError:
-+ gcmkFOOTER();
-+ return status;
-+}
-+
-+gceSTATUS
-+gckOS_DestroySyncPoint(
-+ IN gckOS Os,
-+ IN gctSYNC_POINT SyncPoint
-+ )
-+{
-+ gceSTATUS status;
-+ gcsSYNC_POINT_PTR syncPoint;
-+ gctBOOL acquired = gcvFALSE;
-+
-+ gcmkHEADER_ARG("Os=0x%X SyncPoint=%d", Os, (gctUINT32)(gctUINTPTR_T)SyncPoint);
-+
-+ /* Verify the arguments. */
-+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
-+ gcmkVERIFY_ARGUMENT(SyncPoint != gcvNULL);
-+
-+ gcmkONERROR(gckOS_AcquireMutex(Os, Os->syncPointMutex, gcvINFINITE));
-+ acquired = gcvTRUE;
-+
-+ gcmkONERROR(
-+ _QueryIntegerId(&Os->syncPointDB,
-+ (gctUINT32)(gctUINTPTR_T)SyncPoint,
-+ (gctPOINTER)&syncPoint));
-+
-+ gcmkASSERT(syncPoint->id == (gctUINT32)(gctUINTPTR_T)SyncPoint);
-+
-+ if (atomic_dec_and_test(&syncPoint->ref))
-+ {
-+ gcmkVERIFY_OK(_DestroyIntegerId(&Os->syncPointDB, syncPoint->id));
-+
-+ /* Free the sgianl. */
-+ syncPoint->timeline = gcvNULL;
-+ kfree(syncPoint);
-+ }
-+
-+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Os, Os->syncPointMutex));
-+ acquired = gcvFALSE;
-+
-+ /* Success. */
-+ gcmkFOOTER_NO();
-+ return gcvSTATUS_OK;
-+
-+OnError:
-+ if (acquired)
-+ {
-+ /* Release the mutex. */
-+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Os, Os->syncPointMutex));
-+ }
-+
-+ gcmkFOOTER();
-+ return status;
-+}
-+
-+gceSTATUS
-+gckOS_SignalSyncPoint(
-+ IN gckOS Os,
-+ IN gctSYNC_POINT SyncPoint
-+ )
-+{
-+ gceSTATUS status;
-+ gcsSYNC_POINT_PTR syncPoint;
-+ gctBOOL acquired = gcvFALSE;
-+
-+ gcmkHEADER_ARG("Os=0x%X SyncPoint=%d", Os, (gctUINT32)(gctUINTPTR_T)SyncPoint);
-+
-+ /* Verify the arguments. */
-+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
-+ gcmkVERIFY_ARGUMENT(SyncPoint != gcvNULL);
-+
-+ gcmkONERROR(gckOS_AcquireMutex(Os, Os->syncPointMutex, gcvINFINITE));
-+ acquired = gcvTRUE;
-+
-+ gcmkONERROR(
-+ _QueryIntegerId(&Os->syncPointDB,
-+ (gctUINT32)(gctUINTPTR_T)SyncPoint,
-+ (gctPOINTER)&syncPoint));
-+
-+ gcmkASSERT(syncPoint->id == (gctUINT32)(gctUINTPTR_T)SyncPoint);
-+
-+ /* Get state. */
-+ atomic_set(&syncPoint->state, gcvTRUE);
-+
-+ /* Signal timeline. */
-+ if (syncPoint->timeline)
-+ {
-+ sync_timeline_signal(syncPoint->timeline);
-+ }
-+
-+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Os, Os->syncPointMutex));
-+ acquired = gcvFALSE;
-+
-+ /* Success. */
-+ gcmkFOOTER_NO();
-+ return gcvSTATUS_OK;
-+
-+OnError:
-+ if (acquired)
-+ {
-+ /* Release the mutex. */
-+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Os, Os->syncPointMutex));
-+ }
-+
-+ gcmkFOOTER();
-+ return status;
-+}
-+
-+gceSTATUS
-+gckOS_QuerySyncPoint(
-+ IN gckOS Os,
-+ IN gctSYNC_POINT SyncPoint,
-+ OUT gctBOOL_PTR State
-+ )
-+{
-+ gceSTATUS status;
-+ gcsSYNC_POINT_PTR syncPoint;
-+
-+ gcmkHEADER_ARG("Os=0x%X SyncPoint=%d", Os, (gctUINT32)(gctUINTPTR_T)SyncPoint);
-+
-+ /* Verify the arguments. */
-+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
-+ gcmkVERIFY_ARGUMENT(SyncPoint != gcvNULL);
-+
-+ gcmkONERROR(
-+ _QueryIntegerId(&Os->syncPointDB,
-+ (gctUINT32)(gctUINTPTR_T)SyncPoint,
-+ (gctPOINTER)&syncPoint));
-+
-+ gcmkASSERT(syncPoint->id == (gctUINT32)(gctUINTPTR_T)SyncPoint);
-+
-+ /* Get state. */
-+ *State = atomic_read(&syncPoint->state);
-+
-+ /* Success. */
-+ gcmkFOOTER_ARG("*State=%d", *State);
-+ return gcvSTATUS_OK;
-+
-+OnError:
-+ gcmkFOOTER();
-+ return status;
-+}
-+
-+gceSTATUS
-+gckOS_CreateSyncTimeline(
-+ IN gckOS Os,
-+ OUT gctHANDLE * Timeline
-+ )
-+{
-+ struct viv_sync_timeline * timeline;
-+
-+ /* Create viv sync timeline. */
-+ timeline = viv_sync_timeline_create("viv timeline", Os);
-+
-+ if (timeline == gcvNULL)
-+ {
-+ /* Out of memory. */
-+ return gcvSTATUS_OUT_OF_MEMORY;
-+ }
-+
-+ *Timeline = (gctHANDLE) timeline;
-+ return gcvSTATUS_OK;
-+}
-+
-+gceSTATUS
-+gckOS_DestroySyncTimeline(
-+ IN gckOS Os,
-+ IN gctHANDLE Timeline
-+ )
-+{
-+ struct viv_sync_timeline * timeline;
-+ gcmkASSERT(Timeline != gcvNULL);
-+
-+ /* Destroy timeline. */
-+ timeline = (struct viv_sync_timeline *) Timeline;
-+ sync_timeline_destroy(&timeline->obj);
-+
-+ return gcvSTATUS_OK;
-+}
-+
-+gceSTATUS
-+gckOS_CreateNativeFence(
-+ IN gckOS Os,
-+ IN gctHANDLE Timeline,
-+ IN gctSYNC_POINT SyncPoint,
-+ OUT gctINT * FenceFD
-+ )
-+{
-+ int fd = -1;
-+ struct viv_sync_timeline *timeline;
-+ struct sync_pt * pt = gcvNULL;
-+ struct sync_fence * fence;
-+ char name[32];
-+ gcsSYNC_POINT_PTR syncPoint;
-+ gceSTATUS status;
-+
-+ gcmkHEADER_ARG("Os=0x%X Timeline=0x%X SyncPoint=%d",
-+ Os, Timeline, (gctUINT)(gctUINTPTR_T)SyncPoint);
-+
-+ gcmkONERROR(
-+ _QueryIntegerId(&Os->syncPointDB,
-+ (gctUINT32)(gctUINTPTR_T)SyncPoint,
-+ (gctPOINTER)&syncPoint));
-+
-+ /* Cast timeline. */
-+ timeline = (struct viv_sync_timeline *) Timeline;
-+
-+ fd = get_unused_fd();
-+
-+ if (fd < 0)
-+ {
-+ /* Out of resources. */
-+ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
-+ }
-+
-+ /* Create viv_sync_pt. */
-+ pt = viv_sync_pt_create(timeline, SyncPoint);
-+
-+ if (pt == gcvNULL)
-+ {
-+ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
-+ }
-+
-+ /* Reference sync_timeline. */
-+ syncPoint->timeline = &timeline->obj;
-+
-+ /* Build fence name. */
-+ snprintf(name, 32, "viv sync_fence-%u", (gctUINT)(gctUINTPTR_T)SyncPoint);
-+
-+ /* Create sync_fence. */
-+ fence = sync_fence_create(name, pt);
-+
-+ if (fence == NULL)
-+ {
-+ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
-+ }
-+
-+ /* Install fence to fd. */
-+ sync_fence_install(fence, fd);
-+
-+ *FenceFD = fd;
-+ gcmkFOOTER_ARG("*FenceFD=%d", fd);
-+ return gcvSTATUS_OK;
-+
-+OnError:
-+ /* Error roll back. */
-+ if (pt)
-+ {
-+ sync_pt_free(pt);
-+ }
-+
-+ if (fd > 0)
-+ {
-+ put_unused_fd(fd);
-+ }
-+
-+ gcmkFOOTER();
-+ return status;
-+}
-+#endif
-diff --git a/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_sync.c b/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_sync.c
-new file mode 100644
-index 0000000..7efae1c
---- /dev/null
-+++ b/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_sync.c
-@@ -0,0 +1,174 @@
-+/****************************************************************************
-+*
-+* Copyright (C) 2005 - 2013 by Vivante Corp.
-+*
-+* This program is free software; you can redistribute it and/or modify
-+* it under the terms of the GNU General Public License as published by
-+* the Free Software Foundation; either version 2 of the license, or
-+* (at your option) any later version.
-+*
-+* This program is distributed in the hope that it will be useful,
-+* but WITHOUT ANY WARRANTY; without even the implied warranty of
-+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+* GNU General Public License for more details.
-+*
-+* You should have received a copy of the GNU General Public License
-+* along with this program; if not write to the Free Software
-+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-+*
-+*****************************************************************************/
-+
-+
-+#include <linux/kernel.h>
-+#include <linux/file.h>
-+#include <linux/fs.h>
-+#include <linux/miscdevice.h>
-+#include <linux/module.h>
-+#include <linux/syscalls.h>
-+#include <linux/uaccess.h>
-+
-+#include "gc_hal_kernel_sync.h"
-+
-+#if gcdANDROID_NATIVE_FENCE_SYNC
-+
-+static struct sync_pt *
-+viv_sync_pt_dup(
-+ struct sync_pt * sync_pt
-+ )
-+{
-+ gceSTATUS status;
-+ struct viv_sync_pt *pt;
-+ struct viv_sync_pt *src;
-+ struct viv_sync_timeline *obj;
-+
-+ src = (struct viv_sync_pt *) sync_pt;
-+ obj = (struct viv_sync_timeline *) sync_pt->parent;
-+
-+ /* Create the new sync_pt. */
-+ pt = (struct viv_sync_pt *)
-+ sync_pt_create(&obj->obj, sizeof(struct viv_sync_pt));
-+
-+ pt->stamp = src->stamp;
-+ pt->sync = src->sync;
-+
-+ /* Reference sync point. */
-+ status = gckOS_ReferenceSyncPoint(obj->os, pt->sync);
-+
-+ if (gcmIS_ERROR(status))
-+ {
-+ sync_pt_free((struct sync_pt *)pt);
-+ return NULL;
-+ }
-+
-+ return (struct sync_pt *)pt;
-+}
-+
-+static int
-+viv_sync_pt_has_signaled(
-+ struct sync_pt * sync_pt
-+ )
-+{
-+ gceSTATUS status;
-+ gctBOOL state;
-+ struct viv_sync_pt * pt;
-+ struct viv_sync_timeline * obj;
-+
-+ pt = (struct viv_sync_pt *)sync_pt;
-+ obj = (struct viv_sync_timeline *)sync_pt->parent;
-+
-+ status = gckOS_QuerySyncPoint(obj->os, pt->sync, &state);
-+
-+ if (gcmIS_ERROR(status))
-+ {
-+ /* Error. */
-+ return -1;
-+ }
-+
-+ return state;
-+}
-+
-+static int
-+viv_sync_pt_compare(
-+ struct sync_pt * a,
-+ struct sync_pt * b
-+ )
-+{
-+ int ret;
-+ struct viv_sync_pt * pt1 = (struct viv_sync_pt *) a;
-+ struct viv_sync_pt * pt2 = (struct viv_sync_pt *) b;
-+
-+ ret = (pt1->stamp < pt2->stamp) ? -1
-+ : (pt1->stamp == pt2->stamp) ? 0
-+ : 1;
-+
-+ return ret;
-+}
-+
-+static void
-+viv_sync_pt_free(
-+ struct sync_pt * sync_pt
-+ )
-+{
-+ struct viv_sync_pt * pt;
-+ struct viv_sync_timeline * obj;
-+
-+ pt = (struct viv_sync_pt *) sync_pt;
-+ obj = (struct viv_sync_timeline *) sync_pt->parent;
-+
-+ gckOS_DestroySyncPoint(obj->os, pt->sync);
-+}
-+
-+static struct sync_timeline_ops viv_timeline_ops =
-+{
-+ .driver_name = "viv_sync",
-+ .dup = viv_sync_pt_dup,
-+ .has_signaled = viv_sync_pt_has_signaled,
-+ .compare = viv_sync_pt_compare,
-+ .free_pt = viv_sync_pt_free,
-+};
-+
-+struct viv_sync_timeline *
-+viv_sync_timeline_create(
-+ const char * name,
-+ gckOS os
-+ )
-+{
-+ struct viv_sync_timeline * obj;
-+
-+ obj = (struct viv_sync_timeline *)
-+ sync_timeline_create(&viv_timeline_ops, sizeof(struct viv_sync_timeline), name);
-+
-+ obj->os = os;
-+ obj->stamp = 0;
-+
-+ return obj;
-+}
-+
-+struct sync_pt *
-+viv_sync_pt_create(
-+ struct viv_sync_timeline * obj,
-+ gctSYNC_POINT SyncPoint
-+ )
-+{
-+ gceSTATUS status;
-+ struct viv_sync_pt * pt;
-+
-+ pt = (struct viv_sync_pt *)
-+ sync_pt_create(&obj->obj, sizeof(struct viv_sync_pt));
-+
-+ pt->stamp = obj->stamp++;
-+ pt->sync = SyncPoint;
-+
-+ /* Dup signal. */
-+ status = gckOS_ReferenceSyncPoint(obj->os, SyncPoint);
-+
-+ if (gcmIS_ERROR(status))
-+ {
-+ sync_pt_free((struct sync_pt *)pt);
-+ return NULL;
-+ }
-+
-+ return (struct sync_pt *) pt;
-+}
-+
-+#endif
-diff --git a/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_sync.h b/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_sync.h
-new file mode 100644
-index 0000000..6fc12e5
---- /dev/null
-+++ b/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_sync.h
-@@ -0,0 +1,71 @@
-+/****************************************************************************
-+*
-+* Copyright (C) 2005 - 2013 by Vivante Corp.
-+*
-+* This program is free software; you can redistribute it and/or modify
-+* it under the terms of the GNU General Public License as published by
-+* the Free Software Foundation; either version 2 of the license, or
-+* (at your option) any later version.
-+*
-+* This program is distributed in the hope that it will be useful,
-+* but WITHOUT ANY WARRANTY; without even the implied warranty of
-+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+* GNU General Public License for more details.
-+*
-+* You should have received a copy of the GNU General Public License
-+* along with this program; if not write to the Free Software
-+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-+*
-+*****************************************************************************/
-+
-+
-+#ifndef __gc_hal_kernel_sync_h_
-+#define __gc_hal_kernel_sync_h_
-+
-+#include <linux/types.h>
-+
-+#include <linux/sync.h>
-+
-+#include <gc_hal.h>
-+#include <gc_hal_base.h>
-+
-+struct viv_sync_timeline
-+{
-+ /* Parent object. */
-+ struct sync_timeline obj;
-+
-+ /* Timestamp when sync_pt is created. */
-+ gctUINT stamp;
-+
-+ /* Pointer to os struct. */
-+ gckOS os;
-+};
-+
-+
-+struct viv_sync_pt
-+{
-+ /* Parent object. */
-+ struct sync_pt pt;
-+
-+ /* Reference sync point*/
-+ gctSYNC_POINT sync;
-+
-+ /* Timestamp when sync_pt is created. */
-+ gctUINT stamp;
-+};
-+
-+/* Create viv_sync_timeline object. */
-+struct viv_sync_timeline *
-+viv_sync_timeline_create(
-+ const char * Name,
-+ gckOS Os
-+ );
-+
-+/* Create viv_sync_pt object. */
-+struct sync_pt *
-+viv_sync_pt_create(
-+ struct viv_sync_timeline * Obj,
-+ gctSYNC_POINT SyncPoint
-+ );
-+
-+#endif /* __gc_hal_kernel_sync_h_ */
---
-1.7.9.5
-
diff --git a/recipes-kernel/linux/linux-congatec-3.0.35/defconfig b/recipes-kernel/linux/linux-congatec-3.0.35/defconfig
deleted file mode 100644
index fa861ea..0000000
--- a/recipes-kernel/linux/linux-congatec-3.0.35/defconfig
+++ /dev/null
@@ -1,2684 +0,0 @@
-#
-# Automatically generated make config: don't edit
-# Linux/arm 3.0.35 Kernel Configuration
-#
-CONFIG_ARM=y
-CONFIG_HAVE_PWM=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_HAVE_SCHED_CLOCK=y
-CONFIG_GENERIC_GPIO=y
-# CONFIG_ARCH_USES_GETTIMEOFFSET is not set
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_KTIME_SCALAR=y
-CONFIG_HAVE_PROC_CPU=y
-CONFIG_STACKTRACE_SUPPORT=y
-CONFIG_LOCKDEP_SUPPORT=y
-CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_GENERIC_LOCKBREAK=y
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-CONFIG_ARCH_HAS_CPUFREQ=y
-CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y
-CONFIG_GENERIC_HWEIGHT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_ZONE_DMA=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_FIQ=y
-CONFIG_VECTORS_BASE=0xffff0000
-# CONFIG_ARM_PATCH_PHYS_VIRT is not set
-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-CONFIG_HAVE_IRQ_WORK=y
-CONFIG_IRQ_WORK=y
-
-#
-# General setup
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_INIT_ENV_ARG_LIMIT=32
-CONFIG_CROSS_COMPILE=""
-CONFIG_LOCALVERSION=""
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_HAVE_KERNEL_GZIP=y
-CONFIG_HAVE_KERNEL_LZMA=y
-CONFIG_HAVE_KERNEL_LZO=y
-CONFIG_KERNEL_GZIP=y
-# CONFIG_KERNEL_LZMA is not set
-# CONFIG_KERNEL_LZO is not set
-CONFIG_DEFAULT_HOSTNAME="(none)"
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-CONFIG_SYSVIPC_SYSCTL=y
-# CONFIG_POSIX_MQUEUE is not set
-# CONFIG_BSD_PROCESS_ACCT is not set
-# CONFIG_FHANDLE is not set
-# CONFIG_TASKSTATS is not set
-# CONFIG_AUDIT is not set
-CONFIG_HAVE_GENERIC_HARDIRQS=y
-
-#
-# IRQ subsystem
-#
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_HAVE_SPARSE_IRQ=y
-CONFIG_GENERIC_IRQ_SHOW=y
-# CONFIG_SPARSE_IRQ is not set
-
-#
-# RCU Subsystem
-#
-CONFIG_TREE_PREEMPT_RCU=y
-CONFIG_PREEMPT_RCU=y
-# CONFIG_RCU_TRACE is not set
-CONFIG_RCU_FANOUT=32
-# CONFIG_RCU_FANOUT_EXACT is not set
-# CONFIG_TREE_RCU_TRACE is not set
-# CONFIG_RCU_BOOST is not set
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CGROUPS is not set
-# CONFIG_NAMESPACES is not set
-# CONFIG_SCHED_AUTOGROUP is not set
-# CONFIG_SYSFS_DEPRECATED is not set
-# CONFIG_RELAY is not set
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_RD_GZIP=y
-# CONFIG_RD_BZIP2 is not set
-# CONFIG_RD_LZMA is not set
-# CONFIG_RD_XZ is not set
-# CONFIG_RD_LZO is not set
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_SYSCTL=y
-CONFIG_ANON_INODES=y
-CONFIG_EXPERT=y
-CONFIG_UID16=y
-CONFIG_SYSCTL_SYSCALL=y
-CONFIG_KALLSYMS=y
-CONFIG_HOTPLUG=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_EPOLL=y
-CONFIG_SIGNALFD=y
-CONFIG_TIMERFD=y
-CONFIG_EVENTFD=y
-CONFIG_SHMEM=y
-CONFIG_AIO=y
-CONFIG_EMBEDDED=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_PERF_USE_VMALLOC=y
-
-#
-# Kernel Performance Events And Counters
-#
-CONFIG_PERF_EVENTS=y
-# CONFIG_PERF_COUNTERS is not set
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_SLUB_DEBUG=y
-CONFIG_COMPAT_BRK=y
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
-# CONFIG_SLOB is not set
-# CONFIG_PROFILING is not set
-CONFIG_HAVE_OPROFILE=y
-# CONFIG_KPROBES is not set
-CONFIG_HAVE_KPROBES=y
-CONFIG_HAVE_KRETPROBES=y
-CONFIG_USE_GENERIC_SMP_HELPERS=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_HW_BREAKPOINT=y
-
-#
-# GCOV-based kernel profiling
-#
-# CONFIG_GCOV_KERNEL is not set
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_SLABINFO=y
-CONFIG_RT_MUTEXES=y
-CONFIG_BASE_SMALL=0
-CONFIG_MODULES=y
-# CONFIG_MODULE_FORCE_LOAD is not set
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-# CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_STOP_MACHINE=y
-CONFIG_BLOCK=y
-CONFIG_LBDAF=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_BLK_DEV_INTEGRITY is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-# CONFIG_DEFAULT_DEADLINE is not set
-CONFIG_DEFAULT_CFQ=y
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="cfq"
-# CONFIG_INLINE_SPIN_TRYLOCK is not set
-# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
-# CONFIG_INLINE_SPIN_LOCK is not set
-# CONFIG_INLINE_SPIN_LOCK_BH is not set
-# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
-# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
-# CONFIG_INLINE_SPIN_UNLOCK is not set
-# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
-# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set
-# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
-# CONFIG_INLINE_READ_TRYLOCK is not set
-# CONFIG_INLINE_READ_LOCK is not set
-# CONFIG_INLINE_READ_LOCK_BH is not set
-# CONFIG_INLINE_READ_LOCK_IRQ is not set
-# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
-# CONFIG_INLINE_READ_UNLOCK is not set
-# CONFIG_INLINE_READ_UNLOCK_BH is not set
-# CONFIG_INLINE_READ_UNLOCK_IRQ is not set
-# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
-# CONFIG_INLINE_WRITE_TRYLOCK is not set
-# CONFIG_INLINE_WRITE_LOCK is not set
-# CONFIG_INLINE_WRITE_LOCK_BH is not set
-# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
-# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
-# CONFIG_INLINE_WRITE_UNLOCK is not set
-# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
-# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set
-# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_FREEZER=y
-
-#
-# System Type
-#
-CONFIG_MMU=y
-# CONFIG_ARCH_INTEGRATOR is not set
-# CONFIG_ARCH_REALVIEW is not set
-# CONFIG_ARCH_VERSATILE is not set
-# CONFIG_ARCH_VEXPRESS is not set
-# CONFIG_ARCH_AT91 is not set
-# CONFIG_ARCH_BCMRING is not set
-# CONFIG_ARCH_CLPS711X is not set
-# CONFIG_ARCH_CNS3XXX is not set
-# CONFIG_ARCH_GEMINI is not set
-# CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_EP93XX is not set
-# CONFIG_ARCH_FOOTBRIDGE is not set
-CONFIG_ARCH_MXC=y
-# CONFIG_ARCH_MXS is not set
-# CONFIG_ARCH_NETX is not set
-# CONFIG_ARCH_H720X is not set
-# CONFIG_ARCH_IOP13XX is not set
-# CONFIG_ARCH_IOP32X is not set
-# CONFIG_ARCH_IOP33X is not set
-# CONFIG_ARCH_IXP23XX is not set
-# CONFIG_ARCH_IXP2000 is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_DOVE is not set
-# CONFIG_ARCH_KIRKWOOD is not set
-# CONFIG_ARCH_LOKI is not set
-# CONFIG_ARCH_LPC32XX is not set
-# CONFIG_ARCH_MV78XX0 is not set
-# CONFIG_ARCH_ORION5X is not set
-# CONFIG_ARCH_MMP is not set
-# CONFIG_ARCH_KS8695 is not set
-# CONFIG_ARCH_W90X900 is not set
-# CONFIG_ARCH_NUC93X is not set
-# CONFIG_ARCH_TEGRA is not set
-# CONFIG_ARCH_PNX4008 is not set
-# CONFIG_ARCH_PXA is not set
-# CONFIG_ARCH_MSM is not set
-# CONFIG_ARCH_SHMOBILE is not set
-# CONFIG_ARCH_RPC is not set
-# CONFIG_ARCH_SA1100 is not set
-# CONFIG_ARCH_S3C2410 is not set
-# CONFIG_ARCH_S3C64XX is not set
-# CONFIG_ARCH_S5P64X0 is not set
-# CONFIG_ARCH_S5PC100 is not set
-# CONFIG_ARCH_S5PV210 is not set
-# CONFIG_ARCH_EXYNOS4 is not set
-# CONFIG_ARCH_SHARK is not set
-# CONFIG_ARCH_TCC_926 is not set
-# CONFIG_ARCH_U300 is not set
-# CONFIG_ARCH_U8500 is not set
-# CONFIG_ARCH_NOMADIK is not set
-# CONFIG_ARCH_DAVINCI is not set
-# CONFIG_ARCH_OMAP is not set
-# CONFIG_PLAT_SPEAR is not set
-# CONFIG_ARCH_VT8500 is not set
-CONFIG_GPIO_PCA953X=y
-# CONFIG_KEYBOARD_GPIO_POLLED is not set
-CONFIG_IMX_HAVE_PLATFORM_DMA=y
-CONFIG_IMX_HAVE_PLATFORM_FEC=y
-CONFIG_IMX_HAVE_PLATFORM_FLEXCAN=y
-CONFIG_IMX_HAVE_PLATFORM_FSL_USB2_UDC=y
-CONFIG_IMX_HAVE_PLATFORM_GPMI_NFC=y
-CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT=y
-CONFIG_IMX_HAVE_PLATFORM_IMX_SNVS_RTC=y
-CONFIG_IMX_HAVE_PLATFORM_IMX_CAAM=y
-CONFIG_IMX_HAVE_PLATFORM_IMX_I2C=y
-CONFIG_IMX_HAVE_PLATFORM_IMX_SSI=y
-CONFIG_IMX_HAVE_PLATFORM_IMX_UART=y
-CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI=y
-CONFIG_IMX_HAVE_PLATFORM_MXC_PWM=y
-CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX=y
-CONFIG_IMX_HAVE_PLATFORM_SPI_IMX=y
-CONFIG_IMX_HAVE_PLATFORM_IMX_IPUV3=y
-CONFIG_IMX_HAVE_PLATFORM_IMX_VPU=y
-CONFIG_IMX_HAVE_PLATFORM_IMX_DVFS=y
-CONFIG_IMX_HAVE_PLATFORM_AHCI=y
-CONFIG_IMX_HAVE_PLATFORM_IMX_OCOTP=y
-CONFIG_IMX_HAVE_PLATFORM_IMX_VIIM=y
-CONFIG_IMX_HAVE_PLATFORM_LDB=y
-CONFIG_IMX_HAVE_PLATFORM_IMX_SPDIF=y
-CONFIG_IMX_HAVE_PLATFORM_VIV_GPU=y
-CONFIG_IMX_HAVE_PLATFORM_MXC_HDMI=y
-CONFIG_IMX_HAVE_PLATFORM_IMX_ANATOP_THERMAL=y
-CONFIG_IMX_HAVE_PLATFORM_FSL_OTG=y
-CONFIG_IMX_HAVE_PLATFORM_FSL_USB_WAKEUP=y
-CONFIG_IMX_HAVE_PLATFORM_IMX_PM=y
-CONFIG_IMX_HAVE_PLATFORM_IMX_ASRC=y
-CONFIG_IMX_HAVE_PLATFORM_IMX_MIPI_CSI2=y
-CONFIG_IMX_HAVE_PLATFORM_IMX_VDOA=y
-CONFIG_IMX_HAVE_PLATFORM_IMX_PCIE=y
-
-#
-# Freescale MXC Implementations
-#
-# CONFIG_ARCH_MX1 is not set
-# CONFIG_ARCH_MX2 is not set
-# CONFIG_ARCH_MX25 is not set
-# CONFIG_ARCH_MX3 is not set
-# CONFIG_ARCH_MX503 is not set
-# CONFIG_ARCH_MX51 is not set
-CONFIG_ARCH_MX6=y
-# CONFIG_MACH_IMX_BLUETOOTH_RFKILL is not set
-CONFIG_ARCH_MX6Q=y
-CONFIG_FORCE_MAX_ZONEORDER=14
-CONFIG_SOC_IMX6Q=y
-# CONFIG_MACH_MX6Q_ARM2 is not set
-# CONFIG_MACH_MX6SL_ARM2 is not set
-# CONFIG_MACH_MX6SL_EVK is not set
-# CONFIG_MACH_MX6Q_SABRELITE is not set
-CONFIG_MACH_MX6Q_QMX6=y
-# CONFIG_MACH_MX6Q_SABRESD is not set
-# CONFIG_MACH_MX6Q_SABREAUTO is not set
-# CONFIG_MACH_MX6Q_HDMIDONGLE is not set
-
-#
-# MX6 Options:
-#
-# CONFIG_IMX_PCIE is not set
-CONFIG_USB_EHCI_ARC_H1=y
-CONFIG_USB_FSL_ARC_OTG=y
-# CONFIG_MX6_INTER_LDO_BYPASS is not set
-# CONFIG_MX6_CLK_FOR_BOOTUI_TRANS is not set
-# CONFIG_MX6_ENET_IRQ_TO_GPIO is not set
-CONFIG_ISP1504_MXC=y
-# CONFIG_MXC_IRQ_PRIOR is not set
-CONFIG_MXC_PWM=y
-# CONFIG_MXC_DEBUG_BOARD is not set
-# CONFIG_MXC_REBOOT_MFGMODE is not set
-# CONFIG_MXC_REBOOT_ANDROID_CMD is not set
-CONFIG_ARCH_MXC_IOMUX_V3=y
-CONFIG_ARCH_MXC_AUDMUX_V2=y
-CONFIG_IRAM_ALLOC=y
-CONFIG_CLK_DEBUG=y
-CONFIG_DMA_ZONE_SIZE=184
-
-#
-# System MMU
-#
-
-#
-# Processor Type
-#
-CONFIG_CPU_V7=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_HAS_ASID=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-
-#
-# Processor Features
-#
-CONFIG_ARM_THUMB=y
-# CONFIG_ARM_THUMBEE is not set
-# CONFIG_SWP_EMULATE is not set
-# CONFIG_CPU_ICACHE_DISABLE is not set
-# CONFIG_CPU_DCACHE_DISABLE is not set
-# CONFIG_CPU_BPREDICT_DISABLE is not set
-CONFIG_OUTER_CACHE=y
-CONFIG_OUTER_CACHE_SYNC=y
-CONFIG_CACHE_L2X0=y
-CONFIG_CACHE_PL310=y
-CONFIG_ARM_L1_CACHE_SHIFT=5
-CONFIG_ARM_DMA_MEM_BUFFERABLE=y
-CONFIG_CPU_HAS_PMU=y
-# CONFIG_ARM_ERRATA_430973 is not set
-# CONFIG_ARM_ERRATA_458693 is not set
-# CONFIG_ARM_ERRATA_460075 is not set
-# CONFIG_ARM_ERRATA_742230 is not set
-# CONFIG_ARM_ERRATA_742231 is not set
-# CONFIG_PL310_ERRATA_588369 is not set
-# CONFIG_ARM_ERRATA_720789 is not set
-# CONFIG_PL310_ERRATA_727915 is not set
-CONFIG_ARM_ERRATA_743622=y
-CONFIG_ARM_ERRATA_751472=y
-# CONFIG_ARM_ERRATA_753970 is not set
-CONFIG_ARM_ERRATA_754322=y
-# CONFIG_ARM_ERRATA_754327 is not set
-CONFIG_ARM_GIC=y
-
-#
-# Bus support
-#
-CONFIG_ARM_AMBA=y
-# CONFIG_PCI_SYSCALL is not set
-CONFIG_ARCH_SUPPORTS_MSI=y
-# CONFIG_PCCARD is not set
-CONFIG_ARM_ERRATA_764369=y
-# CONFIG_PL310_ERRATA_769419 is not set
-
-#
-# Kernel Features
-#
-CONFIG_TICK_ONESHOT=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_SMP=y
-CONFIG_SMP_ON_UP=y
-CONFIG_HAVE_ARM_SCU=y
-CONFIG_HAVE_ARM_TWD=y
-# CONFIG_VMSPLIT_3G is not set
-CONFIG_VMSPLIT_2G=y
-# CONFIG_VMSPLIT_1G is not set
-CONFIG_PAGE_OFFSET=0x80000000
-CONFIG_NR_CPUS=4
-CONFIG_HOTPLUG_CPU=y
-CONFIG_LOCAL_TIMERS=y
-# CONFIG_PREEMPT_NONE is not set
-# CONFIG_PREEMPT_VOLUNTARY is not set
-CONFIG_PREEMPT=y
-CONFIG_HZ=100
-# CONFIG_THUMB2_KERNEL is not set
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-CONFIG_HAVE_ARCH_PFN_VALID=y
-CONFIG_HIGHMEM=y
-# CONFIG_HIGHPTE is not set
-CONFIG_HW_PERF_EVENTS=y
-CONFIG_SELECT_MEMORY_MODEL=y
-CONFIG_FLATMEM_MANUAL=y
-CONFIG_FLATMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_SPLIT_PTLOCK_CPUS=4
-CONFIG_COMPACTION=y
-CONFIG_MIGRATION=y
-# CONFIG_PHYS_ADDR_T_64BIT is not set
-CONFIG_ZONE_DMA_FLAG=1
-CONFIG_BOUNCE=y
-CONFIG_VIRT_TO_BUS=y
-CONFIG_KSM=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
-# CONFIG_CLEANCACHE is not set
-CONFIG_ALIGNMENT_TRAP=y
-# CONFIG_UACCESS_WITH_MEMCPY is not set
-# CONFIG_SECCOMP is not set
-# CONFIG_CC_STACKPROTECTOR is not set
-# CONFIG_DEPRECATED_PARAM_STRUCT is not set
-
-#
-# Boot options
-#
-# CONFIG_USE_OF is not set
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="noinitrd console=ttymxc0,115200 root=/dev/mtdblock2 rw rootfstype=jffs2 ip=off"
-CONFIG_CMDLINE_FROM_BOOTLOADER=y
-# CONFIG_CMDLINE_EXTEND is not set
-# CONFIG_CMDLINE_FORCE is not set
-# CONFIG_XIP_KERNEL is not set
-# CONFIG_KEXEC is not set
-# CONFIG_CRASH_DUMP is not set
-# CONFIG_AUTO_ZRELADDR is not set
-
-#
-# CPU Power Management
-#
-
-#
-# CPU Frequency scaling
-#
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_TABLE=y
-CONFIG_CPU_FREQ_STAT=y
-# CONFIG_CPU_FREQ_STAT_DETAILS is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-# CONFIG_CPU_FREQ_GOV_PERFORMANCE is not set
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
-CONFIG_CPU_FREQ_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_FREQ_IMX=y
-# CONFIG_CPU_IDLE is not set
-
-#
-# Floating point emulation
-#
-
-#
-# At least one emulation must be selected
-#
-CONFIG_VFP=y
-CONFIG_VFPv3=y
-CONFIG_NEON=y
-
-#
-# Userspace binary formats
-#
-CONFIG_BINFMT_ELF=y
-# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-CONFIG_HAVE_AOUT=y
-# CONFIG_BINFMT_AOUT is not set
-# CONFIG_BINFMT_MISC is not set
-
-#
-# Power management options
-#
-CONFIG_SUSPEND=y
-# CONFIG_PM_TEST_SUSPEND is not set
-CONFIG_SUSPEND_DEVICE_TIME_DEBUG=y
-CONFIG_SUSPEND_FREEZER=y
-CONFIG_PM_SLEEP=y
-CONFIG_PM_SLEEP_SMP=y
-CONFIG_PM_RUNTIME=y
-CONFIG_PM=y
-CONFIG_PM_DEBUG=y
-# CONFIG_PM_ADVANCED_DEBUG is not set
-CONFIG_CAN_PM_TRACE=y
-CONFIG_APM_EMULATION=y
-CONFIG_PM_RUNTIME_CLK=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_NET=y
-
-#
-# Networking options
-#
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM=y
-# CONFIG_XFRM_USER is not set
-# CONFIG_XFRM_SUB_POLICY is not set
-# CONFIG_XFRM_MIGRATE is not set
-# CONFIG_XFRM_STATISTICS is not set
-# CONFIG_NET_KEY is not set
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_IP_PNP_RARP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE_DEMUX is not set
-# CONFIG_IP_MROUTE is not set
-# CONFIG_ARPD is not set
-# CONFIG_SYN_COOKIES is not set
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_XFRM_TUNNEL is not set
-# CONFIG_INET_TUNNEL is not set
-CONFIG_INET_XFRM_MODE_TRANSPORT=y
-CONFIG_INET_XFRM_MODE_TUNNEL=y
-CONFIG_INET_XFRM_MODE_BEET=y
-# CONFIG_INET_LRO is not set
-CONFIG_INET_DIAG=y
-CONFIG_INET_TCP_DIAG=y
-# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TCP_CONG_CUBIC=y
-CONFIG_DEFAULT_TCP_CONG="cubic"
-# CONFIG_TCP_MD5SIG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_NETWORK_SECMARK is not set
-# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
-# CONFIG_NETFILTER is not set
-# CONFIG_IP_DCCP is not set
-# CONFIG_IP_SCTP is not set
-# CONFIG_RDS is not set
-# CONFIG_TIPC is not set
-# CONFIG_ATM is not set
-# CONFIG_L2TP is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_NET_DSA is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-# CONFIG_PHONET is not set
-# CONFIG_IEEE802154 is not set
-# CONFIG_NET_SCHED is not set
-# CONFIG_DCB is not set
-# CONFIG_BATMAN_ADV is not set
-CONFIG_RPS=y
-CONFIG_RFS_ACCEL=y
-CONFIG_XPS=y
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_HAMRADIO is not set
-CONFIG_CAN=y
-CONFIG_CAN_RAW=y
-CONFIG_CAN_BCM=y
-
-#
-# CAN Device Drivers
-#
-CONFIG_CAN_VCAN=y
-# CONFIG_CAN_SLCAN is not set
-CONFIG_CAN_DEV=y
-CONFIG_CAN_CALC_BITTIMING=y
-# CONFIG_CAN_MCP251X is not set
-CONFIG_HAVE_CAN_FLEXCAN=y
-CONFIG_CAN_FLEXCAN=y
-# CONFIG_CAN_SJA1000 is not set
-# CONFIG_CAN_C_CAN is not set
-
-#
-# CAN USB interfaces
-#
-# CONFIG_CAN_EMS_USB is not set
-# CONFIG_CAN_ESD_USB2 is not set
-# CONFIG_CAN_SOFTING is not set
-# CONFIG_CAN_DEBUG_DEVICES is not set
-# CONFIG_IRDA is not set
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_BNEP_MC_FILTER=y
-CONFIG_BT_BNEP_PROTO_FILTER=y
-CONFIG_BT_HIDP=y
-
-#
-# Bluetooth device drivers
-#
-CONFIG_BT_HCIBTUSB=y
-# CONFIG_BT_HCIBTSDIO is not set
-CONFIG_BT_HCIUART=y
-# CONFIG_BT_HCIUART_H4 is not set
-# CONFIG_BT_HCIUART_BCSP is not set
-CONFIG_BT_HCIUART_ATH3K=y
-# CONFIG_BT_HCIUART_LL is not set
-# CONFIG_BT_HCIBCM203X is not set
-# CONFIG_BT_HCIBPA10X is not set
-# CONFIG_BT_HCIBFUSB is not set
-CONFIG_BT_HCIVHCI=y
-# CONFIG_BT_MRVL is not set
-# CONFIG_BT_ATH3K is not set
-# CONFIG_AF_RXRPC is not set
-CONFIG_WIRELESS=y
-CONFIG_WIRELESS_EXT=y
-CONFIG_WEXT_CORE=y
-CONFIG_WEXT_PROC=y
-CONFIG_WEXT_SPY=y
-CONFIG_WEXT_PRIV=y
-CONFIG_CFG80211=y
-# CONFIG_NL80211_TESTMODE is not set
-# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
-# CONFIG_CFG80211_REG_DEBUG is not set
-CONFIG_CFG80211_DEFAULT_PS=y
-# CONFIG_CFG80211_DEBUGFS is not set
-# CONFIG_CFG80211_INTERNAL_REGDB is not set
-CONFIG_CFG80211_WEXT=y
-CONFIG_WIRELESS_EXT_SYSFS=y
-CONFIG_LIB80211=y
-CONFIG_LIB80211_CRYPT_WEP=y
-CONFIG_LIB80211_CRYPT_CCMP=y
-CONFIG_LIB80211_CRYPT_TKIP=y
-# CONFIG_LIB80211_DEBUG is not set
-# CONFIG_MAC80211 is not set
-# CONFIG_WIMAX is not set
-CONFIG_RFKILL=y
-CONFIG_RFKILL_INPUT=y
-# CONFIG_RFKILL_REGULATOR is not set
-# CONFIG_RFKILL_GPIO is not set
-# CONFIG_NET_9P is not set
-# CONFIG_CAIF is not set
-# CONFIG_CEPH_LIB is not set
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=y
-CONFIG_FIRMWARE_IN_KERNEL=y
-CONFIG_EXTRA_FIRMWARE=""
-# CONFIG_SYS_HYPERVISOR is not set
-CONFIG_CONNECTOR=y
-CONFIG_PROC_EVENTS=y
-CONFIG_MTD=y
-# CONFIG_MTD_DEBUG is not set
-# CONFIG_MTD_TESTS is not set
-# CONFIG_MTD_REDBOOT_PARTS is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-# CONFIG_MTD_AFS_PARTS is not set
-# CONFIG_MTD_AR7_PARTS is not set
-
-#
-# User Modules And Translation Layers
-#
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLKDEVS=y
-CONFIG_MTD_BLOCK=y
-# CONFIG_FTL is not set
-# CONFIG_NFTL is not set
-# CONFIG_INFTL is not set
-# CONFIG_RFD_FTL is not set
-# CONFIG_SSFDC is not set
-# CONFIG_SM_FTL is not set
-# CONFIG_MTD_OOPS is not set
-# CONFIG_MTD_SWAP is not set
-
-#
-# RAM/ROM/Flash chip drivers
-#
-# CONFIG_MTD_CFI is not set
-# CONFIG_MTD_JEDECPROBE is not set
-CONFIG_MTD_MAP_BANK_WIDTH_1=y
-CONFIG_MTD_MAP_BANK_WIDTH_2=y
-CONFIG_MTD_MAP_BANK_WIDTH_4=y
-# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-CONFIG_MTD_CFI_I1=y
-CONFIG_MTD_CFI_I2=y
-# CONFIG_MTD_CFI_I4 is not set
-# CONFIG_MTD_CFI_I8 is not set
-# CONFIG_MTD_RAM is not set
-# CONFIG_MTD_ROM is not set
-# CONFIG_MTD_ABSENT is not set
-
-#
-# Mapping drivers for chip access
-#
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-# CONFIG_MTD_PLATRAM is not set
-
-#
-# Self-contained MTD device drivers
-#
-# CONFIG_MTD_DATAFLASH is not set
-CONFIG_MTD_M25P80=y
-CONFIG_M25PXX_USE_FAST_READ=y
-# CONFIG_MTD_SST25L is not set
-# CONFIG_MTD_SLRAM is not set
-# CONFIG_MTD_PHRAM is not set
-# CONFIG_MTD_MTDRAM is not set
-# CONFIG_MTD_BLOCK2MTD is not set
-
-#
-# Disk-On-Chip Device Drivers
-#
-# CONFIG_MTD_DOC2000 is not set
-# CONFIG_MTD_DOC2001 is not set
-# CONFIG_MTD_DOC2001PLUS is not set
-CONFIG_MTD_NAND_ECC=y
-# CONFIG_MTD_NAND_ECC_SMC is not set
-CONFIG_MTD_NAND=y
-# CONFIG_MTD_NAND_VERIFY_WRITE is not set
-# CONFIG_MTD_NAND_ECC_BCH is not set
-# CONFIG_MTD_SM_COMMON is not set
-# CONFIG_MTD_NAND_MUSEUM_IDS is not set
-# CONFIG_MTD_NAND_GPIO is not set
-CONFIG_MTD_NAND_IDS=y
-# CONFIG_MTD_NAND_DISKONCHIP is not set
-# CONFIG_MTD_NAND_NANDSIM is not set
-# CONFIG_MTD_NAND_GPMI_NAND is not set
-# CONFIG_MTD_NAND_PLATFORM is not set
-# CONFIG_MTD_ALAUDA is not set
-# CONFIG_MTD_ONENAND is not set
-
-#
-# LPDDR flash memory drivers
-#
-# CONFIG_MTD_LPDDR is not set
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_MTD_UBI_BEB_RESERVE=1
-# CONFIG_MTD_UBI_GLUEBI is not set
-# CONFIG_MTD_UBI_DEBUG is not set
-# CONFIG_PARPORT is not set
-CONFIG_BLK_DEV=y
-# CONFIG_BLK_DEV_COW_COMMON is not set
-CONFIG_BLK_DEV_LOOP=y
-# CONFIG_BLK_DEV_CRYPTOLOOP is not set
-# CONFIG_BLK_DEV_DRBD is not set
-# CONFIG_BLK_DEV_NBD is not set
-# CONFIG_BLK_DEV_UB is not set
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=4096
-# CONFIG_BLK_DEV_XIP is not set
-# CONFIG_CDROM_PKTCDVD is not set
-# CONFIG_ATA_OVER_ETH is not set
-# CONFIG_MG_DISK is not set
-# CONFIG_BLK_DEV_RBD is not set
-# CONFIG_SENSORS_LIS3LV02D is not set
-CONFIG_MISC_DEVICES=y
-# CONFIG_AD525X_DPOT is not set
-# CONFIG_INTEL_MID_PTI is not set
-# CONFIG_ICS932S401 is not set
-# CONFIG_ENCLOSURE_SERVICES is not set
-# CONFIG_APDS9802ALS is not set
-# CONFIG_ISL29003 is not set
-# CONFIG_ISL29020 is not set
-# CONFIG_SENSORS_TSL2550 is not set
-# CONFIG_SENSORS_BH1780 is not set
-# CONFIG_SENSORS_BH1770 is not set
-# CONFIG_SENSORS_APDS990X is not set
-# CONFIG_HMC6352 is not set
-# CONFIG_DS1682 is not set
-# CONFIG_TI_DAC7512 is not set
-# CONFIG_BMP085 is not set
-CONFIG_MXS_PERFMON=m
-# CONFIG_C2PORT is not set
-
-#
-# EEPROM support
-#
-# CONFIG_EEPROM_AT24 is not set
-# CONFIG_EEPROM_AT25 is not set
-# CONFIG_EEPROM_LEGACY is not set
-# CONFIG_EEPROM_MAX6875 is not set
-# CONFIG_EEPROM_93CX6 is not set
-# CONFIG_IWMC3200TOP is not set
-
-#
-# Texas Instruments shared transport line discipline
-#
-# CONFIG_TI_ST is not set
-# CONFIG_SENSORS_LIS3_SPI is not set
-# CONFIG_SENSORS_LIS3_I2C is not set
-CONFIG_HAVE_IDE=y
-# CONFIG_IDE is not set
-
-#
-# SCSI device support
-#
-CONFIG_SCSI_MOD=y
-# CONFIG_RAID_ATTRS is not set
-CONFIG_SCSI=y
-CONFIG_SCSI_DMA=y
-# CONFIG_SCSI_TGT is not set
-# CONFIG_SCSI_NETLINK is not set
-CONFIG_SCSI_PROC_FS=y
-
-#
-# SCSI support type (disk, tape, CD-ROM)
-#
-CONFIG_BLK_DEV_SD=y
-# CONFIG_CHR_DEV_ST is not set
-# CONFIG_CHR_DEV_OSST is not set
-# CONFIG_BLK_DEV_SR is not set
-# CONFIG_CHR_DEV_SG is not set
-# CONFIG_CHR_DEV_SCH is not set
-CONFIG_SCSI_MULTI_LUN=y
-# CONFIG_SCSI_CONSTANTS is not set
-# CONFIG_SCSI_LOGGING is not set
-# CONFIG_SCSI_SCAN_ASYNC is not set
-CONFIG_SCSI_WAIT_SCAN=m
-
-#
-# SCSI Transports
-#
-# CONFIG_SCSI_SPI_ATTRS is not set
-# CONFIG_SCSI_FC_ATTRS is not set
-# CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_ATTRS is not set
-# CONFIG_SCSI_SAS_LIBSAS is not set
-# CONFIG_SCSI_SRP_ATTRS is not set
-CONFIG_SCSI_LOWLEVEL=y
-# CONFIG_ISCSI_TCP is not set
-# CONFIG_ISCSI_BOOT_SYSFS is not set
-# CONFIG_LIBFC is not set
-# CONFIG_LIBFCOE is not set
-# CONFIG_SCSI_DEBUG is not set
-# CONFIG_SCSI_DH is not set
-# CONFIG_SCSI_OSD_INITIATOR is not set
-CONFIG_ATA=y
-# CONFIG_ATA_NONSTANDARD is not set
-CONFIG_ATA_VERBOSE_ERROR=y
-# CONFIG_SATA_PMP is not set
-
-#
-# Controllers with non-SFF native interface
-#
-CONFIG_SATA_AHCI_PLATFORM=y
-CONFIG_ATA_SFF=y
-
-#
-# SFF controllers with custom DMA interface
-#
-CONFIG_ATA_BMDMA=y
-
-#
-# SATA SFF controllers with BMDMA
-#
-# CONFIG_SATA_MV is not set
-
-#
-# PATA SFF controllers with BMDMA
-#
-# CONFIG_PATA_ARASAN_CF is not set
-
-#
-# PIO-only SFF controllers
-#
-# CONFIG_PATA_PLATFORM is not set
-
-#
-# Generic fallback / legacy drivers
-#
-# CONFIG_MD is not set
-# CONFIG_TARGET_CORE is not set
-CONFIG_NETDEVICES=y
-# CONFIG_DUMMY is not set
-# CONFIG_BONDING is not set
-# CONFIG_MACVLAN is not set
-# CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
-# CONFIG_VETH is not set
-CONFIG_MII=y
-CONFIG_PHYLIB=y
-
-#
-# MII PHY device drivers
-#
-# CONFIG_MARVELL_PHY is not set
-# CONFIG_DAVICOM_PHY is not set
-# CONFIG_QSEMI_PHY is not set
-# CONFIG_LXT_PHY is not set
-# CONFIG_CICADA_PHY is not set
-# CONFIG_VITESSE_PHY is not set
-# CONFIG_SMSC_PHY is not set
-# CONFIG_BROADCOM_PHY is not set
-# CONFIG_ICPLUS_PHY is not set
-# CONFIG_REALTEK_PHY is not set
-# CONFIG_NATIONAL_PHY is not set
-# CONFIG_STE10XP is not set
-# CONFIG_LSI_ET1011C_PHY is not set
-CONFIG_MICREL_PHY=y
-# CONFIG_FIXED_PHY is not set
-# CONFIG_MDIO_BITBANG is not set
-CONFIG_NET_ETHERNET=y
-# CONFIG_AX88796 is not set
-# CONFIG_SMC91X is not set
-# CONFIG_DM9000 is not set
-# CONFIG_ENC28J60 is not set
-# CONFIG_ETHOC is not set
-# CONFIG_SMC911X is not set
-CONFIG_SMSC911X=y
-# CONFIG_SMSC911X_ARCH_HOOKS is not set
-# CONFIG_DNET is not set
-# CONFIG_IBM_NEW_EMAC_ZMII is not set
-# CONFIG_IBM_NEW_EMAC_RGMII is not set
-# CONFIG_IBM_NEW_EMAC_TAH is not set
-# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
-# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
-# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
-# CONFIG_B44 is not set
-# CONFIG_KS8842 is not set
-# CONFIG_KS8851 is not set
-# CONFIG_KS8851_MLL is not set
-CONFIG_FEC=y
-# CONFIG_FEC_NAPI is not set
-# CONFIG_FEC_1588 is not set
-# CONFIG_FTMAC100 is not set
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN=y
-# CONFIG_USB_ZD1201 is not set
-# CONFIG_USB_NET_RNDIS_WLAN is not set
-CONFIG_ATH_COMMON=m
-# CONFIG_ATH_DEBUG is not set
-CONFIG_ATH6KL=m
-# CONFIG_ATH6KL_DEBUG is not set
-CONFIG_HOSTAP=y
-# CONFIG_HOSTAP_FIRMWARE is not set
-# CONFIG_IWM is not set
-# CONFIG_LIBERTAS is not set
-# CONFIG_MWIFIEX is not set
-
-#
-# Enable WiMAX (Networking options) to see the WiMAX drivers
-#
-
-#
-# USB Network Adapters
-#
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_USBNET is not set
-# CONFIG_USB_HSO is not set
-# CONFIG_USB_IPHETH is not set
-# CONFIG_WAN is not set
-
-#
-# CAIF transport drivers
-#
-# CONFIG_PPP is not set
-# CONFIG_SLIP is not set
-# CONFIG_NETCONSOLE is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
-# CONFIG_ISDN is not set
-# CONFIG_PHONE is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-# CONFIG_INPUT_FF_MEMLESS is not set
-CONFIG_INPUT_POLLDEV=y
-# CONFIG_INPUT_SPARSEKMAP is not set
-
-#
-# Userland interfaces
-#
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-# CONFIG_INPUT_JOYDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_EVBUG is not set
-# CONFIG_INPUT_APMPOWER is not set
-
-#
-# Input Device Drivers
-#
-CONFIG_INPUT_KEYBOARD=y
-# CONFIG_KEYBOARD_ADP5588 is not set
-# CONFIG_KEYBOARD_ADP5589 is not set
-CONFIG_KEYBOARD_ATKBD=y
-# CONFIG_KEYBOARD_QT1070 is not set
-# CONFIG_KEYBOARD_QT2160 is not set
-# CONFIG_KEYBOARD_LKKBD is not set
-CONFIG_KEYBOARD_GPIO=y
-# CONFIG_KEYBOARD_TCA6416 is not set
-# CONFIG_KEYBOARD_MATRIX is not set
-# CONFIG_KEYBOARD_LM8323 is not set
-# CONFIG_KEYBOARD_MAX7359 is not set
-# CONFIG_KEYBOARD_MCS is not set
-# CONFIG_KEYBOARD_MPR121 is not set
-# CONFIG_KEYBOARD_IMX is not set
-# CONFIG_KEYBOARD_NEWTON is not set
-# CONFIG_KEYBOARD_OPENCORES is not set
-# CONFIG_KEYBOARD_STOWAWAY is not set
-# CONFIG_KEYBOARD_SUNKBD is not set
-# CONFIG_KEYBOARD_XTKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TABLET is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-# CONFIG_TOUCHSCREEN_ADS7846 is not set
-# CONFIG_TOUCHSCREEN_AD7877 is not set
-# CONFIG_TOUCHSCREEN_AD7879 is not set
-# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
-# CONFIG_TOUCHSCREEN_BU21013 is not set
-# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set
-# CONFIG_TOUCHSCREEN_DYNAPRO is not set
-# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
-# CONFIG_TOUCHSCREEN_EETI is not set
-CONFIG_TOUCHSCREEN_EGALAX=y
-# CONFIG_TOUCHSCREEN_ELAN is not set
-# CONFIG_TOUCHSCREEN_EGALAX_SINGLE_TOUCH is not set
-# CONFIG_TOUCHSCREEN_FUJITSU is not set
-# CONFIG_TOUCHSCREEN_GUNZE is not set
-# CONFIG_TOUCHSCREEN_ELO is not set
-# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
-# CONFIG_TOUCHSCREEN_MAX11801 is not set
-# CONFIG_TOUCHSCREEN_MCS5000 is not set
-# CONFIG_TOUCHSCREEN_MTOUCH is not set
-# CONFIG_TOUCHSCREEN_INEXIO is not set
-# CONFIG_TOUCHSCREEN_MK712 is not set
-# CONFIG_TOUCHSCREEN_PENMOUNT is not set
-# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
-# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
-# CONFIG_TOUCHSCREEN_WM97XX is not set
-# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
-# CONFIG_TOUCHSCREEN_NOVATEK is not set
-# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
-# CONFIG_TOUCHSCREEN_TSC2005 is not set
-# CONFIG_TOUCHSCREEN_TSC2007 is not set
-# CONFIG_TOUCHSCREEN_W90X900 is not set
-# CONFIG_TOUCHSCREEN_ST1232 is not set
-# CONFIG_TOUCHSCREEN_P1003 is not set
-# CONFIG_TOUCHSCREEN_TPS6507X is not set
-CONFIG_INPUT_MISC=y
-# CONFIG_INPUT_AD714X is not set
-# CONFIG_INPUT_ATI_REMOTE is not set
-# CONFIG_INPUT_ATI_REMOTE2 is not set
-# CONFIG_INPUT_KEYSPAN_REMOTE is not set
-# CONFIG_INPUT_POWERMATE is not set
-# CONFIG_INPUT_YEALINK is not set
-# CONFIG_INPUT_CM109 is not set
-CONFIG_INPUT_UINPUT=y
-# CONFIG_INPUT_PCF8574 is not set
-# CONFIG_INPUT_PWM_BEEPER is not set
-# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
-# CONFIG_INPUT_ADXL34X is not set
-# CONFIG_INPUT_CMA3000 is not set
-CONFIG_INPUT_ISL29023=y
-
-#
-# Hardware I/O ports
-#
-CONFIG_SERIO=y
-CONFIG_SERIO_SERPORT=y
-# CONFIG_SERIO_AMBAKMI is not set
-CONFIG_SERIO_LIBPS2=y
-# CONFIG_SERIO_RAW is not set
-# CONFIG_SERIO_ALTERA_PS2 is not set
-# CONFIG_SERIO_PS2MULT is not set
-# CONFIG_GAMEPORT is not set
-
-#
-# Character devices
-#
-CONFIG_VT=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
-CONFIG_UNIX98_PTYS=y
-# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-# CONFIG_SERIAL_NONSTANDARD is not set
-# CONFIG_N_GSM is not set
-# CONFIG_TRACE_SINK is not set
-CONFIG_DEVKMEM=y
-
-#
-# Serial drivers
-#
-# CONFIG_SERIAL_8250 is not set
-
-#
-# Non-8250 serial port support
-#
-# CONFIG_SERIAL_AMBA_PL010 is not set
-# CONFIG_SERIAL_AMBA_PL011 is not set
-# CONFIG_SERIAL_MAX3100 is not set
-# CONFIG_SERIAL_MAX3107 is not set
-CONFIG_SERIAL_IMX=y
-CONFIG_SERIAL_IMX_CONSOLE=y
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-# CONFIG_SERIAL_TIMBERDALE is not set
-# CONFIG_SERIAL_ALTERA_JTAGUART is not set
-# CONFIG_SERIAL_ALTERA_UART is not set
-# CONFIG_SERIAL_IFX6X60 is not set
-# CONFIG_SERIAL_XILINX_PS_UART is not set
-# CONFIG_TTY_PRINTK is not set
-CONFIG_FSL_OTP=y
-# CONFIG_HVC_DCC is not set
-# CONFIG_IPMI_HANDLER is not set
-CONFIG_HW_RANDOM=y
-# CONFIG_HW_RANDOM_TIMERIOMEM is not set
-# CONFIG_R3964 is not set
-# CONFIG_RAW_DRIVER is not set
-# CONFIG_TCG_TPM is not set
-# CONFIG_RAMOOPS is not set
-CONFIG_MXS_VIIM=y
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_COMPAT=y
-CONFIG_I2C_CHARDEV=y
-# CONFIG_I2C_MUX is not set
-CONFIG_I2C_HELPER_AUTO=y
-
-#
-# I2C Hardware Bus support
-#
-
-#
-# I2C system bus drivers (mostly embedded / system-on-chip)
-#
-# CONFIG_I2C_DESIGNWARE is not set
-# CONFIG_I2C_GPIO is not set
-CONFIG_I2C_IMX=y
-# CONFIG_I2C_OCORES is not set
-# CONFIG_I2C_PCA_PLATFORM is not set
-# CONFIG_I2C_PXA_PCI is not set
-# CONFIG_I2C_SIMTEC is not set
-# CONFIG_I2C_XILINX is not set
-
-#
-# External I2C/SMBus adapter drivers
-#
-# CONFIG_I2C_DIOLAN_U2C is not set
-# CONFIG_I2C_PARPORT_LIGHT is not set
-# CONFIG_I2C_TAOS_EVM is not set
-# CONFIG_I2C_TINY_USB is not set
-
-#
-# Other I2C/SMBus bus drivers
-#
-# CONFIG_I2C_STUB is not set
-# CONFIG_I2C_DEBUG_CORE is not set
-# CONFIG_I2C_DEBUG_ALGO is not set
-# CONFIG_I2C_DEBUG_BUS is not set
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-
-#
-# SPI Master Controller Drivers
-#
-# CONFIG_SPI_ALTERA is not set
-CONFIG_SPI_BITBANG=y
-# CONFIG_SPI_GPIO is not set
-CONFIG_SPI_IMX_VER_2_3=y
-CONFIG_SPI_IMX=y
-# CONFIG_SPI_OC_TINY is not set
-# CONFIG_SPI_PL022 is not set
-# CONFIG_SPI_PXA2XX_PCI is not set
-# CONFIG_SPI_XILINX is not set
-# CONFIG_SPI_DESIGNWARE is not set
-
-#
-# SPI Protocol Masters
-#
-# CONFIG_SPI_SPIDEV is not set
-# CONFIG_SPI_TLE62X0 is not set
-
-#
-# PPS support
-#
-# CONFIG_PPS is not set
-
-#
-# PPS generators support
-#
-
-#
-# PTP clock support
-#
-
-#
-# Enable Device Drivers -> PPS to see the PTP clock options.
-#
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-
-#
-# Memory mapped GPIO drivers:
-#
-# CONFIG_GPIO_BASIC_MMIO is not set
-# CONFIG_GPIO_IT8761E is not set
-# CONFIG_GPIO_PL061 is not set
-
-#
-# I2C GPIO expanders:
-#
-# CONFIG_GPIO_MAX7300 is not set
-# CONFIG_GPIO_MAX732X is not set
-# CONFIG_GPIO_PCA953X_IRQ is not set
-# CONFIG_GPIO_PCF857X is not set
-# CONFIG_GPIO_SX150X is not set
-# CONFIG_GPIO_WM8994 is not set
-# CONFIG_GPIO_ADP5588 is not set
-
-#
-# PCI GPIO expanders:
-#
-
-#
-# SPI GPIO expanders:
-#
-# CONFIG_GPIO_MAX7301 is not set
-# CONFIG_GPIO_MCP23S08 is not set
-# CONFIG_GPIO_MC33880 is not set
-# CONFIG_GPIO_74X164 is not set
-
-#
-# AC97 GPIO expanders:
-#
-
-#
-# MODULbus GPIO expanders:
-#
-# CONFIG_W1 is not set
-CONFIG_POWER_SUPPLY=y
-# CONFIG_POWER_SUPPLY_DEBUG is not set
-# CONFIG_PDA_POWER is not set
-# CONFIG_APM_POWER is not set
-# CONFIG_TEST_POWER is not set
-# CONFIG_BATTERY_DS2780 is not set
-# CONFIG_BATTERY_DS2782 is not set
-# CONFIG_BATTERY_BQ20Z75 is not set
-# CONFIG_BATTERY_BQ27x00 is not set
-# CONFIG_BATTERY_MAX17040 is not set
-# CONFIG_BATTERY_MAX17042 is not set
-# CONFIG_CHARGER_ISP1704 is not set
-CONFIG_CHARGER_MAX8903=y
-# CONFIG_SABRESD_MAX8903 is not set
-# CONFIG_CHARGER_GPIO is not set
-CONFIG_HWMON=y
-# CONFIG_HWMON_VID is not set
-# CONFIG_HWMON_DEBUG_CHIP is not set
-
-#
-# Native drivers
-#
-# CONFIG_SENSORS_AD7414 is not set
-# CONFIG_SENSORS_AD7418 is not set
-# CONFIG_SENSORS_ADCXX is not set
-# CONFIG_SENSORS_ADM1021 is not set
-# CONFIG_SENSORS_ADM1025 is not set
-# CONFIG_SENSORS_ADM1026 is not set
-# CONFIG_SENSORS_ADM1029 is not set
-# CONFIG_SENSORS_ADM1031 is not set
-# CONFIG_SENSORS_ADM9240 is not set
-# CONFIG_SENSORS_ADT7411 is not set
-# CONFIG_SENSORS_ADT7462 is not set
-# CONFIG_SENSORS_ADT7470 is not set
-# CONFIG_SENSORS_ADT7475 is not set
-# CONFIG_SENSORS_ASC7621 is not set
-# CONFIG_SENSORS_ATXP1 is not set
-# CONFIG_SENSORS_DS620 is not set
-# CONFIG_SENSORS_DS1621 is not set
-# CONFIG_SENSORS_F71805F is not set
-# CONFIG_SENSORS_F71882FG is not set
-# CONFIG_SENSORS_F75375S is not set
-# CONFIG_SENSORS_G760A is not set
-# CONFIG_SENSORS_GL518SM is not set
-# CONFIG_SENSORS_GL520SM is not set
-# CONFIG_SENSORS_GPIO_FAN is not set
-# CONFIG_SENSORS_IT87 is not set
-# CONFIG_SENSORS_JC42 is not set
-# CONFIG_SENSORS_LINEAGE is not set
-# CONFIG_SENSORS_LM63 is not set
-# CONFIG_SENSORS_LM70 is not set
-# CONFIG_SENSORS_LM73 is not set
-# CONFIG_SENSORS_LM75 is not set
-# CONFIG_SENSORS_LM77 is not set
-# CONFIG_SENSORS_LM78 is not set
-# CONFIG_SENSORS_LM80 is not set
-# CONFIG_SENSORS_LM83 is not set
-# CONFIG_SENSORS_LM85 is not set
-# CONFIG_SENSORS_LM87 is not set
-# CONFIG_SENSORS_LM90 is not set
-# CONFIG_SENSORS_LM92 is not set
-# CONFIG_SENSORS_LM93 is not set
-# CONFIG_SENSORS_LTC4151 is not set
-# CONFIG_SENSORS_LTC4215 is not set
-# CONFIG_SENSORS_LTC4245 is not set
-# CONFIG_SENSORS_LTC4261 is not set
-# CONFIG_SENSORS_LM95241 is not set
-# CONFIG_SENSORS_MAX1111 is not set
-# CONFIG_SENSORS_MAX16065 is not set
-# CONFIG_SENSORS_MAX1619 is not set
-# CONFIG_SENSORS_MAX6639 is not set
-# CONFIG_SENSORS_MAX6642 is not set
-# CONFIG_SENSORS_MAX17135 is not set
-# CONFIG_SENSORS_MAX6650 is not set
-# CONFIG_SENSORS_PC87360 is not set
-# CONFIG_SENSORS_PC87427 is not set
-# CONFIG_SENSORS_PCF8591 is not set
-# CONFIG_PMBUS is not set
-# CONFIG_SENSORS_SHT15 is not set
-# CONFIG_SENSORS_SHT21 is not set
-# CONFIG_SENSORS_SMM665 is not set
-# CONFIG_SENSORS_DME1737 is not set
-# CONFIG_SENSORS_EMC1403 is not set
-# CONFIG_SENSORS_EMC2103 is not set
-# CONFIG_SENSORS_EMC6W201 is not set
-# CONFIG_SENSORS_SMSC47M1 is not set
-# CONFIG_SENSORS_SMSC47M192 is not set
-# CONFIG_SENSORS_SMSC47B397 is not set
-# CONFIG_SENSORS_SCH5627 is not set
-# CONFIG_SENSORS_ADS1015 is not set
-# CONFIG_SENSORS_ADS7828 is not set
-# CONFIG_SENSORS_ADS7871 is not set
-# CONFIG_SENSORS_AMC6821 is not set
-# CONFIG_SENSORS_THMC50 is not set
-# CONFIG_SENSORS_TMP102 is not set
-# CONFIG_SENSORS_TMP401 is not set
-# CONFIG_SENSORS_TMP421 is not set
-# CONFIG_SENSORS_VT1211 is not set
-# CONFIG_SENSORS_W83781D is not set
-# CONFIG_SENSORS_W83791D is not set
-# CONFIG_SENSORS_W83792D is not set
-# CONFIG_SENSORS_W83793 is not set
-# CONFIG_SENSORS_W83795 is not set
-# CONFIG_SENSORS_W83L785TS is not set
-# CONFIG_SENSORS_W83L786NG is not set
-# CONFIG_SENSORS_W83627HF is not set
-# CONFIG_SENSORS_W83627EHF is not set
-CONFIG_SENSORS_MAG3110=y
-# CONFIG_MXC_MMA8450 is not set
-CONFIG_MXC_MMA8451=y
-CONFIG_THERMAL=y
-# CONFIG_THERMAL_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-
-#
-# Watchdog Device Drivers
-#
-# CONFIG_SOFT_WATCHDOG is not set
-# CONFIG_ARM_SP805_WATCHDOG is not set
-# CONFIG_MPCORE_WATCHDOG is not set
-# CONFIG_MAX63XX_WATCHDOG is not set
-CONFIG_IMX2_WDT=y
-
-#
-# USB-based Watchdog Cards
-#
-# CONFIG_USBPCWATCHDOG is not set
-CONFIG_SSB_POSSIBLE=y
-
-#
-# Sonics Silicon Backplane
-#
-# CONFIG_SSB is not set
-CONFIG_BCMA_POSSIBLE=y
-
-#
-# Broadcom specific AMBA
-#
-# CONFIG_BCMA is not set
-CONFIG_MFD_SUPPORT=y
-CONFIG_MFD_CORE=y
-# CONFIG_MFD_88PM860X is not set
-# CONFIG_MFD_SM501 is not set
-# CONFIG_MFD_ASIC3 is not set
-# CONFIG_HTC_EGPIO is not set
-# CONFIG_HTC_PASIC3 is not set
-# CONFIG_HTC_I2CPLD is not set
-# CONFIG_UCB1400_CORE is not set
-# CONFIG_TPS6105X is not set
-# CONFIG_TPS65010 is not set
-# CONFIG_TPS6507X is not set
-# CONFIG_MFD_TPS6586X is not set
-# CONFIG_TWL4030_CORE is not set
-# CONFIG_MFD_STMPE is not set
-# CONFIG_MFD_TC3589X is not set
-# CONFIG_MFD_TMIO is not set
-# CONFIG_MFD_T7L66XB is not set
-# CONFIG_MFD_TC6387XB is not set
-# CONFIG_MFD_TC6393XB is not set
-# CONFIG_PMIC_DA903X is not set
-# CONFIG_PMIC_ADP5520 is not set
-# CONFIG_MFD_MAX8925 is not set
-# CONFIG_MFD_MAX8997 is not set
-# CONFIG_MFD_MAX8998 is not set
-# CONFIG_MFD_WM8400 is not set
-# CONFIG_MFD_WM831X_I2C is not set
-# CONFIG_MFD_WM831X_SPI is not set
-# CONFIG_MFD_WM8350_I2C is not set
-CONFIG_MFD_WM8994=y
-# CONFIG_MFD_PCF50633 is not set
-# CONFIG_PMIC_DIALOG is not set
-# CONFIG_MFD_MC_PMIC is not set
-# CONFIG_MFD_MC34708 is not set
-CONFIG_MFD_PFUZE=y
-# CONFIG_MFD_MC13XXX is not set
-# CONFIG_ABX500_CORE is not set
-# CONFIG_EZX_PCAP is not set
-# CONFIG_MFD_WL1273_CORE is not set
-# CONFIG_MFD_TPS65910 is not set
-# CONFIG_MFD_MAX17135 is not set
-CONFIG_MFD_MXC_HDMI=y
-CONFIG_REGULATOR=y
-# CONFIG_REGULATOR_DEBUG is not set
-# CONFIG_REGULATOR_DUMMY is not set
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
-# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
-# CONFIG_REGULATOR_BQ24022 is not set
-# CONFIG_REGULATOR_MAX1586 is not set
-# CONFIG_REGULATOR_MAX8649 is not set
-# CONFIG_REGULATOR_MAX8660 is not set
-# CONFIG_REGULATOR_MAX8952 is not set
-# CONFIG_REGULATOR_WM8994 is not set
-# CONFIG_REGULATOR_LP3971 is not set
-# CONFIG_REGULATOR_LP3972 is not set
-# CONFIG_REGULATOR_MC34708 is not set
-CONFIG_REGULATOR_PFUZE100=y
-# CONFIG_REGULATOR_TPS65023 is not set
-# CONFIG_REGULATOR_TPS6507X is not set
-# CONFIG_REGULATOR_ISL6271A is not set
-# CONFIG_REGULATOR_AD5398 is not set
-CONFIG_REGULATOR_ANATOP=y
-# CONFIG_REGULATOR_TPS6524X is not set
-CONFIG_MEDIA_SUPPORT=y
-
-#
-# Multimedia core support
-#
-# CONFIG_MEDIA_CONTROLLER is not set
-CONFIG_VIDEO_DEV=y
-CONFIG_VIDEO_V4L2_COMMON=y
-# CONFIG_DVB_CORE is not set
-CONFIG_VIDEO_MEDIA=y
-
-#
-# Multimedia drivers
-#
-# CONFIG_RC_CORE is not set
-# CONFIG_MEDIA_ATTACH is not set
-CONFIG_MEDIA_TUNER=y
-# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
-CONFIG_MEDIA_TUNER_SIMPLE=y
-CONFIG_MEDIA_TUNER_TDA8290=y
-CONFIG_MEDIA_TUNER_TDA827X=y
-CONFIG_MEDIA_TUNER_TDA18271=y
-CONFIG_MEDIA_TUNER_TDA9887=y
-CONFIG_MEDIA_TUNER_TEA5761=y
-CONFIG_MEDIA_TUNER_TEA5767=y
-CONFIG_MEDIA_TUNER_MT20XX=y
-CONFIG_MEDIA_TUNER_XC2028=y
-CONFIG_MEDIA_TUNER_XC5000=y
-CONFIG_MEDIA_TUNER_MC44S803=y
-CONFIG_VIDEO_V4L2=y
-CONFIG_VIDEOBUF_GEN=y
-CONFIG_VIDEOBUF_DMA_CONTIG=y
-CONFIG_VIDEO_CAPTURE_DRIVERS=y
-# CONFIG_VIDEO_ADV_DEBUG is not set
-# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
-# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
-
-#
-# Encoders, decoders, sensors and other helper chips
-#
-
-#
-# Audio decoders, processors and mixers
-#
-# CONFIG_VIDEO_TVAUDIO is not set
-# CONFIG_VIDEO_TDA7432 is not set
-# CONFIG_VIDEO_TDA9840 is not set
-# CONFIG_VIDEO_TEA6415C is not set
-# CONFIG_VIDEO_TEA6420 is not set
-# CONFIG_VIDEO_MSP3400 is not set
-# CONFIG_VIDEO_CS5345 is not set
-# CONFIG_VIDEO_CS53L32A is not set
-# CONFIG_VIDEO_TLV320AIC23B is not set
-# CONFIG_VIDEO_WM8775 is not set
-# CONFIG_VIDEO_WM8739 is not set
-# CONFIG_VIDEO_VP27SMPX is not set
-
-#
-# RDS decoders
-#
-# CONFIG_VIDEO_SAA6588 is not set
-
-#
-# Video decoders
-#
-# CONFIG_VIDEO_ADV7180 is not set
-# CONFIG_VIDEO_BT819 is not set
-# CONFIG_VIDEO_BT856 is not set
-# CONFIG_VIDEO_BT866 is not set
-# CONFIG_VIDEO_KS0127 is not set
-# CONFIG_VIDEO_SAA7110 is not set
-# CONFIG_VIDEO_SAA711X is not set
-# CONFIG_VIDEO_SAA7191 is not set
-# CONFIG_VIDEO_TVP514X is not set
-# CONFIG_VIDEO_TVP5150 is not set
-# CONFIG_VIDEO_TVP7002 is not set
-# CONFIG_VIDEO_VPX3220 is not set
-
-#
-# Video and audio decoders
-#
-# CONFIG_VIDEO_SAA717X is not set
-# CONFIG_VIDEO_CX25840 is not set
-
-#
-# MPEG video encoders
-#
-# CONFIG_VIDEO_CX2341X is not set
-
-#
-# Video encoders
-#
-# CONFIG_VIDEO_SAA7127 is not set
-# CONFIG_VIDEO_SAA7185 is not set
-# CONFIG_VIDEO_ADV7170 is not set
-# CONFIG_VIDEO_ADV7175 is not set
-# CONFIG_VIDEO_ADV7343 is not set
-# CONFIG_VIDEO_AK881X is not set
-
-#
-# Camera sensor devices
-#
-# CONFIG_VIDEO_OV7670 is not set
-# CONFIG_VIDEO_MT9V011 is not set
-# CONFIG_VIDEO_TCM825X is not set
-
-#
-# Video improvement chips
-#
-# CONFIG_VIDEO_UPD64031A is not set
-# CONFIG_VIDEO_UPD64083 is not set
-
-#
-# Miscelaneous helper chips
-#
-# CONFIG_VIDEO_THS7303 is not set
-# CONFIG_VIDEO_M52790 is not set
-# CONFIG_VIDEO_VIVI is not set
-# CONFIG_VIDEO_MXC_CAMERA is not set
-CONFIG_VIDEO_MXC_OUTPUT=y
-CONFIG_VIDEO_MXC_IPU_OUTPUT=y
-# CONFIG_VIDEO_MXC_IPUV1_WVGA_OUTPUT is not set
-# CONFIG_VIDEO_MXC_OPL is not set
-# CONFIG_VIDEO_CPIA2 is not set
-# CONFIG_VIDEO_TIMBERDALE is not set
-# CONFIG_VIDEO_SR030PC30 is not set
-# CONFIG_VIDEO_NOON010PC30 is not set
-# CONFIG_SOC_CAMERA is not set
-CONFIG_V4L_USB_DRIVERS=y
-CONFIG_USB_VIDEO_CLASS=m
-CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
-CONFIG_USB_GSPCA=m
-# CONFIG_USB_M5602 is not set
-# CONFIG_USB_STV06XX is not set
-# CONFIG_USB_GL860 is not set
-# CONFIG_USB_GSPCA_BENQ is not set
-# CONFIG_USB_GSPCA_CONEX is not set
-# CONFIG_USB_GSPCA_CPIA1 is not set
-# CONFIG_USB_GSPCA_ETOMS is not set
-# CONFIG_USB_GSPCA_FINEPIX is not set
-# CONFIG_USB_GSPCA_JEILINJ is not set
-# CONFIG_USB_GSPCA_KINECT is not set
-# CONFIG_USB_GSPCA_KONICA is not set
-# CONFIG_USB_GSPCA_MARS is not set
-# CONFIG_USB_GSPCA_MR97310A is not set
-# CONFIG_USB_GSPCA_NW80X is not set
-# CONFIG_USB_GSPCA_OV519 is not set
-# CONFIG_USB_GSPCA_OV534 is not set
-# CONFIG_USB_GSPCA_OV534_9 is not set
-# CONFIG_USB_GSPCA_PAC207 is not set
-# CONFIG_USB_GSPCA_PAC7302 is not set
-# CONFIG_USB_GSPCA_PAC7311 is not set
-# CONFIG_USB_GSPCA_SN9C2028 is not set
-# CONFIG_USB_GSPCA_SN9C20X is not set
-# CONFIG_USB_GSPCA_SONIXB is not set
-# CONFIG_USB_GSPCA_SONIXJ is not set
-# CONFIG_USB_GSPCA_SPCA500 is not set
-# CONFIG_USB_GSPCA_SPCA501 is not set
-# CONFIG_USB_GSPCA_SPCA505 is not set
-# CONFIG_USB_GSPCA_SPCA506 is not set
-# CONFIG_USB_GSPCA_SPCA508 is not set
-# CONFIG_USB_GSPCA_SPCA561 is not set
-# CONFIG_USB_GSPCA_SPCA1528 is not set
-# CONFIG_USB_GSPCA_SQ905 is not set
-# CONFIG_USB_GSPCA_SQ905C is not set
-# CONFIG_USB_GSPCA_SQ930X is not set
-# CONFIG_USB_GSPCA_STK014 is not set
-# CONFIG_USB_GSPCA_STV0680 is not set
-# CONFIG_USB_GSPCA_SUNPLUS is not set
-# CONFIG_USB_GSPCA_T613 is not set
-# CONFIG_USB_GSPCA_TV8532 is not set
-# CONFIG_USB_GSPCA_VC032X is not set
-# CONFIG_USB_GSPCA_VICAM is not set
-# CONFIG_USB_GSPCA_XIRLINK_CIT is not set
-# CONFIG_USB_GSPCA_ZC3XX is not set
-# CONFIG_VIDEO_PVRUSB2 is not set
-# CONFIG_VIDEO_HDPVR is not set
-# CONFIG_VIDEO_USBVISION is not set
-# CONFIG_USB_ET61X251 is not set
-# CONFIG_USB_SN9C102 is not set
-# CONFIG_USB_PWC is not set
-# CONFIG_USB_ZR364XX is not set
-# CONFIG_USB_STKWEBCAM is not set
-# CONFIG_USB_S2255 is not set
-# CONFIG_V4L_MEM2MEM_DRIVERS is not set
-# CONFIG_RADIO_ADAPTERS is not set
-
-#
-# Graphics support
-#
-# CONFIG_DRM is not set
-# CONFIG_VGASTATE is not set
-# CONFIG_VIDEO_OUTPUT_CONTROL is not set
-CONFIG_FB=y
-# CONFIG_FIRMWARE_EDID is not set
-# CONFIG_FB_DDC is not set
-# CONFIG_FB_BOOT_VESA_SUPPORT is not set
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
-# CONFIG_FB_SYS_FILLRECT is not set
-# CONFIG_FB_SYS_COPYAREA is not set
-# CONFIG_FB_SYS_IMAGEBLIT is not set
-# CONFIG_FB_FOREIGN_ENDIAN is not set
-# CONFIG_FB_SYS_FOPS is not set
-# CONFIG_FB_WMT_GE_ROPS is not set
-CONFIG_FB_DEFERRED_IO=y
-# CONFIG_FB_SVGALIB is not set
-# CONFIG_FB_MACMODES is not set
-# CONFIG_FB_BACKLIGHT is not set
-CONFIG_FB_MODE_HELPERS=y
-# CONFIG_FB_TILEBLITTING is not set
-
-#
-# Frame buffer hardware drivers
-#
-# CONFIG_FB_ARMCLCD is not set
-# CONFIG_FB_UVESA is not set
-# CONFIG_FB_S1D13XXX is not set
-# CONFIG_FB_TMIO is not set
-# CONFIG_FB_UDL is not set
-# CONFIG_FB_VIRTUAL is not set
-# CONFIG_FB_METRONOME is not set
-# CONFIG_FB_BROADSHEET is not set
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_BACKLIGHT_PWM=y
-# CONFIG_BACKLIGHT_ADP8860 is not set
-# CONFIG_BACKLIGHT_ADP8870 is not set
-
-#
-# Display device support
-#
-# CONFIG_DISPLAY_SUPPORT is not set
-CONFIG_FB_MXC=y
-CONFIG_FB_MXC_EDID=y
-CONFIG_FB_MXC_SYNC_PANEL=y
-# CONFIG_FB_MXC_EPSON_VGA_SYNC_PANEL is not set
-CONFIG_FB_MXC_LDB=y
-CONFIG_FB_MXC_MIPI_DSI=y
-CONFIG_FB_MXC_TRULY_WVGA_SYNC_PANEL=y
-# CONFIG_FB_MXC_CLAA_WVGA_SYNC_PANEL is not set
-# CONFIG_FB_MXC_SEIKO_WVGA_SYNC_PANEL is not set
-# CONFIG_FB_MXC_SII902X is not set
-# CONFIG_FB_MXC_CH7026 is not set
-# CONFIG_FB_MXC_TVOUT_CH7024 is not set
-# CONFIG_FB_MXC_ASYNC_PANEL is not set
-CONFIG_FB_MXC_EINK_PANEL=y
-# CONFIG_FB_MXC_EINK_AUTO_UPDATE_MODE is not set
-# CONFIG_FB_MXC_SIPIX_PANEL is not set
-# CONFIG_FB_MXC_ELCDIF_FB is not set
-CONFIG_FB_MXC_HDMI=y
-
-#
-# Console display driver support
-#
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
-# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
-CONFIG_FONTS=y
-# CONFIG_FONT_8x8 is not set
-CONFIG_FONT_8x16=y
-# CONFIG_FONT_6x11 is not set
-# CONFIG_FONT_7x14 is not set
-# CONFIG_FONT_PEARL_8x8 is not set
-# CONFIG_FONT_ACORN_8x8 is not set
-# CONFIG_FONT_MINI_4x6 is not set
-# CONFIG_FONT_SUN8x16 is not set
-# CONFIG_FONT_SUN12x22 is not set
-# CONFIG_FONT_10x18 is not set
-CONFIG_LOGO=y
-CONFIG_LOGO_LINUX_MONO=y
-CONFIG_LOGO_LINUX_VGA16=y
-CONFIG_LOGO_LINUX_CLUT224=y
-CONFIG_SOUND=y
-# CONFIG_SOUND_OSS_CORE is not set
-CONFIG_SND=y
-CONFIG_SND_TIMER=y
-CONFIG_SND_PCM=y
-CONFIG_SND_HWDEP=y
-CONFIG_SND_RAWMIDI=y
-CONFIG_SND_JACK=y
-# CONFIG_SND_SEQUENCER is not set
-# CONFIG_SND_MIXER_OSS is not set
-# CONFIG_SND_PCM_OSS is not set
-# CONFIG_SND_HRTIMER is not set
-# CONFIG_SND_DYNAMIC_MINORS is not set
-CONFIG_SND_SUPPORT_OLD_API=y
-CONFIG_SND_VERBOSE_PROCFS=y
-# CONFIG_SND_VERBOSE_PRINTK is not set
-# CONFIG_SND_DEBUG is not set
-# CONFIG_SND_RAWMIDI_SEQ is not set
-# CONFIG_SND_OPL3_LIB_SEQ is not set
-# CONFIG_SND_OPL4_LIB_SEQ is not set
-# CONFIG_SND_SBAWE_SEQ is not set
-# CONFIG_SND_EMU10K1_SEQ is not set
-CONFIG_SND_DRIVERS=y
-# CONFIG_SND_DUMMY is not set
-# CONFIG_SND_ALOOP is not set
-# CONFIG_SND_MTPAV is not set
-# CONFIG_SND_SERIAL_U16550 is not set
-# CONFIG_SND_MPU401 is not set
-CONFIG_SND_ARM=y
-# CONFIG_SND_ARMAACI is not set
-CONFIG_SND_SPI=y
-CONFIG_SND_USB=y
-CONFIG_SND_USB_AUDIO=y
-# CONFIG_SND_USB_UA101 is not set
-# CONFIG_SND_USB_CAIAQ is not set
-# CONFIG_SND_USB_6FIRE is not set
-CONFIG_SND_SOC=y
-# CONFIG_SND_SOC_CACHE_LZO is not set
-CONFIG_SND_SOC_AC97_BUS=y
-CONFIG_SND_IMX_SOC=y
-CONFIG_SND_MXC_SOC_MX2=y
-CONFIG_SND_MXC_SOC_SPDIF_DAI=y
-CONFIG_SND_SOC_IMX_SGTL5000=y
-CONFIG_SND_SOC_IMX_WM8958=y
-CONFIG_SND_SOC_IMX_WM8962=y
-# CONFIG_SND_SOC_IMX_SI4763 is not set
-CONFIG_SND_SOC_IMX_SPDIF=y
-CONFIG_SND_SOC_IMX_HDMI=y
-CONFIG_SND_SOC_I2C_AND_SPI=y
-# CONFIG_SND_SOC_ALL_CODECS is not set
-CONFIG_SND_SOC_WM_HUBS=y
-CONFIG_SND_SOC_MXC_HDMI=y
-CONFIG_SND_SOC_MXC_SPDIF=y
-CONFIG_SND_SOC_SGTL5000=y
-CONFIG_SND_SOC_WM8962=y
-CONFIG_SND_SOC_WM8994=y
-# CONFIG_SOUND_PRIME is not set
-CONFIG_AC97_BUS=y
-CONFIG_HID_SUPPORT=y
-CONFIG_HID=y
-CONFIG_HIDRAW=y
-
-#
-# USB Input Devices
-#
-CONFIG_USB_HID=y
-# CONFIG_HID_PID is not set
-# CONFIG_USB_HIDDEV is not set
-
-#
-# Special HID drivers
-#
-CONFIG_HID_A4TECH=m
-# CONFIG_HID_ACRUX is not set
-CONFIG_HID_APPLE=m
-CONFIG_HID_BELKIN=m
-CONFIG_HID_CHERRY=m
-CONFIG_HID_CHICONY=m
-# CONFIG_HID_PRODIKEYS is not set
-CONFIG_HID_CYPRESS=m
-# CONFIG_HID_DRAGONRISE is not set
-# CONFIG_HID_EMS_FF is not set
-# CONFIG_HID_ELECOM is not set
-CONFIG_HID_EZKEY=m
-# CONFIG_HID_KEYTOUCH is not set
-# CONFIG_HID_KYE is not set
-# CONFIG_HID_UCLOGIC is not set
-# CONFIG_HID_WALTOP is not set
-CONFIG_HID_GYRATION=m
-# CONFIG_HID_TWINHAN is not set
-# CONFIG_HID_KENSINGTON is not set
-# CONFIG_HID_LCPOWER is not set
-CONFIG_HID_LOGITECH=m
-# CONFIG_LOGITECH_FF is not set
-# CONFIG_LOGIRUMBLEPAD2_FF is not set
-# CONFIG_LOGIG940_FF is not set
-# CONFIG_LOGIWII_FF is not set
-# CONFIG_HID_MAGICMOUSE is not set
-CONFIG_HID_MICROSOFT=m
-CONFIG_HID_MONTEREY=m
-# CONFIG_HID_MULTITOUCH is not set
-# CONFIG_HID_NTRIG is not set
-# CONFIG_HID_ORTEK is not set
-CONFIG_HID_PANTHERLORD=m
-# CONFIG_PANTHERLORD_FF is not set
-CONFIG_HID_PETALYNX=m
-# CONFIG_HID_PICOLCD is not set
-# CONFIG_HID_QUANTA is not set
-# CONFIG_HID_ROCCAT is not set
-# CONFIG_HID_ROCCAT_ARVO is not set
-# CONFIG_HID_ROCCAT_KONE is not set
-# CONFIG_HID_ROCCAT_KONEPLUS is not set
-# CONFIG_HID_ROCCAT_KOVAPLUS is not set
-# CONFIG_HID_ROCCAT_PYRA is not set
-CONFIG_HID_SAMSUNG=m
-CONFIG_HID_SONY=m
-CONFIG_HID_SUNPLUS=m
-# CONFIG_HID_GREENASIA is not set
-# CONFIG_HID_SMARTJOYPLUS is not set
-# CONFIG_HID_TOPSEED is not set
-# CONFIG_HID_THRUSTMASTER is not set
-# CONFIG_HID_WACOM is not set
-# CONFIG_HID_ZEROPLUS is not set
-# CONFIG_HID_ZYDACRON is not set
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_ARCH_HAS_HCD=y
-# CONFIG_USB_ARCH_HAS_OHCI is not set
-CONFIG_USB_ARCH_HAS_EHCI=y
-CONFIG_USB=y
-# CONFIG_USB_DEBUG is not set
-# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
-
-#
-# Miscellaneous USB options
-#
-# CONFIG_USB_DEVICEFS is not set
-# CONFIG_USB_DEVICE_CLASS is not set
-# CONFIG_USB_DYNAMIC_MINORS is not set
-CONFIG_USB_SUSPEND=y
-CONFIG_USB_OTG=y
-# CONFIG_USB_OTG_WHITELIST is not set
-# CONFIG_USB_OTG_BLACKLIST_HUB is not set
-# CONFIG_USB_MON is not set
-# CONFIG_USB_WUSB is not set
-# CONFIG_USB_WUSB_CBAF is not set
-
-#
-# USB Host Controller Drivers
-#
-# CONFIG_USB_C67X00_HCD is not set
-CONFIG_USB_EHCI_HCD=y
-# CONFIG_FSL_USB_TEST_MODE is not set
-CONFIG_USB_EHCI_ARC=y
-CONFIG_USB_EHCI_ARC_OTG=y
-# CONFIG_USB_EHCI_ARC_HSIC is not set
-# CONFIG_USB_STATIC_IRAM is not set
-CONFIG_USB_EHCI_ROOT_HUB_TT=y
-# CONFIG_USB_EHCI_TT_NEWSCHED is not set
-# CONFIG_USB_EHCI_MXC is not set
-# CONFIG_USB_OXU210HP_HCD is not set
-# CONFIG_USB_ISP116X_HCD is not set
-# CONFIG_USB_ISP1760_HCD is not set
-# CONFIG_USB_ISP1362_HCD is not set
-# CONFIG_USB_SL811_HCD is not set
-# CONFIG_USB_R8A66597_HCD is not set
-# CONFIG_USB_HWA_HCD is not set
-# CONFIG_USB_MUSB_HDRC is not set
-
-#
-# USB Device Class drivers
-#
-# CONFIG_USB_ACM is not set
-# CONFIG_USB_PRINTER is not set
-# CONFIG_USB_WDM is not set
-# CONFIG_USB_TMC is not set
-
-#
-# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
-#
-
-#
-# also be needed; see USB_STORAGE Help for more info
-#
-CONFIG_USB_STORAGE=y
-# CONFIG_USB_STORAGE_DEBUG is not set
-# CONFIG_USB_STORAGE_REALTEK is not set
-# CONFIG_USB_STORAGE_DATAFAB is not set
-# CONFIG_USB_STORAGE_FREECOM is not set
-# CONFIG_USB_STORAGE_ISD200 is not set
-# CONFIG_USB_STORAGE_USBAT is not set
-# CONFIG_USB_STORAGE_SDDR09 is not set
-# CONFIG_USB_STORAGE_SDDR55 is not set
-# CONFIG_USB_STORAGE_JUMPSHOT is not set
-# CONFIG_USB_STORAGE_ALAUDA is not set
-# CONFIG_USB_STORAGE_ONETOUCH is not set
-# CONFIG_USB_STORAGE_KARMA is not set
-# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
-# CONFIG_USB_STORAGE_ENE_UB6250 is not set
-# CONFIG_USB_UAS is not set
-# CONFIG_USB_LIBUSUAL is not set
-
-#
-# USB Imaging devices
-#
-# CONFIG_USB_MDC800 is not set
-# CONFIG_USB_MICROTEK is not set
-
-#
-# USB port drivers
-#
-# CONFIG_USB_SERIAL is not set
-
-#
-# USB Miscellaneous drivers
-#
-# CONFIG_USB_EMI62 is not set
-# CONFIG_USB_EMI26 is not set
-# CONFIG_USB_ADUTUX is not set
-# CONFIG_USB_SEVSEG is not set
-# CONFIG_USB_RIO500 is not set
-# CONFIG_USB_LEGOTOWER is not set
-# CONFIG_USB_LCD is not set
-# CONFIG_USB_LED is not set
-# CONFIG_USB_CYPRESS_CY7C63 is not set
-# CONFIG_USB_CYTHERM is not set
-# CONFIG_USB_IDMOUSE is not set
-# CONFIG_USB_FTDI_ELAN is not set
-# CONFIG_USB_APPLEDISPLAY is not set
-# CONFIG_USB_SISUSBVGA is not set
-# CONFIG_USB_LD is not set
-# CONFIG_USB_TRANCEVIBRATOR is not set
-# CONFIG_USB_IOWARRIOR is not set
-# CONFIG_USB_TEST is not set
-# CONFIG_USB_ISIGHTFW is not set
-# CONFIG_USB_YUREX is not set
-CONFIG_USB_GADGET=y
-# CONFIG_USB_GADGET_DEBUG_FILES is not set
-# CONFIG_USB_GADGET_DEBUG_FS is not set
-CONFIG_USB_GADGET_VBUS_DRAW=2
-CONFIG_USB_GADGET_SELECTED=y
-CONFIG_USB_GADGET_ARC=y
-# CONFIG_IMX_USB_CHARGER is not set
-CONFIG_USB_ARC=y
-# CONFIG_USB_GADGET_FSL_USB2 is not set
-# CONFIG_USB_GADGET_FUSB300 is not set
-# CONFIG_USB_GADGET_R8A66597 is not set
-# CONFIG_USB_GADGET_PXA_U2O is not set
-# CONFIG_USB_GADGET_M66592 is not set
-# CONFIG_USB_GADGET_DUMMY_HCD is not set
-CONFIG_USB_GADGET_DUALSPEED=y
-# CONFIG_USB_ZERO is not set
-CONFIG_USB_AUDIO=m
-CONFIG_USB_ETH=m
-CONFIG_USB_ETH_RNDIS=y
-# CONFIG_USB_ETH_EEM is not set
-# CONFIG_USB_G_NCM is not set
-# CONFIG_USB_GADGETFS is not set
-# CONFIG_USB_FUNCTIONFS is not set
-CONFIG_USB_FILE_STORAGE=m
-# CONFIG_FSL_UTP is not set
-# CONFIG_USB_FILE_STORAGE_TEST is not set
-# CONFIG_USB_MASS_STORAGE is not set
-CONFIG_USB_G_SERIAL=m
-# CONFIG_USB_MIDI_GADGET is not set
-# CONFIG_USB_G_PRINTER is not set
-# CONFIG_USB_CDC_COMPOSITE is not set
-# CONFIG_USB_G_MULTI is not set
-# CONFIG_USB_G_HID is not set
-# CONFIG_USB_G_DBGP is not set
-# CONFIG_USB_G_WEBCAM is not set
-
-#
-# OTG and related infrastructure
-#
-CONFIG_USB_OTG_UTILS=y
-# CONFIG_USB_GPIO_VBUS is not set
-# CONFIG_USB_ULPI is not set
-# CONFIG_NOP_USB_XCEIV is not set
-CONFIG_MXC_OTG=y
-CONFIG_MMC=y
-# CONFIG_MMC_DEBUG is not set
-CONFIG_MMC_UNSAFE_RESUME=y
-# CONFIG_MMC_CLKGATE is not set
-
-#
-# MMC/SD/SDIO Card Drivers
-#
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_BLOCK_MINORS=8
-CONFIG_MMC_BLOCK_BOUNCE=y
-# CONFIG_SDIO_UART is not set
-# CONFIG_MMC_TEST is not set
-
-#
-# MMC/SD/SDIO Host Controller Drivers
-#
-# CONFIG_MMC_ARMMMCI is not set
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_IO_ACCESSORS=y
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MMC_SDHCI_ESDHC_IMX=y
-# CONFIG_MMC_DW is not set
-# CONFIG_MMC_VUB300 is not set
-# CONFIG_MMC_USHC is not set
-# CONFIG_MEMSTICK is not set
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-
-#
-# LED drivers
-#
-# CONFIG_LEDS_LM3530 is not set
-# CONFIG_LEDS_PCA9532 is not set
-# CONFIG_LEDS_GPIO is not set
-# CONFIG_LEDS_LP3944 is not set
-# CONFIG_LEDS_LP5521 is not set
-# CONFIG_LEDS_LP5523 is not set
-# CONFIG_LEDS_PCA955X is not set
-# CONFIG_LEDS_DAC124S085 is not set
-# CONFIG_LEDS_PWM is not set
-# CONFIG_LEDS_REGULATOR is not set
-# CONFIG_LEDS_BD2802 is not set
-# CONFIG_LEDS_LT3593 is not set
-# CONFIG_LEDS_TRIGGERS is not set
-
-#
-# LED Triggers
-#
-
-#
-# LED Triggers
-#
-# CONFIG_NFC_DEVICES is not set
-# CONFIG_ACCESSIBILITY is not set
-CONFIG_RTC_LIB=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_HCTOSYS=y
-CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
-# CONFIG_RTC_DEBUG is not set
-
-#
-# RTC interfaces
-#
-CONFIG_RTC_INTF_SYSFS=y
-CONFIG_RTC_INTF_PROC=y
-CONFIG_RTC_INTF_DEV=y
-CONFIG_RTC_INTF_DEV_UIE_EMUL=y
-# CONFIG_RTC_DRV_TEST is not set
-
-#
-# I2C RTC drivers
-#
-# CONFIG_RTC_DRV_DS1307 is not set
-# CONFIG_RTC_DRV_DS1374 is not set
-# CONFIG_RTC_DRV_DS1672 is not set
-# CONFIG_RTC_DRV_DS3232 is not set
-# CONFIG_RTC_DRV_MAX6900 is not set
-# CONFIG_RTC_DRV_RS5C372 is not set
-# CONFIG_RTC_DRV_ISL1208 is not set
-# CONFIG_RTC_DRV_ISL12022 is not set
-# CONFIG_RTC_DRV_X1205 is not set
-# CONFIG_RTC_DRV_PCF8563 is not set
-# CONFIG_RTC_DRV_PCF8583 is not set
-# CONFIG_RTC_DRV_M41T80 is not set
-# CONFIG_RTC_DRV_BQ32K is not set
-# CONFIG_RTC_DRV_S35390A is not set
-# CONFIG_RTC_DRV_FM3130 is not set
-# CONFIG_RTC_DRV_RX8581 is not set
-# CONFIG_RTC_DRV_RX8025 is not set
-# CONFIG_RTC_DRV_EM3027 is not set
-# CONFIG_RTC_DRV_RV3029C2 is not set
-
-#
-# SPI RTC drivers
-#
-# CONFIG_RTC_DRV_M41T93 is not set
-# CONFIG_RTC_DRV_M41T94 is not set
-# CONFIG_RTC_DRV_DS1305 is not set
-# CONFIG_RTC_DRV_DS1390 is not set
-# CONFIG_RTC_DRV_MAX6902 is not set
-# CONFIG_RTC_DRV_R9701 is not set
-# CONFIG_RTC_DRV_RS5C348 is not set
-# CONFIG_RTC_DRV_DS3234 is not set
-# CONFIG_RTC_DRV_PCF2123 is not set
-
-#
-# Platform RTC drivers
-#
-# CONFIG_RTC_DRV_CMOS is not set
-# CONFIG_RTC_DRV_DS1286 is not set
-# CONFIG_RTC_DRV_DS1511 is not set
-# CONFIG_RTC_DRV_DS1553 is not set
-# CONFIG_RTC_DRV_DS1742 is not set
-# CONFIG_RTC_DRV_STK17TA8 is not set
-# CONFIG_RTC_DRV_M48T86 is not set
-# CONFIG_RTC_DRV_M48T35 is not set
-# CONFIG_RTC_DRV_M48T59 is not set
-# CONFIG_RTC_DRV_MSM6242 is not set
-# CONFIG_RTC_MXC is not set
-# CONFIG_RTC_DRV_MXC_V2 is not set
-CONFIG_RTC_DRV_SNVS=y
-# CONFIG_RTC_DRV_BQ4802 is not set
-# CONFIG_RTC_DRV_RP5C01 is not set
-# CONFIG_RTC_DRV_V3020 is not set
-
-#
-# on-CPU RTC drivers
-#
-# CONFIG_RTC_DRV_PL030 is not set
-# CONFIG_RTC_DRV_PL031 is not set
-CONFIG_DMADEVICES=y
-# CONFIG_DMADEVICES_DEBUG is not set
-
-#
-# DMA Devices
-#
-# CONFIG_AMBA_PL08X is not set
-# CONFIG_DW_DMAC is not set
-CONFIG_MXC_PXP_V2=y
-CONFIG_MXC_PXP_CLIENT_DEVICE=y
-# CONFIG_TIMB_DMA is not set
-CONFIG_IMX_SDMA=y
-# CONFIG_MXS_DMA is not set
-CONFIG_DMA_ENGINE=y
-
-#
-# DMA Clients
-#
-# CONFIG_NET_DMA is not set
-# CONFIG_ASYNC_TX_DMA is not set
-# CONFIG_DMATEST is not set
-# CONFIG_AUXDISPLAY is not set
-# CONFIG_UIO is not set
-# CONFIG_STAGING is not set
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_CLKSRC_MMIO=y
-
-#
-# MXC support drivers
-#
-CONFIG_MXC_IPU=y
-CONFIG_MXC_IPU_V3=y
-CONFIG_MXC_IPU_V3H=y
-
-#
-# MXC SSI support
-#
-# CONFIG_MXC_SSI is not set
-
-#
-# MXC Digital Audio Multiplexer support
-#
-# CONFIG_MXC_DAM is not set
-
-#
-# MXC PMIC support
-#
-# CONFIG_MXC_PMIC_MC13783 is not set
-# CONFIG_MXC_PMIC_MC13892 is not set
-# CONFIG_MXC_PMIC_MC34704 is not set
-# CONFIG_MXC_PMIC_MC9SDZ60 is not set
-# CONFIG_MXC_PMIC_MC9S08DZ60 is not set
-
-#
-# MXC Security Drivers
-#
-# CONFIG_MXC_SECURITY_SCC is not set
-# CONFIG_MXC_SECURITY_RNG is not set
-
-#
-# MXC MPEG4 Encoder Kernel module support
-#
-# CONFIG_MXC_HMP4E is not set
-
-#
-# MXC HARDWARE EVENT
-#
-# CONFIG_MXC_HWEVENT is not set
-
-#
-# MXC VPU(Video Processing Unit) support
-#
-CONFIG_MXC_VPU=y
-# CONFIG_MXC_VPU_DEBUG is not set
-# CONFIG_MX6_VPU_352M is not set
-
-#
-# MXC Asynchronous Sample Rate Converter support
-#
-CONFIG_MXC_ASRC=y
-
-#
-# MXC Bluetooth support
-#
-
-#
-# Broadcom GPS ioctrl support
-#
-
-#
-# MXC Media Local Bus Driver
-#
-CONFIG_MXC_MLB=y
-CONFIG_MXC_MLB150=m
-
-#
-# i.MX ADC support
-#
-# CONFIG_IMX_ADC is not set
-
-#
-# MXC Vivante GPU support
-#
-CONFIG_MXC_GPU_VIV=y
-
-#
-# ANATOP_THERMAL
-#
-CONFIG_ANATOP_THERMAL=y
-
-#
-# MXC MIPI Support
-#
-CONFIG_MXC_MIPI_CSI2=y
-
-#
-# MXC HDMI CEC (Consumer Electronics Control) support
-#
-# CONFIG_MXC_HDMI_CEC is not set
-
-#
-# File systems
-#
-CONFIG_EXT2_FS=y
-# CONFIG_EXT2_FS_XATTR is not set
-# CONFIG_EXT2_FS_XIP is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
-CONFIG_EXT3_FS_XATTR=y
-# CONFIG_EXT3_FS_POSIX_ACL is not set
-# CONFIG_EXT3_FS_SECURITY is not set
-CONFIG_EXT4_FS=y
-CONFIG_EXT4_FS_XATTR=y
-# CONFIG_EXT4_FS_POSIX_ACL is not set
-# CONFIG_EXT4_FS_SECURITY is not set
-# CONFIG_EXT4_DEBUG is not set
-CONFIG_JBD=y
-# CONFIG_JBD_DEBUG is not set
-CONFIG_JBD2=y
-# CONFIG_JBD2_DEBUG is not set
-CONFIG_FS_MBCACHE=y
-# CONFIG_REISERFS_FS is not set
-# CONFIG_JFS_FS is not set
-# CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
-# CONFIG_BTRFS_FS is not set
-# CONFIG_NILFS2_FS is not set
-# CONFIG_FS_POSIX_ACL is not set
-CONFIG_FILE_LOCKING=y
-CONFIG_FSNOTIFY=y
-CONFIG_DNOTIFY=y
-CONFIG_INOTIFY_USER=y
-# CONFIG_FANOTIFY is not set
-# CONFIG_QUOTA is not set
-# CONFIG_QUOTACTL is not set
-CONFIG_AUTOFS4_FS=m
-# CONFIG_FUSE_FS is not set
-
-#
-# Caches
-#
-# CONFIG_FSCACHE is not set
-
-#
-# CD-ROM/DVD Filesystems
-#
-# CONFIG_ISO9660_FS is not set
-# CONFIG_UDF_FS is not set
-
-#
-# DOS/FAT/NT Filesystems
-#
-CONFIG_FAT_FS=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_FAT_DEFAULT_CODEPAGE=437
-CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-# CONFIG_NTFS_FS is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_SYSFS=y
-CONFIG_TMPFS=y
-# CONFIG_TMPFS_POSIX_ACL is not set
-# CONFIG_TMPFS_XATTR is not set
-# CONFIG_HUGETLB_PAGE is not set
-# CONFIG_CONFIGFS_FS is not set
-CONFIG_MISC_FILESYSTEMS=y
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_FS_DEBUG=0
-CONFIG_JFFS2_FS_WRITEBUFFER=y
-# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
-# CONFIG_JFFS2_SUMMARY is not set
-# CONFIG_JFFS2_FS_XATTR is not set
-# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
-CONFIG_JFFS2_ZLIB=y
-# CONFIG_JFFS2_LZO is not set
-CONFIG_JFFS2_RTIME=y
-# CONFIG_JFFS2_RUBIN is not set
-CONFIG_UBIFS_FS=y
-# CONFIG_UBIFS_FS_XATTR is not set
-# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
-CONFIG_UBIFS_FS_LZO=y
-CONFIG_UBIFS_FS_ZLIB=y
-# CONFIG_UBIFS_FS_DEBUG is not set
-# CONFIG_LOGFS is not set
-CONFIG_CRAMFS=y
-# CONFIG_SQUASHFS is not set
-# CONFIG_VXFS_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_OMFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_ROMFS_FS is not set
-# CONFIG_PSTORE is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-CONFIG_NETWORK_FILESYSTEMS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-# CONFIG_NFS_V3_ACL is not set
-# CONFIG_NFS_V4 is not set
-CONFIG_ROOT_NFS=y
-# CONFIG_NFSD is not set
-CONFIG_LOCKD=y
-CONFIG_LOCKD_V4=y
-CONFIG_NFS_COMMON=y
-CONFIG_SUNRPC=y
-# CONFIG_CEPH_FS is not set
-# CONFIG_CIFS is not set
-# CONFIG_NCP_FS is not set
-# CONFIG_CODA_FS is not set
-# CONFIG_AFS_FS is not set
-
-#
-# Partition Types
-#
-CONFIG_PARTITION_ADVANCED=y
-# CONFIG_ACORN_PARTITION is not set
-# CONFIG_OSF_PARTITION is not set
-# CONFIG_AMIGA_PARTITION is not set
-# CONFIG_ATARI_PARTITION is not set
-# CONFIG_MAC_PARTITION is not set
-CONFIG_MSDOS_PARTITION=y
-# CONFIG_BSD_DISKLABEL is not set
-# CONFIG_MINIX_SUBPARTITION is not set
-# CONFIG_SOLARIS_X86_PARTITION is not set
-# CONFIG_UNIXWARE_DISKLABEL is not set
-# CONFIG_LDM_PARTITION is not set
-# CONFIG_SGI_PARTITION is not set
-# CONFIG_ULTRIX_PARTITION is not set
-# CONFIG_SUN_PARTITION is not set
-# CONFIG_KARMA_PARTITION is not set
-CONFIG_EFI_PARTITION=y
-# CONFIG_SYSV68_PARTITION is not set
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="iso8859-1"
-CONFIG_NLS_CODEPAGE_437=y
-# CONFIG_NLS_CODEPAGE_737 is not set
-# CONFIG_NLS_CODEPAGE_775 is not set
-# CONFIG_NLS_CODEPAGE_850 is not set
-# CONFIG_NLS_CODEPAGE_852 is not set
-# CONFIG_NLS_CODEPAGE_855 is not set
-# CONFIG_NLS_CODEPAGE_857 is not set
-# CONFIG_NLS_CODEPAGE_860 is not set
-# CONFIG_NLS_CODEPAGE_861 is not set
-# CONFIG_NLS_CODEPAGE_862 is not set
-# CONFIG_NLS_CODEPAGE_863 is not set
-# CONFIG_NLS_CODEPAGE_864 is not set
-# CONFIG_NLS_CODEPAGE_865 is not set
-# CONFIG_NLS_CODEPAGE_866 is not set
-# CONFIG_NLS_CODEPAGE_869 is not set
-# CONFIG_NLS_CODEPAGE_936 is not set
-# CONFIG_NLS_CODEPAGE_950 is not set
-# CONFIG_NLS_CODEPAGE_932 is not set
-# CONFIG_NLS_CODEPAGE_949 is not set
-# CONFIG_NLS_CODEPAGE_874 is not set
-# CONFIG_NLS_ISO8859_8 is not set
-# CONFIG_NLS_CODEPAGE_1250 is not set
-# CONFIG_NLS_CODEPAGE_1251 is not set
-CONFIG_NLS_ASCII=m
-CONFIG_NLS_ISO8859_1=y
-# CONFIG_NLS_ISO8859_2 is not set
-# CONFIG_NLS_ISO8859_3 is not set
-# CONFIG_NLS_ISO8859_4 is not set
-# CONFIG_NLS_ISO8859_5 is not set
-# CONFIG_NLS_ISO8859_6 is not set
-# CONFIG_NLS_ISO8859_7 is not set
-# CONFIG_NLS_ISO8859_9 is not set
-# CONFIG_NLS_ISO8859_13 is not set
-# CONFIG_NLS_ISO8859_14 is not set
-# CONFIG_NLS_ISO8859_15 is not set
-# CONFIG_NLS_KOI8_R is not set
-# CONFIG_NLS_KOI8_U is not set
-CONFIG_NLS_UTF8=m
-
-#
-# Kernel hacking
-#
-# CONFIG_PRINTK_TIME is not set
-CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
-CONFIG_ENABLE_WARN_DEPRECATED=y
-CONFIG_ENABLE_MUST_CHECK=y
-CONFIG_FRAME_WARN=1024
-# CONFIG_MAGIC_SYSRQ is not set
-# CONFIG_STRIP_ASM_SYMS is not set
-# CONFIG_UNUSED_SYMBOLS is not set
-CONFIG_DEBUG_FS=y
-# CONFIG_HEADERS_CHECK is not set
-# CONFIG_DEBUG_SECTION_MISMATCH is not set
-# CONFIG_DEBUG_KERNEL is not set
-# CONFIG_HARDLOCKUP_DETECTOR is not set
-# CONFIG_SLUB_DEBUG_ON is not set
-# CONFIG_SLUB_STATS is not set
-# CONFIG_SPARSE_RCU_POINTER is not set
-CONFIG_DEBUG_BUGVERBOSE=y
-# CONFIG_DEBUG_MEMORY_INIT is not set
-CONFIG_RCU_CPU_STALL_TIMEOUT=60
-CONFIG_RCU_CPU_STALL_VERBOSE=y
-# CONFIG_LKDTM is not set
-CONFIG_SYSCTL_SYSCALL_CHECK=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_TRACING_SUPPORT=y
-# CONFIG_FTRACE is not set
-# CONFIG_DYNAMIC_DEBUG is not set
-# CONFIG_DMA_API_DEBUG is not set
-# CONFIG_ATOMIC64_SELFTEST is not set
-# CONFIG_SAMPLES is not set
-CONFIG_HAVE_ARCH_KGDB=y
-# CONFIG_TEST_KSTRTOX is not set
-# CONFIG_STRICT_DEVMEM is not set
-CONFIG_ARM_UNWIND=y
-# CONFIG_DEBUG_USER is not set
-CONFIG_OC_ETM=y
-
-#
-# Security options
-#
-# CONFIG_KEYS is not set
-# CONFIG_SECURITY_DMESG_RESTRICT is not set
-# CONFIG_SECURITY is not set
-# CONFIG_SECURITYFS is not set
-CONFIG_DEFAULT_SECURITY_DAC=y
-CONFIG_DEFAULT_SECURITY=""
-CONFIG_CRYPTO=y
-
-#
-# Crypto core or helper
-#
-CONFIG_CRYPTO_ALGAPI=y
-CONFIG_CRYPTO_ALGAPI2=y
-CONFIG_CRYPTO_AEAD2=y
-CONFIG_CRYPTO_BLKCIPHER=y
-CONFIG_CRYPTO_BLKCIPHER2=y
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_HASH2=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_PCOMP2=y
-CONFIG_CRYPTO_MANAGER=y
-CONFIG_CRYPTO_MANAGER2=y
-CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
-# CONFIG_CRYPTO_GF128MUL is not set
-# CONFIG_CRYPTO_NULL is not set
-# CONFIG_CRYPTO_PCRYPT is not set
-CONFIG_CRYPTO_WORKQUEUE=y
-# CONFIG_CRYPTO_CRYPTD is not set
-# CONFIG_CRYPTO_AUTHENC is not set
-CONFIG_CRYPTO_TEST=m
-# CONFIG_CRYPTO_CRYPTODEV is not set
-
-#
-# Authenticated Encryption with Associated Data
-#
-# CONFIG_CRYPTO_CCM is not set
-# CONFIG_CRYPTO_GCM is not set
-# CONFIG_CRYPTO_SEQIV is not set
-
-#
-# Block modes
-#
-CONFIG_CRYPTO_CBC=y
-# CONFIG_CRYPTO_CTR is not set
-# CONFIG_CRYPTO_CTS is not set
-CONFIG_CRYPTO_ECB=y
-# CONFIG_CRYPTO_LRW is not set
-# CONFIG_CRYPTO_PCBC is not set
-# CONFIG_CRYPTO_XTS is not set
-
-#
-# Hash modes
-#
-# CONFIG_CRYPTO_HMAC is not set
-# CONFIG_CRYPTO_XCBC is not set
-# CONFIG_CRYPTO_VMAC is not set
-
-#
-# Digest
-#
-# CONFIG_CRYPTO_CRC32C is not set
-# CONFIG_CRYPTO_GHASH is not set
-# CONFIG_CRYPTO_MD4 is not set
-# CONFIG_CRYPTO_MD5 is not set
-CONFIG_CRYPTO_MICHAEL_MIC=y
-# CONFIG_CRYPTO_RMD128 is not set
-# CONFIG_CRYPTO_RMD160 is not set
-# CONFIG_CRYPTO_RMD256 is not set
-# CONFIG_CRYPTO_RMD320 is not set
-# CONFIG_CRYPTO_SHA1 is not set
-# CONFIG_CRYPTO_SHA256 is not set
-# CONFIG_CRYPTO_SHA512 is not set
-# CONFIG_CRYPTO_TGR192 is not set
-# CONFIG_CRYPTO_WP512 is not set
-
-#
-# Ciphers
-#
-CONFIG_CRYPTO_AES=y
-# CONFIG_CRYPTO_ANUBIS is not set
-CONFIG_CRYPTO_ARC4=y
-# CONFIG_CRYPTO_BLOWFISH is not set
-# CONFIG_CRYPTO_CAMELLIA is not set
-# CONFIG_CRYPTO_CAST5 is not set
-# CONFIG_CRYPTO_CAST6 is not set
-# CONFIG_CRYPTO_DES is not set
-# CONFIG_CRYPTO_FCRYPT is not set
-# CONFIG_CRYPTO_KHAZAD is not set
-# CONFIG_CRYPTO_SALSA20 is not set
-# CONFIG_CRYPTO_SEED is not set
-# CONFIG_CRYPTO_SERPENT is not set
-# CONFIG_CRYPTO_TEA is not set
-# CONFIG_CRYPTO_TWOFISH is not set
-
-#
-# Compression
-#
-CONFIG_CRYPTO_DEFLATE=y
-# CONFIG_CRYPTO_ZLIB is not set
-CONFIG_CRYPTO_LZO=y
-
-#
-# Random Number Generation
-#
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-# CONFIG_CRYPTO_USER_API_HASH is not set
-# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
-CONFIG_CRYPTO_HW=y
-# CONFIG_CRYPTO_DEV_FSL_CAAM is not set
-# CONFIG_CRYPTO_DEV_FSL_CAAM_SM is not set
-# CONFIG_BINARY_PRINTF is not set
-
-#
-# Library routines
-#
-CONFIG_BITREVERSE=y
-CONFIG_RATIONAL=y
-CONFIG_CRC_CCITT=m
-CONFIG_CRC16=y
-# CONFIG_CRC_T10DIF is not set
-# CONFIG_CRC_ITU_T is not set
-CONFIG_CRC32=y
-# CONFIG_CRC7 is not set
-# CONFIG_LIBCRC32C is not set
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-# CONFIG_XZ_DEC is not set
-# CONFIG_XZ_DEC_BCJ is not set
-CONFIG_DECOMPRESS_GZIP=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAS_DMA=y
-CONFIG_CPU_RMAP=y
-CONFIG_NLATTR=y
-# CONFIG_AVERAGE is not set
diff --git a/recipes-kernel/linux/linux-congatec-3.0.35/drm-vivante-Add-00-sufix-in-returned-bus-Id.patch b/recipes-kernel/linux/linux-congatec-3.0.35/drm-vivante-Add-00-sufix-in-returned-bus-Id.patch
deleted file mode 100644
index 815d02c..0000000
--- a/recipes-kernel/linux/linux-congatec-3.0.35/drm-vivante-Add-00-sufix-in-returned-bus-Id.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From b37a944f55a5010bd08297a63db0275540922f32 Mon Sep 17 00:00:00 2001
-From: Otavio Salvador <otavio at ossystems.com.br>
-Date: Thu, 22 Aug 2013 16:31:29 -0300
-Subject: [PATCH] drm/vivante: Add ":00" sufix in returned bus Id
-
-This makes the 3.0.35 compatible with a Xorg driver build for 3.5.7 or
-newer kernels.
-
-Upstream-Status: Inapropriate [embedded specific]
-
-Signed-off-by: Otavio Salvador <otavio at ossystems.com.br>
----
- drivers/gpu/drm/vivante/vivante_drv.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/vivante/vivante_drv.c b/drivers/gpu/drm/vivante/vivante_drv.c
-index 4224608..cea360d 100644
---- a/drivers/gpu/drm/vivante/vivante_drv.c
-+++ b/drivers/gpu/drm/vivante/vivante_drv.c
-@@ -55,7 +55,7 @@
-
- #include "drm_pciids.h"
-
--static char platformdevicename[] = "Vivante GCCore";
-+static char platformdevicename[] = "Vivante GCCore:00";
- static struct platform_device *pplatformdev;
-
- static struct drm_driver driver = {
---
-1.8.4.rc1
-
diff --git a/recipes-kernel/linux/linux-congatec-3.0.35/epdc-Rename-mxcfb_epdc_kernel.h-to-mxc_epdc.h.patch b/recipes-kernel/linux/linux-congatec-3.0.35/epdc-Rename-mxcfb_epdc_kernel.h-to-mxc_epdc.h.patch
deleted file mode 100644
index 0a20b3f..0000000
--- a/recipes-kernel/linux/linux-congatec-3.0.35/epdc-Rename-mxcfb_epdc_kernel.h-to-mxc_epdc.h.patch
+++ /dev/null
@@ -1,143 +0,0 @@
-From 149545df26169d257b144ff78934ce9cb5b6818b Mon Sep 17 00:00:00 2001
-From: Otavio Salvador <otavio at ossystems.com.br>
-Date: Sat, 19 Oct 2013 10:55:11 -0300
-Subject: [PATCH] epdc: Rename mxcfb_epdc_kernel.h to mxc_epdc.h
-Organization: O.S. Systems Software LTDA.
-
-This allow for forward compatibility with imx-test >= 3.10.9-1.0.0.
-
-Signed-off-by: Otavio Salvador <otavio at ossystems.com.br>
----
- drivers/video/mxc/mxc_epdc_fb.c | 2 +-
- include/linux/mxcfb_epdc.h | 49 +++++++++++++++++++++++++++++++++++++++
- include/linux/mxcfb_epdc_kernel.h | 49 ---------------------------------------
- 3 files changed, 50 insertions(+), 50 deletions(-)
- create mode 100644 include/linux/mxcfb_epdc.h
- delete mode 100644 include/linux/mxcfb_epdc_kernel.h
-
-diff --git a/drivers/video/mxc/mxc_epdc_fb.c b/drivers/video/mxc/mxc_epdc_fb.c
-index 4103498..b3ef8ea 100644
---- a/drivers/video/mxc/mxc_epdc_fb.c
-+++ b/drivers/video/mxc/mxc_epdc_fb.c
-@@ -43,7 +43,7 @@
- #include <linux/dmaengine.h>
- #include <linux/pxp_dma.h>
- #include <linux/mxcfb.h>
--#include <linux/mxcfb_epdc_kernel.h>
-+#include <linux/mxcfb_epdc.h>
- #include <linux/gpio.h>
- #include <linux/regulator/driver.h>
- #include <linux/fsl_devices.h>
-diff --git a/include/linux/mxcfb_epdc.h b/include/linux/mxcfb_epdc.h
-new file mode 100644
-index 0000000..06fea6f
---- /dev/null
-+++ b/include/linux/mxcfb_epdc.h
-@@ -0,0 +1,49 @@
-+/*
-+ * Copyright (C) 2010-2012 Freescale Semiconductor, Inc. All Rights Reserved.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ *
-+ */
-+#ifndef _MXCFB_EPDC_KERNEL
-+#define _MXCFB_EPDC_KERNEL
-+
-+void mxc_epdc_fb_set_waveform_modes(struct mxcfb_waveform_modes *modes,
-+ struct fb_info *info);
-+int mxc_epdc_fb_set_temperature(int temperature, struct fb_info *info);
-+int mxc_epdc_fb_set_auto_update(u32 auto_mode, struct fb_info *info);
-+int mxc_epdc_fb_send_update(struct mxcfb_update_data *upd_data,
-+ struct fb_info *info);
-+int mxc_epdc_fb_wait_update_complete(
-+ struct mxcfb_update_marker_data *marker_data,
-+ struct fb_info *info);
-+int mxc_epdc_fb_set_pwrdown_delay(u32 pwrdown_delay,
-+ struct fb_info *info);
-+int mxc_epdc_get_pwrdown_delay(struct fb_info *info);
-+int mxc_epdc_fb_set_upd_scheme(u32 upd_scheme, struct fb_info *info);
-+
-+void mxc_spdc_fb_set_waveform_modes(struct mxcfb_waveform_modes *modes,
-+ struct fb_info *info);
-+int mxc_spdc_fb_set_temperature(int temperature, struct fb_info *info);
-+int mxc_spdc_fb_set_auto_update(u32 auto_mode, struct fb_info *info);
-+int mxc_spdc_fb_send_update(struct mxcfb_update_data *upd_data,
-+ struct fb_info *info);
-+int mxc_spdc_fb_wait_update_complete(
-+ struct mxcfb_update_marker_data *marker_data,
-+ struct fb_info *info);
-+int mxc_spdc_fb_set_pwrdown_delay(u32 pwrdown_delay,
-+ struct fb_info *info);
-+int mxc_spdc_get_pwrdown_delay(struct fb_info *info);
-+int mxc_spdc_fb_set_upd_scheme(u32 upd_scheme, struct fb_info *info);
-+#endif
-diff --git a/include/linux/mxcfb_epdc_kernel.h b/include/linux/mxcfb_epdc_kernel.h
-deleted file mode 100644
-index 06fea6f..0000000
---- a/include/linux/mxcfb_epdc_kernel.h
-+++ /dev/null
-@@ -1,49 +0,0 @@
--/*
-- * Copyright (C) 2010-2012 Freescale Semiconductor, Inc. All Rights Reserved.
-- *
-- * This program is free software; you can redistribute it and/or modify
-- * it under the terms of the GNU General Public License as published by
-- * the Free Software Foundation; either version 2 of the License, or
-- * (at your option) any later version.
-- *
-- * This program is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- * GNU General Public License for more details.
-- *
-- * You should have received a copy of the GNU General Public License
-- * along with this program; if not, write to the Free Software
-- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- *
-- */
--#ifndef _MXCFB_EPDC_KERNEL
--#define _MXCFB_EPDC_KERNEL
--
--void mxc_epdc_fb_set_waveform_modes(struct mxcfb_waveform_modes *modes,
-- struct fb_info *info);
--int mxc_epdc_fb_set_temperature(int temperature, struct fb_info *info);
--int mxc_epdc_fb_set_auto_update(u32 auto_mode, struct fb_info *info);
--int mxc_epdc_fb_send_update(struct mxcfb_update_data *upd_data,
-- struct fb_info *info);
--int mxc_epdc_fb_wait_update_complete(
-- struct mxcfb_update_marker_data *marker_data,
-- struct fb_info *info);
--int mxc_epdc_fb_set_pwrdown_delay(u32 pwrdown_delay,
-- struct fb_info *info);
--int mxc_epdc_get_pwrdown_delay(struct fb_info *info);
--int mxc_epdc_fb_set_upd_scheme(u32 upd_scheme, struct fb_info *info);
--
--void mxc_spdc_fb_set_waveform_modes(struct mxcfb_waveform_modes *modes,
-- struct fb_info *info);
--int mxc_spdc_fb_set_temperature(int temperature, struct fb_info *info);
--int mxc_spdc_fb_set_auto_update(u32 auto_mode, struct fb_info *info);
--int mxc_spdc_fb_send_update(struct mxcfb_update_data *upd_data,
-- struct fb_info *info);
--int mxc_spdc_fb_wait_update_complete(
-- struct mxcfb_update_marker_data *marker_data,
-- struct fb_info *info);
--int mxc_spdc_fb_set_pwrdown_delay(u32 pwrdown_delay,
-- struct fb_info *info);
--int mxc_spdc_get_pwrdown_delay(struct fb_info *info);
--int mxc_spdc_fb_set_upd_scheme(u32 upd_scheme, struct fb_info *info);
--#endif
---
-1.8.4.rc3
-
diff --git a/recipes-kernel/linux/linux-congatec_3.0.35.bb b/recipes-kernel/linux/linux-congatec_3.0.35.bb
deleted file mode 100644
index 428945f..0000000
--- a/recipes-kernel/linux/linux-congatec_3.0.35.bb
+++ /dev/null
@@ -1,26 +0,0 @@
-# Copyright (C) 2011-2013 Freescale Semiconductor
-# Copyright (C) 2012-2014 O.S. Systems Software LTDA.
-# Released under the MIT license (see COPYING.MIT for the terms)
-
-SUMMARY = "Linux Kernel based on Freescale Linux kernel to add support for Congatec boards"
-include recipes-kernel/linux/linux-imx.inc
-
-# Revision of 4.1.0 branch
-SRCREV = "bdde708ebfde4a8c1d3829578d3f6481a343533a"
-LOCALVERSION = "-4.1.0+yocto"
-SRCBRANCH = "imx_3.0.35_4.1.0"
-
-# Patches need for Yocto and not applied by Freescale when doing 4.1.0 branch
-SRC_URI += "file://drm-vivante-Add-00-sufix-in-returned-bus-Id.patch \
- file://epdc-Rename-mxcfb_epdc_kernel.h-to-mxc_epdc.h.patch \
- file://0001-perf-tools-Fix-getrusage-related-build-failure-on-gl.patch \
- file://0002-ARM-7668-1-fix-memset-related-crashes-caused-by-rece.patch \
- file://0003-ARM-7670-1-fix-the-memset-fix.patch \
- file://0004-ENGR00271136-Fix-build-break-when-CONFIG_CLK_DEBUG-i.patch \
- file://0005-ENGR00271359-Add-Multi-touch-support.patch \
- file://0006-Add-support-for-DVI-monitors.patch \
- file://0001-Add-linux-support-for-congatec-evaluation-board-qmx6q.patch \
- file://ENGR00278350-gpu-viante-4.6.9p13-kernel-part-integra.patch \
-"
-
-COMPATIBLE_MACHINE = "(cgtqmx6)"
--
1.9.1
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