[meta-freescale] i.MX6 - LDO Bypass anatop regulator in Linux 3.10.17_1.0.0-GA release

[Fabio Estevam]

On Wed, Aug 20, 2014 at 12:41 PM, ansaris <ansaris at iwavesystems.com> wrote:
> Dear sir/madam,
>
> We are using imx6Q sabresd platform for our development with Linux
> 3.10.17_1.0.0-GA BSP.
>
> http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/?h=imx_3.0.35_4.1.0&id=868d21a7fce9dc90808837e06b0d5e71e38b3b1b
> In above link shows that, the anatop "reg_pu" value is set to 0x1F which
> is linux-3.0.35 kernel.
>
>     @@ -81,6 +101,21 @@ void mx6_cpu_regulator_init(void)
>     regulator_set_voltage(cpu_regulator,
>     cpu_op_tbl[0].cpu_voltage,
>     cpu_op_tbl[0].cpu_voltage);
>     + if (enable_ldo_mode == LDO_MODE_BYPASSED) {
>     + /*digital bypass VDDPU/VDDSOC/VDDARM*/
>     + reg = __raw_readl(ANADIG_REG_CORE);
>     + reg &= ~BM_ANADIG_REG_CORE_REG0_TRG;
>     + reg |= BF_ANADIG_REG_CORE_REG0_TRG(0x1f);
>     + reg &= ~BM_ANADIG_REG_CORE_REG1_TRG;
>     + reg |= BF_ANADIG_REG_CORE_REG1_TRG(0x1f);
>     + reg &= ~BM_ANADIG_REG_CORE_REG2_TRG;
>     + reg |= BF_ANADIG_REG_CORE_REG2_TRG(0x1f);
>     + __raw_writel(reg, ANADIG_REG_CORE);
>     + /* Mask the ANATOP brown out interrupt in the GPC. */
>     + reg = __raw_readl(gpc_base + 0x14);
>     + reg |= 0x80000000;
>     + __raw_writel(reg, gpc_base + 0x14);
>     + }
>     clk_set_rate(cpu_clk, cpu_op_tbl[0].cpu_rate);
>

So this is a kernel code...

> But with reference of Linux 3.10.17_1.0.0-GA BSP, During the LDO bypass
> the "reg_pu" value is not set to 0x1F as mentioned below. Please clarify.
> file:u-boot-imx/arch/arm/cpu/armv7/mx6/soc.c
> void set_anatop_bypass(void)
> {
> struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
> u32 reg = readl(&anatop->reg_core);
> /* bypass VDDARM/VDDSOC */
> reg = reg | (0x1F << 18) | 0x1F;<-- PMU_REG_CORE's reg_arm & reg_soc
> values are set to 0x1F
> writel(reg, &anatop->reg_core);

,but this is a U-boot code.

In U-boot VPU regulator is disabled.