[meta-freescale] [PATCH] arm/mach-mx6: fix pll4 set_rate callback

Otavio Salvador otavio at ossystems.com.br
Wed May 29 07:41:06 PDT 2013

Hello Alexander,

On Wed, May 29, 2013 at 9:23 AM, Alexander Smirnov <
alex.bluesman.smirnov at gmail.com> wrote:

> There is single method to set clock-rate for both audio and video pll-s
> in i.MX6q clock system implementation. That's possible due to they have
> similar set of registers with a different bases. But there is also one
> common register: CCM_ANALOG_MISC2, which contains post-dividers.
> In current implementation, independently of whether audio or video clock
> is going to be set, the mask 0xc0000000 is applied to MISC2 register.
> This means, that if the audio clock rate is changed, the video clock
> post-dividers possibly will be corrupted.
> This patch fixes the issue described above.
> Signed-off-by: Alexander Smirnov <alex.bluesman.smirnov at gmail.com>

I am adding Fabio and Mahesh in Cc so they can take a look in this patch.


Otavio Salvador                             O.S. Systems
http://www.ossystems.com.br        http://projetos.ossystems.com.br
Mobile: +55 (53) 9981-7854            Mobile: +1 (347) 903-9750
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