[meta-freescale] [meta-fsl-arm][PATCH] Added support for i.MX6 series Nitrogen6w board Signed-off-by: Pushpalatha <pushpalatha.sg at mistralsolutions.com>
Pushpalatha
pushpalatha.sg at mistralsolutions.com
Mon Dec 17 04:09:37 PST 2012
---
conf/machine/imx6qnitrogen6w.conf | 18 +
.../support_nitrogen6x_config.patch | 27324 +++++++++++++++++++
recipes-bsp/u-boot/u-boot-fslc_2012.10.bb | 2 +
.../linux-imx-3.0.35/imx6qnitrogen6w/defconfig | 3020 ++
.../support_for_nitrogen6_configuration.patch | 11469 ++++++++
recipes-kernel/linux/linux-imx_3.0.35.bb | 3 +
6 files changed, 41836 insertions(+)
create mode 100644 conf/machine/imx6qnitrogen6w.conf
create mode 100644 recipes-bsp/u-boot/u-boot-fslc-v2012.10/imx6qnitrogen6w/support_nitrogen6x_config.patch
create mode 100644 recipes-kernel/linux/linux-imx-3.0.35/imx6qnitrogen6w/defconfig
create mode 100644 recipes-kernel/linux/linux-imx-3.0.35/imx6qnitrogen6w/support_for_nitrogen6_configuration.patch
diff --git a/conf/machine/imx6qnitrogen6w.conf b/conf/machine/imx6qnitrogen6w.conf
new file mode 100644
index 0000000..474ab26
--- /dev/null
+++ b/conf/machine/imx6qnitrogen6w.conf
@@ -0,0 +1,18 @@
+#@TYPE: Machine
+#@NAME: i.MX6Q Nitrogen6w
+#@DESCRIPTION: Machine configuration for Freescale i.MX6Q Nitrogen6W
+
+include conf/machine/include/imx-base.inc
+include conf/machine/include/tune-cortexa9.inc
+
+SOC_FAMILY = "mx6q:mx6"
+
+KERNEL_DEVICETREE = "${S}/arch/arm/boot/dts/imx6q-nitrogen6w.dts"
+
+UBOOT_MACHINE = "nitrogen6x_config"
+
+SERIAL_CONSOLE = "115200 ttymxc1"
+
+MACHINE_FEATURES += " pci wifi bluetooth"
+
+
diff --git a/recipes-bsp/u-boot/u-boot-fslc-v2012.10/imx6qnitrogen6w/support_nitrogen6x_config.patch b/recipes-bsp/u-boot/u-boot-fslc-v2012.10/imx6qnitrogen6w/support_nitrogen6x_config.patch
new file mode 100644
index 0000000..fa872ee
--- /dev/null
+++ b/recipes-bsp/u-boot/u-boot-fslc-v2012.10/imx6qnitrogen6w/support_nitrogen6x_config.patch
@@ -0,0 +1,27324 @@
+diff --git a/MAINTAINERS b/MAINTAINERS
+index c57b8fd..bf353aa 100644
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -78,6 +78,10 @@ Holger Brunck <holger.brunck at keymile.com>
+ tuge1 MPC8321
+ tuxx1 MPC8321
+
++Cyril Chemparathy <cyril at ti.com>
++
++ tnetv107x_evm tnetv107x
++
+ Conn Clark <clark at esteem.com>
+
+ ESTEEM192E MPC8xx
+@@ -251,10 +255,6 @@ Klaus Heydeck <heydeck at kieback-peter.de>
+ KUP4K MPC855
+ KUP4X MPC859
+
+-Gabriel Huau <contact at huau-gabriel.fr>
+-
+- mini2440 s3c2440
+-
+ Gary Jennejohn <garyj at denx.de>
+
+ quad100hd PPC405EP
+@@ -363,10 +363,6 @@ Frank Panno <fpanno at delphintech.com>
+
+ ep8260 MPC8260
+
+-Chan-Taek Park <c-park at ti.com>
+-
+- tnetv107x_evm tnetv107x
+-
+ Denis Peter <d.peter at mpl.ch>
+
+ MIP405 PPC4xx
+@@ -401,6 +397,8 @@ Stefan Roese <sr at denx.de>
+
+ uc100 MPC857
+
++ TQM85xx MPC8540/8541/8555/8560
++
+ acadia PPC405EZ
+ alpr PPC440GX
+ bamboo PPC440EP
+@@ -731,7 +729,7 @@ Chander Kashyap <k.chander at samsung.com>
+ SMDKV310 ARM ARMV7 (EXYNOS4210 SoC)
+ SMDK5250 ARM ARMV7 (EXYNOS5250 SoC)
+
+-Lukasz Majewski <l.majewski at samsung.com>
++Heungjun Kim <riverful.kim at samsung.com>
+
+ trats ARM ARMV7 (EXYNOS4210 SoC)
+
+@@ -781,11 +779,6 @@ Nagendra T S <nagendra at mistralsolutions.com>
+
+ am3517_crane ARM ARMV7 (AM35x SoC)
+
+-Dinh Nguyen <dinguyen at altera.com>
+-Chin Liang See <clsee at altera.com>
+-
+- socfpga socfpga_cyclone5
+-
+ Sandeep Paulraj <s-paulraj at ti.com>
+
+ davinci_dm355evm ARM926EJS
+@@ -808,7 +801,6 @@ Veli-Pekka Peltola <veli-pekka.peltola at bluegiga.com>
+ Luka Perkov <uboot at lukaperkov.net>
+
+ ib62x0 ARM926EJS
+- iconnect ARM926EJS
+
+ Dave Peverley <dpeverley at mpc-data.co.uk>
+
+@@ -862,8 +854,6 @@ John Rigby <jcrigby at gmail.com>
+
+ Stefan Roese <sr at denx.de>
+
+- x600 ARM926EJS (spear600 Soc)
+-
+ pdnb3 xscale/ixp
+ scpu xscale/ixp
+
+@@ -902,10 +892,6 @@ Matt Sealey <matt at genesi-usa.com>
+ Bo Shen <voice.shen at atmel.com>
+ at91sam9x5ek ARM926EJS (AT91SAM9G15,G25,G35,X25,X35 SoC)
+
+-Michal Simek <monstr at monstr.eu>
+-
+- zynq ARM ARMV7 (Zynq SoC)
+-
+ Nick Thompson <nick.thompson at gefanuc.com>
+
+ da830evm ARM926EJS (DA830/OMAP-L137)
+@@ -1006,15 +992,6 @@ Zhong Hongbo <bocui107 at gmail.com>
+
+ SMDK6400 ARM1176 (S3C6400 SoC)
+
+-Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj at renesas.com>
+-Tetsuyuki Kobayashi <koba at kmckk.co.jp>
+-
+- kzm9g SH73A0 (RMOBILE SoC)
+-
+-Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj at renesas.com>
+-
+- armadillo-800eva R8A7740 (RMOBILE SoC)
+-
+ -------------------------------------------------------------------------
+
+ Unknown / orphaned boards:
+diff --git a/Makefile b/Makefile
+index 09456e0..a40d4cc 100644
+--- a/Makefile
++++ b/Makefile
+@@ -24,7 +24,7 @@
+ VERSION = 2012
+ PATCHLEVEL = 10
+ SUBLEVEL =
+-EXTRAVERSION =
++EXTRAVERSION = -rc1
+ ifneq "$(SUBLEVEL)" ""
+ U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
+ else
+diff --git a/README b/README
+index dd250a0..af76b0c 100644
+--- a/README
++++ b/README
+@@ -704,8 +704,6 @@ The following options need to be configured:
+ - Boot Delay: CONFIG_BOOTDELAY - in seconds
+ Delay before automatically booting the default image;
+ set to -1 to disable autoboot.
+- set to -2 to autoboot with no delay and not check for abort
+- (even when CONFIG_ZERO_BOOTDELAY_CHECK is defined).
+
+ See doc/README.autoboot for these options that
+ work with CONFIG_BOOTDELAY. None are required.
+@@ -816,7 +814,6 @@ The following options need to be configured:
+ CONFIG_CMD_IMLS List all found images
+ CONFIG_CMD_IMMAP * IMMR dump support
+ CONFIG_CMD_IMPORTENV * import an environment
+- CONFIG_CMD_INI * import data from an ini file into the env
+ CONFIG_CMD_IRQ * irqinfo
+ CONFIG_CMD_ITEST Integer/string test of 2 values
+ CONFIG_CMD_JFFS2 * JFFS2 Support
+@@ -858,8 +855,7 @@ The following options need to be configured:
+ CONFIG_CMD_SPI * SPI serial bus support
+ CONFIG_CMD_TFTPSRV * TFTP transfer in server mode
+ CONFIG_CMD_TFTPPUT * TFTP put command (upload)
+- CONFIG_CMD_TIME * run command and report execution time (ARM specific)
+- CONFIG_CMD_TIMER * access to the system tick timer
++ CONFIG_CMD_TIME * run command and report execution time
+ CONFIG_CMD_USB * USB support
+ CONFIG_CMD_CDP * Cisco Discover Protocol support
+ CONFIG_CMD_MFSL * Microblaze FSL support
+@@ -4692,10 +4688,7 @@ Over time, many people have reported problems when trying to use the
+ consider minicom to be broken, and recommend not to use it. Under
+ Unix, I recommend to use C-Kermit for general purpose use (and
+ especially for kermit binary protocol download ("loadb" command), and
+-use "cu" for S-Record download ("loads" command). See
+-http://www.denx.de/wiki/view/DULG/SystemSetup#Section_4.3.
+-for help with kermit.
+-
++use "cu" for S-Record download ("loads" command).
+
+ Nevertheless, if you absolutely want to use it try adding this
+ configuration to your "File transfer protocols" section:
+diff --git a/arch/arm/config.mk b/arch/arm/config.mk
+index 24b9d7c..3f4453a 100644
+--- a/arch/arm/config.mk
++++ b/arch/arm/config.mk
+@@ -87,21 +87,3 @@ endif
+ ifndef CONFIG_NAND_SPL
+ LDFLAGS_u-boot += -pie
+ endif
+-
+-#
+-# FIXME: binutils versions < 2.22 have a bug in the assembler where
+-# branches to weak symbols can be incorrectly optimized in thumb mode
+-# to a short branch (b.n instruction) that won't reach when the symbol
+-# gets preempted
+-#
+-# http://sourceware.org/bugzilla/show_bug.cgi?id=12532
+-#
+-ifeq ($(CONFIG_SYS_THUMB_BUILD),y)
+-ifeq ($(GAS_BUG_12532),)
+-export GAS_BUG_12532:=$(shell if [ $(call binutils-version) -lt 0222 ] ; \
+- then echo y; else echo n; fi)
+-endif
+-ifeq ($(GAS_BUG_12532),y)
+-PLATFORM_RELFLAGS += -fno-optimize-sibling-calls
+-endif
+-endif
+diff --git a/arch/arm/cpu/arm1136/mx35/asm-offsets.c b/arch/arm/cpu/arm1136/mx35/asm-offsets.c
+index d2678e2..26e14da 100644
+--- a/arch/arm/cpu/arm1136/mx35/asm-offsets.c
++++ b/arch/arm/cpu/arm1136/mx35/asm-offsets.c
+@@ -22,7 +22,6 @@
+
+ int main(void)
+ {
+-
+ /* Round up to make sure size gives nice stack alignment */
+ DEFINE(CLKCTL_CCMR, offsetof(struct ccm_regs, ccmr));
+ DEFINE(CLKCTL_PDR0, offsetof(struct ccm_regs, pdr0));
+@@ -38,6 +37,38 @@ int main(void)
+ DEFINE(CLKCTL_CGR0, offsetof(struct ccm_regs, cgr0));
+ DEFINE(CLKCTL_CGR1, offsetof(struct ccm_regs, cgr1));
+ DEFINE(CLKCTL_CGR2, offsetof(struct ccm_regs, cgr2));
++ DEFINE(CLKCTL_CGR3, offsetof(struct ccm_regs, cgr3));
++
++ /* Multi-Layer AHB Crossbar Switch */
++ DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0));
++ DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0));
++ DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1));
++ DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1));
++ DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2));
++ DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2));
++ DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3));
++ DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3));
++ DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4));
++ DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4));
++ DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0));
++ DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1));
++ DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2));
++ DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3));
++ DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4));
++ DEFINE(MAX_MGPCR5, offsetof(struct max_regs, mgpcr5));
++
++ /* AHB <-> IP-Bus Interface */
++ DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7));
++ DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15));
++ DEFINE(AIPS_PACR_0_7, offsetof(struct aips_regs, pacr_0_7));
++ DEFINE(AIPS_PACR_8_15, offsetof(struct aips_regs, pacr_8_15));
++ DEFINE(AIPS_PACR_16_23, offsetof(struct aips_regs, pacr_16_23));
++ DEFINE(AIPS_PACR_24_31, offsetof(struct aips_regs, pacr_24_31));
++ DEFINE(AIPS_OPACR_0_7, offsetof(struct aips_regs, opacr_0_7));
++ DEFINE(AIPS_OPACR_8_15, offsetof(struct aips_regs, opacr_8_15));
++ DEFINE(AIPS_OPACR_16_23, offsetof(struct aips_regs, opacr_16_23));
++ DEFINE(AIPS_OPACR_24_31, offsetof(struct aips_regs, opacr_24_31));
++ DEFINE(AIPS_OPACR_32_39, offsetof(struct aips_regs, opacr_32_39));
+
+ return 0;
+ }
+diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S
+index 3752af9..2483c63 100644
+--- a/arch/arm/cpu/arm1136/start.S
++++ b/arch/arm/cpu/arm1136/start.S
+@@ -190,7 +190,6 @@ stack_setup:
+
+ adr r0, _start
+ cmp r0, r6
+- moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
+ beq clear_bss /* skip relocation */
+ mov r1, r6 /* r1 <- scratch for copy_loop */
+ ldr r3, _bss_start_ofs
+diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S
+index 667a0e0..d613641 100644
+--- a/arch/arm/cpu/arm1176/start.S
++++ b/arch/arm/cpu/arm1176/start.S
+@@ -252,7 +252,6 @@ stack_setup:
+
+ adr r0, _start
+ cmp r0, r6
+- moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
+ beq clear_bss /* skip relocation */
+ mov r1, r6 /* r1 <- scratch for copy_loop */
+ ldr r3, _bss_start_ofs
+diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S
+index 14c9156..9b8604e 100644
+--- a/arch/arm/cpu/arm920t/start.S
++++ b/arch/arm/cpu/arm920t/start.S
+@@ -210,7 +210,6 @@ stack_setup:
+
+ adr r0, _start
+ cmp r0, r6
+- moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
+ beq clear_bss /* skip relocation */
+ mov r1, r6 /* r1 <- scratch for copy_loop */
+ ldr r3, _bss_start_ofs
+diff --git a/arch/arm/cpu/arm925t/start.S b/arch/arm/cpu/arm925t/start.S
+index 3a483f6..1a54416 100644
+--- a/arch/arm/cpu/arm925t/start.S
++++ b/arch/arm/cpu/arm925t/start.S
+@@ -204,7 +204,6 @@ stack_setup:
+
+ adr r0, _start
+ cmp r0, r6
+- moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
+ beq clear_bss /* skip relocation */
+ mov r1, r6 /* r1 <- scratch for copy_loop */
+ ldr r3, _bss_start_ofs
+diff --git a/arch/arm/cpu/arm926ejs/kirkwood/dram.c b/arch/arm/cpu/arm926ejs/kirkwood/dram.c
+index 807894f..181b3e7 100644
+--- a/arch/arm/cpu/arm926ejs/kirkwood/dram.c
++++ b/arch/arm/cpu/arm926ejs/kirkwood/dram.c
+@@ -30,84 +30,38 @@
+
+ DECLARE_GLOBAL_DATA_PTR;
+
+-struct kw_sdram_bank {
+- u32 win_bar;
+- u32 win_sz;
+-};
+-
+-struct kw_sdram_addr_dec {
+- struct kw_sdram_bank sdram_bank[4];
+-};
+-
+-#define KW_REG_CPUCS_WIN_ENABLE (1 << 0)
+-#define KW_REG_CPUCS_WIN_WR_PROTECT (1 << 1)
+-#define KW_REG_CPUCS_WIN_WIN0_CS(x) (((x) & 0x3) << 2)
+-#define KW_REG_CPUCS_WIN_SIZE(x) (((x) & 0xff) << 24)
+-
++#define KW_REG_CPUCS_WIN_BAR(x) (KW_REGISTER(0x1500) + (x * 0x08))
++#define KW_REG_CPUCS_WIN_SZ(x) (KW_REGISTER(0x1504) + (x * 0x08))
+ /*
+ * kw_sdram_bar - reads SDRAM Base Address Register
+ */
+ u32 kw_sdram_bar(enum memory_bank bank)
+ {
+- struct kw_sdram_addr_dec *base =
+- (struct kw_sdram_addr_dec *)KW_REGISTER(0x1500);
+ u32 result = 0;
+- u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz);
++ u32 enable = 0x01 & readl(KW_REG_CPUCS_WIN_SZ(bank));
+
+ if ((!enable) || (bank > BANK3))
+ return 0;
+
+- result = readl(&base->sdram_bank[bank].win_bar);
++ result = readl(KW_REG_CPUCS_WIN_BAR(bank));
+ return result;
+ }
+
+ /*
+- * kw_sdram_bs_set - writes SDRAM Bank size
+- */
+-static void kw_sdram_bs_set(enum memory_bank bank, u32 size)
+-{
+- struct kw_sdram_addr_dec *base =
+- (struct kw_sdram_addr_dec *)KW_REGISTER(0x1500);
+- /* Read current register value */
+- u32 reg = readl(&base->sdram_bank[bank].win_sz);
+-
+- /* Clear window size */
+- reg &= ~KW_REG_CPUCS_WIN_SIZE(0xFF);
+-
+- /* Set new window size */
+- reg |= KW_REG_CPUCS_WIN_SIZE((size - 1) >> 24);
+-
+- writel(reg, &base->sdram_bank[bank].win_sz);
+-}
+-
+-/*
+ * kw_sdram_bs - reads SDRAM Bank size
+ */
+ u32 kw_sdram_bs(enum memory_bank bank)
+ {
+- struct kw_sdram_addr_dec *base =
+- (struct kw_sdram_addr_dec *)KW_REGISTER(0x1500);
+ u32 result = 0;
+- u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz);
++ u32 enable = 0x01 & readl(KW_REG_CPUCS_WIN_SZ(bank));
+
+ if ((!enable) || (bank > BANK3))
+ return 0;
+- result = 0xff000000 & readl(&base->sdram_bank[bank].win_sz);
++ result = 0xff000000 & readl(KW_REG_CPUCS_WIN_SZ(bank));
+ result += 0x01000000;
+ return result;
+ }
+
+-void kw_sdram_size_adjust(enum memory_bank bank)
+-{
+- u32 size;
+-
+- /* probe currently equipped RAM size */
+- size = get_ram_size((void *)kw_sdram_bar(bank), kw_sdram_bs(bank));
+-
+- /* adjust SDRAM window size accordingly */
+- kw_sdram_bs_set(bank, size);
+-}
+-
+ #ifndef CONFIG_SYS_BOARD_DRAM_INIT
+ int dram_init(void)
+ {
+diff --git a/arch/arm/cpu/arm926ejs/mx25/generic.c b/arch/arm/cpu/arm926ejs/mx25/generic.c
+index 4f1aad0..b991418 100644
+--- a/arch/arm/cpu/arm926ejs/mx25/generic.c
++++ b/arch/arm/cpu/arm926ejs/mx25/generic.c
+@@ -29,11 +29,10 @@
+ #include <asm/arch/imx-regs.h>
+ #include <asm/arch/imx25-pinmux.h>
+ #include <asm/arch/clock.h>
+-#ifdef CONFIG_MXC_MMC
+-#include <asm/arch/mxcmmc.h>
+-#endif
+
+ #ifdef CONFIG_FSL_ESDHC
++#include <fsl_esdhc.h>
++
+ DECLARE_GLOBAL_DATA_PTR;
+ #endif
+
+@@ -48,7 +47,7 @@ static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
+ {
+ unsigned int mfi = (pll >> CCM_PLL_MFI_SHIFT)
+ & CCM_PLL_MFI_MASK;
+- unsigned int mfn = (pll >> CCM_PLL_MFN_SHIFT)
++ int mfn = (pll >> CCM_PLL_MFN_SHIFT)
+ & CCM_PLL_MFN_MASK;
+ unsigned int mfd = (pll >> CCM_PLL_MFD_SHIFT)
+ & CCM_PLL_MFD_MASK;
+@@ -56,9 +55,12 @@ static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
+ & CCM_PLL_PD_MASK;
+
+ mfi = mfi <= 5 ? 5 : mfi;
++ mfn = mfn >= 512 ? mfn - 1024 : mfn;
++ mfd += 1;
++ pd += 1;
+
+- return lldiv(2 * (u64) f_ref * (mfi * (mfd + 1) + mfn),
+- (mfd + 1) * (pd + 1));
++ return lldiv(2 * (u64) f_ref * (mfi * mfd + mfn),
++ mfd * pd);
+ }
+
+ static ulong imx_get_mpllclk(void)
+@@ -69,7 +71,7 @@ static ulong imx_get_mpllclk(void)
+ return imx_decode_pll(readl(&ccm->mpctl), fref);
+ }
+
+-ulong imx_get_armclk(void)
++static ulong imx_get_armclk(void)
+ {
+ struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
+ ulong cctl = readl(&ccm->cctl);
+@@ -77,15 +79,15 @@ ulong imx_get_armclk(void)
+ ulong div;
+
+ if (cctl & CCM_CCTL_ARM_SRC)
+- fref = lldiv((fref * 3), 4);
++ fref = lldiv((u64) fref * 3, 4);
+
+ div = ((cctl >> CCM_CCTL_ARM_DIV_SHIFT)
+ & CCM_CCTL_ARM_DIV_MASK) + 1;
+
+- return lldiv(fref, div);
++ return fref / div;
+ }
+
+-ulong imx_get_ahbclk(void)
++static ulong imx_get_ahbclk(void)
+ {
+ struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
+ ulong cctl = readl(&ccm->cctl);
+@@ -95,10 +97,15 @@ ulong imx_get_ahbclk(void)
+ div = ((cctl >> CCM_CCTL_AHB_DIV_SHIFT)
+ & CCM_CCTL_AHB_DIV_MASK) + 1;
+
+- return lldiv(fref, div);
++ return fref / div;
++}
++
++static ulong imx_get_ipgclk(void)
++{
++ return imx_get_ahbclk() / 2;
+ }
+
+-ulong imx_get_perclk(int clk)
++static ulong imx_get_perclk(int clk)
+ {
+ struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
+ ulong fref = imx_get_ahbclk();
+@@ -107,7 +114,7 @@ ulong imx_get_perclk(int clk)
+ div = readl(&ccm->pcdr[CCM_PERCLK_REG(clk)]);
+ div = ((div >> CCM_PERCLK_SHIFT(clk)) & CCM_PERCLK_MASK) + 1;
+
+- return lldiv(fref, div);
++ return fref / div;
+ }
+
+ unsigned int mxc_get_clock(enum mxc_clock clk)
+@@ -117,8 +124,12 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
+ switch (clk) {
+ case MXC_ARM_CLK:
+ return imx_get_armclk();
+- case MXC_FEC_CLK:
++ case MXC_AHB_CLK:
+ return imx_get_ahbclk();
++ case MXC_IPG_CLK:
++ case MXC_CSPI_CLK:
++ case MXC_FEC_CLK:
++ return imx_get_ipgclk();
+ default:
+ return imx_get_perclk(clk);
+ }
+@@ -197,9 +208,13 @@ void enable_caches(void)
+ #endif
+ }
+
++#if defined(CONFIG_FEC_MXC)
++/*
++ * Initializes on-chip ethernet controllers.
++ * to override, implement board_eth_init()
++ */
+ int cpu_eth_init(bd_t *bis)
+ {
+-#if defined(CONFIG_FEC_MXC)
+ struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
+ ulong val;
+
+@@ -207,31 +222,31 @@ int cpu_eth_init(bd_t *bis)
+ val |= (1 << 23);
+ writel(val, &ccm->cgr0);
+ return fecmxc_initialize(bis);
+-#else
+- return 0;
+-#endif
+ }
++#endif
+
+ int get_clocks(void)
+ {
+ #ifdef CONFIG_FSL_ESDHC
+- gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
++#if CONFIG_SYS_FSL_ESDHC_ADDR == IMX_MMC_SDHC2_BASE
++ gd->sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
++#else
++ gd->sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
++#endif
+ #endif
+ return 0;
+ }
+
++#ifdef CONFIG_FSL_ESDHC
+ /*
+ * Initializes on-chip MMC controllers.
+ * to override, implement board_mmc_init()
+ */
+ int cpu_mmc_init(bd_t *bis)
+ {
+-#ifdef CONFIG_MXC_MMC
+- return mxc_mmc_init(bis);
+-#else
+- return 0;
+-#endif
++ return fsl_esdhc_mmc_init(bis);
+ }
++#endif
+
+ #ifdef CONFIG_MXC_UART
+ void mx25_uart1_init_pins(void)
+diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S
+index 2188f7e..521d462 100644
+--- a/arch/arm/cpu/arm926ejs/start.S
++++ b/arch/arm/cpu/arm926ejs/start.S
+@@ -236,7 +236,6 @@ stack_setup:
+ adr r0, _start
+ sub r9, r6, r0 /* r9 <- relocation offset */
+ cmp r0, r6
+- moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
+ beq clear_bss /* skip relocation */
+ mov r1, r6 /* r1 <- scratch for copy loop */
+ ldr r3, _bss_start_ofs
+diff --git a/arch/arm/cpu/arm946es/start.S b/arch/arm/cpu/arm946es/start.S
+index 30e2183..b4d1d2d 100644
+--- a/arch/arm/cpu/arm946es/start.S
++++ b/arch/arm/cpu/arm946es/start.S
+@@ -175,7 +175,6 @@ stack_setup:
+
+ adr r0, _start
+ cmp r0, r6
+- moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
+ beq clear_bss /* skip relocation */
+ mov r1, r6 /* r1 <- scratch for copy_loop */
+ ldr r3, _bss_start_ofs
+diff --git a/arch/arm/cpu/arm_intcm/start.S b/arch/arm/cpu/arm_intcm/start.S
+index a133d19..b85e7d4 100644
+--- a/arch/arm/cpu/arm_intcm/start.S
++++ b/arch/arm/cpu/arm_intcm/start.S
+@@ -171,7 +171,6 @@ stack_setup:
+
+ adr r0, _start
+ cmp r0, r6
+- moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
+ beq clear_bss /* skip relocation */
+ mov r1, r6 /* r1 <- scratch for copy_loop */
+ ldr r3, _bss_start_ofs
+diff --git a/arch/arm/cpu/armv7/config.mk b/arch/arm/cpu/armv7/config.mk
+index 560c084..5407cb6 100644
+--- a/arch/arm/cpu/armv7/config.mk
++++ b/arch/arm/cpu/armv7/config.mk
+@@ -26,8 +26,6 @@ PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
+ # supported by more tool-chains
+ PF_CPPFLAGS_ARMV7 := $(call cc-option, -march=armv7-a, -march=armv5)
+ PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_ARMV7)
+-PF_CPPFLAGS_NO_UNALIGNED := $(call cc-option, -mno-unaligned-access,)
+-PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_NO_UNALIGNED)
+
+ # =========================================================================
+ #
+diff --git a/arch/arm/cpu/armv7/highbank/config.mk b/arch/arm/cpu/armv7/highbank/config.mk
+new file mode 100644
+index 0000000..935a147
+--- /dev/null
++++ b/arch/arm/cpu/armv7/highbank/config.mk
+@@ -0,0 +1 @@
++PLATFORM_CPPFLAGS += -march=armv7-a
+diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c
+index 8fa737a..2709860 100644
+--- a/arch/arm/cpu/armv7/mx5/clock.c
++++ b/arch/arm/cpu/armv7/mx5/clock.c
+@@ -36,7 +36,9 @@ enum pll_clocks {
+ PLL1_CLOCK = 0,
+ PLL2_CLOCK,
+ PLL3_CLOCK,
++#ifdef CONFIG_MX53
+ PLL4_CLOCK,
++#endif
+ PLL_CLOCKS,
+ };
+
+@@ -69,7 +71,7 @@ struct fixed_pll_mfd {
+ };
+
+ const struct fixed_pll_mfd fixed_mfd[] = {
+- {CONFIG_SYS_MX5_HCLK, 24 * 16},
++ {MXC_HCLK, 24 * 16},
+ };
+
+ struct pll_param {
+@@ -89,95 +91,85 @@ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
+
+ void set_usboh3_clk(void)
+ {
+- unsigned int reg;
+-
+- reg = readl(&mxc_ccm->cscmr1) &
+- ~MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK;
+- reg |= 1 << MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET;
+- writel(reg, &mxc_ccm->cscmr1);
+-
+- reg = readl(&mxc_ccm->cscdr1);
+- reg &= ~MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK;
+- reg &= ~MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK;
+- reg |= 4 << MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET;
+- reg |= 1 << MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET;
+-
+- writel(reg, &mxc_ccm->cscdr1);
++ clrsetbits_le32(&mxc_ccm->cscmr1,
++ MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK,
++ MXC_CCM_CSCMR1_USBOH3_CLK_SEL(1));
++ clrsetbits_le32(&mxc_ccm->cscdr1,
++ MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK |
++ MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK,
++ MXC_CCM_CSCDR1_USBOH3_CLK_PRED(4) |
++ MXC_CCM_CSCDR1_USBOH3_CLK_PODF(1));
+ }
+
+ void enable_usboh3_clk(unsigned char enable)
+ {
+- unsigned int reg;
++ unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
+
+- reg = readl(&mxc_ccm->CCGR2);
+- if (enable)
+- reg |= 1 << MXC_CCM_CCGR2_CG14_OFFSET;
+- else
+- reg &= ~(1 << MXC_CCM_CCGR2_CG14_OFFSET);
+- writel(reg, &mxc_ccm->CCGR2);
++ clrsetbits_le32(&mxc_ccm->CCGR2,
++ MXC_CCM_CCGR2_USBOH3_60M(MXC_CCM_CCGR_CG_MASK),
++ MXC_CCM_CCGR2_USBOH3_60M(cg));
+ }
+
+ #ifdef CONFIG_I2C_MXC
+-/* i2c_num can be from 0 - 2 */
++/* i2c_num can be from 0, to 1 for i.MX51 and 2 for i.MX53 */
+ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
+ {
+- u32 reg;
+ u32 mask;
+
++#if defined(CONFIG_MX51)
++ if (i2c_num > 1)
++#elif defined(CONFIG_MX53)
+ if (i2c_num > 2)
++#endif
+ return -EINVAL;
+- mask = MXC_CCM_CCGR_CG_MASK << ((i2c_num + 9) << 1);
+- reg = __raw_readl(&mxc_ccm->CCGR1);
++ mask = MXC_CCM_CCGR_CG_MASK <<
++ (MXC_CCM_CCGR1_I2C1_OFFSET + (i2c_num << 1));
+ if (enable)
+- reg |= mask;
++ setbits_le32(&mxc_ccm->CCGR1, mask);
+ else
+- reg &= ~mask;
+- __raw_writel(reg, &mxc_ccm->CCGR1);
++ clrbits_le32(&mxc_ccm->CCGR1, mask);
+ return 0;
+ }
+ #endif
+
+-void set_usb_phy1_clk(void)
++void set_usb_phy_clk(void)
+ {
+- unsigned int reg;
+-
+- reg = readl(&mxc_ccm->cscmr1);
+- reg &= ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL;
+- writel(reg, &mxc_ccm->cscmr1);
++ clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
+ }
+
++#if defined(CONFIG_MX51)
+ void enable_usb_phy1_clk(unsigned char enable)
+ {
+- unsigned int reg;
++ unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
+
+- reg = readl(&mxc_ccm->CCGR4);
+- if (enable)
+- reg |= 1 << MXC_CCM_CCGR4_CG5_OFFSET;
+- else
+- reg &= ~(1 << MXC_CCM_CCGR4_CG5_OFFSET);
+- writel(reg, &mxc_ccm->CCGR4);
++ clrsetbits_le32(&mxc_ccm->CCGR2,
++ MXC_CCM_CCGR2_USB_PHY(MXC_CCM_CCGR_CG_MASK),
++ MXC_CCM_CCGR2_USB_PHY(cg));
+ }
+
+-void set_usb_phy2_clk(void)
++void enable_usb_phy2_clk(unsigned char enable)
+ {
+- unsigned int reg;
++ /* i.MX51 has a single USB PHY clock, so do nothing here. */
++}
++#elif defined(CONFIG_MX53)
++void enable_usb_phy1_clk(unsigned char enable)
++{
++ unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
+
+- reg = readl(&mxc_ccm->cscmr1);
+- reg &= ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL;
+- writel(reg, &mxc_ccm->cscmr1);
++ clrsetbits_le32(&mxc_ccm->CCGR4,
++ MXC_CCM_CCGR4_USB_PHY1(MXC_CCM_CCGR_CG_MASK),
++ MXC_CCM_CCGR4_USB_PHY1(cg));
+ }
+
+ void enable_usb_phy2_clk(unsigned char enable)
+ {
+- unsigned int reg;
++ unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
+
+- reg = readl(&mxc_ccm->CCGR4);
+- if (enable)
+- reg |= 1 << MXC_CCM_CCGR4_CG6_OFFSET;
+- else
+- reg &= ~(1 << MXC_CCM_CCGR4_CG6_OFFSET);
+- writel(reg, &mxc_ccm->CCGR4);
++ clrsetbits_le32(&mxc_ccm->CCGR4,
++ MXC_CCM_CCGR4_USB_PHY2(MXC_CCM_CCGR_CG_MASK),
++ MXC_CCM_CCGR4_USB_PHY2(cg));
+ }
++#endif
+
+ /*
+ * Calculate the frequency of PLLn.
+@@ -191,19 +183,19 @@ static uint32_t decode_pll(struct mxc_pll_reg *pll, uint32_t infreq)
+ ctrl = readl(&pll->ctrl);
+
+ if (ctrl & MXC_DPLLC_CTL_HFSM) {
+- mfn = __raw_readl(&pll->hfs_mfn);
+- mfd = __raw_readl(&pll->hfs_mfd);
+- op = __raw_readl(&pll->hfs_op);
++ mfn = readl(&pll->hfs_mfn);
++ mfd = readl(&pll->hfs_mfd);
++ op = readl(&pll->hfs_op);
+ } else {
+- mfn = __raw_readl(&pll->mfn);
+- mfd = __raw_readl(&pll->mfd);
+- op = __raw_readl(&pll->op);
++ mfn = readl(&pll->mfn);
++ mfd = readl(&pll->mfd);
++ op = readl(&pll->op);
+ }
+
+ mfd &= MXC_DPLLC_MFD_MFD_MASK;
+ mfn &= MXC_DPLLC_MFN_MFN_MASK;
+ pdf = op & MXC_DPLLC_OP_PDF_MASK;
+- mfi = (op & MXC_DPLLC_OP_MFI_MASK) >> MXC_DPLLC_OP_MFI_OFFSET;
++ mfi = MXC_DPLLC_OP_MFI_RD(op);
+
+ /* 21.2.3 */
+ if (mfi < 5)
+@@ -233,6 +225,44 @@ static uint32_t decode_pll(struct mxc_pll_reg *pll, uint32_t infreq)
+ return ret;
+ }
+
++#ifdef CONFIG_MX51
++/*
++ * This function returns the Frequency Pre-Multiplier clock.
++ */
++static u32 get_fpm(void)
++{
++ u32 mult;
++ u32 ccr = readl(&mxc_ccm->ccr);
++
++ if (ccr & MXC_CCM_CCR_FPM_MULT)
++ mult = 1024;
++ else
++ mult = 512;
++
++ return MXC_CLK32 * mult;
++}
++#endif
++
++/*
++ * This function returns the low power audio clock.
++ */
++static u32 get_lp_apm(void)
++{
++ u32 ret_val = 0;
++ u32 ccsr = readl(&mxc_ccm->ccsr);
++
++ if (ccsr & MXC_CCM_CCSR_LP_APM)
++#if defined(CONFIG_MX51)
++ ret_val = get_fpm();
++#elif defined(CONFIG_MX53)
++ ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);
++#endif
++ else
++ ret_val = MXC_HCLK;
++
++ return ret_val;
++}
++
+ /*
+ * Get mcu main rate
+ */
+@@ -240,9 +270,8 @@ u32 get_mcu_main_clk(void)
+ {
+ u32 reg, freq;
+
+- reg = (__raw_readl(&mxc_ccm->cacrr) & MXC_CCM_CACRR_ARM_PODF_MASK) >>
+- MXC_CCM_CACRR_ARM_PODF_OFFSET;
+- freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
++ reg = MXC_CCM_CACRR_ARM_PODF_RD(readl(&mxc_ccm->cacrr));
++ freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
+ return freq / (reg + 1);
+ }
+
+@@ -253,16 +282,17 @@ u32 get_periph_clk(void)
+ {
+ u32 reg;
+
+- reg = __raw_readl(&mxc_ccm->cbcdr);
++ reg = readl(&mxc_ccm->cbcdr);
+ if (!(reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL))
+- return decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_SYS_MX5_HCLK);
+- reg = __raw_readl(&mxc_ccm->cbcmr);
+- switch ((reg & MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >>
+- MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
++ return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
++ reg = readl(&mxc_ccm->cbcmr);
++ switch (MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(reg)) {
+ case 0:
+- return decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
++ return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
+ case 1:
+- return decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK);
++ return decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
++ case 2:
++ return get_lp_apm();
+ default:
+ return 0;
+ }
+@@ -278,9 +308,8 @@ static u32 get_ipg_clk(void)
+
+ freq = get_ahb_clk();
+
+- reg = __raw_readl(&mxc_ccm->cbcdr);
+- div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
+- MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1;
++ reg = readl(&mxc_ccm->cbcdr);
++ div = MXC_CCM_CBCDR_IPG_PODF_RD(reg) + 1;
+
+ return freq / div;
+ }
+@@ -290,140 +319,140 @@ static u32 get_ipg_clk(void)
+ */
+ static u32 get_ipg_per_clk(void)
+ {
+- u32 pred1, pred2, podf;
++ u32 freq, pred1, pred2, podf;
+
+- if (__raw_readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL)
++ if (readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL)
+ return get_ipg_clk();
+- /* Fixme: not handle what about lpm*/
+- podf = __raw_readl(&mxc_ccm->cbcdr);
+- pred1 = (podf & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >>
+- MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET;
+- pred2 = (podf & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >>
+- MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET;
+- podf = (podf & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >>
+- MXC_CCM_CBCDR_PERCLK_PODF_OFFSET;
+
+- return get_periph_clk() / ((pred1 + 1) * (pred2 + 1) * (podf + 1));
++ if (readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL)
++ freq = get_lp_apm();
++ else
++ freq = get_periph_clk();
++ podf = readl(&mxc_ccm->cbcdr);
++ pred1 = MXC_CCM_CBCDR_PERCLK_PRED1_RD(podf);
++ pred2 = MXC_CCM_CBCDR_PERCLK_PRED2_RD(podf);
++ podf = MXC_CCM_CBCDR_PERCLK_PODF_RD(podf);
++ return freq / ((pred1 + 1) * (pred2 + 1) * (podf + 1));
+ }
+
+-/*
+- * Get the rate of uart clk.
+- */
+-static u32 get_uart_clk(void)
++/* Get the output clock rate of a standard PLL MUX for peripherals. */
++static u32 get_standard_pll_sel_clk(u32 clk_sel)
+ {
+- unsigned int freq, reg, pred, podf;
++ u32 freq;
+
+- reg = __raw_readl(&mxc_ccm->cscmr1);
+- switch ((reg & MXC_CCM_CSCMR1_UART_CLK_SEL_MASK) >>
+- MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET) {
+- case 0x0:
+- freq = decode_pll(mxc_plls[PLL1_CLOCK],
+- CONFIG_SYS_MX5_HCLK);
++ switch (clk_sel & 0x3) {
++ case 0:
++ freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
++ break;
++ case 1:
++ freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
+ break;
+- case 0x1:
+- freq = decode_pll(mxc_plls[PLL2_CLOCK],
+- CONFIG_SYS_MX5_HCLK);
++ case 2:
++ freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
+ break;
+- case 0x2:
+- freq = decode_pll(mxc_plls[PLL3_CLOCK],
+- CONFIG_SYS_MX5_HCLK);
++ case 3:
++ freq = get_lp_apm();
+ break;
+- default:
+- return 66500000;
+ }
+
+- reg = __raw_readl(&mxc_ccm->cscdr1);
++ return freq;
++}
++
++/*
++ * Get the rate of uart clk.
++ */
++static u32 get_uart_clk(void)
++{
++ unsigned int clk_sel, freq, reg, pred, podf;
+
+- pred = (reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >>
+- MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET;
++ reg = readl(&mxc_ccm->cscmr1);
++ clk_sel = MXC_CCM_CSCMR1_UART_CLK_SEL_RD(reg);
++ freq = get_standard_pll_sel_clk(clk_sel);
+
+- podf = (reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
+- MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
++ reg = readl(&mxc_ccm->cscdr1);
++ pred = MXC_CCM_CSCDR1_UART_CLK_PRED_RD(reg);
++ podf = MXC_CCM_CSCDR1_UART_CLK_PODF_RD(reg);
+ freq /= (pred + 1) * (podf + 1);
+
+ return freq;
+ }
+
+ /*
+- * This function returns the low power audio clock.
++ * get cspi clock rate.
+ */
+-static u32 get_lp_apm(void)
++static u32 imx_get_cspiclk(void)
+ {
+- u32 ret_val = 0;
+- u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
+-
+- if (((ccsr >> 9) & 1) == 0)
+- ret_val = CONFIG_SYS_MX5_HCLK;
+- else
+- ret_val = ((32768 * 1024));
++ u32 ret_val = 0, pdf, pre_pdf, clk_sel, freq;
++ u32 cscmr1 = readl(&mxc_ccm->cscmr1);
++ u32 cscdr2 = readl(&mxc_ccm->cscdr2);
+
++ pre_pdf = MXC_CCM_CSCDR2_CSPI_CLK_PRED_RD(cscdr2);
++ pdf = MXC_CCM_CSCDR2_CSPI_CLK_PODF_RD(cscdr2);
++ clk_sel = MXC_CCM_CSCMR1_CSPI_CLK_SEL_RD(cscmr1);
++ freq = get_standard_pll_sel_clk(clk_sel);
++ ret_val = freq / ((pre_pdf + 1) * (pdf + 1));
+ return ret_val;
+ }
+
+ /*
+- * get cspi clock rate.
++ * get esdhc clock rate.
+ */
+-static u32 imx_get_cspiclk(void)
++static u32 get_esdhc_clk(u32 port)
+ {
+- u32 ret_val = 0, pdf, pre_pdf, clk_sel;
+- u32 cscmr1 = __raw_readl(&mxc_ccm->cscmr1);
+- u32 cscdr2 = __raw_readl(&mxc_ccm->cscdr2);
++ u32 clk_sel = 0, pred = 0, podf = 0, freq = 0;
++ u32 cscmr1 = readl(&mxc_ccm->cscmr1);
++ u32 cscdr1 = readl(&mxc_ccm->cscdr1);
+
+- pre_pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) \
+- >> MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET;
+- pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) \
+- >> MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET;
+- clk_sel = (cscmr1 & MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK) \
+- >> MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET;
+-
+- switch (clk_sel) {
++ switch (port) {
+ case 0:
+- ret_val = decode_pll(mxc_plls[PLL1_CLOCK],
+- CONFIG_SYS_MX5_HCLK) /
+- ((pre_pdf + 1) * (pdf + 1));
++ clk_sel = MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_RD(cscmr1);
++ pred = MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_RD(cscdr1);
++ podf = MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_RD(cscdr1);
+ break;
+ case 1:
+- ret_val = decode_pll(mxc_plls[PLL2_CLOCK],
+- CONFIG_SYS_MX5_HCLK) /
+- ((pre_pdf + 1) * (pdf + 1));
++ clk_sel = MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_RD(cscmr1);
++ pred = MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_RD(cscdr1);
++ podf = MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_RD(cscdr1);
+ break;
+ case 2:
+- ret_val = decode_pll(mxc_plls[PLL3_CLOCK],
+- CONFIG_SYS_MX5_HCLK) /
+- ((pre_pdf + 1) * (pdf + 1));
+- break;
++ if (cscmr1 & MXC_CCM_CSCMR1_ESDHC3_CLK_SEL)
++ return get_esdhc_clk(1);
++ else
++ return get_esdhc_clk(0);
++ case 3:
++ if (cscmr1 & MXC_CCM_CSCMR1_ESDHC4_CLK_SEL)
++ return get_esdhc_clk(1);
++ else
++ return get_esdhc_clk(0);
+ default:
+- ret_val = get_lp_apm() / ((pre_pdf + 1) * (pdf + 1));
+ break;
+ }
+
+- return ret_val;
++ freq = get_standard_pll_sel_clk(clk_sel) / ((pred + 1) * (podf + 1));
++ return freq;
+ }
+
+ static u32 get_axi_a_clk(void)
+ {
+- u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
+- u32 pdf = (cbcdr & MXC_CCM_CBCDR_AXI_A_PODF_MASK) \
+- >> MXC_CCM_CBCDR_AXI_A_PODF_OFFSET;
++ u32 cbcdr = readl(&mxc_ccm->cbcdr);
++ u32 pdf = MXC_CCM_CBCDR_AXI_A_PODF_RD(cbcdr);
+
+ return get_periph_clk() / (pdf + 1);
+ }
+
+ static u32 get_axi_b_clk(void)
+ {
+- u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
+- u32 pdf = (cbcdr & MXC_CCM_CBCDR_AXI_B_PODF_MASK) \
+- >> MXC_CCM_CBCDR_AXI_B_PODF_OFFSET;
++ u32 cbcdr = readl(&mxc_ccm->cbcdr);
++ u32 pdf = MXC_CCM_CBCDR_AXI_B_PODF_RD(cbcdr);
+
+ return get_periph_clk() / (pdf + 1);
+ }
+
+ static u32 get_emi_slow_clk(void)
+ {
+- u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
++ u32 cbcdr = readl(&mxc_ccm->cbcdr);
+ u32 emi_clk_sel = cbcdr & MXC_CCM_CBCDR_EMI_CLK_SEL;
+- u32 pdf = (cbcdr & MXC_CCM_CBCDR_EMI_PODF_MASK) \
+- >> MXC_CCM_CBCDR_EMI_PODF_OFFSET;
++ u32 pdf = MXC_CCM_CBCDR_EMI_PODF_RD(cbcdr);
+
+ if (emi_clk_sel)
+ return get_ahb_clk() / (pdf + 1);
+@@ -434,16 +463,14 @@ static u32 get_emi_slow_clk(void)
+ static u32 get_ddr_clk(void)
+ {
+ u32 ret_val = 0;
+- u32 cbcmr = __raw_readl(&mxc_ccm->cbcmr);
+- u32 ddr_clk_sel = (cbcmr & MXC_CCM_CBCMR_DDR_CLK_SEL_MASK) \
+- >> MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET;
++ u32 cbcmr = readl(&mxc_ccm->cbcmr);
++ u32 ddr_clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr);
+ #ifdef CONFIG_MX51
+- u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
++ u32 cbcdr = readl(&mxc_ccm->cbcdr);
+ if (cbcdr & MXC_CCM_CBCDR_DDR_HIFREQ_SEL) {
+- u32 ddr_clk_podf = (cbcdr & MXC_CCM_CBCDR_DDR_PODF_MASK) >> \
+- MXC_CCM_CBCDR_DDR_PODF_OFFSET;
++ u32 ddr_clk_podf = MXC_CCM_CBCDR_DDR_PODF_RD(cbcdr);
+
+- ret_val = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
++ ret_val = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
+ ret_val /= ddr_clk_podf + 1;
+
+ return ret_val;
+@@ -488,9 +515,16 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
+ return get_uart_clk();
+ case MXC_CSPI_CLK:
+ return imx_get_cspiclk();
++ case MXC_ESDHC_CLK:
++ return get_esdhc_clk(0);
++ case MXC_ESDHC2_CLK:
++ return get_esdhc_clk(1);
++ case MXC_ESDHC3_CLK:
++ return get_esdhc_clk(2);
++ case MXC_ESDHC4_CLK:
++ return get_esdhc_clk(3);
+ case MXC_FEC_CLK:
+- return decode_pll(mxc_plls[PLL1_CLOCK],
+- CONFIG_SYS_MX5_HCLK);
++ return get_ipg_clk();
+ case MXC_SATA_CLK:
+ return get_ahb_clk();
+ case MXC_DDR_CLK:
+@@ -506,10 +540,9 @@ u32 imx_get_uartclk(void)
+ return get_uart_clk();
+ }
+
+-
+ u32 imx_get_fecclk(void)
+ {
+- return mxc_get_clock(MXC_IPG_CLK);
++ return get_ipg_clk();
+ }
+
+ static int gcd(int m, int n)
+@@ -611,63 +644,73 @@ static int calc_pll_params(u32 ref, u32 target, struct pll_param *pll)
+
+ #define CHANGE_PLL_SETTINGS(pll, pd, fi, fn, fd) \
+ { \
+- __raw_writel(0x1232, &pll->ctrl); \
+- __raw_writel(0x2, &pll->config); \
+- __raw_writel((((pd) - 1) << 0) | ((fi) << 4), \
+- &pll->op); \
+- __raw_writel(fn, &(pll->mfn)); \
+- __raw_writel((fd) - 1, &pll->mfd); \
+- __raw_writel((((pd) - 1) << 0) | ((fi) << 4), \
+- &pll->hfs_op); \
+- __raw_writel(fn, &pll->hfs_mfn); \
+- __raw_writel((fd) - 1, &pll->hfs_mfd); \
+- __raw_writel(0x1232, &pll->ctrl); \
+- while (!__raw_readl(&pll->ctrl) & 0x1) \
++ writel(0x1232, &pll->ctrl); \
++ writel(0x2, &pll->config); \
++ writel((((pd) - 1) << 0) | ((fi) << 4), \
++ &pll->op); \
++ writel(fn, &(pll->mfn)); \
++ writel((fd) - 1, &pll->mfd); \
++ writel((((pd) - 1) << 0) | ((fi) << 4), \
++ &pll->hfs_op); \
++ writel(fn, &pll->hfs_mfn); \
++ writel((fd) - 1, &pll->hfs_mfd); \
++ writel(0x1232, &pll->ctrl); \
++ while (!readl(&pll->ctrl) & 0x1) \
+ ;\
+ }
+
+ static int config_pll_clk(enum pll_clocks index, struct pll_param *pll_param)
+ {
+- u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
++ u32 ccsr = readl(&mxc_ccm->ccsr);
+ struct mxc_pll_reg *pll = mxc_plls[index];
+
+ switch (index) {
+ case PLL1_CLOCK:
+ /* Switch ARM to PLL2 clock */
+- __raw_writel(ccsr | 0x4, &mxc_ccm->ccsr);
++ writel(ccsr | MXC_CCM_CCSR_PLL1_SW_CLK_SEL,
++ &mxc_ccm->ccsr);
+ CHANGE_PLL_SETTINGS(pll, pll_param->pd,
+ pll_param->mfi, pll_param->mfn,
+ pll_param->mfd);
+ /* Switch back */
+- __raw_writel(ccsr & ~0x4, &mxc_ccm->ccsr);
++ writel(ccsr & ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL,
++ &mxc_ccm->ccsr);
+ break;
+ case PLL2_CLOCK:
+ /* Switch to pll2 bypass clock */
+- __raw_writel(ccsr | 0x2, &mxc_ccm->ccsr);
++ writel(ccsr | MXC_CCM_CCSR_PLL2_SW_CLK_SEL,
++ &mxc_ccm->ccsr);
+ CHANGE_PLL_SETTINGS(pll, pll_param->pd,
+ pll_param->mfi, pll_param->mfn,
+ pll_param->mfd);
+ /* Switch back */
+- __raw_writel(ccsr & ~0x2, &mxc_ccm->ccsr);
++ writel(ccsr & ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL,
++ &mxc_ccm->ccsr);
+ break;
+ case PLL3_CLOCK:
+ /* Switch to pll3 bypass clock */
+- __raw_writel(ccsr | 0x1, &mxc_ccm->ccsr);
++ writel(ccsr | MXC_CCM_CCSR_PLL3_SW_CLK_SEL,
++ &mxc_ccm->ccsr);
+ CHANGE_PLL_SETTINGS(pll, pll_param->pd,
+ pll_param->mfi, pll_param->mfn,
+ pll_param->mfd);
+ /* Switch back */
+- __raw_writel(ccsr & ~0x1, &mxc_ccm->ccsr);
++ writel(ccsr & ~MXC_CCM_CCSR_PLL3_SW_CLK_SEL,
++ &mxc_ccm->ccsr);
+ break;
++#ifdef CONFIG_MX53
+ case PLL4_CLOCK:
+ /* Switch to pll4 bypass clock */
+- __raw_writel(ccsr | 0x20, &mxc_ccm->ccsr);
++ writel(ccsr | MXC_CCM_CCSR_PLL4_SW_CLK_SEL,
++ &mxc_ccm->ccsr);
+ CHANGE_PLL_SETTINGS(pll, pll_param->pd,
+ pll_param->mfi, pll_param->mfn,
+ pll_param->mfd);
+ /* Switch back */
+- __raw_writel(ccsr & ~0x20, &mxc_ccm->ccsr);
++ writel(ccsr & ~MXC_CCM_CCSR_PLL4_SW_CLK_SEL,
++ &mxc_ccm->ccsr);
+ break;
++#endif
+ default:
+ return -EINVAL;
+ }
+@@ -695,7 +738,6 @@ static int config_core_clk(u32 ref, u32 freq)
+
+ static int config_nfc_clk(u32 nfc_clk)
+ {
+- u32 reg;
+ u32 parent_rate = get_emi_slow_clk();
+ u32 div = parent_rate / nfc_clk;
+
+@@ -705,11 +747,10 @@ static int config_nfc_clk(u32 nfc_clk)
+ div++;
+ if (parent_rate / div > NFC_CLK_MAX)
+ div++;
+- reg = __raw_readl(&mxc_ccm->cbcdr);
+- reg &= ~MXC_CCM_CBCDR_NFC_PODF_MASK;
+- reg |= (div - 1) << MXC_CCM_CBCDR_NFC_PODF_OFFSET;
+- __raw_writel(reg, &mxc_ccm->cbcdr);
+- while (__raw_readl(&mxc_ccm->cdhipr) != 0)
++ clrsetbits_le32(&mxc_ccm->cbcdr,
++ MXC_CCM_CBCDR_NFC_PODF_MASK,
++ MXC_CCM_CBCDR_NFC_PODF(div - 1));
++ while (readl(&mxc_ccm->cdhipr) != 0)
+ ;
+ return 0;
+ }
+@@ -722,16 +763,15 @@ static int config_periph_clk(u32 ref, u32 freq)
+
+ memset(&pll_param, 0, sizeof(struct pll_param));
+
+- if (__raw_readl(&mxc_ccm->cbcdr) & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
++ if (readl(&mxc_ccm->cbcdr) & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
+ ret = calc_pll_params(ref, freq, &pll_param);
+ if (ret != 0) {
+ printf("Error:Can't find pll parameters: %d\n",
+ ret);
+ return ret;
+ }
+- switch ((__raw_readl(&mxc_ccm->cbcmr) & \
+- MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >> \
+- MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
++ switch (MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(
++ readl(&mxc_ccm->cbcmr))) {
+ case 0:
+ return config_pll_clk(PLL1_CLOCK, &pll_param);
+ break;
+@@ -750,8 +790,7 @@ static int config_ddr_clk(u32 emi_clk)
+ {
+ u32 clk_src;
+ s32 shift = 0, clk_sel, div = 1;
+- u32 cbcmr = __raw_readl(&mxc_ccm->cbcmr);
+- u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
++ u32 cbcmr = readl(&mxc_ccm->cbcmr);
+
+ if (emi_clk > MAX_DDR_CLK) {
+ printf("Warning:DDR clock should not exceed %d MHz\n",
+@@ -761,7 +800,7 @@ static int config_ddr_clk(u32 emi_clk)
+
+ clk_src = get_periph_clk();
+ /* Find DDR clock input */
+- clk_sel = (cbcmr >> 10) & 0x3;
++ clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr);
+ switch (clk_sel) {
+ case 0:
+ shift = 16;
+@@ -786,12 +825,10 @@ static int config_ddr_clk(u32 emi_clk)
+ if (div > 8)
+ div = 8;
+
+- cbcdr = cbcdr & ~(0x7 << shift);
+- cbcdr |= ((div - 1) << shift);
+- __raw_writel(cbcdr, &mxc_ccm->cbcdr);
+- while (__raw_readl(&mxc_ccm->cdhipr) != 0)
++ clrsetbits_le32(&mxc_ccm->cbcdr, 0x7 << shift, (div - 1) << shift);
++ while (readl(&mxc_ccm->cdhipr) != 0)
+ ;
+- __raw_writel(0x0, &mxc_ccm->ccdr);
++ writel(0x0, &mxc_ccm->ccdr);
+
+ return 0;
+ }
+@@ -862,9 +899,9 @@ void mxc_set_sata_internal_clock(void)
+ u32 *tmp_base =
+ (u32 *)(IIM_BASE_ADDR + 0x180c);
+
+- set_usb_phy1_clk();
++ set_usb_phy_clk();
+
+- writel((readl(tmp_base) & (~0x6)) | 0x4, tmp_base);
++ clrsetbits_le32(tmp_base, 0x6, 0x4);
+ }
+ #endif
+
+@@ -875,14 +912,14 @@ int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+ {
+ u32 freq;
+
+- freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
++ freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
+ printf("PLL1 %8d MHz\n", freq / 1000000);
+- freq = decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_SYS_MX5_HCLK);
++ freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
+ printf("PLL2 %8d MHz\n", freq / 1000000);
+- freq = decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK);
++ freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
+ printf("PLL3 %8d MHz\n", freq / 1000000);
+ #ifdef CONFIG_MX53
+- freq = decode_pll(mxc_plls[PLL4_CLOCK], CONFIG_SYS_MX5_HCLK);
++ freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);
+ printf("PLL4 %8d MHz\n", freq / 1000000);
+ #endif
+
+diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
+index d62093b..529e35b 100644
+--- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S
++++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
+@@ -162,9 +162,9 @@ setup_pll_func:
+ .endm
+
+ .macro init_clock
+-#if defined (CONFIG_MX51)
+ ldr r0, =CCM_BASE_ADDR
+
++#if defined(CONFIG_MX51)
+ /* Gate of clocks to the peripherals first */
+ ldr r1, =0x3FFFFFFF
+ str r1, [r0, #CLKCTL_CCGR0]
+@@ -190,6 +190,21 @@ setup_pll_func:
+ 1: ldr r1, [r0, #CLKCTL_CDHIPR]
+ cmp r1, #0x0
+ bne 1b
++#else
++ ldr r1, =0x3FFFFFFF
++ str r1, [r0, #CLKCTL_CCGR0]
++ str r4, [r0, #CLKCTL_CCGR1]
++ str r4, [r0, #CLKCTL_CCGR2]
++ str r4, [r0, #CLKCTL_CCGR3]
++ str r4, [r0, #CLKCTL_CCGR7]
++
++ ldr r1, =0x00030000
++ str r1, [r0, #CLKCTL_CCGR4]
++ ldr r1, =0x00FFF030
++ str r1, [r0, #CLKCTL_CCGR5]
++ ldr r1, =0x0F00030F
++ str r1, [r0, #CLKCTL_CCGR6]
++#endif
+
+ /* Switch ARM to step clock */
+ mov r1, #0x4
+@@ -202,6 +217,7 @@ setup_pll_func:
+ setup_pll PLL1_BASE_ADDR, 800
+ #endif
+
++#if defined(CONFIG_MX51)
+ setup_pll PLL3_BASE_ADDR, 665
+
+ /* Switch peripheral to PLL 3 */
+@@ -218,7 +234,7 @@ setup_pll_func:
+ str r1, [r0, #CLKCTL_CBCDR]
+ ldr r1, =0x000020C0 | CONFIG_SYS_DDR_CLKSEL
+ str r1, [r0, #CLKCTL_CBCMR]
+-
++#endif
+ setup_pll PLL3_BASE_ADDR, 216
+
+ /* Set the platform clock dividers */
+@@ -228,17 +244,21 @@ setup_pll_func:
+
+ ldr r0, =CCM_BASE_ADDR
+
++#if defined(CONFIG_MX51)
+ /* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */
+ ldr r3, [r4, #ROM_SI_REV]
+ cmp r3, #0x10
+ movls r1, #0x1
+ movhi r1, #0
+-
++#else
++ mov r1, #0
++#endif
+ str r1, [r0, #CLKCTL_CACRR]
+
+ /* Switch ARM back to PLL 1 */
+ str r4, [r0, #CLKCTL_CCSR]
+
++#if defined(CONFIG_MX51)
+ /* setup the rest */
+ /* Use lp_apm (24MHz) source for perclk */
+ ldr r1, =0x000020C2 | CONFIG_SYS_DDR_CLKSEL
+@@ -246,6 +266,7 @@ setup_pll_func:
+ /* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
+ ldr r1, =CONFIG_SYS_CLKTL_CBCDR
+ str r1, [r0, #CLKCTL_CBCDR]
++#endif
+
+ /* Restore the default values in the Gate registers */
+ ldr r1, =0xFFFFFFFF
+@@ -256,127 +277,47 @@ setup_pll_func:
+ str r1, [r0, #CLKCTL_CCGR4]
+ str r1, [r0, #CLKCTL_CCGR5]
+ str r1, [r0, #CLKCTL_CCGR6]
++#if defined(CONFIG_MX53)
++ str r1, [r0, #CLKCTL_CCGR7]
++#endif
+
++#if defined(CONFIG_MX51)
+ /* Use PLL 2 for UART's, get 66.5MHz from it */
+ ldr r1, =0xA5A2A020
+ str r1, [r0, #CLKCTL_CSCMR1]
+ ldr r1, =0x00C30321
+ str r1, [r0, #CLKCTL_CSCDR1]
+- /* make sure divider effective */
+-1: ldr r1, [r0, #CLKCTL_CDHIPR]
+- cmp r1, #0x0
+- bne 1b
+-
+- str r4, [r0, #CLKCTL_CCDR]
+-
+- /* for cko - for ARM div by 8 */
+- mov r1, #0x000A0000
+- add r1, r1, #0x00000F0
+- str r1, [r0, #CLKCTL_CCOSR]
+-#else /* CONFIG_MX53 */
+- ldr r0, =CCM_BASE_ADDR
+-
+- /* Gate of clocks to the peripherals first */
+- ldr r1, =0x3FFFFFFF
+- str r1, [r0, #CLKCTL_CCGR0]
+- str r4, [r0, #CLKCTL_CCGR1]
+- str r4, [r0, #CLKCTL_CCGR2]
+- str r4, [r0, #CLKCTL_CCGR3]
+- str r4, [r0, #CLKCTL_CCGR7]
+- ldr r1, =0x00030000
+- str r1, [r0, #CLKCTL_CCGR4]
+- ldr r1, =0x00FFF030
+- str r1, [r0, #CLKCTL_CCGR5]
+- ldr r1, =0x0F00030F
+- str r1, [r0, #CLKCTL_CCGR6]
+-
+- /* Switch ARM to step clock */
+- mov r1, #0x4
+- str r1, [r0, #CLKCTL_CCSR]
+-
+- setup_pll PLL1_BASE_ADDR, 800
+-
+- setup_pll PLL3_BASE_ADDR, 400
+-
+- /* Switch peripheral to PLL3 */
+- ldr r0, =CCM_BASE_ADDR
+- ldr r1, =0x00015154
+- str r1, [r0, #CLKCTL_CBCMR]
+- ldr r1, =0x02888945
+- orr r1, r1, #(1 << 16)
+- str r1, [r0, #CLKCTL_CBCDR]
+- /* make sure change is effective */
+-1: ldr r1, [r0, #CLKCTL_CDHIPR]
+- cmp r1, #0x0
+- bne 1b
+-
+- setup_pll PLL2_BASE_ADDR, 400
+-
++#elif defined(CONFIG_MX53)
+ /* Switch peripheral to PLL2 */
+ ldr r0, =CCM_BASE_ADDR
+ ldr r1, =0x00808145
+- orr r1, r1, #(2 << 10)
+- orr r1, r1, #(0 << 16)
+- orr r1, r1, #(1 << 19)
++ orr r1, r1, #2 << 10
++ orr r1, r1, #1 << 19
+ str r1, [r0, #CLKCTL_CBCDR]
+
+ ldr r1, =0x00016154
+ str r1, [r0, #CLKCTL_CBCMR]
+-
+- /*change uart clk parent to pll2*/
++ /* Change uart clk parent to pll2*/
+ ldr r1, [r0, #CLKCTL_CSCMR1]
+ and r1, r1, #0xfcffffff
+ orr r1, r1, #0x01000000
+ str r1, [r0, #CLKCTL_CSCMR1]
+-
+- /* make sure change is effective */
+-1: ldr r1, [r0, #CLKCTL_CDHIPR]
+- cmp r1, #0x0
+- bne 1b
+-
+- setup_pll PLL3_BASE_ADDR, 216
+-
+- setup_pll PLL4_BASE_ADDR, 455
+-
+- /* Set the platform clock dividers */
+- ldr r0, =ARM_BASE_ADDR
+- ldr r1, =0x00000124
+- str r1, [r0, #0x14]
+-
+- ldr r0, =CCM_BASE_ADDR
+- mov r1, #0
+- str r1, [r0, #CLKCTL_CACRR]
+-
+- /* Switch ARM back to PLL 1. */
+- mov r1, #0x0
+- str r1, [r0, #CLKCTL_CCSR]
+-
+- /* make uart div=6 */
+ ldr r1, [r0, #CLKCTL_CSCDR1]
+ and r1, r1, #0xffffffc0
+ orr r1, r1, #0x0a
+ str r1, [r0, #CLKCTL_CSCDR1]
++#endif
++ /* make sure divider effective */
++1: ldr r1, [r0, #CLKCTL_CDHIPR]
++ cmp r1, #0x0
++ bne 1b
+
+- /* Restore the default values in the Gate registers */
+- ldr r1, =0xFFFFFFFF
+- str r1, [r0, #CLKCTL_CCGR0]
+- str r1, [r0, #CLKCTL_CCGR1]
+- str r1, [r0, #CLKCTL_CCGR2]
+- str r1, [r0, #CLKCTL_CCGR3]
+- str r1, [r0, #CLKCTL_CCGR4]
+- str r1, [r0, #CLKCTL_CCGR5]
+- str r1, [r0, #CLKCTL_CCGR6]
+- str r1, [r0, #CLKCTL_CCGR7]
+-
+- mov r1, #0x00000
+- str r1, [r0, #CLKCTL_CCDR]
+-
+- /* for cko - for ARM div by 8 */
+- mov r1, #0x000A0000
+- add r1, r1, #0x00000F0
+- str r1, [r0, #CLKCTL_CCOSR]
++ str r4, [r0, #CLKCTL_CCDR]
+
+-#endif /* CONFIG_MX53 */
++ /* for cko - for ARM div by 8 */
++ mov r1, #0x000A0000
++ add r1, r1, #0x00000F0
++ str r1, [r0, #CLKCTL_CCOSR]
+ .endm
+
+ .macro setup_wdog
+@@ -429,9 +370,3 @@ W_DP_665: .word DP_OP_665
+ W_DP_216: .word DP_OP_216
+ .word DP_MFD_216
+ .word DP_MFN_216
+-W_DP_400: .word DP_OP_400
+- .word DP_MFD_400
+- .word DP_MFN_400
+-W_DP_455: .word DP_OP_455
+- .word DP_MFD_455
+- .word DP_MFN_455
+diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
+index 44a81b2..a01d96f 100644
+--- a/arch/arm/cpu/armv7/mx6/clock.c
++++ b/arch/arm/cpu/armv7/mx6/clock.c
+@@ -43,9 +43,9 @@ void enable_usboh3_clk(unsigned char enable)
+
+ reg = __raw_readl(&imx_ccm->CCGR6);
+ if (enable)
+- reg |= MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG0_OFFSET;
++ reg |= MXC_CCM_CCGR6_USBOH3_MASK;
+ else
+- reg &= ~(MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG0_OFFSET);
++ reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
+ __raw_writel(reg, &imx_ccm->CCGR6);
+
+ }
+@@ -59,7 +59,9 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
+
+ if (i2c_num > 2)
+ return -EINVAL;
+- mask = MXC_CCM_CCGR_CG_MASK << ((i2c_num + 3) << 1);
++
++ mask = MXC_CCM_CCGR_CG_MASK
++ << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET + (i2c_num << 1));
+ reg = __raw_readl(&imx_ccm->CCGR2);
+ if (enable)
+ reg |= mask;
+@@ -108,7 +110,7 @@ static u32 get_mcu_main_clk(void)
+ reg = __raw_readl(&imx_ccm->cacrr);
+ reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
+ reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
+- freq = decode_pll(PLL_SYS, CONFIG_SYS_MX6_HCLK);
++ freq = decode_pll(PLL_SYS, MXC_HCLK);
+
+ return freq / (reg + 1);
+ }
+@@ -125,11 +127,11 @@ u32 get_periph_clk(void)
+
+ switch (reg) {
+ case 0:
+- freq = decode_pll(PLL_USBOTG, CONFIG_SYS_MX6_HCLK);
++ freq = decode_pll(PLL_USBOTG, MXC_HCLK);
+ break;
+ case 1:
+ case 2:
+- freq = CONFIG_SYS_MX6_HCLK;
++ freq = MXC_HCLK;
+ break;
+ default:
+ break;
+@@ -141,7 +143,7 @@ u32 get_periph_clk(void)
+
+ switch (reg) {
+ case 0:
+- freq = decode_pll(PLL_BUS, CONFIG_SYS_MX6_HCLK);
++ freq = decode_pll(PLL_BUS, MXC_HCLK);
+ break;
+ case 1:
+ freq = PLL2_PFD2_FREQ;
+@@ -237,7 +239,7 @@ static u32 get_emi_slow_clk(void)
+ root_freq = get_axi_clk();
+ break;
+ case 1:
+- root_freq = decode_pll(PLL_USBOTG, CONFIG_SYS_MX6_HCLK);
++ root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
+ break;
+ case 2:
+ root_freq = PLL2_PFD2_FREQ;
+@@ -309,7 +311,7 @@ u32 imx_get_uartclk(void)
+
+ u32 imx_get_fecclk(void)
+ {
+- return decode_pll(PLL_ENET, CONFIG_SYS_MX6_HCLK);
++ return decode_pll(PLL_ENET, MXC_HCLK);
+ }
+
+ int enable_sata_clock(void)
+@@ -321,7 +323,7 @@ int enable_sata_clock(void)
+
+ /* Enable sata clock */
+ reg = readl(&imx_ccm->CCGR5); /* CCGR5 */
+- reg |= MXC_CCM_CCGR5_CG2_MASK;
++ reg |= MXC_CCM_CCGR5_SATA_MASK;
+ writel(reg, &imx_ccm->CCGR5);
+
+ /* Enable PLLs */
+@@ -390,13 +392,13 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
+ int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+ {
+ u32 freq;
+- freq = decode_pll(PLL_SYS, CONFIG_SYS_MX6_HCLK);
++ freq = decode_pll(PLL_SYS, MXC_HCLK);
+ printf("PLL_SYS %8d MHz\n", freq / 1000000);
+- freq = decode_pll(PLL_BUS, CONFIG_SYS_MX6_HCLK);
++ freq = decode_pll(PLL_BUS, MXC_HCLK);
+ printf("PLL_BUS %8d MHz\n", freq / 1000000);
+- freq = decode_pll(PLL_USBOTG, CONFIG_SYS_MX6_HCLK);
++ freq = decode_pll(PLL_USBOTG, MXC_HCLK);
+ printf("PLL_OTG %8d MHz\n", freq / 1000000);
+- freq = decode_pll(PLL_ENET, CONFIG_SYS_MX6_HCLK);
++ freq = decode_pll(PLL_ENET, MXC_HCLK);
+ printf("PLL_NET %8d MHz\n", freq / 1000000);
+
+ printf("\n");
+diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
+index 7380ffe..bc65767 100644
+--- a/arch/arm/cpu/armv7/mx6/soc.c
++++ b/arch/arm/cpu/armv7/mx6/soc.c
+@@ -146,7 +146,7 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
+ void boot_mode_apply(unsigned cfg_val)
+ {
+ unsigned reg;
+- struct src_regs *psrc = (struct src_regs *)SRC_BASE_ADDR;
++ struct src *psrc = (struct src *)SRC_BASE_ADDR;
+ writel(cfg_val, &psrc->gpr9);
+ reg = readl(&psrc->gpr10);
+ if (cfg_val)
+diff --git a/arch/arm/cpu/armv7/omap-common/config.mk b/arch/arm/cpu/armv7/omap-common/config.mk
+index 217fc14..c400dcc 100644
+--- a/arch/arm/cpu/armv7/omap-common/config.mk
++++ b/arch/arm/cpu/armv7/omap-common/config.mk
+@@ -20,6 +20,15 @@
+ # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ # MA 02111-1307 USA
+ #
++PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
+
+ # Make ARMv5 to allow more compilers to work, even though its v7a.
+ PLATFORM_CPPFLAGS += -march=armv5
++# =========================================================================
++#
++# Supply options according to compiler version
++#
++# =========================================================================
++PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,\
++ $(call cc-option,-malignment-traps,))
++PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
+diff --git a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
+index 3581077..9766563 100644
+--- a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
++++ b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
+@@ -27,7 +27,6 @@
+ */
+
+ #include <asm/arch/omap.h>
+-#include <asm/arch/spl.h>
+ #include <linux/linkage.h>
+
+ ENTRY(save_boot_params)
+@@ -60,9 +59,9 @@ ENTRY(save_boot_params)
+ strb r2, [r3, #BOOT_DEVICE_OFFSET] @ spl_boot_device <- r1
+
+ /* boot mode is passed only for devices that can raw/fat mode */
+- cmp r2, #BOOT_DEVICE_XIP
++ cmp r2, #2
+ blt 2f
+- cmp r2, #BOOT_DEVICE_MMC2
++ cmp r2, #7
+ bgt 2f
+ /* Store the boot mode (raw/FAT) in omap_bootmode */
+ ldr r2, [r0, #DEV_DESC_PTR_OFFSET] @ get the device descriptor ptr
+diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S
+index eacfef8..ebf69fa 100644
+--- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S
++++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S
+@@ -214,7 +214,7 @@ pll_div_val5:
+
+ ENTRY(lowlevel_init)
+ ldr sp, SRAM_STACK
+- str ip, [sp] /* stash ip register */
++ str ip, [sp] /* stash old link register */
+ mov ip, lr /* save link reg across call */
+ #if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
+ /*
+@@ -224,11 +224,12 @@ ENTRY(lowlevel_init)
+ ldr r1, =SRAM_CLK_CODE
+ bl cpy_clk_code
+ #endif /* NAND Boot */
+- mov lr, ip /* restore link reg */
++ bl s_init /* go setup pll, mux, memory */
+ ldr ip, [sp] /* restore save ip */
+- /* tail-call s_init to setup pll, mux, memory */
+- b s_init
++ mov lr, ip /* restore link reg */
+
++ /* back to arch calling code */
++ mov pc, lr
+ ENDPROC(lowlevel_init)
+
+ /* the literal pools origin */
+diff --git a/arch/arm/cpu/armv7/rmobile/Makefile b/arch/arm/cpu/armv7/rmobile/Makefile
+deleted file mode 100644
+index c8999bb..0000000
+--- a/arch/arm/cpu/armv7/rmobile/Makefile
++++ /dev/null
+@@ -1,65 +0,0 @@
+-#
+-# (C) Copyright 2000-2006
+-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+-#
+-# See file CREDITS for list of people who contributed to this
+-# project.
+-#
+-# This program is free software; you can redistribute it and/or
+-# modify it under the terms of the GNU General Public License as
+-# published by the Free Software Foundation; either version 2 of
+-# the License, or (at your option) any later version.
+-#
+-# This program is distributed in the hope that it will be useful,
+-# but WITHOUT ANY WARRANTY; without even the implied warranty of
+-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-# GNU General Public License for more details.
+-#
+-# You should have received a copy of the GNU General Public License
+-# along with this program; if not, write to the Free Software
+-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+-# MA 02111-1307 USA
+-#
+-
+-include $(TOPDIR)/config.mk
+-
+-LIB = $(obj)lib$(SOC).o
+-
+-SOBJS = lowlevel_init.o
+-COBJS-y += cpu_info.o
+-COBJS-y += emac.o
+-
+-COBJS-$(CONFIG_DISPLAY_BOARDINFO) += board.o
+-COBJS-$(CONFIG_GLOBAL_TIMER) += timer.o
+-COBJS-$(CONFIG_R8A7740) += cpu_info-r8a7740.o
+-COBJS-$(CONFIG_R8A7740) += pfc-r8a7740.o
+-COBJS-$(CONFIG_SH73A0) += cpu_info-sh73a0.o
+-COBJS-$(CONFIG_SH73A0) += pfc-sh73a0.o
+-COBJS_LN-$(CONFIG_TMU_TIMER) += sh_timer.o
+-
+-COBJS := $(COBJS-y)
+-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) $(addprefix $(obj),$(COBJS_LN-y:.o=.c))
+-OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS) $(COBJS_LN-y))
+-SOBJS := $(addprefix $(obj),$(SOBJS))
+-START := $(addprefix $(obj),$(START))
+-
+-all: $(obj).depend $(LIB)
+-
+-$(LIB): $(OBJS)
+- $(call cmd_link_o_target, $(OBJS))
+-
+-# from arch/sh/lib/ directory
+-$(obj)sh_timer.c:
+- @rm -f $(obj)sh_timer.c
+- ln -s $(SRCTREE)/arch/sh/lib/time.c $(obj)sh_timer.c
+-
+-#########################################################################
+-
+-# defines $(obj).depend target
+-include $(SRCTREE)/rules.mk
+-
+-sinclude $(obj).depend
+-
+-#########################################################################
+-
+diff --git a/arch/arm/cpu/armv7/rmobile/board.c b/arch/arm/cpu/armv7/rmobile/board.c
+deleted file mode 100644
+index 2622590..0000000
+--- a/arch/arm/cpu/armv7/rmobile/board.c
++++ /dev/null
+@@ -1,31 +0,0 @@
+-/*
+- * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj at renesas.com>
+- * (C) Copyright 2012 Renesas Solutions Corp.
+- *
+- * See file CREDITS for list of people who contributed to this
+- * project.
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of
+- * the License, or (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+- * MA 02111-1307 USA
+- */
+-#include <common.h>
+-#include <asm/io.h>
+-#include <asm/arch/sys_proto.h>
+-
+-int checkboard(void)
+-{
+- printf("Board: %s\n", sysinfo.board_string);
+- return 0;
+-}
+diff --git a/arch/arm/cpu/armv7/rmobile/config.mk b/arch/arm/cpu/armv7/rmobile/config.mk
+deleted file mode 100644
+index 1da0227..0000000
+--- a/arch/arm/cpu/armv7/rmobile/config.mk
++++ /dev/null
+@@ -1,26 +0,0 @@
+-#
+-# (C) Copyright 2002
+-# Gary Jennejohn, DENX Software Engineering, <garyj at denx.de>
+-#
+-# See file CREDITS for list of people who contributed to this
+-# project.
+-#
+-# This program is free software; you can redistribute it and/or
+-# modify it under the terms of the GNU General Public License as
+-# published by the Free Software Foundation; either version 2 of
+-# the License, or (at your option) any later version.
+-#
+-# This program is distributed in the hope that it will be useful,
+-# but WITHOUT ANY WARRANTY; without even the implied warranty of
+-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-# GNU General Public License for more details.
+-#
+-# You should have received a copy of the GNU General Public License
+-# along with this program; if not, write to the Free Software
+-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+-# MA 02111-1307 USA
+-#
+-PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
+-
+-# Make ARMv5 to allow more compilers to work, even though its v7a.
+-PLATFORM_CPPFLAGS += -march=armv5
+diff --git a/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7740.c b/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7740.c
+deleted file mode 100644
+index 2231402..0000000
+--- a/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7740.c
++++ /dev/null
+@@ -1,48 +0,0 @@
+-/*
+- * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj at renesas.com>
+- * (C) Copyright 2012 Renesas Solutions Corp.
+- *
+- * See file CREDITS for list of people who contributed to this
+- * project.
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of
+- * the License, or (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+- * MA 02111-1307 USA
+- */
+-#include <common.h>
+-#include <asm/io.h>
+-
+-u32 rmobile_get_cpu_type(void)
+-{
+- u32 id;
+- u32 type;
+- struct r8a7740_hpb *hpb = (struct r8a7740_hpb *)HPB_BASE;
+-
+- id = readl(hpb->cccr);
+- type = (id >> 8) & 0xFF;
+-
+- return type;
+-}
+-
+-u32 rmobile_get_cpu_rev(void)
+-{
+- u32 id;
+- u32 rev;
+- struct r8a7740_hpb *hpb = (struct r8a7740_hpb *)HPB_BASE;
+-
+- id = readl(hpb->cccr);
+- rev = (id >> 4) & 0xF;
+-
+- return rev;
+-}
+diff --git a/arch/arm/cpu/armv7/rmobile/cpu_info-sh73a0.c b/arch/arm/cpu/armv7/rmobile/cpu_info-sh73a0.c
+deleted file mode 100644
+index 2e7ed49..0000000
+--- a/arch/arm/cpu/armv7/rmobile/cpu_info-sh73a0.c
++++ /dev/null
+@@ -1,60 +0,0 @@
+-/*
+- * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj at renesas.com>
+- * (C) Copyright 2012 Renesas Solutions Corp.
+- *
+- * See file CREDITS for list of people who contributed to this
+- * project.
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of
+- * the License, or (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+- * MA 02111-1307 USA
+- */
+-#include <common.h>
+-#include <asm/io.h>
+-
+-u32 rmobile_get_cpu_type(void)
+-{
+- u32 id;
+- u32 type;
+- struct sh73a0_hpb *hpb = (struct sh73a0_hpb *)HPB_BASE;
+-
+- id = readl(&hpb->cccr);
+- type = (id >> 8) & 0xFF;
+-
+- return type;
+-}
+-
+-u32 rmobile_get_cpu_rev_integer(void)
+-{
+- u32 id;
+- u32 rev;
+- struct sh73a0_hpb *hpb = (struct sh73a0_hpb *)HPB_BASE;
+-
+- id = readl(&hpb->cccr);
+- rev = ((id >> 4) & 0xF) + 1;
+-
+- return rev;
+-}
+-
+-u32 rmobile_get_cpu_rev_fraction(void)
+-{
+- u32 id;
+- u32 rev;
+- struct sh73a0_hpb *hpb = (struct sh73a0_hpb *)HPB_BASE;
+-
+- id = readl(&hpb->cccr);
+- rev = id & 0xF;
+-
+- return rev;
+-}
+diff --git a/arch/arm/cpu/armv7/rmobile/cpu_info.c b/arch/arm/cpu/armv7/rmobile/cpu_info.c
+deleted file mode 100644
+index 0e2b82e..0000000
+--- a/arch/arm/cpu/armv7/rmobile/cpu_info.c
++++ /dev/null
+@@ -1,85 +0,0 @@
+-/*
+- * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj at renesas.com>
+- * (C) Copyright 2012 Renesas Solutions Corp.
+- *
+- * See file CREDITS for list of people who contributed to this
+- * project.
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of
+- * the License, or (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+- * MA 02111-1307 USA
+- */
+-#include <common.h>
+-#include <asm/io.h>
+-
+-#ifdef CONFIG_ARCH_CPU_INIT
+-int arch_cpu_init(void)
+-{
+- icache_enable();
+- return 0;
+-}
+-#endif
+-
+-#ifndef CONFIG_SYS_DCACHE_OFF
+-void enable_caches(void)
+-{
+- dcache_enable();
+-}
+-#endif
+-
+-#ifdef CONFIG_DISPLAY_CPUINFO
+-static u32 __rmobile_get_cpu_type(void)
+-{
+- return 0x0;
+-}
+-u32 rmobile_get_cpu_type(void)
+- __attribute__((weak, alias("__rmobile_get_cpu_type")));
+-
+-static u32 __rmobile_get_cpu_rev_integer(void)
+-{
+- return 0;
+-}
+-u32 rmobile_get_cpu_rev_integer(void)
+- __attribute__((weak, alias("__rmobile_get_cpu_rev_integer")));
+-
+-static u32 __rmobile_get_cpu_rev_fraction(void)
+-{
+- return 0;
+-}
+-u32 rmobile_get_cpu_rev_fraction(void)
+- __attribute__((weak, alias("__rmobile_get_cpu_rev_fraction")));
+-
+-int print_cpuinfo(void)
+-{
+- switch (rmobile_get_cpu_type()) {
+- case 0x37:
+- printf("CPU: Renesas Electronics SH73A0 rev %d.%d\n",
+- rmobile_get_cpu_rev_integer(),
+- rmobile_get_cpu_rev_fraction());
+- break;
+- case 0x40:
+- printf("CPU: Renesas Electronics R8A7740 rev %d.%d\n",
+- rmobile_get_cpu_rev_integer(),
+- rmobile_get_cpu_rev_fraction());
+- break;
+-
+- default:
+- printf("CPU: Renesas Electronics CPU rev %d.%d\n",
+- rmobile_get_cpu_rev_integer(),
+- rmobile_get_cpu_rev_fraction());
+- break;
+- }
+- return 0;
+-}
+-#endif /* CONFIG_DISPLAY_CPUINFO */
+diff --git a/arch/arm/cpu/armv7/rmobile/emac.c b/arch/arm/cpu/armv7/rmobile/emac.c
+deleted file mode 100644
+index da5269e..0000000
+--- a/arch/arm/cpu/armv7/rmobile/emac.c
++++ /dev/null
+@@ -1,36 +0,0 @@
+-/*
+- * RMOBILE EtherMAC initialization.
+- *
+- * Copyright (C) 2012 Renesas Solutions Corp.
+- * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj at renesas.com>
+- *
+- * See file CREDITS for list of people who contributed to this
+- * project.
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of
+- * the License, or (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc.
+- */
+-
+-#include <common.h>
+-#include <asm/errno.h>
+-#include <netdev.h>
+-
+-int cpu_eth_init(bd_t *bis)
+-{
+- int ret = -ENODEV;
+-#ifdef CONFIG_SH_ETHER
+- ret = sh_eth_initialize(bis);
+-#endif
+- return ret;
+-}
+diff --git a/arch/arm/cpu/armv7/rmobile/lowlevel_init.S b/arch/arm/cpu/armv7/rmobile/lowlevel_init.S
+deleted file mode 100644
+index 4fdca06..0000000
+--- a/arch/arm/cpu/armv7/rmobile/lowlevel_init.S
++++ /dev/null
+@@ -1,88 +0,0 @@
+-/*
+- * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.Iwamatsu.yj at renesas.com>
+- * Copyright (C) 2012 Renesas Solutions Corp.
+- *
+- * See file CREDITS for list of people who contributed to this
+- * project.
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of
+- * the License, or (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+- * MA 02111-1307 USA
+- */
+-
+-#include <config.h>
+-#include <linux/linkage.h>
+-
+-ENTRY(lowlevel_init)
+- ldr r0, =MERAM_BASE
+- mov r1, #0x0
+- str r1, [r0]
+-
+- mrc p15, 0, r0, c0, c0, 5
+- ands r0, r0, #0xF
+- beq lowlevel_init__
+- b wait_interrupt
+-
+- .pool
+- .align 4
+-
+-wait_interrupt:
+-#ifdef ICCICR
+- ldr r1, =ICCICR
+- mov r2, #0x0
+- str r2, [r1]
+- mov r2, #0xF0
+- adds r1, r1, #4 /* ICCPMR */
+- str r2, [r1]
+- ldr r1, =ICCICR
+- mov r2, #0x1
+- str r2, [r1]
+-#endif
+-
+-wait_loop:
+- .long 0xE320F003 /* wfi */
+-
+- ldr r2, [r1, #0xC]
+- str r2, [r1, #0x10]
+-
+- ldr r0, =MERAM_BASE
+- ldr r2, [r0]
+- cmp r2, #0
+- movne pc, r2
+-
+- b wait_loop
+-
+-wait_loop_end:
+- .pool
+- .align 4
+-
+-lowlevel_init__:
+-
+- mov r0, #0x200000
+-
+-loop0:
+- subs r0, r0, #1
+- bne loop0
+-
+- ldr sp, MERAM_STACK
+- b s_init
+-
+- .pool
+- .align 4
+-
+-ENDPROC(lowlevel_init)
+- .ltorg
+-
+-MERAM_STACK:
+- .word LOW_LEVEL_MERAM_STACK
+diff --git a/arch/arm/cpu/armv7/rmobile/pfc-r8a7740.c b/arch/arm/cpu/armv7/rmobile/pfc-r8a7740.c
+deleted file mode 100644
+index 5d42a68..0000000
+--- a/arch/arm/cpu/armv7/rmobile/pfc-r8a7740.c
++++ /dev/null
+@@ -1,2612 +0,0 @@
+-/*
+- * R8A7740 processor support
+- *
+- * Copyright (C) 2011 Renesas Solutions Corp.
+- * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; version 2 of the
+- * License.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+- */
+-#include <common.h>
+-#include <sh_pfc.h>
+-#include <asm/gpio.h>
+-#include <asm/arch/irqs.h>
+-
+-#define CPU_ALL_PORT(fn, pfx, sfx) \
+- PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx), \
+- PORT_10(fn, pfx##10, sfx), PORT_90(fn, pfx##1, sfx), \
+- PORT_10(fn, pfx##20, sfx), \
+- PORT_1(fn, pfx##210, sfx), PORT_1(fn, pfx##211, sfx)
+-
+-enum {
+- PINMUX_RESERVED = 0,
+-
+- /* PORT0_DATA -> PORT211_DATA */
+- PINMUX_DATA_BEGIN,
+- PORT_ALL(DATA),
+- PINMUX_DATA_END,
+-
+- /* PORT0_IN -> PORT211_IN */
+- PINMUX_INPUT_BEGIN,
+- PORT_ALL(IN),
+- PINMUX_INPUT_END,
+-
+- /* PORT0_IN_PU -> PORT211_IN_PU */
+- PINMUX_INPUT_PULLUP_BEGIN,
+- PORT_ALL(IN_PU),
+- PINMUX_INPUT_PULLUP_END,
+-
+- /* PORT0_IN_PD -> PORT211_IN_PD */
+- PINMUX_INPUT_PULLDOWN_BEGIN,
+- PORT_ALL(IN_PD),
+- PINMUX_INPUT_PULLDOWN_END,
+-
+- /* PORT0_OUT -> PORT211_OUT */
+- PINMUX_OUTPUT_BEGIN,
+- PORT_ALL(OUT),
+- PINMUX_OUTPUT_END,
+-
+- PINMUX_FUNCTION_BEGIN,
+- PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT211_FN_IN */
+- PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT211_FN_OUT */
+- PORT_ALL(FN0), /* PORT0_FN0 -> PORT211_FN0 */
+- PORT_ALL(FN1), /* PORT0_FN1 -> PORT211_FN1 */
+- PORT_ALL(FN2), /* PORT0_FN2 -> PORT211_FN2 */
+- PORT_ALL(FN3), /* PORT0_FN3 -> PORT211_FN3 */
+- PORT_ALL(FN4), /* PORT0_FN4 -> PORT211_FN4 */
+- PORT_ALL(FN5), /* PORT0_FN5 -> PORT211_FN5 */
+- PORT_ALL(FN6), /* PORT0_FN6 -> PORT211_FN6 */
+- PORT_ALL(FN7), /* PORT0_FN7 -> PORT211_FN7 */
+-
+- MSEL1CR_31_0, MSEL1CR_31_1,
+- MSEL1CR_30_0, MSEL1CR_30_1,
+- MSEL1CR_29_0, MSEL1CR_29_1,
+- MSEL1CR_28_0, MSEL1CR_28_1,
+- MSEL1CR_27_0, MSEL1CR_27_1,
+- MSEL1CR_26_0, MSEL1CR_26_1,
+- MSEL1CR_16_0, MSEL1CR_16_1,
+- MSEL1CR_15_0, MSEL1CR_15_1,
+- MSEL1CR_14_0, MSEL1CR_14_1,
+- MSEL1CR_13_0, MSEL1CR_13_1,
+- MSEL1CR_12_0, MSEL1CR_12_1,
+- MSEL1CR_9_0, MSEL1CR_9_1,
+- MSEL1CR_7_0, MSEL1CR_7_1,
+- MSEL1CR_6_0, MSEL1CR_6_1,
+- MSEL1CR_5_0, MSEL1CR_5_1,
+- MSEL1CR_4_0, MSEL1CR_4_1,
+- MSEL1CR_3_0, MSEL1CR_3_1,
+- MSEL1CR_2_0, MSEL1CR_2_1,
+- MSEL1CR_0_0, MSEL1CR_0_1,
+-
+- MSEL3CR_15_0, MSEL3CR_15_1, /* Trace / Debug ? */
+- MSEL3CR_6_0, MSEL3CR_6_1,
+-
+- MSEL4CR_19_0, MSEL4CR_19_1,
+- MSEL4CR_18_0, MSEL4CR_18_1,
+- MSEL4CR_15_0, MSEL4CR_15_1,
+- MSEL4CR_10_0, MSEL4CR_10_1,
+- MSEL4CR_6_0, MSEL4CR_6_1,
+- MSEL4CR_4_0, MSEL4CR_4_1,
+- MSEL4CR_1_0, MSEL4CR_1_1,
+-
+- MSEL5CR_31_0, MSEL5CR_31_1, /* irq/fiq output */
+- MSEL5CR_30_0, MSEL5CR_30_1,
+- MSEL5CR_29_0, MSEL5CR_29_1,
+- MSEL5CR_27_0, MSEL5CR_27_1,
+- MSEL5CR_25_0, MSEL5CR_25_1,
+- MSEL5CR_23_0, MSEL5CR_23_1,
+- MSEL5CR_21_0, MSEL5CR_21_1,
+- MSEL5CR_19_0, MSEL5CR_19_1,
+- MSEL5CR_17_0, MSEL5CR_17_1,
+- MSEL5CR_15_0, MSEL5CR_15_1,
+- MSEL5CR_14_0, MSEL5CR_14_1,
+- MSEL5CR_13_0, MSEL5CR_13_1,
+- MSEL5CR_12_0, MSEL5CR_12_1,
+- MSEL5CR_11_0, MSEL5CR_11_1,
+- MSEL5CR_10_0, MSEL5CR_10_1,
+- MSEL5CR_8_0, MSEL5CR_8_1,
+- MSEL5CR_7_0, MSEL5CR_7_1,
+- MSEL5CR_6_0, MSEL5CR_6_1,
+- MSEL5CR_5_0, MSEL5CR_5_1,
+- MSEL5CR_4_0, MSEL5CR_4_1,
+- MSEL5CR_3_0, MSEL5CR_3_1,
+- MSEL5CR_2_0, MSEL5CR_2_1,
+- MSEL5CR_0_0, MSEL5CR_0_1,
+- PINMUX_FUNCTION_END,
+-
+- PINMUX_MARK_BEGIN,
+-
+- /* IRQ */
+- IRQ0_PORT2_MARK, IRQ0_PORT13_MARK,
+- IRQ1_MARK,
+- IRQ2_PORT11_MARK, IRQ2_PORT12_MARK,
+- IRQ3_PORT10_MARK, IRQ3_PORT14_MARK,
+- IRQ4_PORT15_MARK, IRQ4_PORT172_MARK,
+- IRQ5_PORT0_MARK, IRQ5_PORT1_MARK,
+- IRQ6_PORT121_MARK, IRQ6_PORT173_MARK,
+- IRQ7_PORT120_MARK, IRQ7_PORT209_MARK,
+- IRQ8_MARK,
+- IRQ9_PORT118_MARK, IRQ9_PORT210_MARK,
+- IRQ10_MARK,
+- IRQ11_MARK,
+- IRQ12_PORT42_MARK, IRQ12_PORT97_MARK,
+- IRQ13_PORT64_MARK, IRQ13_PORT98_MARK,
+- IRQ14_PORT63_MARK, IRQ14_PORT99_MARK,
+- IRQ15_PORT62_MARK, IRQ15_PORT100_MARK,
+- IRQ16_PORT68_MARK, IRQ16_PORT211_MARK,
+- IRQ17_MARK,
+- IRQ18_MARK,
+- IRQ19_MARK,
+- IRQ20_MARK,
+- IRQ21_MARK,
+- IRQ22_MARK,
+- IRQ23_MARK,
+- IRQ24_MARK,
+- IRQ25_MARK,
+- IRQ26_PORT58_MARK, IRQ26_PORT81_MARK,
+- IRQ27_PORT57_MARK, IRQ27_PORT168_MARK,
+- IRQ28_PORT56_MARK, IRQ28_PORT169_MARK,
+- IRQ29_PORT50_MARK, IRQ29_PORT170_MARK,
+- IRQ30_PORT49_MARK, IRQ30_PORT171_MARK,
+- IRQ31_PORT41_MARK, IRQ31_PORT167_MARK,
+-
+- /* Function */
+-
+- /* DBGT */
+- DBGMDT2_MARK, DBGMDT1_MARK, DBGMDT0_MARK,
+- DBGMD10_MARK, DBGMD11_MARK, DBGMD20_MARK,
+- DBGMD21_MARK,
+-
+- /* FSI */
+- FSIAISLD_PORT0_MARK, /* FSIAISLD Port 0/5 */
+- FSIAISLD_PORT5_MARK,
+- FSIASPDIF_PORT9_MARK, /* FSIASPDIF Port 9/18 */
+- FSIASPDIF_PORT18_MARK,
+- FSIAOSLD1_MARK, FSIAOSLD2_MARK, FSIAOLR_MARK,
+- FSIAOBT_MARK, FSIAOSLD_MARK, FSIAOMC_MARK,
+- FSIACK_MARK, FSIAILR_MARK, FSIAIBT_MARK,
+-
+- /* FMSI */
+- FMSISLD_PORT1_MARK, /* FMSISLD Port 1/6 */
+- FMSISLD_PORT6_MARK,
+- FMSIILR_MARK, FMSIIBT_MARK, FMSIOLR_MARK, FMSIOBT_MARK,
+- FMSICK_MARK, FMSOILR_MARK, FMSOIBT_MARK, FMSOOLR_MARK,
+- FMSOOBT_MARK, FMSOSLD_MARK, FMSOCK_MARK,
+-
+- /* SCIFA0 */
+- SCIFA0_SCK_MARK, SCIFA0_CTS_MARK, SCIFA0_RTS_MARK,
+- SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
+-
+- /* SCIFA1 */
+- SCIFA1_CTS_MARK, SCIFA1_SCK_MARK, SCIFA1_RXD_MARK,
+- SCIFA1_TXD_MARK, SCIFA1_RTS_MARK,
+-
+- /* SCIFA2 */
+- SCIFA2_SCK_PORT22_MARK, /* SCIFA2_SCK Port 22/199 */
+- SCIFA2_SCK_PORT199_MARK,
+- SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
+- SCIFA2_CTS_MARK, SCIFA2_RTS_MARK,
+-
+- /* SCIFA3 */
+- SCIFA3_RTS_PORT105_MARK, /* MSEL5CR_8_0 */
+- SCIFA3_SCK_PORT116_MARK,
+- SCIFA3_CTS_PORT117_MARK,
+- SCIFA3_RXD_PORT174_MARK,
+- SCIFA3_TXD_PORT175_MARK,
+-
+- SCIFA3_RTS_PORT161_MARK, /* MSEL5CR_8_1 */
+- SCIFA3_SCK_PORT158_MARK,
+- SCIFA3_CTS_PORT162_MARK,
+- SCIFA3_RXD_PORT159_MARK,
+- SCIFA3_TXD_PORT160_MARK,
+-
+- /* SCIFA4 */
+- SCIFA4_RXD_PORT12_MARK, /* MSEL5CR[12:11] = 00 */
+- SCIFA4_TXD_PORT13_MARK,
+-
+- SCIFA4_RXD_PORT204_MARK, /* MSEL5CR[12:11] = 01 */
+- SCIFA4_TXD_PORT203_MARK,
+-
+- SCIFA4_RXD_PORT94_MARK, /* MSEL5CR[12:11] = 10 */
+- SCIFA4_TXD_PORT93_MARK,
+-
+- SCIFA4_SCK_PORT21_MARK, /* SCIFA4_SCK Port 21/205 */
+- SCIFA4_SCK_PORT205_MARK,
+-
+- /* SCIFA5 */
+- SCIFA5_TXD_PORT20_MARK, /* MSEL5CR[15:14] = 00 */
+- SCIFA5_RXD_PORT10_MARK,
+-
+- SCIFA5_RXD_PORT207_MARK, /* MSEL5CR[15:14] = 01 */
+- SCIFA5_TXD_PORT208_MARK,
+-
+- SCIFA5_TXD_PORT91_MARK, /* MSEL5CR[15:14] = 10 */
+- SCIFA5_RXD_PORT92_MARK,
+-
+- SCIFA5_SCK_PORT23_MARK, /* SCIFA5_SCK Port 23/206 */
+- SCIFA5_SCK_PORT206_MARK,
+-
+- /* SCIFA6 */
+- SCIFA6_SCK_MARK, SCIFA6_RXD_MARK, SCIFA6_TXD_MARK,
+-
+- /* SCIFA7 */
+- SCIFA7_TXD_MARK, SCIFA7_RXD_MARK,
+-
+- /* SCIFAB */
+- SCIFB_SCK_PORT190_MARK, /* MSEL5CR_17_0 */
+- SCIFB_RXD_PORT191_MARK,
+- SCIFB_TXD_PORT192_MARK,
+- SCIFB_RTS_PORT186_MARK,
+- SCIFB_CTS_PORT187_MARK,
+-
+- SCIFB_SCK_PORT2_MARK, /* MSEL5CR_17_1 */
+- SCIFB_RXD_PORT3_MARK,
+- SCIFB_TXD_PORT4_MARK,
+- SCIFB_RTS_PORT172_MARK,
+- SCIFB_CTS_PORT173_MARK,
+-
+- /* LCD0 */
+- LCDC0_SELECT_MARK,
+-
+- LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
+- LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
+- LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
+- LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
+- LCD0_D16_MARK, LCD0_D17_MARK,
+- LCD0_DON_MARK, LCD0_VCPWC_MARK, LCD0_VEPWC_MARK,
+- LCD0_DCK_MARK, LCD0_VSYN_MARK, /* for RGB */
+- LCD0_HSYN_MARK, LCD0_DISP_MARK, /* for RGB */
+- LCD0_WR_MARK, LCD0_RD_MARK, /* for SYS */
+- LCD0_CS_MARK, LCD0_RS_MARK, /* for SYS */
+-
+- LCD0_D21_PORT158_MARK, LCD0_D23_PORT159_MARK, /* MSEL5CR_6_1 */
+- LCD0_D22_PORT160_MARK, LCD0_D20_PORT161_MARK,
+- LCD0_D19_PORT162_MARK, LCD0_D18_PORT163_MARK,
+- LCD0_LCLK_PORT165_MARK,
+-
+- LCD0_D18_PORT40_MARK, LCD0_D22_PORT0_MARK, /* MSEL5CR_6_0 */
+- LCD0_D23_PORT1_MARK, LCD0_D21_PORT2_MARK,
+- LCD0_D20_PORT3_MARK, LCD0_D19_PORT4_MARK,
+- LCD0_LCLK_PORT102_MARK,
+-
+- /* LCD1 */
+- LCDC1_SELECT_MARK,
+-
+- LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
+- LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
+- LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
+- LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
+- LCD1_D16_MARK, LCD1_D17_MARK, LCD1_D18_MARK, LCD1_D19_MARK,
+- LCD1_D20_MARK, LCD1_D21_MARK, LCD1_D22_MARK, LCD1_D23_MARK,
+- LCD1_DON_MARK, LCD1_VCPWC_MARK,
+- LCD1_LCLK_MARK, LCD1_VEPWC_MARK,
+-
+- LCD1_DCK_MARK, LCD1_VSYN_MARK, /* for RGB */
+- LCD1_HSYN_MARK, LCD1_DISP_MARK, /* for RGB */
+- LCD1_RS_MARK, LCD1_CS_MARK, /* for SYS */
+- LCD1_RD_MARK, LCD1_WR_MARK, /* for SYS */
+-
+- /* RSPI */
+- RSPI_SSL0_A_MARK, RSPI_SSL1_A_MARK, RSPI_SSL2_A_MARK,
+- RSPI_SSL3_A_MARK, RSPI_CK_A_MARK, RSPI_MOSI_A_MARK,
+- RSPI_MISO_A_MARK,
+-
+- /* VIO CKO */
+- VIO_CKO1_MARK, /* needs fixup */
+- VIO_CKO2_MARK,
+- VIO_CKO_1_MARK,
+- VIO_CKO_MARK,
+-
+- /* VIO0 */
+- VIO0_D0_MARK, VIO0_D1_MARK, VIO0_D2_MARK, VIO0_D3_MARK,
+- VIO0_D4_MARK, VIO0_D5_MARK, VIO0_D6_MARK, VIO0_D7_MARK,
+- VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
+- VIO0_D12_MARK, VIO0_VD_MARK, VIO0_HD_MARK, VIO0_CLK_MARK,
+- VIO0_FIELD_MARK,
+-
+- VIO0_D13_PORT26_MARK, /* MSEL5CR_27_0 */
+- VIO0_D14_PORT25_MARK,
+- VIO0_D15_PORT24_MARK,
+-
+- VIO0_D13_PORT22_MARK, /* MSEL5CR_27_1 */
+- VIO0_D14_PORT95_MARK,
+- VIO0_D15_PORT96_MARK,
+-
+- /* VIO1 */
+- VIO1_D0_MARK, VIO1_D1_MARK, VIO1_D2_MARK, VIO1_D3_MARK,
+- VIO1_D4_MARK, VIO1_D5_MARK, VIO1_D6_MARK, VIO1_D7_MARK,
+- VIO1_VD_MARK, VIO1_HD_MARK, VIO1_CLK_MARK, VIO1_FIELD_MARK,
+-
+- /* TPU0 */
+- TPU0TO0_MARK, TPU0TO1_MARK, TPU0TO3_MARK,
+- TPU0TO2_PORT66_MARK, /* TPU0TO2 Port 66/202 */
+- TPU0TO2_PORT202_MARK,
+-
+- /* SSP1 0 */
+- STP0_IPD0_MARK, STP0_IPD1_MARK, STP0_IPD2_MARK, STP0_IPD3_MARK,
+- STP0_IPD4_MARK, STP0_IPD5_MARK, STP0_IPD6_MARK, STP0_IPD7_MARK,
+- STP0_IPEN_MARK, STP0_IPCLK_MARK, STP0_IPSYNC_MARK,
+-
+- /* SSP1 1 */
+- STP1_IPD1_MARK, STP1_IPD2_MARK, STP1_IPD3_MARK, STP1_IPD4_MARK,
+- STP1_IPD5_MARK, STP1_IPD6_MARK, STP1_IPD7_MARK, STP1_IPCLK_MARK,
+- STP1_IPSYNC_MARK,
+-
+- STP1_IPD0_PORT186_MARK, /* MSEL5CR_23_0 */
+- STP1_IPEN_PORT187_MARK,
+-
+- STP1_IPD0_PORT194_MARK, /* MSEL5CR_23_1 */
+- STP1_IPEN_PORT193_MARK,
+-
+- /* SIM */
+- SIM_RST_MARK, SIM_CLK_MARK,
+- SIM_D_PORT22_MARK, /* SIM_D Port 22/199 */
+- SIM_D_PORT199_MARK,
+-
+- /* SDHI0 */
+- SDHI0_D0_MARK, SDHI0_D1_MARK, SDHI0_D2_MARK, SDHI0_D3_MARK,
+- SDHI0_CD_MARK, SDHI0_WP_MARK, SDHI0_CMD_MARK, SDHI0_CLK_MARK,
+-
+- /* SDHI1 */
+- SDHI1_D0_MARK, SDHI1_D1_MARK, SDHI1_D2_MARK, SDHI1_D3_MARK,
+- SDHI1_CD_MARK, SDHI1_WP_MARK, SDHI1_CMD_MARK, SDHI1_CLK_MARK,
+-
+- /* SDHI2 */
+- SDHI2_D0_MARK, SDHI2_D1_MARK, SDHI2_D2_MARK, SDHI2_D3_MARK,
+- SDHI2_CLK_MARK, SDHI2_CMD_MARK,
+-
+- SDHI2_CD_PORT24_MARK, /* MSEL5CR_19_0 */
+- SDHI2_WP_PORT25_MARK,
+-
+- SDHI2_WP_PORT177_MARK, /* MSEL5CR_19_1 */
+- SDHI2_CD_PORT202_MARK,
+-
+- /* MSIOF2 */
+- MSIOF2_TXD_MARK, MSIOF2_RXD_MARK, MSIOF2_TSCK_MARK,
+- MSIOF2_SS2_MARK, MSIOF2_TSYNC_MARK, MSIOF2_SS1_MARK,
+- MSIOF2_MCK1_MARK, MSIOF2_MCK0_MARK, MSIOF2_RSYNC_MARK,
+- MSIOF2_RSCK_MARK,
+-
+- /* KEYSC */
+- KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK, KEYIN7_MARK,
+- KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
+- KEYOUT4_MARK, KEYOUT5_MARK, KEYOUT6_MARK, KEYOUT7_MARK,
+-
+- KEYIN0_PORT43_MARK, /* MSEL4CR_18_0 */
+- KEYIN1_PORT44_MARK,
+- KEYIN2_PORT45_MARK,
+- KEYIN3_PORT46_MARK,
+-
+- KEYIN0_PORT58_MARK, /* MSEL4CR_18_1 */
+- KEYIN1_PORT57_MARK,
+- KEYIN2_PORT56_MARK,
+- KEYIN3_PORT55_MARK,
+-
+- /* VOU */
+- DV_D0_MARK, DV_D1_MARK, DV_D2_MARK, DV_D3_MARK,
+- DV_D4_MARK, DV_D5_MARK, DV_D6_MARK, DV_D7_MARK,
+- DV_D8_MARK, DV_D9_MARK, DV_D10_MARK, DV_D11_MARK,
+- DV_D12_MARK, DV_D13_MARK, DV_D14_MARK, DV_D15_MARK,
+- DV_CLK_MARK, DV_VSYNC_MARK, DV_HSYNC_MARK,
+-
+- /* MEMC */
+- MEMC_AD0_MARK, MEMC_AD1_MARK, MEMC_AD2_MARK, MEMC_AD3_MARK,
+- MEMC_AD4_MARK, MEMC_AD5_MARK, MEMC_AD6_MARK, MEMC_AD7_MARK,
+- MEMC_AD8_MARK, MEMC_AD9_MARK, MEMC_AD10_MARK, MEMC_AD11_MARK,
+- MEMC_AD12_MARK, MEMC_AD13_MARK, MEMC_AD14_MARK, MEMC_AD15_MARK,
+- MEMC_CS0_MARK, MEMC_INT_MARK, MEMC_NWE_MARK, MEMC_NOE_MARK,
+-
+- MEMC_CS1_MARK, /* MSEL4CR_6_0 */
+- MEMC_ADV_MARK,
+- MEMC_WAIT_MARK,
+- MEMC_BUSCLK_MARK,
+-
+- MEMC_A1_MARK, /* MSEL4CR_6_1 */
+- MEMC_DREQ0_MARK,
+- MEMC_DREQ1_MARK,
+- MEMC_A0_MARK,
+-
+- /* MMC */
+- MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK,
+- MMC0_D3_PORT71_MARK, MMC0_D4_PORT72_MARK, MMC0_D5_PORT73_MARK,
+- MMC0_D6_PORT74_MARK, MMC0_D7_PORT75_MARK, MMC0_CLK_PORT66_MARK,
+- MMC0_CMD_PORT67_MARK, /* MSEL4CR_15_0 */
+-
+- MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK,
+- MMC1_D3_PORT146_MARK, MMC1_D4_PORT145_MARK, MMC1_D5_PORT144_MARK,
+- MMC1_D6_PORT143_MARK, MMC1_D7_PORT142_MARK, MMC1_CLK_PORT103_MARK,
+- MMC1_CMD_PORT104_MARK, /* MSEL4CR_15_1 */
+-
+- /* MSIOF0 */
+- MSIOF0_SS1_MARK, MSIOF0_SS2_MARK, MSIOF0_RXD_MARK,
+- MSIOF0_TXD_MARK, MSIOF0_MCK0_MARK, MSIOF0_MCK1_MARK,
+- MSIOF0_RSYNC_MARK, MSIOF0_RSCK_MARK, MSIOF0_TSCK_MARK,
+- MSIOF0_TSYNC_MARK,
+-
+- /* MSIOF1 */
+- MSIOF1_RSCK_MARK, MSIOF1_RSYNC_MARK,
+- MSIOF1_MCK0_MARK, MSIOF1_MCK1_MARK,
+-
+- MSIOF1_SS2_PORT116_MARK, MSIOF1_SS1_PORT117_MARK,
+- MSIOF1_RXD_PORT118_MARK, MSIOF1_TXD_PORT119_MARK,
+- MSIOF1_TSYNC_PORT120_MARK,
+- MSIOF1_TSCK_PORT121_MARK, /* MSEL4CR_10_0 */
+-
+- MSIOF1_SS1_PORT67_MARK, MSIOF1_TSCK_PORT72_MARK,
+- MSIOF1_TSYNC_PORT73_MARK, MSIOF1_TXD_PORT74_MARK,
+- MSIOF1_RXD_PORT75_MARK,
+- MSIOF1_SS2_PORT202_MARK, /* MSEL4CR_10_1 */
+-
+- /* GPIO */
+- GPO0_MARK, GPI0_MARK, GPO1_MARK, GPI1_MARK,
+-
+- /* USB0 */
+- USB0_OCI_MARK, USB0_PPON_MARK, VBUS_MARK,
+-
+- /* USB1 */
+- USB1_OCI_MARK, USB1_PPON_MARK,
+-
+- /* BBIF1 */
+- BBIF1_RXD_MARK, BBIF1_TXD_MARK, BBIF1_TSYNC_MARK,
+- BBIF1_TSCK_MARK, BBIF1_RSCK_MARK, BBIF1_RSYNC_MARK,
+- BBIF1_FLOW_MARK, BBIF1_RX_FLOW_N_MARK,
+-
+- /* BBIF2 */
+- BBIF2_TXD2_PORT5_MARK, /* MSEL5CR_0_0 */
+- BBIF2_RXD2_PORT60_MARK,
+- BBIF2_TSYNC2_PORT6_MARK,
+- BBIF2_TSCK2_PORT59_MARK,
+-
+- BBIF2_RXD2_PORT90_MARK, /* MSEL5CR_0_1 */
+- BBIF2_TXD2_PORT183_MARK,
+- BBIF2_TSCK2_PORT89_MARK,
+- BBIF2_TSYNC2_PORT184_MARK,
+-
+- /* BSC / FLCTL / PCMCIA */
+- CS0_MARK, CS2_MARK, CS4_MARK,
+- CS5B_MARK, CS6A_MARK,
+- CS5A_PORT105_MARK, /* CS5A PORT 19/105 */
+- CS5A_PORT19_MARK,
+- IOIS16_MARK, /* ? */
+-
+- A0_MARK, A1_MARK, A2_MARK, A3_MARK,
+- A4_FOE_MARK, /* share with FLCTL */
+- A5_FCDE_MARK, /* share with FLCTL */
+- A6_MARK, A7_MARK, A8_MARK, A9_MARK,
+- A10_MARK, A11_MARK, A12_MARK, A13_MARK,
+- A14_MARK, A15_MARK, A16_MARK, A17_MARK,
+- A18_MARK, A19_MARK, A20_MARK, A21_MARK,
+- A22_MARK, A23_MARK, A24_MARK, A25_MARK,
+- A26_MARK,
+-
+- D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, /* share with FLCTL */
+- D3_NAF3_MARK, D4_NAF4_MARK, D5_NAF5_MARK, /* share with FLCTL */
+- D6_NAF6_MARK, D7_NAF7_MARK, D8_NAF8_MARK, /* share with FLCTL */
+- D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK, /* share with FLCTL */
+- D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, /* share with FLCTL */
+- D15_NAF15_MARK, /* share with FLCTL */
+- D16_MARK, D17_MARK, D18_MARK, D19_MARK,
+- D20_MARK, D21_MARK, D22_MARK, D23_MARK,
+- D24_MARK, D25_MARK, D26_MARK, D27_MARK,
+- D28_MARK, D29_MARK, D30_MARK, D31_MARK,
+-
+- WE0_FWE_MARK, /* share with FLCTL */
+- WE1_MARK,
+- WE2_ICIORD_MARK, /* share with PCMCIA */
+- WE3_ICIOWR_MARK, /* share with PCMCIA */
+- CKO_MARK, BS_MARK, RDWR_MARK,
+- RD_FSC_MARK, /* share with FLCTL */
+- WAIT_PORT177_MARK, /* WAIT Port 90/177 */
+- WAIT_PORT90_MARK,
+-
+- FCE0_MARK, FCE1_MARK, FRB_MARK, /* FLCTL */
+-
+- /* IRDA */
+- IRDA_FIRSEL_MARK, IRDA_IN_MARK, IRDA_OUT_MARK,
+-
+- /* ATAPI */
+- IDE_D0_MARK, IDE_D1_MARK, IDE_D2_MARK, IDE_D3_MARK,
+- IDE_D4_MARK, IDE_D5_MARK, IDE_D6_MARK, IDE_D7_MARK,
+- IDE_D8_MARK, IDE_D9_MARK, IDE_D10_MARK, IDE_D11_MARK,
+- IDE_D12_MARK, IDE_D13_MARK, IDE_D14_MARK, IDE_D15_MARK,
+- IDE_A0_MARK, IDE_A1_MARK, IDE_A2_MARK, IDE_CS0_MARK,
+- IDE_CS1_MARK, IDE_IOWR_MARK, IDE_IORD_MARK, IDE_IORDY_MARK,
+- IDE_INT_MARK, IDE_RST_MARK, IDE_DIRECTION_MARK,
+- IDE_EXBUF_ENB_MARK, IDE_IODACK_MARK, IDE_IODREQ_MARK,
+-
+- /* RMII */
+- RMII_CRS_DV_MARK, RMII_RX_ER_MARK, RMII_RXD0_MARK,
+- RMII_RXD1_MARK, RMII_TX_EN_MARK, RMII_TXD0_MARK,
+- RMII_MDC_MARK, RMII_TXD1_MARK, RMII_MDIO_MARK,
+- RMII_REF50CK_MARK, /* for RMII */
+- RMII_REF125CK_MARK, /* for GMII */
+-
+- /* GEther */
+- ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_ETXD0_MARK, ET_ETXD1_MARK,
+- ET_ETXD2_MARK, ET_ETXD3_MARK,
+- ET_ETXD4_MARK, ET_ETXD5_MARK, /* for GEther */
+- ET_ETXD6_MARK, ET_ETXD7_MARK, /* for GEther */
+- ET_COL_MARK, ET_TX_ER_MARK, ET_RX_CLK_MARK, ET_RX_DV_MARK,
+- ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
+- ET_ERXD4_MARK, ET_ERXD5_MARK, /* for GEther */
+- ET_ERXD6_MARK, ET_ERXD7_MARK, /* for GEther */
+- ET_RX_ER_MARK, ET_CRS_MARK, ET_MDC_MARK, ET_MDIO_MARK,
+- ET_LINK_MARK, ET_PHY_INT_MARK, ET_WOL_MARK, ET_GTX_CLK_MARK,
+-
+- /* DMA0 */
+- DREQ0_MARK, DACK0_MARK,
+-
+- /* DMA1 */
+- DREQ1_MARK, DACK1_MARK,
+-
+- /* SYSC */
+- RESETOUTS_MARK, RESETP_PULLUP_MARK, RESETP_PLAIN_MARK,
+-
+- /* IRREM */
+- IROUT_MARK,
+-
+- /* SDENC */
+- SDENC_CPG_MARK, SDENC_DV_CLKI_MARK,
+-
+- /* DEBUG */
+- EDEBGREQ_PULLUP_MARK, /* for JTAG */
+- EDEBGREQ_PULLDOWN_MARK,
+-
+- TRACEAUD_FROM_VIO_MARK, /* for TRACE/AUD */
+- TRACEAUD_FROM_LCDC0_MARK,
+- TRACEAUD_FROM_MEMC_MARK,
+-
+- PINMUX_MARK_END,
+-};
+-
+-static unsigned short pinmux_data[] = {
+- /* specify valid pin states for each pin in GPIO mode */
+-
+- /* I/O and Pull U/D */
+- PORT_DATA_IO_PD(0), PORT_DATA_IO_PD(1),
+- PORT_DATA_IO_PD(2), PORT_DATA_IO_PD(3),
+- PORT_DATA_IO_PD(4), PORT_DATA_IO_PD(5),
+- PORT_DATA_IO_PD(6), PORT_DATA_IO(7),
+- PORT_DATA_IO(8), PORT_DATA_IO(9),
+-
+- PORT_DATA_IO_PD(10), PORT_DATA_IO_PD(11),
+- PORT_DATA_IO_PD(12), PORT_DATA_IO_PU_PD(13),
+- PORT_DATA_IO_PD(14), PORT_DATA_IO_PD(15),
+- PORT_DATA_IO_PD(16), PORT_DATA_IO_PD(17),
+- PORT_DATA_IO(18), PORT_DATA_IO_PU(19),
+-
+- PORT_DATA_IO_PU_PD(20), PORT_DATA_IO_PD(21),
+- PORT_DATA_IO_PU_PD(22), PORT_DATA_IO(23),
+- PORT_DATA_IO_PU(24), PORT_DATA_IO_PU(25),
+- PORT_DATA_IO_PU(26), PORT_DATA_IO_PU(27),
+- PORT_DATA_IO_PU(28), PORT_DATA_IO_PU(29),
+-
+- PORT_DATA_IO_PU(30), PORT_DATA_IO_PD(31),
+- PORT_DATA_IO_PD(32), PORT_DATA_IO_PD(33),
+- PORT_DATA_IO_PD(34), PORT_DATA_IO_PU(35),
+- PORT_DATA_IO_PU(36), PORT_DATA_IO_PD(37),
+- PORT_DATA_IO_PU(38), PORT_DATA_IO_PD(39),
+-
+- PORT_DATA_IO_PU_PD(40), PORT_DATA_IO_PD(41),
+- PORT_DATA_IO_PD(42), PORT_DATA_IO_PU_PD(43),
+- PORT_DATA_IO_PU_PD(44), PORT_DATA_IO_PU_PD(45),
+- PORT_DATA_IO_PU_PD(46), PORT_DATA_IO_PU_PD(47),
+- PORT_DATA_IO_PU_PD(48), PORT_DATA_IO_PU_PD(49),
+-
+- PORT_DATA_IO_PU_PD(50), PORT_DATA_IO_PD(51),
+- PORT_DATA_IO_PD(52), PORT_DATA_IO_PD(53),
+- PORT_DATA_IO_PD(54), PORT_DATA_IO_PU_PD(55),
+- PORT_DATA_IO_PU_PD(56), PORT_DATA_IO_PU_PD(57),
+- PORT_DATA_IO_PU_PD(58), PORT_DATA_IO_PU_PD(59),
+-
+- PORT_DATA_IO_PU_PD(60), PORT_DATA_IO_PD(61),
+- PORT_DATA_IO_PD(62), PORT_DATA_IO_PD(63),
+- PORT_DATA_IO_PD(64), PORT_DATA_IO_PD(65),
+- PORT_DATA_IO_PU_PD(66), PORT_DATA_IO_PU_PD(67),
+- PORT_DATA_IO_PU_PD(68), PORT_DATA_IO_PU_PD(69),
+-
+- PORT_DATA_IO_PU_PD(70), PORT_DATA_IO_PU_PD(71),
+- PORT_DATA_IO_PU_PD(72), PORT_DATA_IO_PU_PD(73),
+- PORT_DATA_IO_PU_PD(74), PORT_DATA_IO_PU_PD(75),
+- PORT_DATA_IO_PU_PD(76), PORT_DATA_IO_PU_PD(77),
+- PORT_DATA_IO_PU_PD(78), PORT_DATA_IO_PU_PD(79),
+-
+- PORT_DATA_IO_PU_PD(80), PORT_DATA_IO_PU_PD(81),
+- PORT_DATA_IO(82), PORT_DATA_IO_PU_PD(83),
+- PORT_DATA_IO(84), PORT_DATA_IO_PD(85),
+- PORT_DATA_IO_PD(86), PORT_DATA_IO_PD(87),
+- PORT_DATA_IO_PD(88), PORT_DATA_IO_PD(89),
+-
+- PORT_DATA_IO_PD(90), PORT_DATA_IO_PU_PD(91),
+- PORT_DATA_IO_PU_PD(92), PORT_DATA_IO_PU_PD(93),
+- PORT_DATA_IO_PU_PD(94), PORT_DATA_IO_PU_PD(95),
+- PORT_DATA_IO_PU_PD(96), PORT_DATA_IO_PU_PD(97),
+- PORT_DATA_IO_PU_PD(98), PORT_DATA_IO_PU_PD(99),
+-
+- PORT_DATA_IO_PU_PD(100), PORT_DATA_IO(101),
+- PORT_DATA_IO_PU(102), PORT_DATA_IO_PU_PD(103),
+- PORT_DATA_IO_PU(104), PORT_DATA_IO_PU(105),
+- PORT_DATA_IO_PU_PD(106), PORT_DATA_IO(107),
+- PORT_DATA_IO(108), PORT_DATA_IO(109),
+-
+- PORT_DATA_IO(110), PORT_DATA_IO(111),
+- PORT_DATA_IO(112), PORT_DATA_IO(113),
+- PORT_DATA_IO_PU_PD(114), PORT_DATA_IO(115),
+- PORT_DATA_IO_PD(116), PORT_DATA_IO_PD(117),
+- PORT_DATA_IO_PD(118), PORT_DATA_IO_PD(119),
+-
+- PORT_DATA_IO_PD(120), PORT_DATA_IO_PD(121),
+- PORT_DATA_IO_PD(122), PORT_DATA_IO_PD(123),
+- PORT_DATA_IO_PD(124), PORT_DATA_IO(125),
+- PORT_DATA_IO(126), PORT_DATA_IO(127),
+- PORT_DATA_IO(128), PORT_DATA_IO(129),
+-
+- PORT_DATA_IO(130), PORT_DATA_IO(131),
+- PORT_DATA_IO(132), PORT_DATA_IO(133),
+- PORT_DATA_IO(134), PORT_DATA_IO(135),
+- PORT_DATA_IO(136), PORT_DATA_IO(137),
+- PORT_DATA_IO(138), PORT_DATA_IO(139),
+-
+- PORT_DATA_IO(140), PORT_DATA_IO(141),
+- PORT_DATA_IO_PU(142), PORT_DATA_IO_PU(143),
+- PORT_DATA_IO_PU(144), PORT_DATA_IO_PU(145),
+- PORT_DATA_IO_PU(146), PORT_DATA_IO_PU(147),
+- PORT_DATA_IO_PU(148), PORT_DATA_IO_PU(149),
+-
+- PORT_DATA_IO_PU(150), PORT_DATA_IO_PU(151),
+- PORT_DATA_IO_PU(152), PORT_DATA_IO_PU(153),
+- PORT_DATA_IO_PU(154), PORT_DATA_IO_PU(155),
+- PORT_DATA_IO_PU(156), PORT_DATA_IO_PU(157),
+- PORT_DATA_IO_PD(158), PORT_DATA_IO_PD(159),
+-
+- PORT_DATA_IO_PU_PD(160), PORT_DATA_IO_PD(161),
+- PORT_DATA_IO_PD(162), PORT_DATA_IO_PD(163),
+- PORT_DATA_IO_PD(164), PORT_DATA_IO_PD(165),
+- PORT_DATA_IO_PU(166), PORT_DATA_IO_PU(167),
+- PORT_DATA_IO_PU(168), PORT_DATA_IO_PU(169),
+-
+- PORT_DATA_IO_PU(170), PORT_DATA_IO_PU(171),
+- PORT_DATA_IO_PD(172), PORT_DATA_IO_PD(173),
+- PORT_DATA_IO_PD(174), PORT_DATA_IO_PD(175),
+- PORT_DATA_IO_PU(176), PORT_DATA_IO_PU_PD(177),
+- PORT_DATA_IO_PU(178), PORT_DATA_IO_PD(179),
+-
+- PORT_DATA_IO_PD(180), PORT_DATA_IO_PU(181),
+- PORT_DATA_IO_PU(182), PORT_DATA_IO(183),
+- PORT_DATA_IO_PD(184), PORT_DATA_IO_PD(185),
+- PORT_DATA_IO_PD(186), PORT_DATA_IO_PD(187),
+- PORT_DATA_IO_PD(188), PORT_DATA_IO_PD(189),
+-
+- PORT_DATA_IO_PD(190), PORT_DATA_IO_PD(191),
+- PORT_DATA_IO_PD(192), PORT_DATA_IO_PU_PD(193),
+- PORT_DATA_IO_PU_PD(194), PORT_DATA_IO_PD(195),
+- PORT_DATA_IO_PU_PD(196), PORT_DATA_IO_PD(197),
+- PORT_DATA_IO_PU_PD(198), PORT_DATA_IO_PU_PD(199),
+-
+- PORT_DATA_IO_PU_PD(200), PORT_DATA_IO_PU(201),
+- PORT_DATA_IO_PU_PD(202), PORT_DATA_IO(203),
+- PORT_DATA_IO_PU_PD(204), PORT_DATA_IO_PU_PD(205),
+- PORT_DATA_IO_PU_PD(206), PORT_DATA_IO_PU_PD(207),
+- PORT_DATA_IO_PU_PD(208), PORT_DATA_IO_PD(209),
+-
+- PORT_DATA_IO_PD(210), PORT_DATA_IO_PD(211),
+-
+- /* Port0 */
+- PINMUX_DATA(DBGMDT2_MARK, PORT0_FN1),
+- PINMUX_DATA(FSIAISLD_PORT0_MARK, PORT0_FN2, MSEL5CR_3_0),
+- PINMUX_DATA(FSIAOSLD1_MARK, PORT0_FN3),
+- PINMUX_DATA(LCD0_D22_PORT0_MARK, PORT0_FN4, MSEL5CR_6_0),
+- PINMUX_DATA(SCIFA7_RXD_MARK, PORT0_FN6),
+- PINMUX_DATA(LCD1_D4_MARK, PORT0_FN7),
+- PINMUX_DATA(IRQ5_PORT0_MARK, PORT0_FN0, MSEL1CR_5_0),
+-
+- /* Port1 */
+- PINMUX_DATA(DBGMDT1_MARK, PORT1_FN1),
+- PINMUX_DATA(FMSISLD_PORT1_MARK, PORT1_FN2, MSEL5CR_5_0),
+- PINMUX_DATA(FSIAOSLD2_MARK, PORT1_FN3),
+- PINMUX_DATA(LCD0_D23_PORT1_MARK, PORT1_FN4, MSEL5CR_6_0),
+- PINMUX_DATA(SCIFA7_TXD_MARK, PORT1_FN6),
+- PINMUX_DATA(LCD1_D3_MARK, PORT1_FN7),
+- PINMUX_DATA(IRQ5_PORT1_MARK, PORT1_FN0, MSEL1CR_5_1),
+-
+- /* Port2 */
+- PINMUX_DATA(DBGMDT0_MARK, PORT2_FN1),
+- PINMUX_DATA(SCIFB_SCK_PORT2_MARK, PORT2_FN2, MSEL5CR_17_1),
+- PINMUX_DATA(LCD0_D21_PORT2_MARK, PORT2_FN4, MSEL5CR_6_0),
+- PINMUX_DATA(LCD1_D2_MARK, PORT2_FN7),
+- PINMUX_DATA(IRQ0_PORT2_MARK, PORT2_FN0, MSEL1CR_0_1),
+-
+- /* Port3 */
+- PINMUX_DATA(DBGMD21_MARK, PORT3_FN1),
+- PINMUX_DATA(SCIFB_RXD_PORT3_MARK, PORT3_FN2, MSEL5CR_17_1),
+- PINMUX_DATA(LCD0_D20_PORT3_MARK, PORT3_FN4, MSEL5CR_6_0),
+- PINMUX_DATA(LCD1_D1_MARK, PORT3_FN7),
+-
+- /* Port4 */
+- PINMUX_DATA(DBGMD20_MARK, PORT4_FN1),
+- PINMUX_DATA(SCIFB_TXD_PORT4_MARK, PORT4_FN2, MSEL5CR_17_1),
+- PINMUX_DATA(LCD0_D19_PORT4_MARK, PORT4_FN4, MSEL5CR_6_0),
+- PINMUX_DATA(LCD1_D0_MARK, PORT4_FN7),
+-
+- /* Port5 */
+- PINMUX_DATA(DBGMD11_MARK, PORT5_FN1),
+- PINMUX_DATA(BBIF2_TXD2_PORT5_MARK, PORT5_FN2, MSEL5CR_0_0),
+- PINMUX_DATA(FSIAISLD_PORT5_MARK, PORT5_FN4, MSEL5CR_3_1),
+- PINMUX_DATA(RSPI_SSL0_A_MARK, PORT5_FN6),
+- PINMUX_DATA(LCD1_VCPWC_MARK, PORT5_FN7),
+-
+- /* Port6 */
+- PINMUX_DATA(DBGMD10_MARK, PORT6_FN1),
+- PINMUX_DATA(BBIF2_TSYNC2_PORT6_MARK, PORT6_FN2, MSEL5CR_0_0),
+- PINMUX_DATA(FMSISLD_PORT6_MARK, PORT6_FN4, MSEL5CR_5_1),
+- PINMUX_DATA(RSPI_SSL1_A_MARK, PORT6_FN6),
+- PINMUX_DATA(LCD1_VEPWC_MARK, PORT6_FN7),
+-
+- /* Port7 */
+- PINMUX_DATA(FSIAOLR_MARK, PORT7_FN1),
+-
+- /* Port8 */
+- PINMUX_DATA(FSIAOBT_MARK, PORT8_FN1),
+-
+- /* Port9 */
+- PINMUX_DATA(FSIAOSLD_MARK, PORT9_FN1),
+- PINMUX_DATA(FSIASPDIF_PORT9_MARK, PORT9_FN2, MSEL5CR_4_0),
+-
+- /* Port10 */
+- PINMUX_DATA(FSIAOMC_MARK, PORT10_FN1),
+- PINMUX_DATA(SCIFA5_RXD_PORT10_MARK, PORT10_FN3, MSEL5CR_14_0,
+- MSEL5CR_15_0),
+- PINMUX_DATA(IRQ3_PORT10_MARK, PORT10_FN0, MSEL1CR_3_0),
+-
+- /* Port11 */
+- PINMUX_DATA(FSIACK_MARK, PORT11_FN1),
+- PINMUX_DATA(IRQ2_PORT11_MARK, PORT11_FN0, MSEL1CR_2_0),
+-
+- /* Port12 */
+- PINMUX_DATA(FSIAILR_MARK, PORT12_FN1),
+- PINMUX_DATA(SCIFA4_RXD_PORT12_MARK, PORT12_FN2, MSEL5CR_12_0,
+- MSEL5CR_11_0),
+- PINMUX_DATA(LCD1_RS_MARK, PORT12_FN6),
+- PINMUX_DATA(LCD1_DISP_MARK, PORT12_FN7),
+- PINMUX_DATA(IRQ2_PORT12_MARK, PORT12_FN0, MSEL1CR_2_1),
+-
+- /* Port13 */
+- PINMUX_DATA(FSIAIBT_MARK, PORT13_FN1),
+- PINMUX_DATA(SCIFA4_TXD_PORT13_MARK, PORT13_FN2, MSEL5CR_12_0,
+- MSEL5CR_11_0),
+- PINMUX_DATA(LCD1_RD_MARK, PORT13_FN7),
+- PINMUX_DATA(IRQ0_PORT13_MARK, PORT13_FN0, MSEL1CR_0_0),
+-
+- /* Port14 */
+- PINMUX_DATA(FMSOILR_MARK, PORT14_FN1),
+- PINMUX_DATA(FMSIILR_MARK, PORT14_FN2),
+- PINMUX_DATA(VIO_CKO1_MARK, PORT14_FN3),
+- PINMUX_DATA(LCD1_D23_MARK, PORT14_FN7),
+- PINMUX_DATA(IRQ3_PORT14_MARK, PORT14_FN0, MSEL1CR_3_1),
+-
+- /* Port15 */
+- PINMUX_DATA(FMSOIBT_MARK, PORT15_FN1),
+- PINMUX_DATA(FMSIIBT_MARK, PORT15_FN2),
+- PINMUX_DATA(VIO_CKO2_MARK, PORT15_FN3),
+- PINMUX_DATA(LCD1_D22_MARK, PORT15_FN7),
+- PINMUX_DATA(IRQ4_PORT15_MARK, PORT15_FN0, MSEL1CR_4_0),
+-
+- /* Port16 */
+- PINMUX_DATA(FMSOOLR_MARK, PORT16_FN1),
+- PINMUX_DATA(FMSIOLR_MARK, PORT16_FN2),
+-
+- /* Port17 */
+- PINMUX_DATA(FMSOOBT_MARK, PORT17_FN1),
+- PINMUX_DATA(FMSIOBT_MARK, PORT17_FN2),
+-
+- /* Port18 */
+- PINMUX_DATA(FMSOSLD_MARK, PORT18_FN1),
+- PINMUX_DATA(FSIASPDIF_PORT18_MARK, PORT18_FN2, MSEL5CR_4_1),
+-
+- /* Port19 */
+- PINMUX_DATA(FMSICK_MARK, PORT19_FN1),
+- PINMUX_DATA(CS5A_PORT19_MARK, PORT19_FN7, MSEL5CR_2_1),
+- PINMUX_DATA(IRQ10_MARK, PORT19_FN0),
+-
+- /* Port20 */
+- PINMUX_DATA(FMSOCK_MARK, PORT20_FN1),
+- PINMUX_DATA(SCIFA5_TXD_PORT20_MARK, PORT20_FN3, MSEL5CR_15_0,
+- MSEL5CR_14_0),
+- PINMUX_DATA(IRQ1_MARK, PORT20_FN0),
+-
+- /* Port21 */
+- PINMUX_DATA(SCIFA1_CTS_MARK, PORT21_FN1),
+- PINMUX_DATA(SCIFA4_SCK_PORT21_MARK, PORT21_FN2, MSEL5CR_10_0),
+- PINMUX_DATA(TPU0TO1_MARK, PORT21_FN4),
+- PINMUX_DATA(VIO1_FIELD_MARK, PORT21_FN5),
+- PINMUX_DATA(STP0_IPD5_MARK, PORT21_FN6),
+- PINMUX_DATA(LCD1_D10_MARK, PORT21_FN7),
+-
+- /* Port22 */
+- PINMUX_DATA(SCIFA2_SCK_PORT22_MARK, PORT22_FN1, MSEL5CR_7_0),
+- PINMUX_DATA(SIM_D_PORT22_MARK, PORT22_FN4, MSEL5CR_21_0),
+- PINMUX_DATA(VIO0_D13_PORT22_MARK, PORT22_FN7, MSEL5CR_27_1),
+-
+- /* Port23 */
+- PINMUX_DATA(SCIFA1_RTS_MARK, PORT23_FN1),
+- PINMUX_DATA(SCIFA5_SCK_PORT23_MARK, PORT23_FN3, MSEL5CR_13_0),
+- PINMUX_DATA(TPU0TO0_MARK, PORT23_FN4),
+- PINMUX_DATA(VIO_CKO_1_MARK, PORT23_FN5),
+- PINMUX_DATA(STP0_IPD2_MARK, PORT23_FN6),
+- PINMUX_DATA(LCD1_D7_MARK, PORT23_FN7),
+-
+- /* Port24 */
+- PINMUX_DATA(VIO0_D15_PORT24_MARK, PORT24_FN1, MSEL5CR_27_0),
+- PINMUX_DATA(VIO1_D7_MARK, PORT24_FN5),
+- PINMUX_DATA(SCIFA6_SCK_MARK, PORT24_FN6),
+- PINMUX_DATA(SDHI2_CD_PORT24_MARK, PORT24_FN7, MSEL5CR_19_0),
+-
+- /* Port25 */
+- PINMUX_DATA(VIO0_D14_PORT25_MARK, PORT25_FN1, MSEL5CR_27_0),
+- PINMUX_DATA(VIO1_D6_MARK, PORT25_FN5),
+- PINMUX_DATA(SCIFA6_RXD_MARK, PORT25_FN6),
+- PINMUX_DATA(SDHI2_WP_PORT25_MARK, PORT25_FN7, MSEL5CR_19_0),
+-
+- /* Port26 */
+- PINMUX_DATA(VIO0_D13_PORT26_MARK, PORT26_FN1, MSEL5CR_27_0),
+- PINMUX_DATA(VIO1_D5_MARK, PORT26_FN5),
+- PINMUX_DATA(SCIFA6_TXD_MARK, PORT26_FN6),
+-
+- /* Port27 - Port39 Function */
+- PINMUX_DATA(VIO0_D7_MARK, PORT27_FN1),
+- PINMUX_DATA(VIO0_D6_MARK, PORT28_FN1),
+- PINMUX_DATA(VIO0_D5_MARK, PORT29_FN1),
+- PINMUX_DATA(VIO0_D4_MARK, PORT30_FN1),
+- PINMUX_DATA(VIO0_D3_MARK, PORT31_FN1),
+- PINMUX_DATA(VIO0_D2_MARK, PORT32_FN1),
+- PINMUX_DATA(VIO0_D1_MARK, PORT33_FN1),
+- PINMUX_DATA(VIO0_D0_MARK, PORT34_FN1),
+- PINMUX_DATA(VIO0_CLK_MARK, PORT35_FN1),
+- PINMUX_DATA(VIO_CKO_MARK, PORT36_FN1),
+- PINMUX_DATA(VIO0_HD_MARK, PORT37_FN1),
+- PINMUX_DATA(VIO0_FIELD_MARK, PORT38_FN1),
+- PINMUX_DATA(VIO0_VD_MARK, PORT39_FN1),
+-
+- /* Port38 IRQ */
+- PINMUX_DATA(IRQ25_MARK, PORT38_FN0),
+-
+- /* Port40 */
+- PINMUX_DATA(LCD0_D18_PORT40_MARK, PORT40_FN4, MSEL5CR_6_0),
+- PINMUX_DATA(RSPI_CK_A_MARK, PORT40_FN6),
+- PINMUX_DATA(LCD1_LCLK_MARK, PORT40_FN7),
+-
+- /* Port41 */
+- PINMUX_DATA(LCD0_D17_MARK, PORT41_FN1),
+- PINMUX_DATA(MSIOF2_SS1_MARK, PORT41_FN2),
+- PINMUX_DATA(IRQ31_PORT41_MARK, PORT41_FN0, MSEL1CR_31_1),
+-
+- /* Port42 */
+- PINMUX_DATA(LCD0_D16_MARK, PORT42_FN1),
+- PINMUX_DATA(MSIOF2_MCK1_MARK, PORT42_FN2),
+- PINMUX_DATA(IRQ12_PORT42_MARK, PORT42_FN0, MSEL1CR_12_1),
+-
+- /* Port43 */
+- PINMUX_DATA(LCD0_D15_MARK, PORT43_FN1),
+- PINMUX_DATA(MSIOF2_MCK0_MARK, PORT43_FN2),
+- PINMUX_DATA(KEYIN0_PORT43_MARK, PORT43_FN3, MSEL4CR_18_0),
+- PINMUX_DATA(DV_D15_MARK, PORT43_FN6),
+-
+- /* Port44 */
+- PINMUX_DATA(LCD0_D14_MARK, PORT44_FN1),
+- PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT44_FN2),
+- PINMUX_DATA(KEYIN1_PORT44_MARK, PORT44_FN3, MSEL4CR_18_0),
+- PINMUX_DATA(DV_D14_MARK, PORT44_FN6),
+-
+- /* Port45 */
+- PINMUX_DATA(LCD0_D13_MARK, PORT45_FN1),
+- PINMUX_DATA(MSIOF2_RSCK_MARK, PORT45_FN2),
+- PINMUX_DATA(KEYIN2_PORT45_MARK, PORT45_FN3, MSEL4CR_18_0),
+- PINMUX_DATA(DV_D13_MARK, PORT45_FN6),
+-
+- /* Port46 */
+- PINMUX_DATA(LCD0_D12_MARK, PORT46_FN1),
+- PINMUX_DATA(KEYIN3_PORT46_MARK, PORT46_FN3, MSEL4CR_18_0),
+- PINMUX_DATA(DV_D12_MARK, PORT46_FN6),
+-
+- /* Port47 */
+- PINMUX_DATA(LCD0_D11_MARK, PORT47_FN1),
+- PINMUX_DATA(KEYIN4_MARK, PORT47_FN3),
+- PINMUX_DATA(DV_D11_MARK, PORT47_FN6),
+-
+- /* Port48 */
+- PINMUX_DATA(LCD0_D10_MARK, PORT48_FN1),
+- PINMUX_DATA(KEYIN5_MARK, PORT48_FN3),
+- PINMUX_DATA(DV_D10_MARK, PORT48_FN6),
+-
+- /* Port49 */
+- PINMUX_DATA(LCD0_D9_MARK, PORT49_FN1),
+- PINMUX_DATA(KEYIN6_MARK, PORT49_FN3),
+- PINMUX_DATA(DV_D9_MARK, PORT49_FN6),
+- PINMUX_DATA(IRQ30_PORT49_MARK, PORT49_FN0, MSEL1CR_30_1),
+-
+- /* Port50 */
+- PINMUX_DATA(LCD0_D8_MARK, PORT50_FN1),
+- PINMUX_DATA(KEYIN7_MARK, PORT50_FN3),
+- PINMUX_DATA(DV_D8_MARK, PORT50_FN6),
+- PINMUX_DATA(IRQ29_PORT50_MARK, PORT50_FN0, MSEL1CR_29_1),
+-
+- /* Port51 */
+- PINMUX_DATA(LCD0_D7_MARK, PORT51_FN1),
+- PINMUX_DATA(KEYOUT0_MARK, PORT51_FN3),
+- PINMUX_DATA(DV_D7_MARK, PORT51_FN6),
+-
+- /* Port52 */
+- PINMUX_DATA(LCD0_D6_MARK, PORT52_FN1),
+- PINMUX_DATA(KEYOUT1_MARK, PORT52_FN3),
+- PINMUX_DATA(DV_D6_MARK, PORT52_FN6),
+-
+- /* Port53 */
+- PINMUX_DATA(LCD0_D5_MARK, PORT53_FN1),
+- PINMUX_DATA(KEYOUT2_MARK, PORT53_FN3),
+- PINMUX_DATA(DV_D5_MARK, PORT53_FN6),
+-
+- /* Port54 */
+- PINMUX_DATA(LCD0_D4_MARK, PORT54_FN1),
+- PINMUX_DATA(KEYOUT3_MARK, PORT54_FN3),
+- PINMUX_DATA(DV_D4_MARK, PORT54_FN6),
+-
+- /* Port55 */
+- PINMUX_DATA(LCD0_D3_MARK, PORT55_FN1),
+- PINMUX_DATA(KEYOUT4_MARK, PORT55_FN3),
+- PINMUX_DATA(KEYIN3_PORT55_MARK, PORT55_FN4, MSEL4CR_18_1),
+- PINMUX_DATA(DV_D3_MARK, PORT55_FN6),
+-
+- /* Port56 */
+- PINMUX_DATA(LCD0_D2_MARK, PORT56_FN1),
+- PINMUX_DATA(KEYOUT5_MARK, PORT56_FN3),
+- PINMUX_DATA(KEYIN2_PORT56_MARK, PORT56_FN4, MSEL4CR_18_1),
+- PINMUX_DATA(DV_D2_MARK, PORT56_FN6),
+- PINMUX_DATA(IRQ28_PORT56_MARK, PORT56_FN0, MSEL1CR_28_1),
+-
+- /* Port57 */
+- PINMUX_DATA(LCD0_D1_MARK, PORT57_FN1),
+- PINMUX_DATA(KEYOUT6_MARK, PORT57_FN3),
+- PINMUX_DATA(KEYIN1_PORT57_MARK, PORT57_FN4, MSEL4CR_18_1),
+- PINMUX_DATA(DV_D1_MARK, PORT57_FN6),
+- PINMUX_DATA(IRQ27_PORT57_MARK, PORT57_FN0, MSEL1CR_27_1),
+-
+- /* Port58 */
+- PINMUX_DATA(LCD0_D0_MARK, PORT58_FN1),
+- PINMUX_DATA(KEYOUT7_MARK, PORT58_FN3),
+- PINMUX_DATA(KEYIN0_PORT58_MARK, PORT58_FN4, MSEL4CR_18_1),
+- PINMUX_DATA(DV_D0_MARK, PORT58_FN6),
+- PINMUX_DATA(IRQ26_PORT58_MARK, PORT58_FN0, MSEL1CR_26_1),
+-
+- /* Port59 */
+- PINMUX_DATA(LCD0_VCPWC_MARK, PORT59_FN1),
+- PINMUX_DATA(BBIF2_TSCK2_PORT59_MARK, PORT59_FN2, MSEL5CR_0_0),
+- PINMUX_DATA(RSPI_MOSI_A_MARK, PORT59_FN6),
+-
+- /* Port60 */
+- PINMUX_DATA(LCD0_VEPWC_MARK, PORT60_FN1),
+- PINMUX_DATA(BBIF2_RXD2_PORT60_MARK, PORT60_FN2, MSEL5CR_0_0),
+- PINMUX_DATA(RSPI_MISO_A_MARK, PORT60_FN6),
+-
+- /* Port61 */
+- PINMUX_DATA(LCD0_DON_MARK, PORT61_FN1),
+- PINMUX_DATA(MSIOF2_TXD_MARK, PORT61_FN2),
+-
+- /* Port62 */
+- PINMUX_DATA(LCD0_DCK_MARK, PORT62_FN1),
+- PINMUX_DATA(LCD0_WR_MARK, PORT62_FN4),
+- PINMUX_DATA(DV_CLK_MARK, PORT62_FN6),
+- PINMUX_DATA(IRQ15_PORT62_MARK, PORT62_FN0, MSEL1CR_15_1),
+-
+- /* Port63 */
+- PINMUX_DATA(LCD0_VSYN_MARK, PORT63_FN1),
+- PINMUX_DATA(DV_VSYNC_MARK, PORT63_FN6),
+- PINMUX_DATA(IRQ14_PORT63_MARK, PORT63_FN0, MSEL1CR_14_1),
+-
+- /* Port64 */
+- PINMUX_DATA(LCD0_HSYN_MARK, PORT64_FN1),
+- PINMUX_DATA(LCD0_CS_MARK, PORT64_FN4),
+- PINMUX_DATA(DV_HSYNC_MARK, PORT64_FN6),
+- PINMUX_DATA(IRQ13_PORT64_MARK, PORT64_FN0, MSEL1CR_13_1),
+-
+- /* Port65 */
+- PINMUX_DATA(LCD0_DISP_MARK, PORT65_FN1),
+- PINMUX_DATA(MSIOF2_TSCK_MARK, PORT65_FN2),
+- PINMUX_DATA(LCD0_RS_MARK, PORT65_FN4),
+-
+- /* Port66 */
+- PINMUX_DATA(MEMC_INT_MARK, PORT66_FN1),
+- PINMUX_DATA(TPU0TO2_PORT66_MARK, PORT66_FN3, MSEL5CR_25_0),
+- PINMUX_DATA(MMC0_CLK_PORT66_MARK, PORT66_FN4, MSEL4CR_15_0),
+- PINMUX_DATA(SDHI1_CLK_MARK, PORT66_FN6),
+-
+- /* Port67 - Port73 Function1 */
+- PINMUX_DATA(MEMC_CS0_MARK, PORT67_FN1),
+- PINMUX_DATA(MEMC_AD8_MARK, PORT68_FN1),
+- PINMUX_DATA(MEMC_AD9_MARK, PORT69_FN1),
+- PINMUX_DATA(MEMC_AD10_MARK, PORT70_FN1),
+- PINMUX_DATA(MEMC_AD11_MARK, PORT71_FN1),
+- PINMUX_DATA(MEMC_AD12_MARK, PORT72_FN1),
+- PINMUX_DATA(MEMC_AD13_MARK, PORT73_FN1),
+-
+- /* Port67 - Port73 Function2 */
+- PINMUX_DATA(MSIOF1_SS1_PORT67_MARK, PORT67_FN2, MSEL4CR_10_1),
+- PINMUX_DATA(MSIOF1_RSCK_MARK, PORT68_FN2),
+- PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT69_FN2),
+- PINMUX_DATA(MSIOF1_MCK0_MARK, PORT70_FN2),
+- PINMUX_DATA(MSIOF1_MCK1_MARK, PORT71_FN2),
+- PINMUX_DATA(MSIOF1_TSCK_PORT72_MARK, PORT72_FN2, MSEL4CR_10_1),
+- PINMUX_DATA(MSIOF1_TSYNC_PORT73_MARK, PORT73_FN2, MSEL4CR_10_1),
+-
+- /* Port67 - Port73 Function4 */
+- PINMUX_DATA(MMC0_CMD_PORT67_MARK, PORT67_FN4, MSEL4CR_15_0),
+- PINMUX_DATA(MMC0_D0_PORT68_MARK, PORT68_FN4, MSEL4CR_15_0),
+- PINMUX_DATA(MMC0_D1_PORT69_MARK, PORT69_FN4, MSEL4CR_15_0),
+- PINMUX_DATA(MMC0_D2_PORT70_MARK, PORT70_FN4, MSEL4CR_15_0),
+- PINMUX_DATA(MMC0_D3_PORT71_MARK, PORT71_FN4, MSEL4CR_15_0),
+- PINMUX_DATA(MMC0_D4_PORT72_MARK, PORT72_FN4, MSEL4CR_15_0),
+- PINMUX_DATA(MMC0_D5_PORT73_MARK, PORT73_FN4, MSEL4CR_15_0),
+-
+- /* Port67 - Port73 Function6 */
+- PINMUX_DATA(SDHI1_CMD_MARK, PORT67_FN6),
+- PINMUX_DATA(SDHI1_D0_MARK, PORT68_FN6),
+- PINMUX_DATA(SDHI1_D1_MARK, PORT69_FN6),
+- PINMUX_DATA(SDHI1_D2_MARK, PORT70_FN6),
+- PINMUX_DATA(SDHI1_D3_MARK, PORT71_FN6),
+- PINMUX_DATA(SDHI1_CD_MARK, PORT72_FN6),
+- PINMUX_DATA(SDHI1_WP_MARK, PORT73_FN6),
+-
+- /* Port67 - Port71 IRQ */
+- PINMUX_DATA(IRQ20_MARK, PORT67_FN0),
+- PINMUX_DATA(IRQ16_PORT68_MARK, PORT68_FN0, MSEL1CR_16_0),
+- PINMUX_DATA(IRQ17_MARK, PORT69_FN0),
+- PINMUX_DATA(IRQ18_MARK, PORT70_FN0),
+- PINMUX_DATA(IRQ19_MARK, PORT71_FN0),
+-
+- /* Port74 */
+- PINMUX_DATA(MEMC_AD14_MARK, PORT74_FN1),
+- PINMUX_DATA(MSIOF1_TXD_PORT74_MARK, PORT74_FN2, MSEL4CR_10_1),
+- PINMUX_DATA(MMC0_D6_PORT74_MARK, PORT74_FN4, MSEL4CR_15_0),
+- PINMUX_DATA(STP1_IPD7_MARK, PORT74_FN6),
+- PINMUX_DATA(LCD1_D21_MARK, PORT74_FN7),
+-
+- /* Port75 */
+- PINMUX_DATA(MEMC_AD15_MARK, PORT75_FN1),
+- PINMUX_DATA(MSIOF1_RXD_PORT75_MARK, PORT75_FN2, MSEL4CR_10_1),
+- PINMUX_DATA(MMC0_D7_PORT75_MARK, PORT75_FN4, MSEL4CR_15_0),
+- PINMUX_DATA(STP1_IPD6_MARK, PORT75_FN6),
+- PINMUX_DATA(LCD1_D20_MARK, PORT75_FN7),
+-
+- /* Port76 - Port80 Function */
+- PINMUX_DATA(SDHI0_CMD_MARK, PORT76_FN1),
+- PINMUX_DATA(SDHI0_D0_MARK, PORT77_FN1),
+- PINMUX_DATA(SDHI0_D1_MARK, PORT78_FN1),
+- PINMUX_DATA(SDHI0_D2_MARK, PORT79_FN1),
+- PINMUX_DATA(SDHI0_D3_MARK, PORT80_FN1),
+-
+- /* Port81 */
+- PINMUX_DATA(SDHI0_CD_MARK, PORT81_FN1),
+- PINMUX_DATA(IRQ26_PORT81_MARK, PORT81_FN0, MSEL1CR_26_0),
+-
+- /* Port82 - Port88 Function */
+- PINMUX_DATA(SDHI0_CLK_MARK, PORT82_FN1),
+- PINMUX_DATA(SDHI0_WP_MARK, PORT83_FN1),
+- PINMUX_DATA(RESETOUTS_MARK, PORT84_FN1),
+- PINMUX_DATA(USB0_PPON_MARK, PORT85_FN1),
+- PINMUX_DATA(USB0_OCI_MARK, PORT86_FN1),
+- PINMUX_DATA(USB1_PPON_MARK, PORT87_FN1),
+- PINMUX_DATA(USB1_OCI_MARK, PORT88_FN1),
+-
+- /* Port89 */
+- PINMUX_DATA(DREQ0_MARK, PORT89_FN1),
+- PINMUX_DATA(BBIF2_TSCK2_PORT89_MARK, PORT89_FN2, MSEL5CR_0_1),
+- PINMUX_DATA(RSPI_SSL3_A_MARK, PORT89_FN6),
+-
+- /* Port90 */
+- PINMUX_DATA(DACK0_MARK, PORT90_FN1),
+- PINMUX_DATA(BBIF2_RXD2_PORT90_MARK, PORT90_FN2, MSEL5CR_0_1),
+- PINMUX_DATA(RSPI_SSL2_A_MARK, PORT90_FN6),
+- PINMUX_DATA(WAIT_PORT90_MARK, PORT90_FN7, MSEL5CR_2_1),
+-
+- /* Port91 */
+- PINMUX_DATA(MEMC_AD0_MARK, PORT91_FN1),
+- PINMUX_DATA(BBIF1_RXD_MARK, PORT91_FN2),
+- PINMUX_DATA(SCIFA5_TXD_PORT91_MARK, PORT91_FN3, MSEL5CR_15_1,
+- MSEL5CR_14_0),
+- PINMUX_DATA(LCD1_D5_MARK, PORT91_FN7),
+-
+- /* Port92 */
+- PINMUX_DATA(MEMC_AD1_MARK, PORT92_FN1),
+- PINMUX_DATA(BBIF1_TSYNC_MARK, PORT92_FN2),
+- PINMUX_DATA(SCIFA5_RXD_PORT92_MARK, PORT92_FN3, MSEL5CR_15_1,
+- MSEL5CR_14_0),
+- PINMUX_DATA(STP0_IPD1_MARK, PORT92_FN6),
+- PINMUX_DATA(LCD1_D6_MARK, PORT92_FN7),
+-
+- /* Port93 */
+- PINMUX_DATA(MEMC_AD2_MARK, PORT93_FN1),
+- PINMUX_DATA(BBIF1_TSCK_MARK, PORT93_FN2),
+- PINMUX_DATA(SCIFA4_TXD_PORT93_MARK, PORT93_FN3, MSEL5CR_12_1,
+- MSEL5CR_11_0),
+- PINMUX_DATA(STP0_IPD3_MARK, PORT93_FN6),
+- PINMUX_DATA(LCD1_D8_MARK, PORT93_FN7),
+-
+- /* Port94 */
+- PINMUX_DATA(MEMC_AD3_MARK, PORT94_FN1),
+- PINMUX_DATA(BBIF1_TXD_MARK, PORT94_FN2),
+- PINMUX_DATA(SCIFA4_RXD_PORT94_MARK, PORT94_FN3, MSEL5CR_12_1,
+- MSEL5CR_11_0),
+- PINMUX_DATA(STP0_IPD4_MARK, PORT94_FN6),
+- PINMUX_DATA(LCD1_D9_MARK, PORT94_FN7),
+-
+- /* Port95 */
+- PINMUX_DATA(MEMC_CS1_MARK, PORT95_FN1, MSEL4CR_6_0),
+- PINMUX_DATA(MEMC_A1_MARK, PORT95_FN1, MSEL4CR_6_1),
+-
+- PINMUX_DATA(SCIFA2_CTS_MARK, PORT95_FN2),
+- PINMUX_DATA(SIM_RST_MARK, PORT95_FN4),
+- PINMUX_DATA(VIO0_D14_PORT95_MARK, PORT95_FN7, MSEL5CR_27_1),
+- PINMUX_DATA(IRQ22_MARK, PORT95_FN0),
+-
+- /* Port96 */
+- PINMUX_DATA(MEMC_ADV_MARK, PORT96_FN1, MSEL4CR_6_0),
+- PINMUX_DATA(MEMC_DREQ0_MARK, PORT96_FN1, MSEL4CR_6_1),
+-
+- PINMUX_DATA(SCIFA2_RTS_MARK, PORT96_FN2),
+- PINMUX_DATA(SIM_CLK_MARK, PORT96_FN4),
+- PINMUX_DATA(VIO0_D15_PORT96_MARK, PORT96_FN7, MSEL5CR_27_1),
+- PINMUX_DATA(IRQ23_MARK, PORT96_FN0),
+-
+- /* Port97 */
+- PINMUX_DATA(MEMC_AD4_MARK, PORT97_FN1),
+- PINMUX_DATA(BBIF1_RSCK_MARK, PORT97_FN2),
+- PINMUX_DATA(LCD1_CS_MARK, PORT97_FN6),
+- PINMUX_DATA(LCD1_HSYN_MARK, PORT97_FN7),
+- PINMUX_DATA(IRQ12_PORT97_MARK, PORT97_FN0, MSEL1CR_12_0),
+-
+- /* Port98 */
+- PINMUX_DATA(MEMC_AD5_MARK, PORT98_FN1),
+- PINMUX_DATA(BBIF1_RSYNC_MARK, PORT98_FN2),
+- PINMUX_DATA(LCD1_VSYN_MARK, PORT98_FN7),
+- PINMUX_DATA(IRQ13_PORT98_MARK, PORT98_FN0, MSEL1CR_13_0),
+-
+- /* Port99 */
+- PINMUX_DATA(MEMC_AD6_MARK, PORT99_FN1),
+- PINMUX_DATA(BBIF1_FLOW_MARK, PORT99_FN2),
+- PINMUX_DATA(LCD1_WR_MARK, PORT99_FN6),
+- PINMUX_DATA(LCD1_DCK_MARK, PORT99_FN7),
+- PINMUX_DATA(IRQ14_PORT99_MARK, PORT99_FN0, MSEL1CR_14_0),
+-
+- /* Port100 */
+- PINMUX_DATA(MEMC_AD7_MARK, PORT100_FN1),
+- PINMUX_DATA(BBIF1_RX_FLOW_N_MARK, PORT100_FN2),
+- PINMUX_DATA(LCD1_DON_MARK, PORT100_FN7),
+- PINMUX_DATA(IRQ15_PORT100_MARK, PORT100_FN0, MSEL1CR_15_0),
+-
+- /* Port101 */
+- PINMUX_DATA(FCE0_MARK, PORT101_FN1),
+-
+- /* Port102 */
+- PINMUX_DATA(FRB_MARK, PORT102_FN1),
+- PINMUX_DATA(LCD0_LCLK_PORT102_MARK, PORT102_FN4, MSEL5CR_6_0),
+-
+- /* Port103 */
+- PINMUX_DATA(CS5B_MARK, PORT103_FN1),
+- PINMUX_DATA(FCE1_MARK, PORT103_FN2),
+- PINMUX_DATA(MMC1_CLK_PORT103_MARK, PORT103_FN3, MSEL4CR_15_1),
+-
+- /* Port104 */
+- PINMUX_DATA(CS6A_MARK, PORT104_FN1),
+- PINMUX_DATA(MMC1_CMD_PORT104_MARK, PORT104_FN3, MSEL4CR_15_1),
+- PINMUX_DATA(IRQ11_MARK, PORT104_FN0),
+-
+- /* Port105 */
+- PINMUX_DATA(CS5A_PORT105_MARK, PORT105_FN1, MSEL5CR_2_0),
+- PINMUX_DATA(SCIFA3_RTS_PORT105_MARK, PORT105_FN4, MSEL5CR_8_0),
+-
+- /* Port106 */
+- PINMUX_DATA(IOIS16_MARK, PORT106_FN1),
+- PINMUX_DATA(IDE_EXBUF_ENB_MARK, PORT106_FN6),
+-
+- /* Port107 - Port115 Function */
+- PINMUX_DATA(WE3_ICIOWR_MARK, PORT107_FN1),
+- PINMUX_DATA(WE2_ICIORD_MARK, PORT108_FN1),
+- PINMUX_DATA(CS0_MARK, PORT109_FN1),
+- PINMUX_DATA(CS2_MARK, PORT110_FN1),
+- PINMUX_DATA(CS4_MARK, PORT111_FN1),
+- PINMUX_DATA(WE1_MARK, PORT112_FN1),
+- PINMUX_DATA(WE0_FWE_MARK, PORT113_FN1),
+- PINMUX_DATA(RDWR_MARK, PORT114_FN1),
+- PINMUX_DATA(RD_FSC_MARK, PORT115_FN1),
+-
+- /* Port116 */
+- PINMUX_DATA(A25_MARK, PORT116_FN1),
+- PINMUX_DATA(MSIOF0_SS2_MARK, PORT116_FN2),
+- PINMUX_DATA(MSIOF1_SS2_PORT116_MARK, PORT116_FN3, MSEL4CR_10_0),
+- PINMUX_DATA(SCIFA3_SCK_PORT116_MARK, PORT116_FN4, MSEL5CR_8_0),
+- PINMUX_DATA(GPO1_MARK, PORT116_FN5),
+-
+- /* Port117 */
+- PINMUX_DATA(A24_MARK, PORT117_FN1),
+- PINMUX_DATA(MSIOF0_SS1_MARK, PORT117_FN2),
+- PINMUX_DATA(MSIOF1_SS1_PORT117_MARK, PORT117_FN3, MSEL4CR_10_0),
+- PINMUX_DATA(SCIFA3_CTS_PORT117_MARK, PORT117_FN4, MSEL5CR_8_0),
+- PINMUX_DATA(GPO0_MARK, PORT117_FN5),
+-
+- /* Port118 */
+- PINMUX_DATA(A23_MARK, PORT118_FN1),
+- PINMUX_DATA(MSIOF0_MCK1_MARK, PORT118_FN2),
+- PINMUX_DATA(MSIOF1_RXD_PORT118_MARK, PORT118_FN3, MSEL4CR_10_0),
+- PINMUX_DATA(GPI1_MARK, PORT118_FN5),
+- PINMUX_DATA(IRQ9_PORT118_MARK, PORT118_FN0, MSEL1CR_9_0),
+-
+- /* Port119 */
+- PINMUX_DATA(A22_MARK, PORT119_FN1),
+- PINMUX_DATA(MSIOF0_MCK0_MARK, PORT119_FN2),
+- PINMUX_DATA(MSIOF1_TXD_PORT119_MARK, PORT119_FN3, MSEL4CR_10_0),
+- PINMUX_DATA(GPI0_MARK, PORT119_FN5),
+- PINMUX_DATA(IRQ8_MARK, PORT119_FN0),
+-
+- /* Port120 */
+- PINMUX_DATA(A21_MARK, PORT120_FN1),
+- PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT120_FN2),
+- PINMUX_DATA(MSIOF1_TSYNC_PORT120_MARK, PORT120_FN3, MSEL4CR_10_0),
+- PINMUX_DATA(IRQ7_PORT120_MARK, PORT120_FN0, MSEL1CR_7_0),
+-
+- /* Port121 */
+- PINMUX_DATA(A20_MARK, PORT121_FN1),
+- PINMUX_DATA(MSIOF0_RSCK_MARK, PORT121_FN2),
+- PINMUX_DATA(MSIOF1_TSCK_PORT121_MARK, PORT121_FN3, MSEL4CR_10_0),
+- PINMUX_DATA(IRQ6_PORT121_MARK, PORT121_FN0, MSEL1CR_6_0),
+-
+- /* Port122 */
+- PINMUX_DATA(A19_MARK, PORT122_FN1),
+- PINMUX_DATA(MSIOF0_RXD_MARK, PORT122_FN2),
+-
+- /* Port123 */
+- PINMUX_DATA(A18_MARK, PORT123_FN1),
+- PINMUX_DATA(MSIOF0_TSCK_MARK, PORT123_FN2),
+-
+- /* Port124 */
+- PINMUX_DATA(A17_MARK, PORT124_FN1),
+- PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT124_FN2),
+-
+- /* Port125 - Port141 Function */
+- PINMUX_DATA(A16_MARK, PORT125_FN1),
+- PINMUX_DATA(A15_MARK, PORT126_FN1),
+- PINMUX_DATA(A14_MARK, PORT127_FN1),
+- PINMUX_DATA(A13_MARK, PORT128_FN1),
+- PINMUX_DATA(A12_MARK, PORT129_FN1),
+- PINMUX_DATA(A11_MARK, PORT130_FN1),
+- PINMUX_DATA(A10_MARK, PORT131_FN1),
+- PINMUX_DATA(A9_MARK, PORT132_FN1),
+- PINMUX_DATA(A8_MARK, PORT133_FN1),
+- PINMUX_DATA(A7_MARK, PORT134_FN1),
+- PINMUX_DATA(A6_MARK, PORT135_FN1),
+- PINMUX_DATA(A5_FCDE_MARK, PORT136_FN1),
+- PINMUX_DATA(A4_FOE_MARK, PORT137_FN1),
+- PINMUX_DATA(A3_MARK, PORT138_FN1),
+- PINMUX_DATA(A2_MARK, PORT139_FN1),
+- PINMUX_DATA(A1_MARK, PORT140_FN1),
+- PINMUX_DATA(CKO_MARK, PORT141_FN1),
+-
+- /* Port142 - Port157 Function1 */
+- PINMUX_DATA(D15_NAF15_MARK, PORT142_FN1),
+- PINMUX_DATA(D14_NAF14_MARK, PORT143_FN1),
+- PINMUX_DATA(D13_NAF13_MARK, PORT144_FN1),
+- PINMUX_DATA(D12_NAF12_MARK, PORT145_FN1),
+- PINMUX_DATA(D11_NAF11_MARK, PORT146_FN1),
+- PINMUX_DATA(D10_NAF10_MARK, PORT147_FN1),
+- PINMUX_DATA(D9_NAF9_MARK, PORT148_FN1),
+- PINMUX_DATA(D8_NAF8_MARK, PORT149_FN1),
+- PINMUX_DATA(D7_NAF7_MARK, PORT150_FN1),
+- PINMUX_DATA(D6_NAF6_MARK, PORT151_FN1),
+- PINMUX_DATA(D5_NAF5_MARK, PORT152_FN1),
+- PINMUX_DATA(D4_NAF4_MARK, PORT153_FN1),
+- PINMUX_DATA(D3_NAF3_MARK, PORT154_FN1),
+- PINMUX_DATA(D2_NAF2_MARK, PORT155_FN1),
+- PINMUX_DATA(D1_NAF1_MARK, PORT156_FN1),
+- PINMUX_DATA(D0_NAF0_MARK, PORT157_FN1),
+-
+- /* Port142 - Port149 Function3 */
+- PINMUX_DATA(MMC1_D7_PORT142_MARK, PORT142_FN3, MSEL4CR_15_1),
+- PINMUX_DATA(MMC1_D6_PORT143_MARK, PORT143_FN3, MSEL4CR_15_1),
+- PINMUX_DATA(MMC1_D5_PORT144_MARK, PORT144_FN3, MSEL4CR_15_1),
+- PINMUX_DATA(MMC1_D4_PORT145_MARK, PORT145_FN3, MSEL4CR_15_1),
+- PINMUX_DATA(MMC1_D3_PORT146_MARK, PORT146_FN3, MSEL4CR_15_1),
+- PINMUX_DATA(MMC1_D2_PORT147_MARK, PORT147_FN3, MSEL4CR_15_1),
+- PINMUX_DATA(MMC1_D1_PORT148_MARK, PORT148_FN3, MSEL4CR_15_1),
+- PINMUX_DATA(MMC1_D0_PORT149_MARK, PORT149_FN3, MSEL4CR_15_1),
+-
+- /* Port158 */
+- PINMUX_DATA(D31_MARK, PORT158_FN1),
+- PINMUX_DATA(SCIFA3_SCK_PORT158_MARK, PORT158_FN2, MSEL5CR_8_1),
+- PINMUX_DATA(RMII_REF125CK_MARK, PORT158_FN3),
+- PINMUX_DATA(LCD0_D21_PORT158_MARK, PORT158_FN4, MSEL5CR_6_1),
+- PINMUX_DATA(IRDA_FIRSEL_MARK, PORT158_FN5),
+- PINMUX_DATA(IDE_D15_MARK, PORT158_FN6),
+-
+- /* Port159 */
+- PINMUX_DATA(D30_MARK, PORT159_FN1),
+- PINMUX_DATA(SCIFA3_RXD_PORT159_MARK, PORT159_FN2, MSEL5CR_8_1),
+- PINMUX_DATA(RMII_REF50CK_MARK, PORT159_FN3),
+- PINMUX_DATA(LCD0_D23_PORT159_MARK, PORT159_FN4, MSEL5CR_6_1),
+- PINMUX_DATA(IDE_D14_MARK, PORT159_FN6),
+-
+- /* Port160 */
+- PINMUX_DATA(D29_MARK, PORT160_FN1),
+- PINMUX_DATA(SCIFA3_TXD_PORT160_MARK, PORT160_FN2, MSEL5CR_8_1),
+- PINMUX_DATA(LCD0_D22_PORT160_MARK, PORT160_FN4, MSEL5CR_6_1),
+- PINMUX_DATA(VIO1_HD_MARK, PORT160_FN5),
+- PINMUX_DATA(IDE_D13_MARK, PORT160_FN6),
+-
+- /* Port161 */
+- PINMUX_DATA(D28_MARK, PORT161_FN1),
+- PINMUX_DATA(SCIFA3_RTS_PORT161_MARK, PORT161_FN2, MSEL5CR_8_1),
+- PINMUX_DATA(ET_RX_DV_MARK, PORT161_FN3),
+- PINMUX_DATA(LCD0_D20_PORT161_MARK, PORT161_FN4, MSEL5CR_6_1),
+- PINMUX_DATA(IRDA_IN_MARK, PORT161_FN5),
+- PINMUX_DATA(IDE_D12_MARK, PORT161_FN6),
+-
+- /* Port162 */
+- PINMUX_DATA(D27_MARK, PORT162_FN1),
+- PINMUX_DATA(SCIFA3_CTS_PORT162_MARK, PORT162_FN2, MSEL5CR_8_1),
+- PINMUX_DATA(LCD0_D19_PORT162_MARK, PORT162_FN4, MSEL5CR_6_1),
+- PINMUX_DATA(IRDA_OUT_MARK, PORT162_FN5),
+- PINMUX_DATA(IDE_D11_MARK, PORT162_FN6),
+-
+- /* Port163 */
+- PINMUX_DATA(D26_MARK, PORT163_FN1),
+- PINMUX_DATA(MSIOF2_SS2_MARK, PORT163_FN2),
+- PINMUX_DATA(ET_COL_MARK, PORT163_FN3),
+- PINMUX_DATA(LCD0_D18_PORT163_MARK, PORT163_FN4, MSEL5CR_6_1),
+- PINMUX_DATA(IROUT_MARK, PORT163_FN5),
+- PINMUX_DATA(IDE_D10_MARK, PORT163_FN6),
+-
+- /* Port164 */
+- PINMUX_DATA(D25_MARK, PORT164_FN1),
+- PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT164_FN2),
+- PINMUX_DATA(ET_PHY_INT_MARK, PORT164_FN3),
+- PINMUX_DATA(LCD0_RD_MARK, PORT164_FN4),
+- PINMUX_DATA(IDE_D9_MARK, PORT164_FN6),
+-
+- /* Port165 */
+- PINMUX_DATA(D24_MARK, PORT165_FN1),
+- PINMUX_DATA(MSIOF2_RXD_MARK, PORT165_FN2),
+- PINMUX_DATA(LCD0_LCLK_PORT165_MARK, PORT165_FN4, MSEL5CR_6_1),
+- PINMUX_DATA(IDE_D8_MARK, PORT165_FN6),
+-
+- /* Port166 - Port171 Function1 */
+- PINMUX_DATA(D21_MARK, PORT166_FN1),
+- PINMUX_DATA(D20_MARK, PORT167_FN1),
+- PINMUX_DATA(D19_MARK, PORT168_FN1),
+- PINMUX_DATA(D18_MARK, PORT169_FN1),
+- PINMUX_DATA(D17_MARK, PORT170_FN1),
+- PINMUX_DATA(D16_MARK, PORT171_FN1),
+-
+- /* Port166 - Port171 Function3 */
+- PINMUX_DATA(ET_ETXD5_MARK, PORT166_FN3),
+- PINMUX_DATA(ET_ETXD4_MARK, PORT167_FN3),
+- PINMUX_DATA(ET_ETXD3_MARK, PORT168_FN3),
+- PINMUX_DATA(ET_ETXD2_MARK, PORT169_FN3),
+- PINMUX_DATA(ET_ETXD1_MARK, PORT170_FN3),
+- PINMUX_DATA(ET_ETXD0_MARK, PORT171_FN3),
+-
+- /* Port166 - Port171 Function6 */
+- PINMUX_DATA(IDE_D5_MARK, PORT166_FN6),
+- PINMUX_DATA(IDE_D4_MARK, PORT167_FN6),
+- PINMUX_DATA(IDE_D3_MARK, PORT168_FN6),
+- PINMUX_DATA(IDE_D2_MARK, PORT169_FN6),
+- PINMUX_DATA(IDE_D1_MARK, PORT170_FN6),
+- PINMUX_DATA(IDE_D0_MARK, PORT171_FN6),
+-
+- /* Port167 - Port171 IRQ */
+- PINMUX_DATA(IRQ31_PORT167_MARK, PORT167_FN0, MSEL1CR_31_0),
+- PINMUX_DATA(IRQ27_PORT168_MARK, PORT168_FN0, MSEL1CR_27_0),
+- PINMUX_DATA(IRQ28_PORT169_MARK, PORT169_FN0, MSEL1CR_28_0),
+- PINMUX_DATA(IRQ29_PORT170_MARK, PORT170_FN0, MSEL1CR_29_0),
+- PINMUX_DATA(IRQ30_PORT171_MARK, PORT171_FN0, MSEL1CR_30_0),
+-
+- /* Port172 */
+- PINMUX_DATA(D23_MARK, PORT172_FN1),
+- PINMUX_DATA(SCIFB_RTS_PORT172_MARK, PORT172_FN2, MSEL5CR_17_1),
+- PINMUX_DATA(ET_ETXD7_MARK, PORT172_FN3),
+- PINMUX_DATA(IDE_D7_MARK, PORT172_FN6),
+- PINMUX_DATA(IRQ4_PORT172_MARK, PORT172_FN0, MSEL1CR_4_1),
+-
+- /* Port173 */
+- PINMUX_DATA(D22_MARK, PORT173_FN1),
+- PINMUX_DATA(SCIFB_CTS_PORT173_MARK, PORT173_FN2, MSEL5CR_17_1),
+- PINMUX_DATA(ET_ETXD6_MARK, PORT173_FN3),
+- PINMUX_DATA(IDE_D6_MARK, PORT173_FN6),
+- PINMUX_DATA(IRQ6_PORT173_MARK, PORT173_FN0, MSEL1CR_6_1),
+-
+- /* Port174 */
+- PINMUX_DATA(A26_MARK, PORT174_FN1),
+- PINMUX_DATA(MSIOF0_TXD_MARK, PORT174_FN2),
+- PINMUX_DATA(ET_RX_CLK_MARK, PORT174_FN3),
+- PINMUX_DATA(SCIFA3_RXD_PORT174_MARK, PORT174_FN4, MSEL5CR_8_0),
+-
+- /* Port175 */
+- PINMUX_DATA(A0_MARK, PORT175_FN1),
+- PINMUX_DATA(BS_MARK, PORT175_FN2),
+- PINMUX_DATA(ET_WOL_MARK, PORT175_FN3),
+- PINMUX_DATA(SCIFA3_TXD_PORT175_MARK, PORT175_FN4, MSEL5CR_8_0),
+-
+- /* Port176 */
+- PINMUX_DATA(ET_GTX_CLK_MARK, PORT176_FN3),
+-
+- /* Port177 */
+- PINMUX_DATA(WAIT_PORT177_MARK, PORT177_FN1, MSEL5CR_2_0),
+- PINMUX_DATA(ET_LINK_MARK, PORT177_FN3),
+- PINMUX_DATA(IDE_IOWR_MARK, PORT177_FN6),
+- PINMUX_DATA(SDHI2_WP_PORT177_MARK, PORT177_FN7, MSEL5CR_19_1),
+-
+- /* Port178 */
+- PINMUX_DATA(VIO0_D12_MARK, PORT178_FN1),
+- PINMUX_DATA(VIO1_D4_MARK, PORT178_FN5),
+- PINMUX_DATA(IDE_IORD_MARK, PORT178_FN6),
+-
+- /* Port179 */
+- PINMUX_DATA(VIO0_D11_MARK, PORT179_FN1),
+- PINMUX_DATA(VIO1_D3_MARK, PORT179_FN5),
+- PINMUX_DATA(IDE_IORDY_MARK, PORT179_FN6),
+-
+- /* Port180 */
+- PINMUX_DATA(VIO0_D10_MARK, PORT180_FN1),
+- PINMUX_DATA(TPU0TO3_MARK, PORT180_FN4),
+- PINMUX_DATA(VIO1_D2_MARK, PORT180_FN5),
+- PINMUX_DATA(IDE_INT_MARK, PORT180_FN6),
+- PINMUX_DATA(IRQ24_MARK, PORT180_FN0),
+-
+- /* Port181 */
+- PINMUX_DATA(VIO0_D9_MARK, PORT181_FN1),
+- PINMUX_DATA(VIO1_D1_MARK, PORT181_FN5),
+- PINMUX_DATA(IDE_RST_MARK, PORT181_FN6),
+-
+- /* Port182 */
+- PINMUX_DATA(VIO0_D8_MARK, PORT182_FN1),
+- PINMUX_DATA(VIO1_D0_MARK, PORT182_FN5),
+- PINMUX_DATA(IDE_DIRECTION_MARK, PORT182_FN6),
+-
+- /* Port183 */
+- PINMUX_DATA(DREQ1_MARK, PORT183_FN1),
+- PINMUX_DATA(BBIF2_TXD2_PORT183_MARK, PORT183_FN2, MSEL5CR_0_1),
+- PINMUX_DATA(ET_TX_EN_MARK, PORT183_FN3),
+-
+- /* Port184 */
+- PINMUX_DATA(DACK1_MARK, PORT184_FN1),
+- PINMUX_DATA(BBIF2_TSYNC2_PORT184_MARK, PORT184_FN2, MSEL5CR_0_1),
+- PINMUX_DATA(ET_TX_CLK_MARK, PORT184_FN3),
+-
+- /* Port185 - Port192 Function1 */
+- PINMUX_DATA(SCIFA1_SCK_MARK, PORT185_FN1),
+- PINMUX_DATA(SCIFB_RTS_PORT186_MARK, PORT186_FN1, MSEL5CR_17_0),
+- PINMUX_DATA(SCIFB_CTS_PORT187_MARK, PORT187_FN1, MSEL5CR_17_0),
+- PINMUX_DATA(SCIFA0_SCK_MARK, PORT188_FN1),
+- PINMUX_DATA(SCIFB_SCK_PORT190_MARK, PORT190_FN1, MSEL5CR_17_0),
+- PINMUX_DATA(SCIFB_RXD_PORT191_MARK, PORT191_FN1, MSEL5CR_17_0),
+- PINMUX_DATA(SCIFB_TXD_PORT192_MARK, PORT192_FN1, MSEL5CR_17_0),
+-
+- /* Port185 - Port192 Function3 */
+- PINMUX_DATA(ET_ERXD0_MARK, PORT185_FN3),
+- PINMUX_DATA(ET_ERXD1_MARK, PORT186_FN3),
+- PINMUX_DATA(ET_ERXD2_MARK, PORT187_FN3),
+- PINMUX_DATA(ET_ERXD3_MARK, PORT188_FN3),
+- PINMUX_DATA(ET_ERXD4_MARK, PORT189_FN3),
+- PINMUX_DATA(ET_ERXD5_MARK, PORT190_FN3),
+- PINMUX_DATA(ET_ERXD6_MARK, PORT191_FN3),
+- PINMUX_DATA(ET_ERXD7_MARK, PORT192_FN3),
+-
+- /* Port185 - Port192 Function6 */
+- PINMUX_DATA(STP1_IPCLK_MARK, PORT185_FN6),
+- PINMUX_DATA(STP1_IPD0_PORT186_MARK, PORT186_FN6, MSEL5CR_23_0),
+- PINMUX_DATA(STP1_IPEN_PORT187_MARK, PORT187_FN6, MSEL5CR_23_0),
+- PINMUX_DATA(STP1_IPSYNC_MARK, PORT188_FN6),
+- PINMUX_DATA(STP0_IPCLK_MARK, PORT189_FN6),
+- PINMUX_DATA(STP0_IPD0_MARK, PORT190_FN6),
+- PINMUX_DATA(STP0_IPEN_MARK, PORT191_FN6),
+- PINMUX_DATA(STP0_IPSYNC_MARK, PORT192_FN6),
+-
+- /* Port193 */
+- PINMUX_DATA(SCIFA0_CTS_MARK, PORT193_FN1),
+- PINMUX_DATA(RMII_CRS_DV_MARK, PORT193_FN3),
+- PINMUX_DATA(STP1_IPEN_PORT193_MARK, PORT193_FN6, MSEL5CR_23_1),
+- PINMUX_DATA(LCD1_D17_MARK, PORT193_FN7),
+-
+- /* Port194 */
+- PINMUX_DATA(SCIFA0_RTS_MARK, PORT194_FN1),
+- PINMUX_DATA(RMII_RX_ER_MARK, PORT194_FN3),
+- PINMUX_DATA(STP1_IPD0_PORT194_MARK, PORT194_FN6, MSEL5CR_23_1),
+- PINMUX_DATA(LCD1_D16_MARK, PORT194_FN7),
+-
+- /* Port195 */
+- PINMUX_DATA(SCIFA1_RXD_MARK, PORT195_FN1),
+- PINMUX_DATA(RMII_RXD0_MARK, PORT195_FN3),
+- PINMUX_DATA(STP1_IPD3_MARK, PORT195_FN6),
+- PINMUX_DATA(LCD1_D15_MARK, PORT195_FN7),
+-
+- /* Port196 */
+- PINMUX_DATA(SCIFA1_TXD_MARK, PORT196_FN1),
+- PINMUX_DATA(RMII_RXD1_MARK, PORT196_FN3),
+- PINMUX_DATA(STP1_IPD2_MARK, PORT196_FN6),
+- PINMUX_DATA(LCD1_D14_MARK, PORT196_FN7),
+-
+- /* Port197 */
+- PINMUX_DATA(SCIFA0_RXD_MARK, PORT197_FN1),
+- PINMUX_DATA(VIO1_CLK_MARK, PORT197_FN5),
+- PINMUX_DATA(STP1_IPD5_MARK, PORT197_FN6),
+- PINMUX_DATA(LCD1_D19_MARK, PORT197_FN7),
+-
+- /* Port198 */
+- PINMUX_DATA(SCIFA0_TXD_MARK, PORT198_FN1),
+- PINMUX_DATA(VIO1_VD_MARK, PORT198_FN5),
+- PINMUX_DATA(STP1_IPD4_MARK, PORT198_FN6),
+- PINMUX_DATA(LCD1_D18_MARK, PORT198_FN7),
+-
+- /* Port199 */
+- PINMUX_DATA(MEMC_NWE_MARK, PORT199_FN1),
+- PINMUX_DATA(SCIFA2_SCK_PORT199_MARK, PORT199_FN2, MSEL5CR_7_1),
+- PINMUX_DATA(RMII_TX_EN_MARK, PORT199_FN3),
+- PINMUX_DATA(SIM_D_PORT199_MARK, PORT199_FN4, MSEL5CR_21_1),
+- PINMUX_DATA(STP1_IPD1_MARK, PORT199_FN6),
+- PINMUX_DATA(LCD1_D13_MARK, PORT199_FN7),
+-
+- /* Port200 */
+- PINMUX_DATA(MEMC_NOE_MARK, PORT200_FN1),
+- PINMUX_DATA(SCIFA2_RXD_MARK, PORT200_FN2),
+- PINMUX_DATA(RMII_TXD0_MARK, PORT200_FN3),
+- PINMUX_DATA(STP0_IPD7_MARK, PORT200_FN6),
+- PINMUX_DATA(LCD1_D12_MARK, PORT200_FN7),
+-
+- /* Port201 */
+- PINMUX_DATA(MEMC_WAIT_MARK, PORT201_FN1, MSEL4CR_6_0),
+- PINMUX_DATA(MEMC_DREQ1_MARK, PORT201_FN1, MSEL4CR_6_1),
+-
+- PINMUX_DATA(SCIFA2_TXD_MARK, PORT201_FN2),
+- PINMUX_DATA(RMII_TXD1_MARK, PORT201_FN3),
+- PINMUX_DATA(STP0_IPD6_MARK, PORT201_FN6),
+- PINMUX_DATA(LCD1_D11_MARK, PORT201_FN7),
+-
+- /* Port202 */
+- PINMUX_DATA(MEMC_BUSCLK_MARK, PORT202_FN1, MSEL4CR_6_0),
+- PINMUX_DATA(MEMC_A0_MARK, PORT202_FN1, MSEL4CR_6_1),
+-
+- PINMUX_DATA(MSIOF1_SS2_PORT202_MARK, PORT202_FN2, MSEL4CR_10_1),
+- PINMUX_DATA(RMII_MDC_MARK, PORT202_FN3),
+- PINMUX_DATA(TPU0TO2_PORT202_MARK, PORT202_FN4, MSEL5CR_25_1),
+- PINMUX_DATA(IDE_CS0_MARK, PORT202_FN6),
+- PINMUX_DATA(SDHI2_CD_PORT202_MARK, PORT202_FN7, MSEL5CR_19_1),
+- PINMUX_DATA(IRQ21_MARK, PORT202_FN0),
+-
+- /* Port203 - Port208 Function1 */
+- PINMUX_DATA(SDHI2_CLK_MARK, PORT203_FN1),
+- PINMUX_DATA(SDHI2_CMD_MARK, PORT204_FN1),
+- PINMUX_DATA(SDHI2_D0_MARK, PORT205_FN1),
+- PINMUX_DATA(SDHI2_D1_MARK, PORT206_FN1),
+- PINMUX_DATA(SDHI2_D2_MARK, PORT207_FN1),
+- PINMUX_DATA(SDHI2_D3_MARK, PORT208_FN1),
+-
+- /* Port203 - Port208 Function3 */
+- PINMUX_DATA(ET_TX_ER_MARK, PORT203_FN3),
+- PINMUX_DATA(ET_RX_ER_MARK, PORT204_FN3),
+- PINMUX_DATA(ET_CRS_MARK, PORT205_FN3),
+- PINMUX_DATA(ET_MDC_MARK, PORT206_FN3),
+- PINMUX_DATA(ET_MDIO_MARK, PORT207_FN3),
+- PINMUX_DATA(RMII_MDIO_MARK, PORT208_FN3),
+-
+- /* Port203 - Port208 Function6 */
+- PINMUX_DATA(IDE_A2_MARK, PORT203_FN6),
+- PINMUX_DATA(IDE_A1_MARK, PORT204_FN6),
+- PINMUX_DATA(IDE_A0_MARK, PORT205_FN6),
+- PINMUX_DATA(IDE_IODACK_MARK, PORT206_FN6),
+- PINMUX_DATA(IDE_IODREQ_MARK, PORT207_FN6),
+- PINMUX_DATA(IDE_CS1_MARK, PORT208_FN6),
+-
+- /* Port203 - Port208 Function7 */
+- PINMUX_DATA(SCIFA4_TXD_PORT203_MARK, PORT203_FN7, MSEL5CR_12_0,
+- MSEL5CR_11_1),
+- PINMUX_DATA(SCIFA4_RXD_PORT204_MARK, PORT204_FN7, MSEL5CR_12_0,
+- MSEL5CR_11_1),
+- PINMUX_DATA(SCIFA4_SCK_PORT205_MARK, PORT205_FN7, MSEL5CR_10_1),
+- PINMUX_DATA(SCIFA5_SCK_PORT206_MARK, PORT206_FN7, MSEL5CR_13_1),
+- PINMUX_DATA(SCIFA5_RXD_PORT207_MARK, PORT207_FN7, MSEL5CR_15_0,
+- MSEL5CR_14_1),
+- PINMUX_DATA(SCIFA5_TXD_PORT208_MARK, PORT208_FN7, MSEL5CR_15_0,
+- MSEL5CR_14_1),
+-
+- /* Port209 */
+- PINMUX_DATA(VBUS_MARK, PORT209_FN1),
+- PINMUX_DATA(IRQ7_PORT209_MARK, PORT209_FN0, MSEL1CR_7_1),
+-
+- /* Port210 */
+- PINMUX_DATA(IRQ9_PORT210_MARK, PORT210_FN0, MSEL1CR_9_1),
+-
+- /* Port211 */
+- PINMUX_DATA(IRQ16_PORT211_MARK, PORT211_FN0, MSEL1CR_16_1),
+-
+- /* LCDC select */
+- PINMUX_DATA(LCDC0_SELECT_MARK, MSEL3CR_6_0),
+- PINMUX_DATA(LCDC1_SELECT_MARK, MSEL3CR_6_1),
+-
+- /* SDENC */
+- PINMUX_DATA(SDENC_CPG_MARK, MSEL4CR_19_0),
+- PINMUX_DATA(SDENC_DV_CLKI_MARK, MSEL4CR_19_1),
+-
+- /* SYSC */
+- PINMUX_DATA(RESETP_PULLUP_MARK, MSEL4CR_4_0),
+- PINMUX_DATA(RESETP_PLAIN_MARK, MSEL4CR_4_1),
+-
+- /* DEBUG */
+- PINMUX_DATA(EDEBGREQ_PULLDOWN_MARK, MSEL4CR_1_0),
+- PINMUX_DATA(EDEBGREQ_PULLUP_MARK, MSEL4CR_1_1),
+-
+- PINMUX_DATA(TRACEAUD_FROM_VIO_MARK, MSEL5CR_30_0, MSEL5CR_29_0),
+- PINMUX_DATA(TRACEAUD_FROM_LCDC0_MARK, MSEL5CR_30_0, MSEL5CR_29_1),
+- PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK, MSEL5CR_30_1, MSEL5CR_29_0),
+-};
+-
+-static struct pinmux_gpio pinmux_gpios[] = {
+-
+- /* PORT */
+- GPIO_PORT_ALL(),
+-
+- /* IRQ */
+- GPIO_FN(IRQ0_PORT2), GPIO_FN(IRQ0_PORT13),
+- GPIO_FN(IRQ1),
+- GPIO_FN(IRQ2_PORT11), GPIO_FN(IRQ2_PORT12),
+- GPIO_FN(IRQ3_PORT10), GPIO_FN(IRQ3_PORT14),
+- GPIO_FN(IRQ4_PORT15), GPIO_FN(IRQ4_PORT172),
+- GPIO_FN(IRQ5_PORT0), GPIO_FN(IRQ5_PORT1),
+- GPIO_FN(IRQ6_PORT121), GPIO_FN(IRQ6_PORT173),
+- GPIO_FN(IRQ7_PORT120), GPIO_FN(IRQ7_PORT209),
+- GPIO_FN(IRQ8),
+- GPIO_FN(IRQ9_PORT118), GPIO_FN(IRQ9_PORT210),
+- GPIO_FN(IRQ10),
+- GPIO_FN(IRQ11),
+- GPIO_FN(IRQ12_PORT42), GPIO_FN(IRQ12_PORT97),
+- GPIO_FN(IRQ13_PORT64), GPIO_FN(IRQ13_PORT98),
+- GPIO_FN(IRQ14_PORT63), GPIO_FN(IRQ14_PORT99),
+- GPIO_FN(IRQ15_PORT62), GPIO_FN(IRQ15_PORT100),
+- GPIO_FN(IRQ16_PORT68), GPIO_FN(IRQ16_PORT211),
+- GPIO_FN(IRQ17),
+- GPIO_FN(IRQ18),
+- GPIO_FN(IRQ19),
+- GPIO_FN(IRQ20),
+- GPIO_FN(IRQ21),
+- GPIO_FN(IRQ22),
+- GPIO_FN(IRQ23),
+- GPIO_FN(IRQ24),
+- GPIO_FN(IRQ25),
+- GPIO_FN(IRQ26_PORT58), GPIO_FN(IRQ26_PORT81),
+- GPIO_FN(IRQ27_PORT57), GPIO_FN(IRQ27_PORT168),
+- GPIO_FN(IRQ28_PORT56), GPIO_FN(IRQ28_PORT169),
+- GPIO_FN(IRQ29_PORT50), GPIO_FN(IRQ29_PORT170),
+- GPIO_FN(IRQ30_PORT49), GPIO_FN(IRQ30_PORT171),
+- GPIO_FN(IRQ31_PORT41), GPIO_FN(IRQ31_PORT167),
+-
+- /* Function */
+-
+- /* DBGT */
+- GPIO_FN(DBGMDT2), GPIO_FN(DBGMDT1), GPIO_FN(DBGMDT0),
+- GPIO_FN(DBGMD10), GPIO_FN(DBGMD11), GPIO_FN(DBGMD20),
+- GPIO_FN(DBGMD21),
+-
+- /* FSI */
+- GPIO_FN(FSIAISLD_PORT0), /* FSIAISLD Port 0/5 */
+- GPIO_FN(FSIAISLD_PORT5),
+- GPIO_FN(FSIASPDIF_PORT9), /* FSIASPDIF Port 9/18 */
+- GPIO_FN(FSIASPDIF_PORT18),
+- GPIO_FN(FSIAOSLD1), GPIO_FN(FSIAOSLD2), GPIO_FN(FSIAOLR),
+- GPIO_FN(FSIAOBT), GPIO_FN(FSIAOSLD), GPIO_FN(FSIAOMC),
+- GPIO_FN(FSIACK), GPIO_FN(FSIAILR), GPIO_FN(FSIAIBT),
+-
+- /* FMSI */
+- GPIO_FN(FMSISLD_PORT1), /* FMSISLD Port 1/6 */
+- GPIO_FN(FMSISLD_PORT6),
+- GPIO_FN(FMSIILR), GPIO_FN(FMSIIBT), GPIO_FN(FMSIOLR),
+- GPIO_FN(FMSIOBT), GPIO_FN(FMSICK), GPIO_FN(FMSOILR),
+- GPIO_FN(FMSOIBT), GPIO_FN(FMSOOLR), GPIO_FN(FMSOOBT),
+- GPIO_FN(FMSOSLD), GPIO_FN(FMSOCK),
+-
+- /* SCIFA0 */
+- GPIO_FN(SCIFA0_SCK), GPIO_FN(SCIFA0_CTS), GPIO_FN(SCIFA0_RTS),
+- GPIO_FN(SCIFA0_RXD), GPIO_FN(SCIFA0_TXD),
+-
+- /* SCIFA1 */
+- GPIO_FN(SCIFA1_CTS), GPIO_FN(SCIFA1_SCK),
+- GPIO_FN(SCIFA1_RXD), GPIO_FN(SCIFA1_TXD), GPIO_FN(SCIFA1_RTS),
+-
+- /* SCIFA2 */
+- GPIO_FN(SCIFA2_SCK_PORT22), /* SCIFA2_SCK Port 22/199 */
+- GPIO_FN(SCIFA2_SCK_PORT199),
+- GPIO_FN(SCIFA2_RXD), GPIO_FN(SCIFA2_TXD),
+- GPIO_FN(SCIFA2_CTS), GPIO_FN(SCIFA2_RTS),
+-
+- /* SCIFA3 */
+- GPIO_FN(SCIFA3_RTS_PORT105), /* MSEL5CR_8_0 */
+- GPIO_FN(SCIFA3_SCK_PORT116),
+- GPIO_FN(SCIFA3_CTS_PORT117),
+- GPIO_FN(SCIFA3_RXD_PORT174),
+- GPIO_FN(SCIFA3_TXD_PORT175),
+-
+- GPIO_FN(SCIFA3_RTS_PORT161), /* MSEL5CR_8_1 */
+- GPIO_FN(SCIFA3_SCK_PORT158),
+- GPIO_FN(SCIFA3_CTS_PORT162),
+- GPIO_FN(SCIFA3_RXD_PORT159),
+- GPIO_FN(SCIFA3_TXD_PORT160),
+-
+- /* SCIFA4 */
+- GPIO_FN(SCIFA4_RXD_PORT12), /* MSEL5CR[12:11] = 00 */
+- GPIO_FN(SCIFA4_TXD_PORT13),
+-
+- GPIO_FN(SCIFA4_RXD_PORT204), /* MSEL5CR[12:11] = 01 */
+- GPIO_FN(SCIFA4_TXD_PORT203),
+-
+- GPIO_FN(SCIFA4_RXD_PORT94), /* MSEL5CR[12:11] = 10 */
+- GPIO_FN(SCIFA4_TXD_PORT93),
+-
+- GPIO_FN(SCIFA4_SCK_PORT21), /* SCIFA4_SCK Port 21/205 */
+- GPIO_FN(SCIFA4_SCK_PORT205),
+-
+- /* SCIFA5 */
+- GPIO_FN(SCIFA5_TXD_PORT20), /* MSEL5CR[15:14] = 00 */
+- GPIO_FN(SCIFA5_RXD_PORT10),
+-
+- GPIO_FN(SCIFA5_RXD_PORT207), /* MSEL5CR[15:14] = 01 */
+- GPIO_FN(SCIFA5_TXD_PORT208),
+-
+- GPIO_FN(SCIFA5_TXD_PORT91), /* MSEL5CR[15:14] = 10 */
+- GPIO_FN(SCIFA5_RXD_PORT92),
+-
+- GPIO_FN(SCIFA5_SCK_PORT23), /* SCIFA5_SCK Port 23/206 */
+- GPIO_FN(SCIFA5_SCK_PORT206),
+-
+- /* SCIFA6 */
+- GPIO_FN(SCIFA6_SCK), GPIO_FN(SCIFA6_RXD), GPIO_FN(SCIFA6_TXD),
+-
+- /* SCIFA7 */
+- GPIO_FN(SCIFA7_TXD), GPIO_FN(SCIFA7_RXD),
+-
+- /* SCIFAB */
+- GPIO_FN(SCIFB_SCK_PORT190), /* MSEL5CR_17_0 */
+- GPIO_FN(SCIFB_RXD_PORT191),
+- GPIO_FN(SCIFB_TXD_PORT192),
+- GPIO_FN(SCIFB_RTS_PORT186),
+- GPIO_FN(SCIFB_CTS_PORT187),
+-
+- GPIO_FN(SCIFB_SCK_PORT2), /* MSEL5CR_17_1 */
+- GPIO_FN(SCIFB_RXD_PORT3),
+- GPIO_FN(SCIFB_TXD_PORT4),
+- GPIO_FN(SCIFB_RTS_PORT172),
+- GPIO_FN(SCIFB_CTS_PORT173),
+-
+- /* LCD0 */
+- GPIO_FN(LCD0_D0), GPIO_FN(LCD0_D1), GPIO_FN(LCD0_D2),
+- GPIO_FN(LCD0_D3), GPIO_FN(LCD0_D4), GPIO_FN(LCD0_D5),
+- GPIO_FN(LCD0_D6), GPIO_FN(LCD0_D7), GPIO_FN(LCD0_D8),
+- GPIO_FN(LCD0_D9), GPIO_FN(LCD0_D10), GPIO_FN(LCD0_D11),
+- GPIO_FN(LCD0_D12), GPIO_FN(LCD0_D13), GPIO_FN(LCD0_D14),
+- GPIO_FN(LCD0_D15), GPIO_FN(LCD0_D16), GPIO_FN(LCD0_D17),
+- GPIO_FN(LCD0_DON), GPIO_FN(LCD0_VCPWC), GPIO_FN(LCD0_VEPWC),
+- GPIO_FN(LCD0_DCK), GPIO_FN(LCD0_VSYN),
+- GPIO_FN(LCD0_HSYN), GPIO_FN(LCD0_DISP),
+- GPIO_FN(LCD0_WR), GPIO_FN(LCD0_RD),
+- GPIO_FN(LCD0_CS), GPIO_FN(LCD0_RS),
+-
+- GPIO_FN(LCD0_D18_PORT163), GPIO_FN(LCD0_D19_PORT162),
+- GPIO_FN(LCD0_D20_PORT161), GPIO_FN(LCD0_D21_PORT158),
+- GPIO_FN(LCD0_D22_PORT160), GPIO_FN(LCD0_D23_PORT159),
+- GPIO_FN(LCD0_LCLK_PORT165), /* MSEL5CR_6_1 */
+-
+- GPIO_FN(LCD0_D18_PORT40), GPIO_FN(LCD0_D19_PORT4),
+- GPIO_FN(LCD0_D20_PORT3), GPIO_FN(LCD0_D21_PORT2),
+- GPIO_FN(LCD0_D22_PORT0), GPIO_FN(LCD0_D23_PORT1),
+- GPIO_FN(LCD0_LCLK_PORT102), /* MSEL5CR_6_0 */
+-
+- /* LCD1 */
+- GPIO_FN(LCD1_D0), GPIO_FN(LCD1_D1), GPIO_FN(LCD1_D2),
+- GPIO_FN(LCD1_D3), GPIO_FN(LCD1_D4), GPIO_FN(LCD1_D5),
+- GPIO_FN(LCD1_D6), GPIO_FN(LCD1_D7), GPIO_FN(LCD1_D8),
+- GPIO_FN(LCD1_D9), GPIO_FN(LCD1_D10), GPIO_FN(LCD1_D11),
+- GPIO_FN(LCD1_D12), GPIO_FN(LCD1_D13), GPIO_FN(LCD1_D14),
+- GPIO_FN(LCD1_D15), GPIO_FN(LCD1_D16), GPIO_FN(LCD1_D17),
+- GPIO_FN(LCD1_D18), GPIO_FN(LCD1_D19), GPIO_FN(LCD1_D20),
+- GPIO_FN(LCD1_D21), GPIO_FN(LCD1_D22), GPIO_FN(LCD1_D23),
+- GPIO_FN(LCD1_RS), GPIO_FN(LCD1_RD), GPIO_FN(LCD1_CS),
+- GPIO_FN(LCD1_WR), GPIO_FN(LCD1_DCK), GPIO_FN(LCD1_DON),
+- GPIO_FN(LCD1_VCPWC), GPIO_FN(LCD1_LCLK), GPIO_FN(LCD1_HSYN),
+- GPIO_FN(LCD1_VSYN), GPIO_FN(LCD1_VEPWC), GPIO_FN(LCD1_DISP),
+-
+- /* RSPI */
+- GPIO_FN(RSPI_SSL0_A), GPIO_FN(RSPI_SSL1_A), GPIO_FN(RSPI_SSL2_A),
+- GPIO_FN(RSPI_SSL3_A), GPIO_FN(RSPI_CK_A), GPIO_FN(RSPI_MOSI_A),
+- GPIO_FN(RSPI_MISO_A),
+-
+- /* VIO CKO */
+- GPIO_FN(VIO_CKO1),
+- GPIO_FN(VIO_CKO2),
+- GPIO_FN(VIO_CKO_1),
+- GPIO_FN(VIO_CKO),
+-
+- /* VIO0 */
+- GPIO_FN(VIO0_D0), GPIO_FN(VIO0_D1), GPIO_FN(VIO0_D2),
+- GPIO_FN(VIO0_D3), GPIO_FN(VIO0_D4), GPIO_FN(VIO0_D5),
+- GPIO_FN(VIO0_D6), GPIO_FN(VIO0_D7), GPIO_FN(VIO0_D8),
+- GPIO_FN(VIO0_D9), GPIO_FN(VIO0_D10), GPIO_FN(VIO0_D11),
+- GPIO_FN(VIO0_D12), GPIO_FN(VIO0_VD), GPIO_FN(VIO0_HD),
+- GPIO_FN(VIO0_CLK), GPIO_FN(VIO0_FIELD),
+-
+- GPIO_FN(VIO0_D13_PORT26), /* MSEL5CR_27_0 */
+- GPIO_FN(VIO0_D14_PORT25),
+- GPIO_FN(VIO0_D15_PORT24),
+-
+- GPIO_FN(VIO0_D13_PORT22), /* MSEL5CR_27_1 */
+- GPIO_FN(VIO0_D14_PORT95),
+- GPIO_FN(VIO0_D15_PORT96),
+-
+- /* VIO1 */
+- GPIO_FN(VIO1_D0), GPIO_FN(VIO1_D1), GPIO_FN(VIO1_D2),
+- GPIO_FN(VIO1_D3), GPIO_FN(VIO1_D4), GPIO_FN(VIO1_D5),
+- GPIO_FN(VIO1_D6), GPIO_FN(VIO1_D7), GPIO_FN(VIO1_VD),
+- GPIO_FN(VIO1_HD), GPIO_FN(VIO1_CLK), GPIO_FN(VIO1_FIELD),
+-
+- /* TPU0 */
+- GPIO_FN(TPU0TO0), GPIO_FN(TPU0TO1), GPIO_FN(TPU0TO3),
+- GPIO_FN(TPU0TO2_PORT66), /* TPU0TO2 Port 66/202 */
+- GPIO_FN(TPU0TO2_PORT202),
+-
+- /* SSP1 0 */
+- GPIO_FN(STP0_IPD0), GPIO_FN(STP0_IPD1), GPIO_FN(STP0_IPD2),
+- GPIO_FN(STP0_IPD3), GPIO_FN(STP0_IPD4), GPIO_FN(STP0_IPD5),
+- GPIO_FN(STP0_IPD6), GPIO_FN(STP0_IPD7), GPIO_FN(STP0_IPEN),
+- GPIO_FN(STP0_IPCLK), GPIO_FN(STP0_IPSYNC),
+-
+- /* SSP1 1 */
+- GPIO_FN(STP1_IPD1), GPIO_FN(STP1_IPD2), GPIO_FN(STP1_IPD3),
+- GPIO_FN(STP1_IPD4), GPIO_FN(STP1_IPD5), GPIO_FN(STP1_IPD6),
+- GPIO_FN(STP1_IPD7), GPIO_FN(STP1_IPCLK), GPIO_FN(STP1_IPSYNC),
+-
+- GPIO_FN(STP1_IPD0_PORT186), /* MSEL5CR_23_0 */
+- GPIO_FN(STP1_IPEN_PORT187),
+-
+- GPIO_FN(STP1_IPD0_PORT194), /* MSEL5CR_23_1 */
+- GPIO_FN(STP1_IPEN_PORT193),
+-
+- /* SIM */
+- GPIO_FN(SIM_RST), GPIO_FN(SIM_CLK),
+- GPIO_FN(SIM_D_PORT22), /* SIM_D Port 22/199 */
+- GPIO_FN(SIM_D_PORT199),
+-
+- /* SDHI0 */
+- GPIO_FN(SDHI0_D0), GPIO_FN(SDHI0_D1), GPIO_FN(SDHI0_D2),
+- GPIO_FN(SDHI0_D3), GPIO_FN(SDHI0_CD), GPIO_FN(SDHI0_WP),
+- GPIO_FN(SDHI0_CMD), GPIO_FN(SDHI0_CLK),
+-
+- /* SDHI1 */
+- GPIO_FN(SDHI1_D0), GPIO_FN(SDHI1_D1), GPIO_FN(SDHI1_D2),
+- GPIO_FN(SDHI1_D3), GPIO_FN(SDHI1_CD), GPIO_FN(SDHI1_WP),
+- GPIO_FN(SDHI1_CMD), GPIO_FN(SDHI1_CLK),
+-
+- /* SDHI2 */
+- GPIO_FN(SDHI2_D0), GPIO_FN(SDHI2_D1), GPIO_FN(SDHI2_D2),
+- GPIO_FN(SDHI2_D3), GPIO_FN(SDHI2_CLK), GPIO_FN(SDHI2_CMD),
+-
+- GPIO_FN(SDHI2_CD_PORT24), /* MSEL5CR_19_0 */
+- GPIO_FN(SDHI2_WP_PORT25),
+-
+- GPIO_FN(SDHI2_WP_PORT177), /* MSEL5CR_19_1 */
+- GPIO_FN(SDHI2_CD_PORT202),
+-
+- /* MSIOF2 */
+- GPIO_FN(MSIOF2_TXD), GPIO_FN(MSIOF2_RXD), GPIO_FN(MSIOF2_TSCK),
+- GPIO_FN(MSIOF2_SS2), GPIO_FN(MSIOF2_TSYNC), GPIO_FN(MSIOF2_SS1),
+- GPIO_FN(MSIOF2_MCK1), GPIO_FN(MSIOF2_MCK0), GPIO_FN(MSIOF2_RSYNC),
+- GPIO_FN(MSIOF2_RSCK),
+-
+- /* KEYSC */
+- GPIO_FN(KEYIN4), GPIO_FN(KEYIN5),
+- GPIO_FN(KEYIN6), GPIO_FN(KEYIN7),
+- GPIO_FN(KEYOUT0), GPIO_FN(KEYOUT1), GPIO_FN(KEYOUT2),
+- GPIO_FN(KEYOUT3), GPIO_FN(KEYOUT4), GPIO_FN(KEYOUT5),
+- GPIO_FN(KEYOUT6), GPIO_FN(KEYOUT7),
+-
+- GPIO_FN(KEYIN0_PORT43), /* MSEL4CR_18_0 */
+- GPIO_FN(KEYIN1_PORT44),
+- GPIO_FN(KEYIN2_PORT45),
+- GPIO_FN(KEYIN3_PORT46),
+-
+- GPIO_FN(KEYIN0_PORT58), /* MSEL4CR_18_1 */
+- GPIO_FN(KEYIN1_PORT57),
+- GPIO_FN(KEYIN2_PORT56),
+- GPIO_FN(KEYIN3_PORT55),
+-
+- /* VOU */
+- GPIO_FN(DV_D0), GPIO_FN(DV_D1), GPIO_FN(DV_D2),
+- GPIO_FN(DV_D3), GPIO_FN(DV_D4), GPIO_FN(DV_D5),
+- GPIO_FN(DV_D6), GPIO_FN(DV_D7), GPIO_FN(DV_D8),
+- GPIO_FN(DV_D9), GPIO_FN(DV_D10), GPIO_FN(DV_D11),
+- GPIO_FN(DV_D12), GPIO_FN(DV_D13), GPIO_FN(DV_D14),
+- GPIO_FN(DV_D15), GPIO_FN(DV_CLK),
+- GPIO_FN(DV_VSYNC), GPIO_FN(DV_HSYNC),
+-
+- /* MEMC */
+- GPIO_FN(MEMC_AD0), GPIO_FN(MEMC_AD1), GPIO_FN(MEMC_AD2),
+- GPIO_FN(MEMC_AD3), GPIO_FN(MEMC_AD4), GPIO_FN(MEMC_AD5),
+- GPIO_FN(MEMC_AD6), GPIO_FN(MEMC_AD7), GPIO_FN(MEMC_AD8),
+- GPIO_FN(MEMC_AD9), GPIO_FN(MEMC_AD10), GPIO_FN(MEMC_AD11),
+- GPIO_FN(MEMC_AD12), GPIO_FN(MEMC_AD13), GPIO_FN(MEMC_AD14),
+- GPIO_FN(MEMC_AD15), GPIO_FN(MEMC_CS0), GPIO_FN(MEMC_INT),
+- GPIO_FN(MEMC_NWE), GPIO_FN(MEMC_NOE), GPIO_FN(MEMC_CS1),
+- GPIO_FN(MEMC_A1), GPIO_FN(MEMC_ADV), GPIO_FN(MEMC_DREQ0),
+- GPIO_FN(MEMC_WAIT), GPIO_FN(MEMC_DREQ1), GPIO_FN(MEMC_BUSCLK),
+- GPIO_FN(MEMC_A0),
+-
+- /* MMC */
+- GPIO_FN(MMC0_D0_PORT68), GPIO_FN(MMC0_D1_PORT69),
+- GPIO_FN(MMC0_D2_PORT70), GPIO_FN(MMC0_D3_PORT71),
+- GPIO_FN(MMC0_D4_PORT72), GPIO_FN(MMC0_D5_PORT73),
+- GPIO_FN(MMC0_D6_PORT74), GPIO_FN(MMC0_D7_PORT75),
+- GPIO_FN(MMC0_CLK_PORT66),
+- GPIO_FN(MMC0_CMD_PORT67), /* MSEL4CR_15_0 */
+-
+- GPIO_FN(MMC1_D0_PORT149), GPIO_FN(MMC1_D1_PORT148),
+- GPIO_FN(MMC1_D2_PORT147), GPIO_FN(MMC1_D3_PORT146),
+- GPIO_FN(MMC1_D4_PORT145), GPIO_FN(MMC1_D5_PORT144),
+- GPIO_FN(MMC1_D6_PORT143), GPIO_FN(MMC1_D7_PORT142),
+- GPIO_FN(MMC1_CLK_PORT103),
+- GPIO_FN(MMC1_CMD_PORT104), /* MSEL4CR_15_1 */
+-
+- /* MSIOF0 */
+- GPIO_FN(MSIOF0_SS1), GPIO_FN(MSIOF0_SS2), GPIO_FN(MSIOF0_RXD),
+- GPIO_FN(MSIOF0_TXD), GPIO_FN(MSIOF0_MCK0), GPIO_FN(MSIOF0_MCK1),
+- GPIO_FN(MSIOF0_RSYNC), GPIO_FN(MSIOF0_RSCK), GPIO_FN(MSIOF0_TSCK),
+- GPIO_FN(MSIOF0_TSYNC),
+-
+- /* MSIOF1 */
+- GPIO_FN(MSIOF1_RSCK), GPIO_FN(MSIOF1_RSYNC),
+- GPIO_FN(MSIOF1_MCK0), GPIO_FN(MSIOF1_MCK1),
+-
+- GPIO_FN(MSIOF1_SS2_PORT116), GPIO_FN(MSIOF1_SS1_PORT117),
+- GPIO_FN(MSIOF1_RXD_PORT118), GPIO_FN(MSIOF1_TXD_PORT119),
+- GPIO_FN(MSIOF1_TSYNC_PORT120),
+- GPIO_FN(MSIOF1_TSCK_PORT121), /* MSEL4CR_10_0 */
+-
+- GPIO_FN(MSIOF1_SS1_PORT67), GPIO_FN(MSIOF1_TSCK_PORT72),
+- GPIO_FN(MSIOF1_TSYNC_PORT73), GPIO_FN(MSIOF1_TXD_PORT74),
+- GPIO_FN(MSIOF1_RXD_PORT75),
+- GPIO_FN(MSIOF1_SS2_PORT202), /* MSEL4CR_10_1 */
+-
+- /* GPIO */
+- GPIO_FN(GPO0), GPIO_FN(GPI0),
+- GPIO_FN(GPO1), GPIO_FN(GPI1),
+-
+- /* USB0 */
+- GPIO_FN(USB0_OCI), GPIO_FN(USB0_PPON), GPIO_FN(VBUS),
+-
+- /* USB1 */
+- GPIO_FN(USB1_OCI), GPIO_FN(USB1_PPON),
+-
+- /* BBIF1 */
+- GPIO_FN(BBIF1_RXD), GPIO_FN(BBIF1_TXD), GPIO_FN(BBIF1_TSYNC),
+- GPIO_FN(BBIF1_TSCK), GPIO_FN(BBIF1_RSCK), GPIO_FN(BBIF1_RSYNC),
+- GPIO_FN(BBIF1_FLOW), GPIO_FN(BBIF1_RX_FLOW_N),
+-
+- /* BBIF2 */
+- GPIO_FN(BBIF2_TXD2_PORT5), /* MSEL5CR_0_0 */
+- GPIO_FN(BBIF2_RXD2_PORT60),
+- GPIO_FN(BBIF2_TSYNC2_PORT6),
+- GPIO_FN(BBIF2_TSCK2_PORT59),
+-
+- GPIO_FN(BBIF2_RXD2_PORT90), /* MSEL5CR_0_1 */
+- GPIO_FN(BBIF2_TXD2_PORT183),
+- GPIO_FN(BBIF2_TSCK2_PORT89),
+- GPIO_FN(BBIF2_TSYNC2_PORT184),
+-
+- /* BSC / FLCTL / PCMCIA */
+- GPIO_FN(CS0), GPIO_FN(CS2), GPIO_FN(CS4),
+- GPIO_FN(CS5B), GPIO_FN(CS6A),
+- GPIO_FN(CS5A_PORT105), /* CS5A PORT 19/105 */
+- GPIO_FN(CS5A_PORT19),
+- GPIO_FN(IOIS16), /* ? */
+-
+- GPIO_FN(A0), GPIO_FN(A1), GPIO_FN(A2), GPIO_FN(A3),
+- GPIO_FN(A4_FOE), GPIO_FN(A5_FCDE), /* share with FLCTL */
+- GPIO_FN(A6), GPIO_FN(A7), GPIO_FN(A8), GPIO_FN(A9),
+- GPIO_FN(A10), GPIO_FN(A11), GPIO_FN(A12), GPIO_FN(A13),
+- GPIO_FN(A14), GPIO_FN(A15), GPIO_FN(A16), GPIO_FN(A17),
+- GPIO_FN(A18), GPIO_FN(A19), GPIO_FN(A20), GPIO_FN(A21),
+- GPIO_FN(A22), GPIO_FN(A23), GPIO_FN(A24), GPIO_FN(A25),
+- GPIO_FN(A26),
+-
+- GPIO_FN(D0_NAF0), GPIO_FN(D1_NAF1), /* share with FLCTL */
+- GPIO_FN(D2_NAF2), GPIO_FN(D3_NAF3), /* share with FLCTL */
+- GPIO_FN(D4_NAF4), GPIO_FN(D5_NAF5), /* share with FLCTL */
+- GPIO_FN(D6_NAF6), GPIO_FN(D7_NAF7), /* share with FLCTL */
+- GPIO_FN(D8_NAF8), GPIO_FN(D9_NAF9), /* share with FLCTL */
+- GPIO_FN(D10_NAF10), GPIO_FN(D11_NAF11), /* share with FLCTL */
+- GPIO_FN(D12_NAF12), GPIO_FN(D13_NAF13), /* share with FLCTL */
+- GPIO_FN(D14_NAF14), GPIO_FN(D15_NAF15), /* share with FLCTL */
+- GPIO_FN(D16), GPIO_FN(D17), GPIO_FN(D18), GPIO_FN(D19),
+- GPIO_FN(D20), GPIO_FN(D21), GPIO_FN(D22), GPIO_FN(D23),
+- GPIO_FN(D24), GPIO_FN(D25), GPIO_FN(D26), GPIO_FN(D27),
+- GPIO_FN(D28), GPIO_FN(D29), GPIO_FN(D30), GPIO_FN(D31),
+-
+- GPIO_FN(WE0_FWE), /* share with FLCTL */
+- GPIO_FN(WE1),
+- GPIO_FN(WE2_ICIORD), /* share with PCMCIA */
+- GPIO_FN(WE3_ICIOWR), /* share with PCMCIA */
+- GPIO_FN(CKO), GPIO_FN(BS), GPIO_FN(RDWR),
+- GPIO_FN(RD_FSC), /* share with FLCTL */
+- GPIO_FN(WAIT_PORT177), /* WAIT Port 90/177 */
+- GPIO_FN(WAIT_PORT90),
+-
+- GPIO_FN(FCE0), GPIO_FN(FCE1), GPIO_FN(FRB), /* FLCTL */
+-
+- /* IRDA */
+- GPIO_FN(IRDA_FIRSEL), GPIO_FN(IRDA_IN), GPIO_FN(IRDA_OUT),
+-
+- /* ATAPI */
+- GPIO_FN(IDE_D0), GPIO_FN(IDE_D1), GPIO_FN(IDE_D2),
+- GPIO_FN(IDE_D3), GPIO_FN(IDE_D4), GPIO_FN(IDE_D5),
+- GPIO_FN(IDE_D6), GPIO_FN(IDE_D7), GPIO_FN(IDE_D8),
+- GPIO_FN(IDE_D9), GPIO_FN(IDE_D10), GPIO_FN(IDE_D11),
+- GPIO_FN(IDE_D12), GPIO_FN(IDE_D13), GPIO_FN(IDE_D14),
+- GPIO_FN(IDE_D15), GPIO_FN(IDE_A0), GPIO_FN(IDE_A1),
+- GPIO_FN(IDE_A2), GPIO_FN(IDE_CS0), GPIO_FN(IDE_CS1),
+- GPIO_FN(IDE_IOWR), GPIO_FN(IDE_IORD), GPIO_FN(IDE_IORDY),
+- GPIO_FN(IDE_INT), GPIO_FN(IDE_RST), GPIO_FN(IDE_DIRECTION),
+- GPIO_FN(IDE_EXBUF_ENB), GPIO_FN(IDE_IODACK), GPIO_FN(IDE_IODREQ),
+-
+- /* RMII */
+- GPIO_FN(RMII_CRS_DV), GPIO_FN(RMII_RX_ER), GPIO_FN(RMII_RXD0),
+- GPIO_FN(RMII_RXD1), GPIO_FN(RMII_TX_EN), GPIO_FN(RMII_TXD0),
+- GPIO_FN(RMII_MDC), GPIO_FN(RMII_TXD1), GPIO_FN(RMII_MDIO),
+- GPIO_FN(RMII_REF50CK), GPIO_FN(RMII_REF125CK), /* for GMII */
+-
+- /* GEther */
+- GPIO_FN(ET_TX_CLK), GPIO_FN(ET_TX_EN), GPIO_FN(ET_ETXD0),
+- GPIO_FN(ET_ETXD1), GPIO_FN(ET_ETXD2), GPIO_FN(ET_ETXD3),
+- GPIO_FN(ET_ETXD4), GPIO_FN(ET_ETXD5), /* for GEther */
+- GPIO_FN(ET_ETXD6), GPIO_FN(ET_ETXD7), /* for GEther */
+- GPIO_FN(ET_COL), GPIO_FN(ET_TX_ER), GPIO_FN(ET_RX_CLK),
+- GPIO_FN(ET_RX_DV), GPIO_FN(ET_ERXD0), GPIO_FN(ET_ERXD1),
+- GPIO_FN(ET_ERXD2), GPIO_FN(ET_ERXD3),
+- GPIO_FN(ET_ERXD4), GPIO_FN(ET_ERXD5), /* for GEther */
+- GPIO_FN(ET_ERXD6), GPIO_FN(ET_ERXD7), /* for GEther */
+- GPIO_FN(ET_RX_ER), GPIO_FN(ET_CRS), GPIO_FN(ET_MDC),
+- GPIO_FN(ET_MDIO), GPIO_FN(ET_LINK), GPIO_FN(ET_PHY_INT),
+- GPIO_FN(ET_WOL), GPIO_FN(ET_GTX_CLK),
+-
+- /* DMA0 */
+- GPIO_FN(DREQ0), GPIO_FN(DACK0),
+-
+- /* DMA1 */
+- GPIO_FN(DREQ1), GPIO_FN(DACK1),
+-
+- /* SYSC */
+- GPIO_FN(RESETOUTS),
+-
+- /* IRREM */
+- GPIO_FN(IROUT),
+-
+- /* LCDC */
+- GPIO_FN(LCDC0_SELECT),
+- GPIO_FN(LCDC1_SELECT),
+-
+- /* SDENC */
+- GPIO_FN(SDENC_CPG),
+- GPIO_FN(SDENC_DV_CLKI),
+-
+- /* SYSC */
+- GPIO_FN(RESETP_PULLUP),
+- GPIO_FN(RESETP_PLAIN),
+-
+- /* DEBUG */
+- GPIO_FN(EDEBGREQ_PULLDOWN),
+- GPIO_FN(EDEBGREQ_PULLUP),
+-
+- GPIO_FN(TRACEAUD_FROM_VIO),
+- GPIO_FN(TRACEAUD_FROM_LCDC0),
+- GPIO_FN(TRACEAUD_FROM_MEMC),
+-};
+-
+-static struct pinmux_cfg_reg pinmux_config_regs[] = {
+- PORTCR(0, 0xe6050000), /* PORT0CR */
+- PORTCR(1, 0xe6050001), /* PORT1CR */
+- PORTCR(2, 0xe6050002), /* PORT2CR */
+- PORTCR(3, 0xe6050003), /* PORT3CR */
+- PORTCR(4, 0xe6050004), /* PORT4CR */
+- PORTCR(5, 0xe6050005), /* PORT5CR */
+- PORTCR(6, 0xe6050006), /* PORT6CR */
+- PORTCR(7, 0xe6050007), /* PORT7CR */
+- PORTCR(8, 0xe6050008), /* PORT8CR */
+- PORTCR(9, 0xe6050009), /* PORT9CR */
+- PORTCR(10, 0xe605000a), /* PORT10CR */
+- PORTCR(11, 0xe605000b), /* PORT11CR */
+- PORTCR(12, 0xe605000c), /* PORT12CR */
+- PORTCR(13, 0xe605000d), /* PORT13CR */
+- PORTCR(14, 0xe605000e), /* PORT14CR */
+- PORTCR(15, 0xe605000f), /* PORT15CR */
+- PORTCR(16, 0xe6050010), /* PORT16CR */
+- PORTCR(17, 0xe6050011), /* PORT17CR */
+- PORTCR(18, 0xe6050012), /* PORT18CR */
+- PORTCR(19, 0xe6050013), /* PORT19CR */
+- PORTCR(20, 0xe6050014), /* PORT20CR */
+- PORTCR(21, 0xe6050015), /* PORT21CR */
+- PORTCR(22, 0xe6050016), /* PORT22CR */
+- PORTCR(23, 0xe6050017), /* PORT23CR */
+- PORTCR(24, 0xe6050018), /* PORT24CR */
+- PORTCR(25, 0xe6050019), /* PORT25CR */
+- PORTCR(26, 0xe605001a), /* PORT26CR */
+- PORTCR(27, 0xe605001b), /* PORT27CR */
+- PORTCR(28, 0xe605001c), /* PORT28CR */
+- PORTCR(29, 0xe605001d), /* PORT29CR */
+- PORTCR(30, 0xe605001e), /* PORT30CR */
+- PORTCR(31, 0xe605001f), /* PORT31CR */
+- PORTCR(32, 0xe6050020), /* PORT32CR */
+- PORTCR(33, 0xe6050021), /* PORT33CR */
+- PORTCR(34, 0xe6050022), /* PORT34CR */
+- PORTCR(35, 0xe6050023), /* PORT35CR */
+- PORTCR(36, 0xe6050024), /* PORT36CR */
+- PORTCR(37, 0xe6050025), /* PORT37CR */
+- PORTCR(38, 0xe6050026), /* PORT38CR */
+- PORTCR(39, 0xe6050027), /* PORT39CR */
+- PORTCR(40, 0xe6050028), /* PORT40CR */
+- PORTCR(41, 0xe6050029), /* PORT41CR */
+- PORTCR(42, 0xe605002a), /* PORT42CR */
+- PORTCR(43, 0xe605002b), /* PORT43CR */
+- PORTCR(44, 0xe605002c), /* PORT44CR */
+- PORTCR(45, 0xe605002d), /* PORT45CR */
+- PORTCR(46, 0xe605002e), /* PORT46CR */
+- PORTCR(47, 0xe605002f), /* PORT47CR */
+- PORTCR(48, 0xe6050030), /* PORT48CR */
+- PORTCR(49, 0xe6050031), /* PORT49CR */
+- PORTCR(50, 0xe6050032), /* PORT50CR */
+- PORTCR(51, 0xe6050033), /* PORT51CR */
+- PORTCR(52, 0xe6050034), /* PORT52CR */
+- PORTCR(53, 0xe6050035), /* PORT53CR */
+- PORTCR(54, 0xe6050036), /* PORT54CR */
+- PORTCR(55, 0xe6050037), /* PORT55CR */
+- PORTCR(56, 0xe6050038), /* PORT56CR */
+- PORTCR(57, 0xe6050039), /* PORT57CR */
+- PORTCR(58, 0xe605003a), /* PORT58CR */
+- PORTCR(59, 0xe605003b), /* PORT59CR */
+- PORTCR(60, 0xe605003c), /* PORT60CR */
+- PORTCR(61, 0xe605003d), /* PORT61CR */
+- PORTCR(62, 0xe605003e), /* PORT62CR */
+- PORTCR(63, 0xe605003f), /* PORT63CR */
+- PORTCR(64, 0xe6050040), /* PORT64CR */
+- PORTCR(65, 0xe6050041), /* PORT65CR */
+- PORTCR(66, 0xe6050042), /* PORT66CR */
+- PORTCR(67, 0xe6050043), /* PORT67CR */
+- PORTCR(68, 0xe6050044), /* PORT68CR */
+- PORTCR(69, 0xe6050045), /* PORT69CR */
+- PORTCR(70, 0xe6050046), /* PORT70CR */
+- PORTCR(71, 0xe6050047), /* PORT71CR */
+- PORTCR(72, 0xe6050048), /* PORT72CR */
+- PORTCR(73, 0xe6050049), /* PORT73CR */
+- PORTCR(74, 0xe605004a), /* PORT74CR */
+- PORTCR(75, 0xe605004b), /* PORT75CR */
+- PORTCR(76, 0xe605004c), /* PORT76CR */
+- PORTCR(77, 0xe605004d), /* PORT77CR */
+- PORTCR(78, 0xe605004e), /* PORT78CR */
+- PORTCR(79, 0xe605004f), /* PORT79CR */
+- PORTCR(80, 0xe6050050), /* PORT80CR */
+- PORTCR(81, 0xe6050051), /* PORT81CR */
+- PORTCR(82, 0xe6050052), /* PORT82CR */
+- PORTCR(83, 0xe6050053), /* PORT83CR */
+-
+- PORTCR(84, 0xe6051054), /* PORT84CR */
+- PORTCR(85, 0xe6051055), /* PORT85CR */
+- PORTCR(86, 0xe6051056), /* PORT86CR */
+- PORTCR(87, 0xe6051057), /* PORT87CR */
+- PORTCR(88, 0xe6051058), /* PORT88CR */
+- PORTCR(89, 0xe6051059), /* PORT89CR */
+- PORTCR(90, 0xe605105a), /* PORT90CR */
+- PORTCR(91, 0xe605105b), /* PORT91CR */
+- PORTCR(92, 0xe605105c), /* PORT92CR */
+- PORTCR(93, 0xe605105d), /* PORT93CR */
+- PORTCR(94, 0xe605105e), /* PORT94CR */
+- PORTCR(95, 0xe605105f), /* PORT95CR */
+- PORTCR(96, 0xe6051060), /* PORT96CR */
+- PORTCR(97, 0xe6051061), /* PORT97CR */
+- PORTCR(98, 0xe6051062), /* PORT98CR */
+- PORTCR(99, 0xe6051063), /* PORT99CR */
+- PORTCR(100, 0xe6051064), /* PORT100CR */
+- PORTCR(101, 0xe6051065), /* PORT101CR */
+- PORTCR(102, 0xe6051066), /* PORT102CR */
+- PORTCR(103, 0xe6051067), /* PORT103CR */
+- PORTCR(104, 0xe6051068), /* PORT104CR */
+- PORTCR(105, 0xe6051069), /* PORT105CR */
+- PORTCR(106, 0xe605106a), /* PORT106CR */
+- PORTCR(107, 0xe605106b), /* PORT107CR */
+- PORTCR(108, 0xe605106c), /* PORT108CR */
+- PORTCR(109, 0xe605106d), /* PORT109CR */
+- PORTCR(110, 0xe605106e), /* PORT110CR */
+- PORTCR(111, 0xe605106f), /* PORT111CR */
+- PORTCR(112, 0xe6051070), /* PORT112CR */
+- PORTCR(113, 0xe6051071), /* PORT113CR */
+- PORTCR(114, 0xe6051072), /* PORT114CR */
+-
+- PORTCR(115, 0xe6052073), /* PORT115CR */
+- PORTCR(116, 0xe6052074), /* PORT116CR */
+- PORTCR(117, 0xe6052075), /* PORT117CR */
+- PORTCR(118, 0xe6052076), /* PORT118CR */
+- PORTCR(119, 0xe6052077), /* PORT119CR */
+- PORTCR(120, 0xe6052078), /* PORT120CR */
+- PORTCR(121, 0xe6052079), /* PORT121CR */
+- PORTCR(122, 0xe605207a), /* PORT122CR */
+- PORTCR(123, 0xe605207b), /* PORT123CR */
+- PORTCR(124, 0xe605207c), /* PORT124CR */
+- PORTCR(125, 0xe605207d), /* PORT125CR */
+- PORTCR(126, 0xe605207e), /* PORT126CR */
+- PORTCR(127, 0xe605207f), /* PORT127CR */
+- PORTCR(128, 0xe6052080), /* PORT128CR */
+- PORTCR(129, 0xe6052081), /* PORT129CR */
+- PORTCR(130, 0xe6052082), /* PORT130CR */
+- PORTCR(131, 0xe6052083), /* PORT131CR */
+- PORTCR(132, 0xe6052084), /* PORT132CR */
+- PORTCR(133, 0xe6052085), /* PORT133CR */
+- PORTCR(134, 0xe6052086), /* PORT134CR */
+- PORTCR(135, 0xe6052087), /* PORT135CR */
+- PORTCR(136, 0xe6052088), /* PORT136CR */
+- PORTCR(137, 0xe6052089), /* PORT137CR */
+- PORTCR(138, 0xe605208a), /* PORT138CR */
+- PORTCR(139, 0xe605208b), /* PORT139CR */
+- PORTCR(140, 0xe605208c), /* PORT140CR */
+- PORTCR(141, 0xe605208d), /* PORT141CR */
+- PORTCR(142, 0xe605208e), /* PORT142CR */
+- PORTCR(143, 0xe605208f), /* PORT143CR */
+- PORTCR(144, 0xe6052090), /* PORT144CR */
+- PORTCR(145, 0xe6052091), /* PORT145CR */
+- PORTCR(146, 0xe6052092), /* PORT146CR */
+- PORTCR(147, 0xe6052093), /* PORT147CR */
+- PORTCR(148, 0xe6052094), /* PORT148CR */
+- PORTCR(149, 0xe6052095), /* PORT149CR */
+- PORTCR(150, 0xe6052096), /* PORT150CR */
+- PORTCR(151, 0xe6052097), /* PORT151CR */
+- PORTCR(152, 0xe6052098), /* PORT152CR */
+- PORTCR(153, 0xe6052099), /* PORT153CR */
+- PORTCR(154, 0xe605209a), /* PORT154CR */
+- PORTCR(155, 0xe605209b), /* PORT155CR */
+- PORTCR(156, 0xe605209c), /* PORT156CR */
+- PORTCR(157, 0xe605209d), /* PORT157CR */
+- PORTCR(158, 0xe605209e), /* PORT158CR */
+- PORTCR(159, 0xe605209f), /* PORT159CR */
+- PORTCR(160, 0xe60520a0), /* PORT160CR */
+- PORTCR(161, 0xe60520a1), /* PORT161CR */
+- PORTCR(162, 0xe60520a2), /* PORT162CR */
+- PORTCR(163, 0xe60520a3), /* PORT163CR */
+- PORTCR(164, 0xe60520a4), /* PORT164CR */
+- PORTCR(165, 0xe60520a5), /* PORT165CR */
+- PORTCR(166, 0xe60520a6), /* PORT166CR */
+- PORTCR(167, 0xe60520a7), /* PORT167CR */
+- PORTCR(168, 0xe60520a8), /* PORT168CR */
+- PORTCR(169, 0xe60520a9), /* PORT169CR */
+- PORTCR(170, 0xe60520aa), /* PORT170CR */
+- PORTCR(171, 0xe60520ab), /* PORT171CR */
+- PORTCR(172, 0xe60520ac), /* PORT172CR */
+- PORTCR(173, 0xe60520ad), /* PORT173CR */
+- PORTCR(174, 0xe60520ae), /* PORT174CR */
+- PORTCR(175, 0xe60520af), /* PORT175CR */
+- PORTCR(176, 0xe60520b0), /* PORT176CR */
+- PORTCR(177, 0xe60520b1), /* PORT177CR */
+- PORTCR(178, 0xe60520b2), /* PORT178CR */
+- PORTCR(179, 0xe60520b3), /* PORT179CR */
+- PORTCR(180, 0xe60520b4), /* PORT180CR */
+- PORTCR(181, 0xe60520b5), /* PORT181CR */
+- PORTCR(182, 0xe60520b6), /* PORT182CR */
+- PORTCR(183, 0xe60520b7), /* PORT183CR */
+- PORTCR(184, 0xe60520b8), /* PORT184CR */
+- PORTCR(185, 0xe60520b9), /* PORT185CR */
+- PORTCR(186, 0xe60520ba), /* PORT186CR */
+- PORTCR(187, 0xe60520bb), /* PORT187CR */
+- PORTCR(188, 0xe60520bc), /* PORT188CR */
+- PORTCR(189, 0xe60520bd), /* PORT189CR */
+- PORTCR(190, 0xe60520be), /* PORT190CR */
+- PORTCR(191, 0xe60520bf), /* PORT191CR */
+- PORTCR(192, 0xe60520c0), /* PORT192CR */
+- PORTCR(193, 0xe60520c1), /* PORT193CR */
+- PORTCR(194, 0xe60520c2), /* PORT194CR */
+- PORTCR(195, 0xe60520c3), /* PORT195CR */
+- PORTCR(196, 0xe60520c4), /* PORT196CR */
+- PORTCR(197, 0xe60520c5), /* PORT197CR */
+- PORTCR(198, 0xe60520c6), /* PORT198CR */
+- PORTCR(199, 0xe60520c7), /* PORT199CR */
+- PORTCR(200, 0xe60520c8), /* PORT200CR */
+- PORTCR(201, 0xe60520c9), /* PORT201CR */
+- PORTCR(202, 0xe60520ca), /* PORT202CR */
+- PORTCR(203, 0xe60520cb), /* PORT203CR */
+- PORTCR(204, 0xe60520cc), /* PORT204CR */
+- PORTCR(205, 0xe60520cd), /* PORT205CR */
+- PORTCR(206, 0xe60520ce), /* PORT206CR */
+- PORTCR(207, 0xe60520cf), /* PORT207CR */
+- PORTCR(208, 0xe60520d0), /* PORT208CR */
+- PORTCR(209, 0xe60520d1), /* PORT209CR */
+-
+- PORTCR(210, 0xe60530d2), /* PORT210CR */
+- PORTCR(211, 0xe60530d3), /* PORT211CR */
+-
+- { PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1) {
+- MSEL1CR_31_0, MSEL1CR_31_1,
+- MSEL1CR_30_0, MSEL1CR_30_1,
+- MSEL1CR_29_0, MSEL1CR_29_1,
+- MSEL1CR_28_0, MSEL1CR_28_1,
+- MSEL1CR_27_0, MSEL1CR_27_1,
+- MSEL1CR_26_0, MSEL1CR_26_1,
+- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+- 0, 0, 0, 0, 0, 0, 0, 0,
+- MSEL1CR_16_0, MSEL1CR_16_1,
+- MSEL1CR_15_0, MSEL1CR_15_1,
+- MSEL1CR_14_0, MSEL1CR_14_1,
+- MSEL1CR_13_0, MSEL1CR_13_1,
+- MSEL1CR_12_0, MSEL1CR_12_1,
+- 0, 0, 0, 0,
+- MSEL1CR_9_0, MSEL1CR_9_1,
+- 0, 0,
+- MSEL1CR_7_0, MSEL1CR_7_1,
+- MSEL1CR_6_0, MSEL1CR_6_1,
+- MSEL1CR_5_0, MSEL1CR_5_1,
+- MSEL1CR_4_0, MSEL1CR_4_1,
+- MSEL1CR_3_0, MSEL1CR_3_1,
+- MSEL1CR_2_0, MSEL1CR_2_1,
+- 0, 0,
+- MSEL1CR_0_0, MSEL1CR_0_1,
+- }
+- },
+- { PINMUX_CFG_REG("MSEL3CR", 0xE6058020, 32, 1) {
+- 0, 0, 0, 0, 0, 0, 0, 0,
+- 0, 0, 0, 0, 0, 0, 0, 0,
+- 0, 0, 0, 0, 0, 0, 0, 0,
+- 0, 0, 0, 0, 0, 0, 0, 0,
+- MSEL3CR_15_0, MSEL3CR_15_1,
+- 0, 0, 0, 0, 0, 0, 0, 0,
+- 0, 0, 0, 0, 0, 0, 0, 0,
+- MSEL3CR_6_0, MSEL3CR_6_1,
+- 0, 0, 0, 0, 0, 0, 0, 0,
+- 0, 0, 0, 0,
+- }
+- },
+- { PINMUX_CFG_REG("MSEL4CR", 0xE6058024, 32, 1) {
+- 0, 0, 0, 0, 0, 0, 0, 0,
+- 0, 0, 0, 0, 0, 0, 0, 0,
+- 0, 0, 0, 0, 0, 0, 0, 0,
+- MSEL4CR_19_0, MSEL4CR_19_1,
+- MSEL4CR_18_0, MSEL4CR_18_1,
+- 0, 0, 0, 0,
+- MSEL4CR_15_0, MSEL4CR_15_1,
+- 0, 0, 0, 0, 0, 0, 0, 0,
+- MSEL4CR_10_0, MSEL4CR_10_1,
+- 0, 0, 0, 0, 0, 0,
+- MSEL4CR_6_0, MSEL4CR_6_1,
+- 0, 0,
+- MSEL4CR_4_0, MSEL4CR_4_1,
+- 0, 0, 0, 0,
+- MSEL4CR_1_0, MSEL4CR_1_1,
+- 0, 0,
+- }
+- },
+- { PINMUX_CFG_REG("MSEL5CR", 0xE6058028, 32, 1) {
+- MSEL5CR_31_0, MSEL5CR_31_1,
+- MSEL5CR_30_0, MSEL5CR_30_1,
+- MSEL5CR_29_0, MSEL5CR_29_1,
+- 0, 0,
+- MSEL5CR_27_0, MSEL5CR_27_1,
+- 0, 0,
+- MSEL5CR_25_0, MSEL5CR_25_1,
+- 0, 0,
+- MSEL5CR_23_0, MSEL5CR_23_1,
+- 0, 0,
+- MSEL5CR_21_0, MSEL5CR_21_1,
+- 0, 0,
+- MSEL5CR_19_0, MSEL5CR_19_1,
+- 0, 0,
+- MSEL5CR_17_0, MSEL5CR_17_1,
+- 0, 0,
+- MSEL5CR_15_0, MSEL5CR_15_1,
+- MSEL5CR_14_0, MSEL5CR_14_1,
+- MSEL5CR_13_0, MSEL5CR_13_1,
+- MSEL5CR_12_0, MSEL5CR_12_1,
+- MSEL5CR_11_0, MSEL5CR_11_1,
+- MSEL5CR_10_0, MSEL5CR_10_1,
+- 0, 0,
+- MSEL5CR_8_0, MSEL5CR_8_1,
+- MSEL5CR_7_0, MSEL5CR_7_1,
+- MSEL5CR_6_0, MSEL5CR_6_1,
+- MSEL5CR_5_0, MSEL5CR_5_1,
+- MSEL5CR_4_0, MSEL5CR_4_1,
+- MSEL5CR_3_0, MSEL5CR_3_1,
+- MSEL5CR_2_0, MSEL5CR_2_1,
+- 0, 0,
+- MSEL5CR_0_0, MSEL5CR_0_1,
+- }
+- },
+- { },
+-};
+-
+-static struct pinmux_data_reg pinmux_data_regs[] = {
+- { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054800, 32) {
+- PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
+- PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
+- PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
+- PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
+- PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
+- PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
+- PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
+- PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA }
+- },
+- { PINMUX_DATA_REG("PORTL063_032DR", 0xe6054804, 32) {
+- PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
+- PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
+- PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
+- PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
+- PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
+- PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
+- PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
+- PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA }
+- },
+- { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054808, 32) {
+- 0, 0, 0, 0,
+- 0, 0, 0, 0,
+- 0, 0, 0, 0,
+- PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
+- PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
+- PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
+- PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
+- PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA }
+- },
+- { PINMUX_DATA_REG("PORTD095_064DR", 0xe6055808, 32) {
+- PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
+- PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
+- PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
+- 0, 0, 0, 0,
+- 0, 0, 0, 0,
+- 0, 0, 0, 0,
+- 0, 0, 0, 0,
+- 0, 0, 0, 0 }
+- },
+- { PINMUX_DATA_REG("PORTD127_096DR", 0xe605580c, 32) {
+- 0, 0, 0, 0,
+- 0, 0, 0, 0,
+- 0, 0, 0, 0,
+- 0, PORT114_DATA, PORT113_DATA, PORT112_DATA,
+- PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
+- PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
+- PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
+- PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA }
+- },
+- { PINMUX_DATA_REG("PORTR127_096DR", 0xe605680C, 32) {
+- PORT127_DATA, PORT126_DATA, PORT125_DATA, PORT124_DATA,
+- PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA,
+- PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
+- PORT115_DATA, 0, 0, 0,
+- 0, 0, 0, 0,
+- 0, 0, 0, 0,
+- 0, 0, 0, 0,
+- 0, 0, 0, 0 }
+- },
+- { PINMUX_DATA_REG("PORTR159_128DR", 0xe6056810, 32) {
+- PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
+- PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
+- PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
+- PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
+- PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
+- PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
+- PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
+- PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA }
+- },
+- { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056814, 32) {
+- PORT191_DATA, PORT190_DATA, PORT189_DATA, PORT188_DATA,
+- PORT187_DATA, PORT186_DATA, PORT185_DATA, PORT184_DATA,
+- PORT183_DATA, PORT182_DATA, PORT181_DATA, PORT180_DATA,
+- PORT179_DATA, PORT178_DATA, PORT177_DATA, PORT176_DATA,
+- PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA,
+- PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
+- PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA,
+- PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA }
+- },
+- { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056818, 32) {
+- 0, 0, 0, 0,
+- 0, 0, 0, 0,
+- 0, 0, 0, 0,
+- 0, 0, PORT209_DATA, PORT208_DATA,
+- PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
+- PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
+- PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
+- PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA }
+- },
+- { PINMUX_DATA_REG("PORTU223_192DR", 0xe6057818, 32) {
+- 0, 0, 0, 0,
+- 0, 0, 0, 0,
+- 0, 0, 0, 0,
+- PORT211_DATA, PORT210_DATA, 0, 0,
+- 0, 0, 0, 0,
+- 0, 0, 0, 0,
+- 0, 0, 0, 0,
+- 0, 0, 0, 0 }
+- },
+- { },
+-};
+-
+-static struct pinmux_irq pinmux_irqs[] = {
+- PINMUX_IRQ(evt2irq(0x0200), PORT2_FN0, PORT13_FN0), /* IRQ0A */
+- PINMUX_IRQ(evt2irq(0x0220), PORT20_FN0), /* IRQ1A */
+- PINMUX_IRQ(evt2irq(0x0240), PORT11_FN0, PORT12_FN0), /* IRQ2A */
+- PINMUX_IRQ(evt2irq(0x0260), PORT10_FN0, PORT14_FN0), /* IRQ3A */
+- PINMUX_IRQ(evt2irq(0x0280), PORT15_FN0, PORT172_FN0), /* IRQ4A */
+- PINMUX_IRQ(evt2irq(0x02A0), PORT0_FN0, PORT1_FN0), /* IRQ5A */
+- PINMUX_IRQ(evt2irq(0x02C0), PORT121_FN0, PORT173_FN0), /* IRQ6A */
+- PINMUX_IRQ(evt2irq(0x02E0), PORT120_FN0, PORT209_FN0), /* IRQ7A */
+- PINMUX_IRQ(evt2irq(0x0300), PORT119_FN0), /* IRQ8A */
+- PINMUX_IRQ(evt2irq(0x0320), PORT118_FN0, PORT210_FN0), /* IRQ9A */
+- PINMUX_IRQ(evt2irq(0x0340), PORT19_FN0), /* IRQ10A */
+- PINMUX_IRQ(evt2irq(0x0360), PORT104_FN0), /* IRQ11A */
+- PINMUX_IRQ(evt2irq(0x0380), PORT42_FN0, PORT97_FN0), /* IRQ12A */
+- PINMUX_IRQ(evt2irq(0x03A0), PORT64_FN0, PORT98_FN0), /* IRQ13A */
+- PINMUX_IRQ(evt2irq(0x03C0), PORT63_FN0, PORT99_FN0), /* IRQ14A */
+- PINMUX_IRQ(evt2irq(0x03E0), PORT62_FN0, PORT100_FN0), /* IRQ15A */
+- PINMUX_IRQ(evt2irq(0x3200), PORT68_FN0, PORT211_FN0), /* IRQ16A */
+- PINMUX_IRQ(evt2irq(0x3220), PORT69_FN0), /* IRQ17A */
+- PINMUX_IRQ(evt2irq(0x3240), PORT70_FN0), /* IRQ18A */
+- PINMUX_IRQ(evt2irq(0x3260), PORT71_FN0), /* IRQ19A */
+- PINMUX_IRQ(evt2irq(0x3280), PORT67_FN0), /* IRQ20A */
+- PINMUX_IRQ(evt2irq(0x32A0), PORT202_FN0), /* IRQ21A */
+- PINMUX_IRQ(evt2irq(0x32C0), PORT95_FN0), /* IRQ22A */
+- PINMUX_IRQ(evt2irq(0x32E0), PORT96_FN0), /* IRQ23A */
+- PINMUX_IRQ(evt2irq(0x3300), PORT180_FN0), /* IRQ24A */
+- PINMUX_IRQ(evt2irq(0x3320), PORT38_FN0), /* IRQ25A */
+- PINMUX_IRQ(evt2irq(0x3340), PORT58_FN0, PORT81_FN0), /* IRQ26A */
+- PINMUX_IRQ(evt2irq(0x3360), PORT57_FN0, PORT168_FN0), /* IRQ27A */
+- PINMUX_IRQ(evt2irq(0x3380), PORT56_FN0, PORT169_FN0), /* IRQ28A */
+- PINMUX_IRQ(evt2irq(0x33A0), PORT50_FN0, PORT170_FN0), /* IRQ29A */
+- PINMUX_IRQ(evt2irq(0x33C0), PORT49_FN0, PORT171_FN0), /* IRQ30A */
+- PINMUX_IRQ(evt2irq(0x33E0), PORT41_FN0, PORT167_FN0), /* IRQ31A */
+-};
+-
+-static struct pinmux_info r8a7740_pinmux_info = {
+- .name = "r8a7740_pfc",
+- .reserved_id = PINMUX_RESERVED,
+- .data = { PINMUX_DATA_BEGIN,
+- PINMUX_DATA_END },
+- .input = { PINMUX_INPUT_BEGIN,
+- PINMUX_INPUT_END },
+- .input_pu = { PINMUX_INPUT_PULLUP_BEGIN,
+- PINMUX_INPUT_PULLUP_END },
+- .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN,
+- PINMUX_INPUT_PULLDOWN_END },
+- .output = { PINMUX_OUTPUT_BEGIN,
+- PINMUX_OUTPUT_END },
+- .mark = { PINMUX_MARK_BEGIN,
+- PINMUX_MARK_END },
+- .function = { PINMUX_FUNCTION_BEGIN,
+- PINMUX_FUNCTION_END },
+-
+- .first_gpio = GPIO_PORT0,
+- .last_gpio = GPIO_FN_TRACEAUD_FROM_MEMC,
+-
+- .gpios = pinmux_gpios,
+- .cfg_regs = pinmux_config_regs,
+- .data_regs = pinmux_data_regs,
+-
+- .gpio_data = pinmux_data,
+- .gpio_data_size = ARRAY_SIZE(pinmux_data),
+-
+- .gpio_irq = pinmux_irqs,
+- .gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
+-};
+-
+-void r8a7740_pinmux_init(void)
+-{
+- register_pinmux(&r8a7740_pinmux_info);
+-}
+diff --git a/arch/arm/cpu/armv7/rmobile/pfc-sh73a0.c b/arch/arm/cpu/armv7/rmobile/pfc-sh73a0.c
+deleted file mode 100644
+index 55dab7c..0000000
+--- a/arch/arm/cpu/armv7/rmobile/pfc-sh73a0.c
++++ /dev/null
+@@ -1,2807 +0,0 @@
+-/*
+- * sh73a0 processor support - PFC hardware block
+- *
+- * Copyright (C) 2010 Renesas Solutions Corp.
+- * Copyright (C) 2010 NISHIMOTO Hiroki
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; version 2 of the
+- * License.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+- */
+-
+-#include <common.h>
+-#include <sh_pfc.h>
+-#include <asm/arch/sh73a0-gpio.h>
+-
+-#define CPU_ALL_PORT(fn, pfx, sfx) \
+- PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
+- PORT_10(fn, pfx##2, sfx), PORT_10(fn, pfx##3, sfx), \
+- PORT_10(fn, pfx##4, sfx), PORT_10(fn, pfx##5, sfx), \
+- PORT_10(fn, pfx##6, sfx), PORT_10(fn, pfx##7, sfx), \
+- PORT_10(fn, pfx##8, sfx), PORT_10(fn, pfx##9, sfx), \
+- PORT_10(fn, pfx##10, sfx), \
+- PORT_1(fn, pfx##110, sfx), PORT_1(fn, pfx##111, sfx), \
+- PORT_1(fn, pfx##112, sfx), PORT_1(fn, pfx##113, sfx), \
+- PORT_1(fn, pfx##114, sfx), PORT_1(fn, pfx##115, sfx), \
+- PORT_1(fn, pfx##116, sfx), PORT_1(fn, pfx##117, sfx), \
+- PORT_1(fn, pfx##118, sfx), \
+- PORT_1(fn, pfx##128, sfx), PORT_1(fn, pfx##129, sfx), \
+- PORT_10(fn, pfx##13, sfx), PORT_10(fn, pfx##14, sfx), \
+- PORT_10(fn, pfx##15, sfx), \
+- PORT_1(fn, pfx##160, sfx), PORT_1(fn, pfx##161, sfx), \
+- PORT_1(fn, pfx##162, sfx), PORT_1(fn, pfx##163, sfx), \
+- PORT_1(fn, pfx##164, sfx), \
+- PORT_1(fn, pfx##192, sfx), PORT_1(fn, pfx##193, sfx), \
+- PORT_1(fn, pfx##194, sfx), PORT_1(fn, pfx##195, sfx), \
+- PORT_1(fn, pfx##196, sfx), PORT_1(fn, pfx##197, sfx), \
+- PORT_1(fn, pfx##198, sfx), PORT_1(fn, pfx##199, sfx), \
+- PORT_10(fn, pfx##20, sfx), PORT_10(fn, pfx##21, sfx), \
+- PORT_10(fn, pfx##22, sfx), PORT_10(fn, pfx##23, sfx), \
+- PORT_10(fn, pfx##24, sfx), PORT_10(fn, pfx##25, sfx), \
+- PORT_10(fn, pfx##26, sfx), PORT_10(fn, pfx##27, sfx), \
+- PORT_1(fn, pfx##280, sfx), PORT_1(fn, pfx##281, sfx), \
+- PORT_1(fn, pfx##282, sfx), \
+- PORT_1(fn, pfx##288, sfx), PORT_1(fn, pfx##289, sfx), \
+- PORT_10(fn, pfx##29, sfx), PORT_10(fn, pfx##30, sfx)
+-
+-enum {
+- PINMUX_RESERVED = 0,
+-
+- PINMUX_DATA_BEGIN,
+- PORT_ALL(DATA), /* PORT0_DATA -> PORT309_DATA */
+- PINMUX_DATA_END,
+-
+- PINMUX_INPUT_BEGIN,
+- PORT_ALL(IN), /* PORT0_IN -> PORT309_IN */
+- PINMUX_INPUT_END,
+-
+- PINMUX_INPUT_PULLUP_BEGIN,
+- PORT_ALL(IN_PU), /* PORT0_IN_PU -> PORT309_IN_PU */
+- PINMUX_INPUT_PULLUP_END,
+-
+- PINMUX_INPUT_PULLDOWN_BEGIN,
+- PORT_ALL(IN_PD), /* PORT0_IN_PD -> PORT309_IN_PD */
+- PINMUX_INPUT_PULLDOWN_END,
+-
+- PINMUX_OUTPUT_BEGIN,
+- PORT_ALL(OUT), /* PORT0_OUT -> PORT309_OUT */
+- PINMUX_OUTPUT_END,
+-
+- PINMUX_FUNCTION_BEGIN,
+- PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT309_FN_IN */
+- PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT309_FN_OUT */
+- PORT_ALL(FN0), /* PORT0_FN0 -> PORT309_FN0 */
+- PORT_ALL(FN1), /* PORT0_FN1 -> PORT309_FN1 */
+- PORT_ALL(FN2), /* PORT0_FN2 -> PORT309_FN2 */
+- PORT_ALL(FN3), /* PORT0_FN3 -> PORT309_FN3 */
+- PORT_ALL(FN4), /* PORT0_FN4 -> PORT309_FN4 */
+- PORT_ALL(FN5), /* PORT0_FN5 -> PORT309_FN5 */
+- PORT_ALL(FN6), /* PORT0_FN6 -> PORT309_FN6 */
+- PORT_ALL(FN7), /* PORT0_FN7 -> PORT309_FN7 */
+-
+- MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1,
+- MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1,
+- MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1,
+- MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1,
+- MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1,
+- MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1,
+- MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1,
+- MSEL2CR_MSEL11_0, MSEL2CR_MSEL11_1,
+- MSEL2CR_MSEL10_0, MSEL2CR_MSEL10_1,
+- MSEL2CR_MSEL9_0, MSEL2CR_MSEL9_1,
+- MSEL2CR_MSEL8_0, MSEL2CR_MSEL8_1,
+- MSEL2CR_MSEL7_0, MSEL2CR_MSEL7_1,
+- MSEL2CR_MSEL6_0, MSEL2CR_MSEL6_1,
+- MSEL2CR_MSEL4_0, MSEL2CR_MSEL4_1,
+- MSEL2CR_MSEL5_0, MSEL2CR_MSEL5_1,
+- MSEL2CR_MSEL3_0, MSEL2CR_MSEL3_1,
+- MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1,
+- MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1,
+- MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1,
+- MSEL3CR_MSEL28_0, MSEL3CR_MSEL28_1,
+- MSEL3CR_MSEL15_0, MSEL3CR_MSEL15_1,
+- MSEL3CR_MSEL11_0, MSEL3CR_MSEL11_1,
+- MSEL3CR_MSEL9_0, MSEL3CR_MSEL9_1,
+- MSEL3CR_MSEL6_0, MSEL3CR_MSEL6_1,
+- MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1,
+- MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1,
+- MSEL4CR_MSEL27_0, MSEL4CR_MSEL27_1,
+- MSEL4CR_MSEL26_0, MSEL4CR_MSEL26_1,
+- MSEL4CR_MSEL22_0, MSEL4CR_MSEL22_1,
+- MSEL4CR_MSEL21_0, MSEL4CR_MSEL21_1,
+- MSEL4CR_MSEL20_0, MSEL4CR_MSEL20_1,
+- MSEL4CR_MSEL19_0, MSEL4CR_MSEL19_1,
+- MSEL4CR_MSEL15_0, MSEL4CR_MSEL15_1,
+- MSEL4CR_MSEL13_0, MSEL4CR_MSEL13_1,
+- MSEL4CR_MSEL12_0, MSEL4CR_MSEL12_1,
+- MSEL4CR_MSEL11_0, MSEL4CR_MSEL11_1,
+- MSEL4CR_MSEL10_0, MSEL4CR_MSEL10_1,
+- MSEL4CR_MSEL9_0, MSEL4CR_MSEL9_1,
+- MSEL4CR_MSEL8_0, MSEL4CR_MSEL8_1,
+- MSEL4CR_MSEL7_0, MSEL4CR_MSEL7_1,
+- MSEL4CR_MSEL4_0, MSEL4CR_MSEL4_1,
+- MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1,
+- PINMUX_FUNCTION_END,
+-
+- PINMUX_MARK_BEGIN,
+- /* Hardware manual Table 25-1 (Function 0-7) */
+- VBUS_0_MARK,
+- GPI0_MARK,
+- GPI1_MARK,
+- GPI2_MARK,
+- GPI3_MARK,
+- GPI4_MARK,
+- GPI5_MARK,
+- GPI6_MARK,
+- GPI7_MARK,
+- SCIFA7_RXD_MARK,
+- SCIFA7_CTS__MARK,
+- GPO7_MARK, MFG0_OUT2_MARK,
+- GPO6_MARK, MFG1_OUT2_MARK,
+- GPO5_MARK, SCIFA0_SCK_MARK, FSICOSLDT3_MARK, PORT16_VIO_CKOR_MARK,
+- SCIFA0_TXD_MARK,
+- SCIFA7_TXD_MARK,
+- SCIFA7_RTS__MARK, PORT19_VIO_CKO2_MARK,
+- GPO0_MARK,
+- GPO1_MARK,
+- GPO2_MARK, STATUS0_MARK,
+- GPO3_MARK, STATUS1_MARK,
+- GPO4_MARK, STATUS2_MARK,
+- VINT_MARK,
+- TCKON_MARK,
+- XDVFS1_MARK, PORT27_I2C_SCL2_MARK, PORT27_I2C_SCL3_MARK, \
+- MFG0_OUT1_MARK, PORT27_IROUT_MARK,
+- XDVFS2_MARK, PORT28_I2C_SDA2_MARK, PORT28_I2C_SDA3_MARK, \
+- PORT28_TPU1TO1_MARK,
+- SIM_RST_MARK, PORT29_TPU1TO1_MARK,
+- SIM_CLK_MARK, PORT30_VIO_CKOR_MARK,
+- SIM_D_MARK, PORT31_IROUT_MARK,
+- SCIFA4_TXD_MARK,
+- SCIFA4_RXD_MARK, XWUP_MARK,
+- SCIFA4_RTS__MARK,
+- SCIFA4_CTS__MARK,
+- FSIBOBT_MARK, FSIBIBT_MARK,
+- FSIBOLR_MARK, FSIBILR_MARK,
+- FSIBOSLD_MARK,
+- FSIBISLD_MARK,
+- VACK_MARK,
+- XTAL1L_MARK,
+- SCIFA0_RTS__MARK, FSICOSLDT2_MARK,
+- SCIFA0_RXD_MARK,
+- SCIFA0_CTS__MARK, FSICOSLDT1_MARK,
+- FSICOBT_MARK, FSICIBT_MARK, FSIDOBT_MARK, FSIDIBT_MARK,
+- FSICOLR_MARK, FSICILR_MARK, FSIDOLR_MARK, FSIDILR_MARK,
+- FSICOSLD_MARK, PORT47_FSICSPDIF_MARK,
+- FSICISLD_MARK, FSIDISLD_MARK,
+- FSIACK_MARK, PORT49_IRDA_OUT_MARK, PORT49_IROUT_MARK, FSIAOMC_MARK,
+- FSIAOLR_MARK, BBIF2_TSYNC2_MARK, TPU2TO2_MARK, FSIAILR_MARK,
+-
+- FSIAOBT_MARK, BBIF2_TSCK2_MARK, TPU2TO3_MARK, FSIAIBT_MARK,
+- FSIAOSLD_MARK, BBIF2_TXD2_MARK,
+- FSIASPDIF_MARK, PORT53_IRDA_IN_MARK, TPU3TO3_MARK, FSIBSPDIF_MARK, \
+- PORT53_FSICSPDIF_MARK,
+- FSIBCK_MARK, PORT54_IRDA_FIRSEL_MARK, TPU3TO2_MARK, FSIBOMC_MARK, \
+- FSICCK_MARK, FSICOMC_MARK,
+- FSIAISLD_MARK, TPU0TO0_MARK,
+- A0_MARK, BS__MARK,
+- A12_MARK, PORT58_KEYOUT7_MARK, TPU4TO2_MARK,
+- A13_MARK, PORT59_KEYOUT6_MARK, TPU0TO1_MARK,
+- A14_MARK, KEYOUT5_MARK,
+- A15_MARK, KEYOUT4_MARK,
+- A16_MARK, KEYOUT3_MARK, MSIOF0_SS1_MARK,
+- A17_MARK, KEYOUT2_MARK, MSIOF0_TSYNC_MARK,
+- A18_MARK, KEYOUT1_MARK, MSIOF0_TSCK_MARK,
+- A19_MARK, KEYOUT0_MARK, MSIOF0_TXD_MARK,
+- A20_MARK, KEYIN0_MARK, MSIOF0_RSCK_MARK,
+- A21_MARK, KEYIN1_MARK, MSIOF0_RSYNC_MARK,
+- A22_MARK, KEYIN2_MARK, MSIOF0_MCK0_MARK,
+- A23_MARK, KEYIN3_MARK, MSIOF0_MCK1_MARK,
+- A24_MARK, KEYIN4_MARK, MSIOF0_RXD_MARK,
+- A25_MARK, KEYIN5_MARK, MSIOF0_SS2_MARK,
+- A26_MARK, KEYIN6_MARK,
+- KEYIN7_MARK,
+- D0_NAF0_MARK,
+- D1_NAF1_MARK,
+- D2_NAF2_MARK,
+- D3_NAF3_MARK,
+- D4_NAF4_MARK,
+- D5_NAF5_MARK,
+- D6_NAF6_MARK,
+- D7_NAF7_MARK,
+- D8_NAF8_MARK,
+- D9_NAF9_MARK,
+- D10_NAF10_MARK,
+- D11_NAF11_MARK,
+- D12_NAF12_MARK,
+- D13_NAF13_MARK,
+- D14_NAF14_MARK,
+- D15_NAF15_MARK,
+- CS4__MARK,
+- CS5A__MARK, PORT91_RDWR_MARK,
+- CS5B__MARK, FCE1__MARK,
+- CS6B__MARK, DACK0_MARK,
+- FCE0__MARK, CS6A__MARK,
+- WAIT__MARK, DREQ0_MARK,
+- RD__FSC_MARK,
+- WE0__FWE_MARK, RDWR_FWE_MARK,
+- WE1__MARK,
+- FRB_MARK,
+- CKO_MARK,
+- NBRSTOUT__MARK,
+- NBRST__MARK,
+- BBIF2_TXD_MARK,
+- BBIF2_RXD_MARK,
+- BBIF2_SYNC_MARK,
+- BBIF2_SCK_MARK,
+- SCIFA3_CTS__MARK, MFG3_IN2_MARK,
+- SCIFA3_RXD_MARK, MFG3_IN1_MARK,
+- BBIF1_SS2_MARK, SCIFA3_RTS__MARK, MFG3_OUT1_MARK,
+- SCIFA3_TXD_MARK,
+- HSI_RX_DATA_MARK, BBIF1_RXD_MARK,
+- HSI_TX_WAKE_MARK, BBIF1_TSCK_MARK,
+- HSI_TX_DATA_MARK, BBIF1_TSYNC_MARK,
+- HSI_TX_READY_MARK, BBIF1_TXD_MARK,
+- HSI_RX_READY_MARK, BBIF1_RSCK_MARK, PORT115_I2C_SCL2_MARK, \
+- PORT115_I2C_SCL3_MARK,
+- HSI_RX_WAKE_MARK, BBIF1_RSYNC_MARK, PORT116_I2C_SDA2_MARK, \
+- PORT116_I2C_SDA3_MARK,
+- HSI_RX_FLAG_MARK, BBIF1_SS1_MARK, BBIF1_FLOW_MARK,
+- HSI_TX_FLAG_MARK,
+- VIO_VD_MARK, PORT128_LCD2VSYN_MARK, VIO2_VD_MARK, LCD2D0_MARK,
+-
+- VIO_HD_MARK, PORT129_LCD2HSYN_MARK, PORT129_LCD2CS__MARK, \
+- VIO2_HD_MARK, LCD2D1_MARK,
+- VIO_D0_MARK, PORT130_MSIOF2_RXD_MARK, LCD2D10_MARK,
+- VIO_D1_MARK, PORT131_KEYOUT6_MARK, PORT131_MSIOF2_SS1_MARK, \
+- PORT131_KEYOUT11_MARK, LCD2D11_MARK,
+- VIO_D2_MARK, PORT132_KEYOUT7_MARK, PORT132_MSIOF2_SS2_MARK, \
+- PORT132_KEYOUT10_MARK, LCD2D12_MARK,
+- VIO_D3_MARK, MSIOF2_TSYNC_MARK, LCD2D13_MARK,
+- VIO_D4_MARK, MSIOF2_TXD_MARK, LCD2D14_MARK,
+- VIO_D5_MARK, MSIOF2_TSCK_MARK, LCD2D15_MARK,
+- VIO_D6_MARK, PORT136_KEYOUT8_MARK, LCD2D16_MARK,
+- VIO_D7_MARK, PORT137_KEYOUT9_MARK, LCD2D17_MARK,
+- VIO_D8_MARK, PORT138_KEYOUT8_MARK, VIO2_D0_MARK, LCD2D6_MARK,
+- VIO_D9_MARK, PORT139_KEYOUT9_MARK, VIO2_D1_MARK, LCD2D7_MARK,
+- VIO_D10_MARK, TPU0TO2_MARK, VIO2_D2_MARK, LCD2D8_MARK,
+- VIO_D11_MARK, TPU0TO3_MARK, VIO2_D3_MARK, LCD2D9_MARK,
+- VIO_D12_MARK, PORT142_KEYOUT10_MARK, VIO2_D4_MARK, LCD2D2_MARK,
+- VIO_D13_MARK, PORT143_KEYOUT11_MARK, PORT143_KEYOUT6_MARK, \
+- VIO2_D5_MARK, LCD2D3_MARK,
+- VIO_D14_MARK, PORT144_KEYOUT7_MARK, VIO2_D6_MARK, LCD2D4_MARK,
+- VIO_D15_MARK, TPU1TO3_MARK, PORT145_LCD2DISP_MARK, \
+- PORT145_LCD2RS_MARK, VIO2_D7_MARK, LCD2D5_MARK,
+- VIO_CLK_MARK, LCD2DCK_MARK, PORT146_LCD2WR__MARK, VIO2_CLK_MARK, \
+- LCD2D18_MARK,
+- VIO_FIELD_MARK, LCD2RD__MARK, VIO2_FIELD_MARK, LCD2D19_MARK,
+- VIO_CKO_MARK,
+- A27_MARK, PORT149_RDWR_MARK, MFG0_IN1_MARK, PORT149_KEYOUT9_MARK,
+- MFG0_IN2_MARK,
+- TS_SPSYNC3_MARK, MSIOF2_RSCK_MARK,
+- TS_SDAT3_MARK, MSIOF2_RSYNC_MARK,
+- TPU1TO2_MARK, TS_SDEN3_MARK, PORT153_MSIOF2_SS1_MARK,
+- SCIFA2_TXD1_MARK, MSIOF2_MCK0_MARK,
+- SCIFA2_RXD1_MARK, MSIOF2_MCK1_MARK,
+- SCIFA2_RTS1__MARK, PORT156_MSIOF2_SS2_MARK,
+- SCIFA2_CTS1__MARK, PORT157_MSIOF2_RXD_MARK,
+- DINT__MARK, SCIFA2_SCK1_MARK, TS_SCK3_MARK,
+- PORT159_SCIFB_SCK_MARK, PORT159_SCIFA5_SCK_MARK, NMI_MARK,
+- PORT160_SCIFB_TXD_MARK, PORT160_SCIFA5_TXD_MARK,
+- PORT161_SCIFB_CTS__MARK, PORT161_SCIFA5_CTS__MARK,
+- PORT162_SCIFB_RXD_MARK, PORT162_SCIFA5_RXD_MARK,
+- PORT163_SCIFB_RTS__MARK, PORT163_SCIFA5_RTS__MARK, TPU3TO0_MARK,
+- LCDD0_MARK,
+- LCDD1_MARK, PORT193_SCIFA5_CTS__MARK, BBIF2_TSYNC1_MARK,
+- LCDD2_MARK, PORT194_SCIFA5_RTS__MARK, BBIF2_TSCK1_MARK,
+- LCDD3_MARK, PORT195_SCIFA5_RXD_MARK, BBIF2_TXD1_MARK,
+- LCDD4_MARK, PORT196_SCIFA5_TXD_MARK,
+- LCDD5_MARK, PORT197_SCIFA5_SCK_MARK, MFG2_OUT2_MARK, TPU2TO1_MARK,
+- LCDD6_MARK,
+- LCDD7_MARK, TPU4TO1_MARK, MFG4_OUT2_MARK,
+- LCDD8_MARK, D16_MARK,
+- LCDD9_MARK, D17_MARK,
+- LCDD10_MARK, D18_MARK,
+- LCDD11_MARK, D19_MARK,
+- LCDD12_MARK, D20_MARK,
+- LCDD13_MARK, D21_MARK,
+- LCDD14_MARK, D22_MARK,
+- LCDD15_MARK, PORT207_MSIOF0L_SS1_MARK, D23_MARK,
+- LCDD16_MARK, PORT208_MSIOF0L_SS2_MARK, D24_MARK,
+- LCDD17_MARK, D25_MARK,
+- LCDD18_MARK, DREQ2_MARK, PORT210_MSIOF0L_SS1_MARK, D26_MARK,
+- LCDD19_MARK, PORT211_MSIOF0L_SS2_MARK, D27_MARK,
+- LCDD20_MARK, TS_SPSYNC1_MARK, MSIOF0L_MCK0_MARK, D28_MARK,
+- LCDD21_MARK, TS_SDAT1_MARK, MSIOF0L_MCK1_MARK, D29_MARK,
+- LCDD22_MARK, TS_SDEN1_MARK, MSIOF0L_RSCK_MARK, D30_MARK,
+- LCDD23_MARK, TS_SCK1_MARK, MSIOF0L_RSYNC_MARK, D31_MARK,
+- LCDDCK_MARK, LCDWR__MARK,
+- LCDRD__MARK, DACK2_MARK, PORT217_LCD2RS_MARK, MSIOF0L_TSYNC_MARK, \
+- VIO2_FIELD3_MARK, PORT217_LCD2DISP_MARK,
+- LCDHSYN_MARK, LCDCS__MARK, LCDCS2__MARK, DACK3_MARK, \
+- PORT218_VIO_CKOR_MARK,
+- LCDDISP_MARK, LCDRS_MARK, PORT219_LCD2WR__MARK, DREQ3_MARK, \
+- MSIOF0L_TSCK_MARK, VIO2_CLK3_MARK, LCD2DCK_2_MARK,
+- LCDVSYN_MARK, LCDVSYN2_MARK,
+- LCDLCLK_MARK, DREQ1_MARK, PORT221_LCD2CS__MARK, PWEN_MARK, \
+- MSIOF0L_RXD_MARK, VIO2_HD3_MARK, PORT221_LCD2HSYN_MARK,
+- LCDDON_MARK, LCDDON2_MARK, DACK1_MARK, OVCN_MARK, MSIOF0L_TXD_MARK, \
+- VIO2_VD3_MARK, PORT222_LCD2VSYN_MARK,
+-
+- SCIFA1_TXD_MARK, OVCN2_MARK,
+- EXTLP_MARK, SCIFA1_SCK_MARK, PORT226_VIO_CKO2_MARK,
+- SCIFA1_RTS__MARK, IDIN_MARK,
+- SCIFA1_RXD_MARK,
+- SCIFA1_CTS__MARK, MFG1_IN1_MARK,
+- MSIOF1_TXD_MARK, SCIFA2_TXD2_MARK,
+- MSIOF1_TSYNC_MARK, SCIFA2_CTS2__MARK,
+- MSIOF1_TSCK_MARK, SCIFA2_SCK2_MARK,
+- MSIOF1_RXD_MARK, SCIFA2_RXD2_MARK,
+- MSIOF1_RSCK_MARK, SCIFA2_RTS2__MARK, VIO2_CLK2_MARK, LCD2D20_MARK,
+- MSIOF1_RSYNC_MARK, MFG1_IN2_MARK, VIO2_VD2_MARK, LCD2D21_MARK,
+- MSIOF1_MCK0_MARK, PORT236_I2C_SDA2_MARK,
+- MSIOF1_MCK1_MARK, PORT237_I2C_SCL2_MARK,
+- MSIOF1_SS1_MARK, VIO2_FIELD2_MARK, LCD2D22_MARK,
+- MSIOF1_SS2_MARK, VIO2_HD2_MARK, LCD2D23_MARK,
+- SCIFA6_TXD_MARK,
+- PORT241_IRDA_OUT_MARK, PORT241_IROUT_MARK, MFG4_OUT1_MARK, TPU4TO0_MARK,
+- PORT242_IRDA_IN_MARK, MFG4_IN2_MARK,
+- PORT243_IRDA_FIRSEL_MARK, PORT243_VIO_CKO2_MARK,
+- PORT244_SCIFA5_CTS__MARK, MFG2_IN1_MARK, PORT244_SCIFB_CTS__MARK, \
+- MSIOF2R_RXD_MARK,
+- PORT245_SCIFA5_RTS__MARK, MFG2_IN2_MARK, PORT245_SCIFB_RTS__MARK, \
+- MSIOF2R_TXD_MARK,
+- PORT246_SCIFA5_RXD_MARK, MFG1_OUT1_MARK, PORT246_SCIFB_RXD_MARK, \
+- TPU1TO0_MARK,
+- PORT247_SCIFA5_TXD_MARK, MFG3_OUT2_MARK, PORT247_SCIFB_TXD_MARK, \
+- TPU3TO1_MARK,
+- PORT248_SCIFA5_SCK_MARK, MFG2_OUT1_MARK, PORT248_SCIFB_SCK_MARK, \
+- TPU2TO0_MARK, PORT248_I2C_SCL3_MARK, MSIOF2R_TSCK_MARK,
+- PORT249_IROUT_MARK, MFG4_IN1_MARK, PORT249_I2C_SDA3_MARK, \
+- MSIOF2R_TSYNC_MARK,
+- SDHICLK0_MARK,
+- SDHICD0_MARK,
+- SDHID0_0_MARK,
+- SDHID0_1_MARK,
+- SDHID0_2_MARK,
+- SDHID0_3_MARK,
+- SDHICMD0_MARK,
+- SDHIWP0_MARK,
+- SDHICLK1_MARK,
+- SDHID1_0_MARK, TS_SPSYNC2_MARK,
+- SDHID1_1_MARK, TS_SDAT2_MARK,
+- SDHID1_2_MARK, TS_SDEN2_MARK,
+- SDHID1_3_MARK, TS_SCK2_MARK,
+- SDHICMD1_MARK,
+- SDHICLK2_MARK,
+- SDHID2_0_MARK, TS_SPSYNC4_MARK,
+- SDHID2_1_MARK, TS_SDAT4_MARK,
+- SDHID2_2_MARK, TS_SDEN4_MARK,
+- SDHID2_3_MARK, TS_SCK4_MARK,
+- SDHICMD2_MARK,
+- MMCCLK0_MARK,
+- MMCD0_0_MARK,
+- MMCD0_1_MARK,
+- MMCD0_2_MARK,
+- MMCD0_3_MARK,
+- MMCD0_4_MARK, TS_SPSYNC5_MARK,
+- MMCD0_5_MARK, TS_SDAT5_MARK,
+- MMCD0_6_MARK, TS_SDEN5_MARK,
+- MMCD0_7_MARK, TS_SCK5_MARK,
+- MMCCMD0_MARK,
+- RESETOUTS__MARK, EXTAL2OUT_MARK,
+- MCP_WAIT__MCP_FRB_MARK,
+- MCP_CKO_MARK, MMCCLK1_MARK,
+- MCP_D15_MCP_NAF15_MARK,
+- MCP_D14_MCP_NAF14_MARK,
+- MCP_D13_MCP_NAF13_MARK,
+- MCP_D12_MCP_NAF12_MARK,
+- MCP_D11_MCP_NAF11_MARK,
+- MCP_D10_MCP_NAF10_MARK,
+- MCP_D9_MCP_NAF9_MARK,
+- MCP_D8_MCP_NAF8_MARK, MMCCMD1_MARK,
+- MCP_D7_MCP_NAF7_MARK, MMCD1_7_MARK,
+-
+- MCP_D6_MCP_NAF6_MARK, MMCD1_6_MARK,
+- MCP_D5_MCP_NAF5_MARK, MMCD1_5_MARK,
+- MCP_D4_MCP_NAF4_MARK, MMCD1_4_MARK,
+- MCP_D3_MCP_NAF3_MARK, MMCD1_3_MARK,
+- MCP_D2_MCP_NAF2_MARK, MMCD1_2_MARK,
+- MCP_D1_MCP_NAF1_MARK, MMCD1_1_MARK,
+- MCP_D0_MCP_NAF0_MARK, MMCD1_0_MARK,
+- MCP_NBRSTOUT__MARK,
+- MCP_WE0__MCP_FWE_MARK, MCP_RDWR_MCP_FWE_MARK,
+-
+- /* MSEL2 special cases */
+- TSIF2_TS_XX1_MARK,
+- TSIF2_TS_XX2_MARK,
+- TSIF2_TS_XX3_MARK,
+- TSIF2_TS_XX4_MARK,
+- TSIF2_TS_XX5_MARK,
+- TSIF1_TS_XX1_MARK,
+- TSIF1_TS_XX2_MARK,
+- TSIF1_TS_XX3_MARK,
+- TSIF1_TS_XX4_MARK,
+- TSIF1_TS_XX5_MARK,
+- TSIF0_TS_XX1_MARK,
+- TSIF0_TS_XX2_MARK,
+- TSIF0_TS_XX3_MARK,
+- TSIF0_TS_XX4_MARK,
+- TSIF0_TS_XX5_MARK,
+- MST1_TS_XX1_MARK,
+- MST1_TS_XX2_MARK,
+- MST1_TS_XX3_MARK,
+- MST1_TS_XX4_MARK,
+- MST1_TS_XX5_MARK,
+- MST0_TS_XX1_MARK,
+- MST0_TS_XX2_MARK,
+- MST0_TS_XX3_MARK,
+- MST0_TS_XX4_MARK,
+- MST0_TS_XX5_MARK,
+-
+- /* MSEL3 special cases */
+- SDHI0_VCCQ_MC0_ON_MARK,
+- SDHI0_VCCQ_MC0_OFF_MARK,
+- DEBUG_MON_VIO_MARK,
+- DEBUG_MON_LCDD_MARK,
+- LCDC_LCDC0_MARK,
+- LCDC_LCDC1_MARK,
+-
+- /* MSEL4 special cases */
+- IRQ9_MEM_INT_MARK,
+- IRQ9_MCP_INT_MARK,
+- A11_MARK,
+- KEYOUT8_MARK,
+- TPU4TO3_MARK,
+- RESETA_N_PU_ON_MARK,
+- RESETA_N_PU_OFF_MARK,
+- EDBGREQ_PD_MARK,
+- EDBGREQ_PU_MARK,
+-
+- /* Functions with pull-ups */
+- KEYIN0_PU_MARK,
+- KEYIN1_PU_MARK,
+- KEYIN2_PU_MARK,
+- KEYIN3_PU_MARK,
+- KEYIN4_PU_MARK,
+- KEYIN5_PU_MARK,
+- KEYIN6_PU_MARK,
+- KEYIN7_PU_MARK,
+- SDHICD0_PU_MARK,
+- SDHID0_0_PU_MARK,
+- SDHID0_1_PU_MARK,
+- SDHID0_2_PU_MARK,
+- SDHID0_3_PU_MARK,
+- SDHICMD0_PU_MARK,
+- SDHIWP0_PU_MARK,
+- SDHID1_0_PU_MARK,
+- SDHID1_1_PU_MARK,
+- SDHID1_2_PU_MARK,
+- SDHID1_3_PU_MARK,
+- SDHICMD1_PU_MARK,
+- SDHID2_0_PU_MARK,
+- SDHID2_1_PU_MARK,
+- SDHID2_2_PU_MARK,
+- SDHID2_3_PU_MARK,
+- SDHICMD2_PU_MARK,
+- MMCCMD0_PU_MARK,
+- MMCCMD1_PU_MARK,
+- MMCD0_0_PU_MARK,
+- MMCD0_1_PU_MARK,
+- MMCD0_2_PU_MARK,
+- MMCD0_3_PU_MARK,
+- MMCD0_4_PU_MARK,
+- MMCD0_5_PU_MARK,
+- MMCD0_6_PU_MARK,
+- MMCD0_7_PU_MARK,
+- FSIBISLD_PU_MARK,
+- FSIACK_PU_MARK,
+- FSIAILR_PU_MARK,
+- FSIAIBT_PU_MARK,
+- FSIAISLD_PU_MARK,
+-
+- PINMUX_MARK_END,
+-};
+-
+-static unsigned short pinmux_data[] = {
+- /* specify valid pin states for each pin in GPIO mode */
+-
+- /* Table 25-1 (I/O and Pull U/D) */
+- PORT_DATA_I_PD(0),
+- PORT_DATA_I_PU(1),
+- PORT_DATA_I_PU(2),
+- PORT_DATA_I_PU(3),
+- PORT_DATA_I_PU(4),
+- PORT_DATA_I_PU(5),
+- PORT_DATA_I_PU(6),
+- PORT_DATA_I_PU(7),
+- PORT_DATA_I_PU(8),
+- PORT_DATA_I_PD(9),
+- PORT_DATA_I_PD(10),
+- PORT_DATA_I_PU_PD(11),
+- PORT_DATA_IO_PU_PD(12),
+- PORT_DATA_IO_PU_PD(13),
+- PORT_DATA_IO_PU_PD(14),
+- PORT_DATA_IO_PU_PD(15),
+- PORT_DATA_IO_PD(16),
+- PORT_DATA_IO_PD(17),
+- PORT_DATA_IO_PU(18),
+- PORT_DATA_IO_PU(19),
+- PORT_DATA_O(20),
+- PORT_DATA_O(21),
+- PORT_DATA_O(22),
+- PORT_DATA_O(23),
+- PORT_DATA_O(24),
+- PORT_DATA_I_PD(25),
+- PORT_DATA_I_PD(26),
+- PORT_DATA_IO_PU(27),
+- PORT_DATA_IO_PU(28),
+- PORT_DATA_IO_PD(29),
+- PORT_DATA_IO_PD(30),
+- PORT_DATA_IO_PU(31),
+- PORT_DATA_IO_PD(32),
+- PORT_DATA_I_PU_PD(33),
+- PORT_DATA_IO_PD(34),
+- PORT_DATA_I_PU_PD(35),
+- PORT_DATA_IO_PD(36),
+- PORT_DATA_IO(37),
+- PORT_DATA_O(38),
+- PORT_DATA_I_PU(39),
+- PORT_DATA_I_PU_PD(40),
+- PORT_DATA_O(41),
+- PORT_DATA_IO_PD(42),
+- PORT_DATA_IO_PU_PD(43),
+- PORT_DATA_IO_PU_PD(44),
+- PORT_DATA_IO_PD(45),
+- PORT_DATA_IO_PD(46),
+- PORT_DATA_IO_PD(47),
+- PORT_DATA_I_PD(48),
+- PORT_DATA_IO_PU_PD(49),
+- PORT_DATA_IO_PD(50),
+-
+- PORT_DATA_IO_PD(51),
+- PORT_DATA_O(52),
+- PORT_DATA_IO_PU_PD(53),
+- PORT_DATA_IO_PU_PD(54),
+- PORT_DATA_IO_PD(55),
+- PORT_DATA_I_PU_PD(56),
+- PORT_DATA_IO(57),
+- PORT_DATA_IO(58),
+- PORT_DATA_IO(59),
+- PORT_DATA_IO(60),
+- PORT_DATA_IO(61),
+- PORT_DATA_IO_PD(62),
+- PORT_DATA_IO_PD(63),
+- PORT_DATA_IO_PU_PD(64),
+- PORT_DATA_IO_PD(65),
+- PORT_DATA_IO_PU_PD(66),
+- PORT_DATA_IO_PU_PD(67),
+- PORT_DATA_IO_PU_PD(68),
+- PORT_DATA_IO_PU_PD(69),
+- PORT_DATA_IO_PU_PD(70),
+- PORT_DATA_IO_PU_PD(71),
+- PORT_DATA_IO_PU_PD(72),
+- PORT_DATA_I_PU_PD(73),
+- PORT_DATA_IO_PU(74),
+- PORT_DATA_IO_PU(75),
+- PORT_DATA_IO_PU(76),
+- PORT_DATA_IO_PU(77),
+- PORT_DATA_IO_PU(78),
+- PORT_DATA_IO_PU(79),
+- PORT_DATA_IO_PU(80),
+- PORT_DATA_IO_PU(81),
+- PORT_DATA_IO_PU(82),
+- PORT_DATA_IO_PU(83),
+- PORT_DATA_IO_PU(84),
+- PORT_DATA_IO_PU(85),
+- PORT_DATA_IO_PU(86),
+- PORT_DATA_IO_PU(87),
+- PORT_DATA_IO_PU(88),
+- PORT_DATA_IO_PU(89),
+- PORT_DATA_O(90),
+- PORT_DATA_IO_PU(91),
+- PORT_DATA_O(92),
+- PORT_DATA_IO_PU(93),
+- PORT_DATA_O(94),
+- PORT_DATA_I_PU_PD(95),
+- PORT_DATA_IO(96),
+- PORT_DATA_IO(97),
+- PORT_DATA_IO(98),
+- PORT_DATA_I_PU(99),
+- PORT_DATA_O(100),
+- PORT_DATA_O(101),
+- PORT_DATA_I_PU(102),
+- PORT_DATA_IO_PD(103),
+- PORT_DATA_I_PU_PD(104),
+- PORT_DATA_I_PD(105),
+- PORT_DATA_I_PD(106),
+- PORT_DATA_I_PU_PD(107),
+- PORT_DATA_I_PU_PD(108),
+- PORT_DATA_IO_PD(109),
+- PORT_DATA_IO_PD(110),
+- PORT_DATA_IO_PU_PD(111),
+- PORT_DATA_IO_PU_PD(112),
+- PORT_DATA_IO_PU_PD(113),
+- PORT_DATA_IO_PD(114),
+- PORT_DATA_IO_PU(115),
+- PORT_DATA_IO_PU(116),
+- PORT_DATA_IO_PU_PD(117),
+- PORT_DATA_IO_PU_PD(118),
+- PORT_DATA_IO_PD(128),
+-
+- PORT_DATA_IO_PD(129),
+- PORT_DATA_IO_PU_PD(130),
+- PORT_DATA_IO_PD(131),
+- PORT_DATA_IO_PD(132),
+- PORT_DATA_IO_PD(133),
+- PORT_DATA_IO_PU_PD(134),
+- PORT_DATA_IO_PU_PD(135),
+- PORT_DATA_IO_PU_PD(136),
+- PORT_DATA_IO_PU_PD(137),
+- PORT_DATA_IO_PD(138),
+- PORT_DATA_IO_PD(139),
+- PORT_DATA_IO_PD(140),
+- PORT_DATA_IO_PD(141),
+- PORT_DATA_IO_PD(142),
+- PORT_DATA_IO_PD(143),
+- PORT_DATA_IO_PU_PD(144),
+- PORT_DATA_IO_PD(145),
+- PORT_DATA_IO_PU_PD(146),
+- PORT_DATA_IO_PU_PD(147),
+- PORT_DATA_IO_PU_PD(148),
+- PORT_DATA_IO_PU_PD(149),
+- PORT_DATA_I_PU_PD(150),
+- PORT_DATA_IO_PU_PD(151),
+- PORT_DATA_IO_PU_PD(152),
+- PORT_DATA_IO_PD(153),
+- PORT_DATA_IO_PD(154),
+- PORT_DATA_I_PU_PD(155),
+- PORT_DATA_IO_PU_PD(156),
+- PORT_DATA_I_PD(157),
+- PORT_DATA_IO_PD(158),
+- PORT_DATA_IO_PU_PD(159),
+- PORT_DATA_IO_PU_PD(160),
+- PORT_DATA_I_PU_PD(161),
+- PORT_DATA_I_PU_PD(162),
+- PORT_DATA_IO_PU_PD(163),
+- PORT_DATA_I_PU_PD(164),
+- PORT_DATA_IO_PD(192),
+- PORT_DATA_IO_PU_PD(193),
+- PORT_DATA_IO_PD(194),
+- PORT_DATA_IO_PU_PD(195),
+- PORT_DATA_IO_PD(196),
+- PORT_DATA_IO_PD(197),
+- PORT_DATA_IO_PD(198),
+- PORT_DATA_IO_PD(199),
+- PORT_DATA_IO_PU_PD(200),
+- PORT_DATA_IO_PU_PD(201),
+- PORT_DATA_IO_PU_PD(202),
+- PORT_DATA_IO_PU_PD(203),
+- PORT_DATA_IO_PU_PD(204),
+- PORT_DATA_IO_PU_PD(205),
+- PORT_DATA_IO_PU_PD(206),
+- PORT_DATA_IO_PD(207),
+- PORT_DATA_IO_PD(208),
+- PORT_DATA_IO_PD(209),
+- PORT_DATA_IO_PD(210),
+- PORT_DATA_IO_PD(211),
+- PORT_DATA_IO_PD(212),
+- PORT_DATA_IO_PD(213),
+- PORT_DATA_IO_PU_PD(214),
+- PORT_DATA_IO_PU_PD(215),
+- PORT_DATA_IO_PD(216),
+- PORT_DATA_IO_PD(217),
+- PORT_DATA_O(218),
+- PORT_DATA_IO_PD(219),
+- PORT_DATA_IO_PD(220),
+- PORT_DATA_IO_PU_PD(221),
+- PORT_DATA_IO_PU_PD(222),
+- PORT_DATA_I_PU_PD(223),
+- PORT_DATA_I_PU_PD(224),
+-
+- PORT_DATA_IO_PU_PD(225),
+- PORT_DATA_O(226),
+- PORT_DATA_IO_PU_PD(227),
+- PORT_DATA_I_PU_PD(228),
+- PORT_DATA_I_PD(229),
+- PORT_DATA_IO(230),
+- PORT_DATA_IO_PU_PD(231),
+- PORT_DATA_IO_PU_PD(232),
+- PORT_DATA_I_PU_PD(233),
+- PORT_DATA_IO_PU_PD(234),
+- PORT_DATA_IO_PU_PD(235),
+- PORT_DATA_IO_PU_PD(236),
+- PORT_DATA_IO_PD(237),
+- PORT_DATA_IO_PU_PD(238),
+- PORT_DATA_IO_PU_PD(239),
+- PORT_DATA_IO_PU_PD(240),
+- PORT_DATA_O(241),
+- PORT_DATA_I_PD(242),
+- PORT_DATA_IO_PU_PD(243),
+- PORT_DATA_IO_PU_PD(244),
+- PORT_DATA_IO_PU_PD(245),
+- PORT_DATA_IO_PU_PD(246),
+- PORT_DATA_IO_PU_PD(247),
+- PORT_DATA_IO_PU_PD(248),
+- PORT_DATA_IO_PU_PD(249),
+- PORT_DATA_IO_PU_PD(250),
+- PORT_DATA_IO_PU_PD(251),
+- PORT_DATA_IO_PU_PD(252),
+- PORT_DATA_IO_PU_PD(253),
+- PORT_DATA_IO_PU_PD(254),
+- PORT_DATA_IO_PU_PD(255),
+- PORT_DATA_IO_PU_PD(256),
+- PORT_DATA_IO_PU_PD(257),
+- PORT_DATA_IO_PU_PD(258),
+- PORT_DATA_IO_PU_PD(259),
+- PORT_DATA_IO_PU_PD(260),
+- PORT_DATA_IO_PU_PD(261),
+- PORT_DATA_IO_PU_PD(262),
+- PORT_DATA_IO_PU_PD(263),
+- PORT_DATA_IO_PU_PD(264),
+- PORT_DATA_IO_PU_PD(265),
+- PORT_DATA_IO_PU_PD(266),
+- PORT_DATA_IO_PU_PD(267),
+- PORT_DATA_IO_PU_PD(268),
+- PORT_DATA_IO_PU_PD(269),
+- PORT_DATA_IO_PU_PD(270),
+- PORT_DATA_IO_PU_PD(271),
+- PORT_DATA_IO_PU_PD(272),
+- PORT_DATA_IO_PU_PD(273),
+- PORT_DATA_IO_PU_PD(274),
+- PORT_DATA_IO_PU_PD(275),
+- PORT_DATA_IO_PU_PD(276),
+- PORT_DATA_IO_PU_PD(277),
+- PORT_DATA_IO_PU_PD(278),
+- PORT_DATA_IO_PU_PD(279),
+- PORT_DATA_IO_PU_PD(280),
+- PORT_DATA_O(281),
+- PORT_DATA_O(282),
+- PORT_DATA_I_PU(288),
+- PORT_DATA_IO_PU_PD(289),
+- PORT_DATA_IO_PU_PD(290),
+- PORT_DATA_IO_PU_PD(291),
+- PORT_DATA_IO_PU_PD(292),
+- PORT_DATA_IO_PU_PD(293),
+- PORT_DATA_IO_PU_PD(294),
+- PORT_DATA_IO_PU_PD(295),
+- PORT_DATA_IO_PU_PD(296),
+- PORT_DATA_IO_PU_PD(297),
+- PORT_DATA_IO_PU_PD(298),
+-
+- PORT_DATA_IO_PU_PD(299),
+- PORT_DATA_IO_PU_PD(300),
+- PORT_DATA_IO_PU_PD(301),
+- PORT_DATA_IO_PU_PD(302),
+- PORT_DATA_IO_PU_PD(303),
+- PORT_DATA_IO_PU_PD(304),
+- PORT_DATA_IO_PU_PD(305),
+- PORT_DATA_O(306),
+- PORT_DATA_O(307),
+- PORT_DATA_I_PU(308),
+- PORT_DATA_O(309),
+-
+- /* Table 25-1 (Function 0-7) */
+- PINMUX_DATA(VBUS_0_MARK, PORT0_FN1),
+- PINMUX_DATA(GPI0_MARK, PORT1_FN1),
+- PINMUX_DATA(GPI1_MARK, PORT2_FN1),
+- PINMUX_DATA(GPI2_MARK, PORT3_FN1),
+- PINMUX_DATA(GPI3_MARK, PORT4_FN1),
+- PINMUX_DATA(GPI4_MARK, PORT5_FN1),
+- PINMUX_DATA(GPI5_MARK, PORT6_FN1),
+- PINMUX_DATA(GPI6_MARK, PORT7_FN1),
+- PINMUX_DATA(GPI7_MARK, PORT8_FN1),
+- PINMUX_DATA(SCIFA7_RXD_MARK, PORT12_FN2),
+- PINMUX_DATA(SCIFA7_CTS__MARK, PORT13_FN2),
+- PINMUX_DATA(GPO7_MARK, PORT14_FN1), \
+- PINMUX_DATA(MFG0_OUT2_MARK, PORT14_FN4),
+- PINMUX_DATA(GPO6_MARK, PORT15_FN1), \
+- PINMUX_DATA(MFG1_OUT2_MARK, PORT15_FN4),
+- PINMUX_DATA(GPO5_MARK, PORT16_FN1), \
+- PINMUX_DATA(SCIFA0_SCK_MARK, PORT16_FN2), \
+- PINMUX_DATA(FSICOSLDT3_MARK, PORT16_FN3), \
+- PINMUX_DATA(PORT16_VIO_CKOR_MARK, PORT16_FN4),
+- PINMUX_DATA(SCIFA0_TXD_MARK, PORT17_FN2),
+- PINMUX_DATA(SCIFA7_TXD_MARK, PORT18_FN2),
+- PINMUX_DATA(SCIFA7_RTS__MARK, PORT19_FN2), \
+- PINMUX_DATA(PORT19_VIO_CKO2_MARK, PORT19_FN3),
+- PINMUX_DATA(GPO0_MARK, PORT20_FN1),
+- PINMUX_DATA(GPO1_MARK, PORT21_FN1),
+- PINMUX_DATA(GPO2_MARK, PORT22_FN1), \
+- PINMUX_DATA(STATUS0_MARK, PORT22_FN2),
+- PINMUX_DATA(GPO3_MARK, PORT23_FN1), \
+- PINMUX_DATA(STATUS1_MARK, PORT23_FN2),
+- PINMUX_DATA(GPO4_MARK, PORT24_FN1), \
+- PINMUX_DATA(STATUS2_MARK, PORT24_FN2),
+- PINMUX_DATA(VINT_MARK, PORT25_FN1),
+- PINMUX_DATA(TCKON_MARK, PORT26_FN1),
+- PINMUX_DATA(XDVFS1_MARK, PORT27_FN1), \
+- PINMUX_DATA(PORT27_I2C_SCL2_MARK, PORT27_FN2, MSEL2CR_MSEL17_0,
+- MSEL2CR_MSEL16_1), \
+- PINMUX_DATA(PORT27_I2C_SCL3_MARK, PORT27_FN3, MSEL2CR_MSEL19_0,
+- MSEL2CR_MSEL18_1), \
+- PINMUX_DATA(MFG0_OUT1_MARK, PORT27_FN4), \
+- PINMUX_DATA(PORT27_IROUT_MARK, PORT27_FN7),
+- PINMUX_DATA(XDVFS2_MARK, PORT28_FN1), \
+- PINMUX_DATA(PORT28_I2C_SDA2_MARK, PORT28_FN2, MSEL2CR_MSEL17_0,
+- MSEL2CR_MSEL16_1), \
+- PINMUX_DATA(PORT28_I2C_SDA3_MARK, PORT28_FN3, MSEL2CR_MSEL19_0,
+- MSEL2CR_MSEL18_1), \
+- PINMUX_DATA(PORT28_TPU1TO1_MARK, PORT28_FN7),
+- PINMUX_DATA(SIM_RST_MARK, PORT29_FN1), \
+- PINMUX_DATA(PORT29_TPU1TO1_MARK, PORT29_FN4),
+- PINMUX_DATA(SIM_CLK_MARK, PORT30_FN1), \
+- PINMUX_DATA(PORT30_VIO_CKOR_MARK, PORT30_FN4),
+- PINMUX_DATA(SIM_D_MARK, PORT31_FN1), \
+- PINMUX_DATA(PORT31_IROUT_MARK, PORT31_FN4),
+- PINMUX_DATA(SCIFA4_TXD_MARK, PORT32_FN2),
+- PINMUX_DATA(SCIFA4_RXD_MARK, PORT33_FN2), \
+- PINMUX_DATA(XWUP_MARK, PORT33_FN3),
+- PINMUX_DATA(SCIFA4_RTS__MARK, PORT34_FN2),
+- PINMUX_DATA(SCIFA4_CTS__MARK, PORT35_FN2),
+- PINMUX_DATA(FSIBOBT_MARK, PORT36_FN1), \
+- PINMUX_DATA(FSIBIBT_MARK, PORT36_FN2),
+- PINMUX_DATA(FSIBOLR_MARK, PORT37_FN1), \
+- PINMUX_DATA(FSIBILR_MARK, PORT37_FN2),
+- PINMUX_DATA(FSIBOSLD_MARK, PORT38_FN1),
+- PINMUX_DATA(FSIBISLD_MARK, PORT39_FN1),
+- PINMUX_DATA(VACK_MARK, PORT40_FN1),
+- PINMUX_DATA(XTAL1L_MARK, PORT41_FN1),
+- PINMUX_DATA(SCIFA0_RTS__MARK, PORT42_FN2), \
+- PINMUX_DATA(FSICOSLDT2_MARK, PORT42_FN3),
+- PINMUX_DATA(SCIFA0_RXD_MARK, PORT43_FN2),
+- PINMUX_DATA(SCIFA0_CTS__MARK, PORT44_FN2), \
+- PINMUX_DATA(FSICOSLDT1_MARK, PORT44_FN3),
+- PINMUX_DATA(FSICOBT_MARK, PORT45_FN1), \
+- PINMUX_DATA(FSICIBT_MARK, PORT45_FN2), \
+- PINMUX_DATA(FSIDOBT_MARK, PORT45_FN3), \
+- PINMUX_DATA(FSIDIBT_MARK, PORT45_FN4),
+- PINMUX_DATA(FSICOLR_MARK, PORT46_FN1), \
+- PINMUX_DATA(FSICILR_MARK, PORT46_FN2), \
+- PINMUX_DATA(FSIDOLR_MARK, PORT46_FN3), \
+- PINMUX_DATA(FSIDILR_MARK, PORT46_FN4),
+- PINMUX_DATA(FSICOSLD_MARK, PORT47_FN1), \
+- PINMUX_DATA(PORT47_FSICSPDIF_MARK, PORT47_FN2),
+- PINMUX_DATA(FSICISLD_MARK, PORT48_FN1), \
+- PINMUX_DATA(FSIDISLD_MARK, PORT48_FN3),
+- PINMUX_DATA(FSIACK_MARK, PORT49_FN1), \
+- PINMUX_DATA(PORT49_IRDA_OUT_MARK, PORT49_FN2, MSEL4CR_MSEL19_1), \
+- PINMUX_DATA(PORT49_IROUT_MARK, PORT49_FN4), \
+- PINMUX_DATA(FSIAOMC_MARK, PORT49_FN5),
+- PINMUX_DATA(FSIAOLR_MARK, PORT50_FN1), \
+- PINMUX_DATA(BBIF2_TSYNC2_MARK, PORT50_FN2), \
+- PINMUX_DATA(TPU2TO2_MARK, PORT50_FN3), \
+- PINMUX_DATA(FSIAILR_MARK, PORT50_FN5),
+-
+- PINMUX_DATA(FSIAOBT_MARK, PORT51_FN1), \
+- PINMUX_DATA(BBIF2_TSCK2_MARK, PORT51_FN2), \
+- PINMUX_DATA(TPU2TO3_MARK, PORT51_FN3), \
+- PINMUX_DATA(FSIAIBT_MARK, PORT51_FN5),
+- PINMUX_DATA(FSIAOSLD_MARK, PORT52_FN1), \
+- PINMUX_DATA(BBIF2_TXD2_MARK, PORT52_FN2),
+- PINMUX_DATA(FSIASPDIF_MARK, PORT53_FN1), \
+- PINMUX_DATA(PORT53_IRDA_IN_MARK, PORT53_FN2, MSEL4CR_MSEL19_1), \
+- PINMUX_DATA(TPU3TO3_MARK, PORT53_FN3), \
+- PINMUX_DATA(FSIBSPDIF_MARK, PORT53_FN5), \
+- PINMUX_DATA(PORT53_FSICSPDIF_MARK, PORT53_FN6),
+- PINMUX_DATA(FSIBCK_MARK, PORT54_FN1), \
+- PINMUX_DATA(PORT54_IRDA_FIRSEL_MARK, PORT54_FN2, MSEL4CR_MSEL19_1), \
+- PINMUX_DATA(TPU3TO2_MARK, PORT54_FN3), \
+- PINMUX_DATA(FSIBOMC_MARK, PORT54_FN5), \
+- PINMUX_DATA(FSICCK_MARK, PORT54_FN6), \
+- PINMUX_DATA(FSICOMC_MARK, PORT54_FN7),
+- PINMUX_DATA(FSIAISLD_MARK, PORT55_FN1), \
+- PINMUX_DATA(TPU0TO0_MARK, PORT55_FN3),
+- PINMUX_DATA(A0_MARK, PORT57_FN1), \
+- PINMUX_DATA(BS__MARK, PORT57_FN2),
+- PINMUX_DATA(A12_MARK, PORT58_FN1), \
+- PINMUX_DATA(PORT58_KEYOUT7_MARK, PORT58_FN2), \
+- PINMUX_DATA(TPU4TO2_MARK, PORT58_FN4),
+- PINMUX_DATA(A13_MARK, PORT59_FN1), \
+- PINMUX_DATA(PORT59_KEYOUT6_MARK, PORT59_FN2), \
+- PINMUX_DATA(TPU0TO1_MARK, PORT59_FN4),
+- PINMUX_DATA(A14_MARK, PORT60_FN1), \
+- PINMUX_DATA(KEYOUT5_MARK, PORT60_FN2),
+- PINMUX_DATA(A15_MARK, PORT61_FN1), \
+- PINMUX_DATA(KEYOUT4_MARK, PORT61_FN2),
+- PINMUX_DATA(A16_MARK, PORT62_FN1), \
+- PINMUX_DATA(KEYOUT3_MARK, PORT62_FN2), \
+- PINMUX_DATA(MSIOF0_SS1_MARK, PORT62_FN4, MSEL3CR_MSEL11_0),
+- PINMUX_DATA(A17_MARK, PORT63_FN1), \
+- PINMUX_DATA(KEYOUT2_MARK, PORT63_FN2), \
+- PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT63_FN4, MSEL3CR_MSEL11_0),
+- PINMUX_DATA(A18_MARK, PORT64_FN1), \
+- PINMUX_DATA(KEYOUT1_MARK, PORT64_FN2), \
+- PINMUX_DATA(MSIOF0_TSCK_MARK, PORT64_FN4, MSEL3CR_MSEL11_0),
+- PINMUX_DATA(A19_MARK, PORT65_FN1), \
+- PINMUX_DATA(KEYOUT0_MARK, PORT65_FN2), \
+- PINMUX_DATA(MSIOF0_TXD_MARK, PORT65_FN4, MSEL3CR_MSEL11_0),
+- PINMUX_DATA(A20_MARK, PORT66_FN1), \
+- PINMUX_DATA(KEYIN0_MARK, PORT66_FN2), \
+- PINMUX_DATA(MSIOF0_RSCK_MARK, PORT66_FN4, MSEL3CR_MSEL11_0),
+- PINMUX_DATA(A21_MARK, PORT67_FN1), \
+- PINMUX_DATA(KEYIN1_MARK, PORT67_FN2), \
+- PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT67_FN4, MSEL3CR_MSEL11_0),
+- PINMUX_DATA(A22_MARK, PORT68_FN1), \
+- PINMUX_DATA(KEYIN2_MARK, PORT68_FN2), \
+- PINMUX_DATA(MSIOF0_MCK0_MARK, PORT68_FN4, MSEL3CR_MSEL11_0),
+- PINMUX_DATA(A23_MARK, PORT69_FN1), \
+- PINMUX_DATA(KEYIN3_MARK, PORT69_FN2), \
+- PINMUX_DATA(MSIOF0_MCK1_MARK, PORT69_FN4, MSEL3CR_MSEL11_0),
+- PINMUX_DATA(A24_MARK, PORT70_FN1), \
+- PINMUX_DATA(KEYIN4_MARK, PORT70_FN2), \
+- PINMUX_DATA(MSIOF0_RXD_MARK, PORT70_FN4, MSEL3CR_MSEL11_0),
+- PINMUX_DATA(A25_MARK, PORT71_FN1), \
+- PINMUX_DATA(KEYIN5_MARK, PORT71_FN2), \
+- PINMUX_DATA(MSIOF0_SS2_MARK, PORT71_FN4, MSEL3CR_MSEL11_0),
+- PINMUX_DATA(A26_MARK, PORT72_FN1), \
+- PINMUX_DATA(KEYIN6_MARK, PORT72_FN2),
+- PINMUX_DATA(KEYIN7_MARK, PORT73_FN2),
+- PINMUX_DATA(D0_NAF0_MARK, PORT74_FN1),
+- PINMUX_DATA(D1_NAF1_MARK, PORT75_FN1),
+- PINMUX_DATA(D2_NAF2_MARK, PORT76_FN1),
+- PINMUX_DATA(D3_NAF3_MARK, PORT77_FN1),
+- PINMUX_DATA(D4_NAF4_MARK, PORT78_FN1),
+- PINMUX_DATA(D5_NAF5_MARK, PORT79_FN1),
+- PINMUX_DATA(D6_NAF6_MARK, PORT80_FN1),
+- PINMUX_DATA(D7_NAF7_MARK, PORT81_FN1),
+- PINMUX_DATA(D8_NAF8_MARK, PORT82_FN1),
+- PINMUX_DATA(D9_NAF9_MARK, PORT83_FN1),
+- PINMUX_DATA(D10_NAF10_MARK, PORT84_FN1),
+- PINMUX_DATA(D11_NAF11_MARK, PORT85_FN1),
+- PINMUX_DATA(D12_NAF12_MARK, PORT86_FN1),
+- PINMUX_DATA(D13_NAF13_MARK, PORT87_FN1),
+- PINMUX_DATA(D14_NAF14_MARK, PORT88_FN1),
+- PINMUX_DATA(D15_NAF15_MARK, PORT89_FN1),
+- PINMUX_DATA(CS4__MARK, PORT90_FN1),
+- PINMUX_DATA(CS5A__MARK, PORT91_FN1), \
+- PINMUX_DATA(PORT91_RDWR_MARK, PORT91_FN2),
+- PINMUX_DATA(CS5B__MARK, PORT92_FN1), \
+- PINMUX_DATA(FCE1__MARK, PORT92_FN2),
+- PINMUX_DATA(CS6B__MARK, PORT93_FN1), \
+- PINMUX_DATA(DACK0_MARK, PORT93_FN4),
+- PINMUX_DATA(FCE0__MARK, PORT94_FN1), \
+- PINMUX_DATA(CS6A__MARK, PORT94_FN2),
+- PINMUX_DATA(WAIT__MARK, PORT95_FN1), \
+- PINMUX_DATA(DREQ0_MARK, PORT95_FN2),
+- PINMUX_DATA(RD__FSC_MARK, PORT96_FN1),
+- PINMUX_DATA(WE0__FWE_MARK, PORT97_FN1), \
+- PINMUX_DATA(RDWR_FWE_MARK, PORT97_FN2),
+- PINMUX_DATA(WE1__MARK, PORT98_FN1),
+- PINMUX_DATA(FRB_MARK, PORT99_FN1),
+- PINMUX_DATA(CKO_MARK, PORT100_FN1),
+- PINMUX_DATA(NBRSTOUT__MARK, PORT101_FN1),
+- PINMUX_DATA(NBRST__MARK, PORT102_FN1),
+- PINMUX_DATA(BBIF2_TXD_MARK, PORT103_FN3),
+- PINMUX_DATA(BBIF2_RXD_MARK, PORT104_FN3),
+- PINMUX_DATA(BBIF2_SYNC_MARK, PORT105_FN3),
+- PINMUX_DATA(BBIF2_SCK_MARK, PORT106_FN3),
+- PINMUX_DATA(SCIFA3_CTS__MARK, PORT107_FN3), \
+- PINMUX_DATA(MFG3_IN2_MARK, PORT107_FN4),
+- PINMUX_DATA(SCIFA3_RXD_MARK, PORT108_FN3), \
+- PINMUX_DATA(MFG3_IN1_MARK, PORT108_FN4),
+- PINMUX_DATA(BBIF1_SS2_MARK, PORT109_FN2), \
+- PINMUX_DATA(SCIFA3_RTS__MARK, PORT109_FN3), \
+- PINMUX_DATA(MFG3_OUT1_MARK, PORT109_FN4),
+- PINMUX_DATA(SCIFA3_TXD_MARK, PORT110_FN3),
+- PINMUX_DATA(HSI_RX_DATA_MARK, PORT111_FN1), \
+- PINMUX_DATA(BBIF1_RXD_MARK, PORT111_FN3),
+- PINMUX_DATA(HSI_TX_WAKE_MARK, PORT112_FN1), \
+- PINMUX_DATA(BBIF1_TSCK_MARK, PORT112_FN3),
+- PINMUX_DATA(HSI_TX_DATA_MARK, PORT113_FN1), \
+- PINMUX_DATA(BBIF1_TSYNC_MARK, PORT113_FN3),
+- PINMUX_DATA(HSI_TX_READY_MARK, PORT114_FN1), \
+- PINMUX_DATA(BBIF1_TXD_MARK, PORT114_FN3),
+- PINMUX_DATA(HSI_RX_READY_MARK, PORT115_FN1), \
+- PINMUX_DATA(BBIF1_RSCK_MARK, PORT115_FN3), \
+- PINMUX_DATA(PORT115_I2C_SCL2_MARK, PORT115_FN5, MSEL2CR_MSEL17_1), \
+- PINMUX_DATA(PORT115_I2C_SCL3_MARK, PORT115_FN6, MSEL2CR_MSEL19_1),
+- PINMUX_DATA(HSI_RX_WAKE_MARK, PORT116_FN1), \
+- PINMUX_DATA(BBIF1_RSYNC_MARK, PORT116_FN3), \
+- PINMUX_DATA(PORT116_I2C_SDA2_MARK, PORT116_FN5, MSEL2CR_MSEL17_1), \
+- PINMUX_DATA(PORT116_I2C_SDA3_MARK, PORT116_FN6, MSEL2CR_MSEL19_1),
+- PINMUX_DATA(HSI_RX_FLAG_MARK, PORT117_FN1), \
+- PINMUX_DATA(BBIF1_SS1_MARK, PORT117_FN2), \
+- PINMUX_DATA(BBIF1_FLOW_MARK, PORT117_FN3),
+- PINMUX_DATA(HSI_TX_FLAG_MARK, PORT118_FN1),
+- PINMUX_DATA(VIO_VD_MARK, PORT128_FN1), \
+- PINMUX_DATA(PORT128_LCD2VSYN_MARK, PORT128_FN4, MSEL3CR_MSEL2_0), \
+- PINMUX_DATA(VIO2_VD_MARK, PORT128_FN6, MSEL4CR_MSEL27_0), \
+- PINMUX_DATA(LCD2D0_MARK, PORT128_FN7),
+-
+- PINMUX_DATA(VIO_HD_MARK, PORT129_FN1), \
+- PINMUX_DATA(PORT129_LCD2HSYN_MARK, PORT129_FN4), \
+- PINMUX_DATA(PORT129_LCD2CS__MARK, PORT129_FN5), \
+- PINMUX_DATA(VIO2_HD_MARK, PORT129_FN6, MSEL4CR_MSEL27_0), \
+- PINMUX_DATA(LCD2D1_MARK, PORT129_FN7),
+- PINMUX_DATA(VIO_D0_MARK, PORT130_FN1), \
+- PINMUX_DATA(PORT130_MSIOF2_RXD_MARK, PORT130_FN3, MSEL4CR_MSEL11_0,
+- MSEL4CR_MSEL10_1), \
+- PINMUX_DATA(LCD2D10_MARK, PORT130_FN7),
+- PINMUX_DATA(VIO_D1_MARK, PORT131_FN1), \
+- PINMUX_DATA(PORT131_KEYOUT6_MARK, PORT131_FN2), \
+- PINMUX_DATA(PORT131_MSIOF2_SS1_MARK, PORT131_FN3), \
+- PINMUX_DATA(PORT131_KEYOUT11_MARK, PORT131_FN4), \
+- PINMUX_DATA(LCD2D11_MARK, PORT131_FN7),
+- PINMUX_DATA(VIO_D2_MARK, PORT132_FN1), \
+- PINMUX_DATA(PORT132_KEYOUT7_MARK, PORT132_FN2), \
+- PINMUX_DATA(PORT132_MSIOF2_SS2_MARK, PORT132_FN3), \
+- PINMUX_DATA(PORT132_KEYOUT10_MARK, PORT132_FN4), \
+- PINMUX_DATA(LCD2D12_MARK, PORT132_FN7),
+- PINMUX_DATA(VIO_D3_MARK, PORT133_FN1), \
+- PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT133_FN3, MSEL4CR_MSEL11_0), \
+- PINMUX_DATA(LCD2D13_MARK, PORT133_FN7),
+- PINMUX_DATA(VIO_D4_MARK, PORT134_FN1), \
+- PINMUX_DATA(MSIOF2_TXD_MARK, PORT134_FN3, MSEL4CR_MSEL11_0), \
+- PINMUX_DATA(LCD2D14_MARK, PORT134_FN7),
+- PINMUX_DATA(VIO_D5_MARK, PORT135_FN1), \
+- PINMUX_DATA(MSIOF2_TSCK_MARK, PORT135_FN3, MSEL4CR_MSEL11_0), \
+- PINMUX_DATA(LCD2D15_MARK, PORT135_FN7),
+- PINMUX_DATA(VIO_D6_MARK, PORT136_FN1), \
+- PINMUX_DATA(PORT136_KEYOUT8_MARK, PORT136_FN2), \
+- PINMUX_DATA(LCD2D16_MARK, PORT136_FN7),
+- PINMUX_DATA(VIO_D7_MARK, PORT137_FN1), \
+- PINMUX_DATA(PORT137_KEYOUT9_MARK, PORT137_FN2), \
+- PINMUX_DATA(LCD2D17_MARK, PORT137_FN7),
+- PINMUX_DATA(VIO_D8_MARK, PORT138_FN1), \
+- PINMUX_DATA(PORT138_KEYOUT8_MARK, PORT138_FN2), \
+- PINMUX_DATA(VIO2_D0_MARK, PORT138_FN6), \
+- PINMUX_DATA(LCD2D6_MARK, PORT138_FN7),
+- PINMUX_DATA(VIO_D9_MARK, PORT139_FN1), \
+- PINMUX_DATA(PORT139_KEYOUT9_MARK, PORT139_FN2), \
+- PINMUX_DATA(VIO2_D1_MARK, PORT139_FN6), \
+- PINMUX_DATA(LCD2D7_MARK, PORT139_FN7),
+- PINMUX_DATA(VIO_D10_MARK, PORT140_FN1), \
+- PINMUX_DATA(TPU0TO2_MARK, PORT140_FN4), \
+- PINMUX_DATA(VIO2_D2_MARK, PORT140_FN6), \
+- PINMUX_DATA(LCD2D8_MARK, PORT140_FN7),
+- PINMUX_DATA(VIO_D11_MARK, PORT141_FN1), \
+- PINMUX_DATA(TPU0TO3_MARK, PORT141_FN4), \
+- PINMUX_DATA(VIO2_D3_MARK, PORT141_FN6), \
+- PINMUX_DATA(LCD2D9_MARK, PORT141_FN7),
+- PINMUX_DATA(VIO_D12_MARK, PORT142_FN1), \
+- PINMUX_DATA(PORT142_KEYOUT10_MARK, PORT142_FN2), \
+- PINMUX_DATA(VIO2_D4_MARK, PORT142_FN6), \
+- PINMUX_DATA(LCD2D2_MARK, PORT142_FN7),
+- PINMUX_DATA(VIO_D13_MARK, PORT143_FN1), \
+- PINMUX_DATA(PORT143_KEYOUT11_MARK, PORT143_FN2), \
+- PINMUX_DATA(PORT143_KEYOUT6_MARK, PORT143_FN3), \
+- PINMUX_DATA(VIO2_D5_MARK, PORT143_FN6), \
+- PINMUX_DATA(LCD2D3_MARK, PORT143_FN7),
+- PINMUX_DATA(VIO_D14_MARK, PORT144_FN1), \
+- PINMUX_DATA(PORT144_KEYOUT7_MARK, PORT144_FN2), \
+- PINMUX_DATA(VIO2_D6_MARK, PORT144_FN6), \
+- PINMUX_DATA(LCD2D4_MARK, PORT144_FN7),
+- PINMUX_DATA(VIO_D15_MARK, PORT145_FN1), \
+- PINMUX_DATA(TPU1TO3_MARK, PORT145_FN3), \
+- PINMUX_DATA(PORT145_LCD2DISP_MARK, PORT145_FN4), \
+- PINMUX_DATA(PORT145_LCD2RS_MARK, PORT145_FN5), \
+- PINMUX_DATA(VIO2_D7_MARK, PORT145_FN6), \
+- PINMUX_DATA(LCD2D5_MARK, PORT145_FN7),
+- PINMUX_DATA(VIO_CLK_MARK, PORT146_FN1), \
+- PINMUX_DATA(LCD2DCK_MARK, PORT146_FN4), \
+- PINMUX_DATA(PORT146_LCD2WR__MARK, PORT146_FN5), \
+- PINMUX_DATA(VIO2_CLK_MARK, PORT146_FN6, MSEL4CR_MSEL27_0), \
+- PINMUX_DATA(LCD2D18_MARK, PORT146_FN7),
+- PINMUX_DATA(VIO_FIELD_MARK, PORT147_FN1), \
+- PINMUX_DATA(LCD2RD__MARK, PORT147_FN4), \
+- PINMUX_DATA(VIO2_FIELD_MARK, PORT147_FN6, MSEL4CR_MSEL27_0), \
+- PINMUX_DATA(LCD2D19_MARK, PORT147_FN7),
+- PINMUX_DATA(VIO_CKO_MARK, PORT148_FN1),
+- PINMUX_DATA(A27_MARK, PORT149_FN1), \
+- PINMUX_DATA(PORT149_RDWR_MARK, PORT149_FN2), \
+- PINMUX_DATA(MFG0_IN1_MARK, PORT149_FN3), \
+- PINMUX_DATA(PORT149_KEYOUT9_MARK, PORT149_FN4),
+- PINMUX_DATA(MFG0_IN2_MARK, PORT150_FN3),
+- PINMUX_DATA(TS_SPSYNC3_MARK, PORT151_FN4), \
+- PINMUX_DATA(MSIOF2_RSCK_MARK, PORT151_FN5),
+- PINMUX_DATA(TS_SDAT3_MARK, PORT152_FN4), \
+- PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT152_FN5),
+- PINMUX_DATA(TPU1TO2_MARK, PORT153_FN3), \
+- PINMUX_DATA(TS_SDEN3_MARK, PORT153_FN4), \
+- PINMUX_DATA(PORT153_MSIOF2_SS1_MARK, PORT153_FN5),
+- PINMUX_DATA(SCIFA2_TXD1_MARK, PORT154_FN2, MSEL3CR_MSEL9_0), \
+- PINMUX_DATA(MSIOF2_MCK0_MARK, PORT154_FN5),
+- PINMUX_DATA(SCIFA2_RXD1_MARK, PORT155_FN2, MSEL3CR_MSEL9_0), \
+- PINMUX_DATA(MSIOF2_MCK1_MARK, PORT155_FN5),
+- PINMUX_DATA(SCIFA2_RTS1__MARK, PORT156_FN2, MSEL3CR_MSEL9_0), \
+- PINMUX_DATA(PORT156_MSIOF2_SS2_MARK, PORT156_FN5),
+- PINMUX_DATA(SCIFA2_CTS1__MARK, PORT157_FN2, MSEL3CR_MSEL9_0), \
+- PINMUX_DATA(PORT157_MSIOF2_RXD_MARK, PORT157_FN5, MSEL4CR_MSEL11_0,
+- MSEL4CR_MSEL10_0),
+- PINMUX_DATA(DINT__MARK, PORT158_FN1), \
+- PINMUX_DATA(SCIFA2_SCK1_MARK, PORT158_FN2, MSEL3CR_MSEL9_0), \
+- PINMUX_DATA(TS_SCK3_MARK, PORT158_FN4),
+- PINMUX_DATA(PORT159_SCIFB_SCK_MARK, PORT159_FN1, MSEL4CR_MSEL22_0), \
+- PINMUX_DATA(PORT159_SCIFA5_SCK_MARK, PORT159_FN2, MSEL4CR_MSEL21_1), \
+- PINMUX_DATA(NMI_MARK, PORT159_FN3),
+- PINMUX_DATA(PORT160_SCIFB_TXD_MARK, PORT160_FN1, MSEL4CR_MSEL22_0), \
+- PINMUX_DATA(PORT160_SCIFA5_TXD_MARK, PORT160_FN2, MSEL4CR_MSEL21_1),
+- PINMUX_DATA(PORT161_SCIFB_CTS__MARK, PORT161_FN1, MSEL4CR_MSEL22_0), \
+- PINMUX_DATA(PORT161_SCIFA5_CTS__MARK, PORT161_FN2, MSEL4CR_MSEL21_1),
+- PINMUX_DATA(PORT162_SCIFB_RXD_MARK, PORT162_FN1, MSEL4CR_MSEL22_0), \
+- PINMUX_DATA(PORT162_SCIFA5_RXD_MARK, PORT162_FN2, MSEL4CR_MSEL21_1),
+- PINMUX_DATA(PORT163_SCIFB_RTS__MARK, PORT163_FN1, MSEL4CR_MSEL22_0), \
+- PINMUX_DATA(PORT163_SCIFA5_RTS__MARK, PORT163_FN2, MSEL4CR_MSEL21_1), \
+- PINMUX_DATA(TPU3TO0_MARK, PORT163_FN5),
+- PINMUX_DATA(LCDD0_MARK, PORT192_FN1),
+- PINMUX_DATA(LCDD1_MARK, PORT193_FN1), \
+- PINMUX_DATA(PORT193_SCIFA5_CTS__MARK, PORT193_FN3, MSEL4CR_MSEL21_0,
+- MSEL4CR_MSEL20_1), \
+- PINMUX_DATA(BBIF2_TSYNC1_MARK, PORT193_FN5),
+- PINMUX_DATA(LCDD2_MARK, PORT194_FN1), \
+- PINMUX_DATA(PORT194_SCIFA5_RTS__MARK, PORT194_FN3, MSEL4CR_MSEL21_0,
+- MSEL4CR_MSEL20_1), \
+- PINMUX_DATA(BBIF2_TSCK1_MARK, PORT194_FN5),
+- PINMUX_DATA(LCDD3_MARK, PORT195_FN1), \
+- PINMUX_DATA(PORT195_SCIFA5_RXD_MARK, PORT195_FN3, MSEL4CR_MSEL21_0,
+- MSEL4CR_MSEL20_1), \
+- PINMUX_DATA(BBIF2_TXD1_MARK, PORT195_FN5),
+- PINMUX_DATA(LCDD4_MARK, PORT196_FN1), \
+- PINMUX_DATA(PORT196_SCIFA5_TXD_MARK, PORT196_FN3, MSEL4CR_MSEL21_0,
+- MSEL4CR_MSEL20_1),
+- PINMUX_DATA(LCDD5_MARK, PORT197_FN1), \
+- PINMUX_DATA(PORT197_SCIFA5_SCK_MARK, PORT197_FN3, MSEL4CR_MSEL21_0,
+- MSEL4CR_MSEL20_1), \
+- PINMUX_DATA(MFG2_OUT2_MARK, PORT197_FN5), \
+- PINMUX_DATA(TPU2TO1_MARK, PORT197_FN7),
+- PINMUX_DATA(LCDD6_MARK, PORT198_FN1),
+- PINMUX_DATA(LCDD7_MARK, PORT199_FN1), \
+- PINMUX_DATA(TPU4TO1_MARK, PORT199_FN2), \
+- PINMUX_DATA(MFG4_OUT2_MARK, PORT199_FN5),
+- PINMUX_DATA(LCDD8_MARK, PORT200_FN1), \
+- PINMUX_DATA(D16_MARK, PORT200_FN6),
+- PINMUX_DATA(LCDD9_MARK, PORT201_FN1), \
+- PINMUX_DATA(D17_MARK, PORT201_FN6),
+- PINMUX_DATA(LCDD10_MARK, PORT202_FN1), \
+- PINMUX_DATA(D18_MARK, PORT202_FN6),
+- PINMUX_DATA(LCDD11_MARK, PORT203_FN1), \
+- PINMUX_DATA(D19_MARK, PORT203_FN6),
+- PINMUX_DATA(LCDD12_MARK, PORT204_FN1), \
+- PINMUX_DATA(D20_MARK, PORT204_FN6),
+- PINMUX_DATA(LCDD13_MARK, PORT205_FN1), \
+- PINMUX_DATA(D21_MARK, PORT205_FN6),
+- PINMUX_DATA(LCDD14_MARK, PORT206_FN1), \
+- PINMUX_DATA(D22_MARK, PORT206_FN6),
+- PINMUX_DATA(LCDD15_MARK, PORT207_FN1), \
+- PINMUX_DATA(PORT207_MSIOF0L_SS1_MARK, PORT207_FN2, MSEL3CR_MSEL11_1), \
+- PINMUX_DATA(D23_MARK, PORT207_FN6),
+- PINMUX_DATA(LCDD16_MARK, PORT208_FN1), \
+- PINMUX_DATA(PORT208_MSIOF0L_SS2_MARK, PORT208_FN2, MSEL3CR_MSEL11_1), \
+- PINMUX_DATA(D24_MARK, PORT208_FN6),
+- PINMUX_DATA(LCDD17_MARK, PORT209_FN1), \
+- PINMUX_DATA(D25_MARK, PORT209_FN6),
+- PINMUX_DATA(LCDD18_MARK, PORT210_FN1), \
+- PINMUX_DATA(DREQ2_MARK, PORT210_FN2), \
+- PINMUX_DATA(PORT210_MSIOF0L_SS1_MARK, PORT210_FN5, MSEL3CR_MSEL11_1), \
+- PINMUX_DATA(D26_MARK, PORT210_FN6),
+- PINMUX_DATA(LCDD19_MARK, PORT211_FN1), \
+- PINMUX_DATA(PORT211_MSIOF0L_SS2_MARK, PORT211_FN5, MSEL3CR_MSEL11_1), \
+- PINMUX_DATA(D27_MARK, PORT211_FN6),
+- PINMUX_DATA(LCDD20_MARK, PORT212_FN1), \
+- PINMUX_DATA(TS_SPSYNC1_MARK, PORT212_FN2), \
+- PINMUX_DATA(MSIOF0L_MCK0_MARK, PORT212_FN5, MSEL3CR_MSEL11_1), \
+- PINMUX_DATA(D28_MARK, PORT212_FN6),
+- PINMUX_DATA(LCDD21_MARK, PORT213_FN1), \
+- PINMUX_DATA(TS_SDAT1_MARK, PORT213_FN2), \
+- PINMUX_DATA(MSIOF0L_MCK1_MARK, PORT213_FN5, MSEL3CR_MSEL11_1), \
+- PINMUX_DATA(D29_MARK, PORT213_FN6),
+- PINMUX_DATA(LCDD22_MARK, PORT214_FN1), \
+- PINMUX_DATA(TS_SDEN1_MARK, PORT214_FN2), \
+- PINMUX_DATA(MSIOF0L_RSCK_MARK, PORT214_FN5, MSEL3CR_MSEL11_1), \
+- PINMUX_DATA(D30_MARK, PORT214_FN6),
+- PINMUX_DATA(LCDD23_MARK, PORT215_FN1), \
+- PINMUX_DATA(TS_SCK1_MARK, PORT215_FN2), \
+- PINMUX_DATA(MSIOF0L_RSYNC_MARK, PORT215_FN5, MSEL3CR_MSEL11_1), \
+- PINMUX_DATA(D31_MARK, PORT215_FN6),
+- PINMUX_DATA(LCDDCK_MARK, PORT216_FN1), \
+- PINMUX_DATA(LCDWR__MARK, PORT216_FN2),
+- PINMUX_DATA(LCDRD__MARK, PORT217_FN1), \
+- PINMUX_DATA(DACK2_MARK, PORT217_FN2), \
+- PINMUX_DATA(PORT217_LCD2RS_MARK, PORT217_FN3), \
+- PINMUX_DATA(MSIOF0L_TSYNC_MARK, PORT217_FN5, MSEL3CR_MSEL11_1), \
+- PINMUX_DATA(VIO2_FIELD3_MARK, PORT217_FN6, MSEL4CR_MSEL27_1,
+- MSEL4CR_MSEL26_1), \
+- PINMUX_DATA(PORT217_LCD2DISP_MARK, PORT217_FN7),
+- PINMUX_DATA(LCDHSYN_MARK, PORT218_FN1), \
+- PINMUX_DATA(LCDCS__MARK, PORT218_FN2), \
+- PINMUX_DATA(LCDCS2__MARK, PORT218_FN3), \
+- PINMUX_DATA(DACK3_MARK, PORT218_FN4), \
+- PINMUX_DATA(PORT218_VIO_CKOR_MARK, PORT218_FN5),
+- PINMUX_DATA(LCDDISP_MARK, PORT219_FN1), \
+- PINMUX_DATA(LCDRS_MARK, PORT219_FN2), \
+- PINMUX_DATA(PORT219_LCD2WR__MARK, PORT219_FN3), \
+- PINMUX_DATA(DREQ3_MARK, PORT219_FN4), \
+- PINMUX_DATA(MSIOF0L_TSCK_MARK, PORT219_FN5, MSEL3CR_MSEL11_1), \
+- PINMUX_DATA(VIO2_CLK3_MARK, PORT219_FN6, MSEL4CR_MSEL27_1,
+- MSEL4CR_MSEL26_1), \
+- PINMUX_DATA(LCD2DCK_2_MARK, PORT219_FN7),
+- PINMUX_DATA(LCDVSYN_MARK, PORT220_FN1), \
+- PINMUX_DATA(LCDVSYN2_MARK, PORT220_FN2),
+- PINMUX_DATA(LCDLCLK_MARK, PORT221_FN1), \
+- PINMUX_DATA(DREQ1_MARK, PORT221_FN2), \
+- PINMUX_DATA(PORT221_LCD2CS__MARK, PORT221_FN3), \
+- PINMUX_DATA(PWEN_MARK, PORT221_FN4), \
+- PINMUX_DATA(MSIOF0L_RXD_MARK, PORT221_FN5, MSEL3CR_MSEL11_1), \
+- PINMUX_DATA(VIO2_HD3_MARK, PORT221_FN6, MSEL4CR_MSEL27_1,
+- MSEL4CR_MSEL26_1), \
+- PINMUX_DATA(PORT221_LCD2HSYN_MARK, PORT221_FN7),
+- PINMUX_DATA(LCDDON_MARK, PORT222_FN1), \
+- PINMUX_DATA(LCDDON2_MARK, PORT222_FN2), \
+- PINMUX_DATA(DACK1_MARK, PORT222_FN3), \
+- PINMUX_DATA(OVCN_MARK, PORT222_FN4), \
+- PINMUX_DATA(MSIOF0L_TXD_MARK, PORT222_FN5, MSEL3CR_MSEL11_1), \
+- PINMUX_DATA(VIO2_VD3_MARK, PORT222_FN6, MSEL4CR_MSEL27_1,
+- MSEL4CR_MSEL26_1), \
+- PINMUX_DATA(PORT222_LCD2VSYN_MARK, PORT222_FN7, MSEL3CR_MSEL2_1),
+-
+- PINMUX_DATA(SCIFA1_TXD_MARK, PORT225_FN2), \
+- PINMUX_DATA(OVCN2_MARK, PORT225_FN4),
+- PINMUX_DATA(EXTLP_MARK, PORT226_FN1), \
+- PINMUX_DATA(SCIFA1_SCK_MARK, PORT226_FN2), \
+- PINMUX_DATA(PORT226_VIO_CKO2_MARK, PORT226_FN5),
+- PINMUX_DATA(SCIFA1_RTS__MARK, PORT227_FN2), \
+- PINMUX_DATA(IDIN_MARK, PORT227_FN4),
+- PINMUX_DATA(SCIFA1_RXD_MARK, PORT228_FN2),
+- PINMUX_DATA(SCIFA1_CTS__MARK, PORT229_FN2), \
+- PINMUX_DATA(MFG1_IN1_MARK, PORT229_FN3),
+- PINMUX_DATA(MSIOF1_TXD_MARK, PORT230_FN1), \
+- PINMUX_DATA(SCIFA2_TXD2_MARK, PORT230_FN2, MSEL3CR_MSEL9_1),
+- PINMUX_DATA(MSIOF1_TSYNC_MARK, PORT231_FN1), \
+- PINMUX_DATA(SCIFA2_CTS2__MARK, PORT231_FN2, MSEL3CR_MSEL9_1),
+- PINMUX_DATA(MSIOF1_TSCK_MARK, PORT232_FN1), \
+- PINMUX_DATA(SCIFA2_SCK2_MARK, PORT232_FN2, MSEL3CR_MSEL9_1),
+- PINMUX_DATA(MSIOF1_RXD_MARK, PORT233_FN1), \
+- PINMUX_DATA(SCIFA2_RXD2_MARK, PORT233_FN2, MSEL3CR_MSEL9_1),
+- PINMUX_DATA(MSIOF1_RSCK_MARK, PORT234_FN1), \
+- PINMUX_DATA(SCIFA2_RTS2__MARK, PORT234_FN2, MSEL3CR_MSEL9_1), \
+- PINMUX_DATA(VIO2_CLK2_MARK, PORT234_FN6, MSEL4CR_MSEL27_1,
+- MSEL4CR_MSEL26_0), \
+- PINMUX_DATA(LCD2D20_MARK, PORT234_FN7),
+- PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT235_FN1), \
+- PINMUX_DATA(MFG1_IN2_MARK, PORT235_FN3), \
+- PINMUX_DATA(VIO2_VD2_MARK, PORT235_FN6, MSEL4CR_MSEL27_1,
+- MSEL4CR_MSEL26_0), \
+- PINMUX_DATA(LCD2D21_MARK, PORT235_FN7),
+- PINMUX_DATA(MSIOF1_MCK0_MARK, PORT236_FN1), \
+- PINMUX_DATA(PORT236_I2C_SDA2_MARK, PORT236_FN2, MSEL2CR_MSEL17_0,
+- MSEL2CR_MSEL16_0),
+- PINMUX_DATA(MSIOF1_MCK1_MARK, PORT237_FN1), \
+- PINMUX_DATA(PORT237_I2C_SCL2_MARK, PORT237_FN2, MSEL2CR_MSEL17_0,
+- MSEL2CR_MSEL16_0),
+- PINMUX_DATA(MSIOF1_SS1_MARK, PORT238_FN1), \
+- PINMUX_DATA(VIO2_FIELD2_MARK, PORT238_FN6, MSEL4CR_MSEL27_1,
+- MSEL4CR_MSEL26_0), \
+- PINMUX_DATA(LCD2D22_MARK, PORT238_FN7),
+- PINMUX_DATA(MSIOF1_SS2_MARK, PORT239_FN1), \
+- PINMUX_DATA(VIO2_HD2_MARK, PORT239_FN6, MSEL4CR_MSEL27_1,
+- MSEL4CR_MSEL26_0), \
+- PINMUX_DATA(LCD2D23_MARK, PORT239_FN7),
+- PINMUX_DATA(SCIFA6_TXD_MARK, PORT240_FN1),
+- PINMUX_DATA(PORT241_IRDA_OUT_MARK, PORT241_FN1, MSEL4CR_MSEL19_0), \
+- PINMUX_DATA(PORT241_IROUT_MARK, PORT241_FN2), \
+- PINMUX_DATA(MFG4_OUT1_MARK, PORT241_FN3), \
+- PINMUX_DATA(TPU4TO0_MARK, PORT241_FN4),
+- PINMUX_DATA(PORT242_IRDA_IN_MARK, PORT242_FN1, MSEL4CR_MSEL19_0), \
+- PINMUX_DATA(MFG4_IN2_MARK, PORT242_FN3),
+- PINMUX_DATA(PORT243_IRDA_FIRSEL_MARK, PORT243_FN1, MSEL4CR_MSEL19_0), \
+- PINMUX_DATA(PORT243_VIO_CKO2_MARK, PORT243_FN2),
+- PINMUX_DATA(PORT244_SCIFA5_CTS__MARK, PORT244_FN1, MSEL4CR_MSEL21_0,
+- MSEL4CR_MSEL20_0), \
+- PINMUX_DATA(MFG2_IN1_MARK, PORT244_FN2), \
+- PINMUX_DATA(PORT244_SCIFB_CTS__MARK, PORT244_FN3, MSEL4CR_MSEL22_1), \
+- PINMUX_DATA(MSIOF2R_RXD_MARK, PORT244_FN7, MSEL4CR_MSEL11_1),
+- PINMUX_DATA(PORT245_SCIFA5_RTS__MARK, PORT245_FN1, MSEL4CR_MSEL21_0,
+- MSEL4CR_MSEL20_0), \
+- PINMUX_DATA(MFG2_IN2_MARK, PORT245_FN2), \
+- PINMUX_DATA(PORT245_SCIFB_RTS__MARK, PORT245_FN3, MSEL4CR_MSEL22_1), \
+- PINMUX_DATA(MSIOF2R_TXD_MARK, PORT245_FN7, MSEL4CR_MSEL11_1),
+- PINMUX_DATA(PORT246_SCIFA5_RXD_MARK, PORT246_FN1, MSEL4CR_MSEL21_0,
+- MSEL4CR_MSEL20_0), \
+- PINMUX_DATA(MFG1_OUT1_MARK, PORT246_FN2), \
+- PINMUX_DATA(PORT246_SCIFB_RXD_MARK, PORT246_FN3, MSEL4CR_MSEL22_1), \
+- PINMUX_DATA(TPU1TO0_MARK, PORT246_FN4),
+- PINMUX_DATA(PORT247_SCIFA5_TXD_MARK, PORT247_FN1, MSEL4CR_MSEL21_0,
+- MSEL4CR_MSEL20_0), \
+- PINMUX_DATA(MFG3_OUT2_MARK, PORT247_FN2), \
+- PINMUX_DATA(PORT247_SCIFB_TXD_MARK, PORT247_FN3, MSEL4CR_MSEL22_1), \
+- PINMUX_DATA(TPU3TO1_MARK, PORT247_FN4),
+- PINMUX_DATA(PORT248_SCIFA5_SCK_MARK, PORT248_FN1, MSEL4CR_MSEL21_0,
+- MSEL4CR_MSEL20_0), \
+- PINMUX_DATA(MFG2_OUT1_MARK, PORT248_FN2), \
+- PINMUX_DATA(PORT248_SCIFB_SCK_MARK, PORT248_FN3, MSEL4CR_MSEL22_1), \
+- PINMUX_DATA(TPU2TO0_MARK, PORT248_FN4), \
+- PINMUX_DATA(PORT248_I2C_SCL3_MARK, PORT248_FN5, MSEL2CR_MSEL19_0,
+- MSEL2CR_MSEL18_0), \
+- PINMUX_DATA(MSIOF2R_TSCK_MARK, PORT248_FN7, MSEL4CR_MSEL11_1),
+- PINMUX_DATA(PORT249_IROUT_MARK, PORT249_FN1), \
+- PINMUX_DATA(MFG4_IN1_MARK, PORT249_FN2), \
+- PINMUX_DATA(PORT249_I2C_SDA3_MARK, PORT249_FN5, MSEL2CR_MSEL19_0,
+- MSEL2CR_MSEL18_0), \
+- PINMUX_DATA(MSIOF2R_TSYNC_MARK, PORT249_FN7, MSEL4CR_MSEL11_1),
+- PINMUX_DATA(SDHICLK0_MARK, PORT250_FN1),
+- PINMUX_DATA(SDHICD0_MARK, PORT251_FN1),
+- PINMUX_DATA(SDHID0_0_MARK, PORT252_FN1),
+- PINMUX_DATA(SDHID0_1_MARK, PORT253_FN1),
+- PINMUX_DATA(SDHID0_2_MARK, PORT254_FN1),
+- PINMUX_DATA(SDHID0_3_MARK, PORT255_FN1),
+- PINMUX_DATA(SDHICMD0_MARK, PORT256_FN1),
+- PINMUX_DATA(SDHIWP0_MARK, PORT257_FN1),
+- PINMUX_DATA(SDHICLK1_MARK, PORT258_FN1),
+- PINMUX_DATA(SDHID1_0_MARK, PORT259_FN1), \
+- PINMUX_DATA(TS_SPSYNC2_MARK, PORT259_FN3),
+- PINMUX_DATA(SDHID1_1_MARK, PORT260_FN1), \
+- PINMUX_DATA(TS_SDAT2_MARK, PORT260_FN3),
+- PINMUX_DATA(SDHID1_2_MARK, PORT261_FN1), \
+- PINMUX_DATA(TS_SDEN2_MARK, PORT261_FN3),
+- PINMUX_DATA(SDHID1_3_MARK, PORT262_FN1), \
+- PINMUX_DATA(TS_SCK2_MARK, PORT262_FN3),
+- PINMUX_DATA(SDHICMD1_MARK, PORT263_FN1),
+- PINMUX_DATA(SDHICLK2_MARK, PORT264_FN1),
+- PINMUX_DATA(SDHID2_0_MARK, PORT265_FN1), \
+- PINMUX_DATA(TS_SPSYNC4_MARK, PORT265_FN3),
+- PINMUX_DATA(SDHID2_1_MARK, PORT266_FN1), \
+- PINMUX_DATA(TS_SDAT4_MARK, PORT266_FN3),
+- PINMUX_DATA(SDHID2_2_MARK, PORT267_FN1), \
+- PINMUX_DATA(TS_SDEN4_MARK, PORT267_FN3),
+- PINMUX_DATA(SDHID2_3_MARK, PORT268_FN1), \
+- PINMUX_DATA(TS_SCK4_MARK, PORT268_FN3),
+- PINMUX_DATA(SDHICMD2_MARK, PORT269_FN1),
+- PINMUX_DATA(MMCCLK0_MARK, PORT270_FN1, MSEL4CR_MSEL15_0),
+- PINMUX_DATA(MMCD0_0_MARK, PORT271_FN1, PORT271_IN_PU,
+- MSEL4CR_MSEL15_0),
+- PINMUX_DATA(MMCD0_1_MARK, PORT272_FN1, PORT272_IN_PU,
+- MSEL4CR_MSEL15_0),
+- PINMUX_DATA(MMCD0_2_MARK, PORT273_FN1, PORT273_IN_PU,
+- MSEL4CR_MSEL15_0),
+- PINMUX_DATA(MMCD0_3_MARK, PORT274_FN1, PORT274_IN_PU,
+- MSEL4CR_MSEL15_0),
+- PINMUX_DATA(MMCD0_4_MARK, PORT275_FN1, PORT275_IN_PU,
+- MSEL4CR_MSEL15_0), \
+- PINMUX_DATA(TS_SPSYNC5_MARK, PORT275_FN3),
+- PINMUX_DATA(MMCD0_5_MARK, PORT276_FN1, PORT276_IN_PU,
+- MSEL4CR_MSEL15_0), \
+- PINMUX_DATA(TS_SDAT5_MARK, PORT276_FN3),
+- PINMUX_DATA(MMCD0_6_MARK, PORT277_FN1, PORT277_IN_PU,
+- MSEL4CR_MSEL15_0), \
+- PINMUX_DATA(TS_SDEN5_MARK, PORT277_FN3),
+- PINMUX_DATA(MMCD0_7_MARK, PORT278_FN1, PORT278_IN_PU,
+- MSEL4CR_MSEL15_0), \
+- PINMUX_DATA(TS_SCK5_MARK, PORT278_FN3),
+- PINMUX_DATA(MMCCMD0_MARK, PORT279_FN1, PORT279_IN_PU,
+- MSEL4CR_MSEL15_0),
+- PINMUX_DATA(RESETOUTS__MARK, PORT281_FN1), \
+- PINMUX_DATA(EXTAL2OUT_MARK, PORT281_FN2),
+- PINMUX_DATA(MCP_WAIT__MCP_FRB_MARK, PORT288_FN1),
+- PINMUX_DATA(MCP_CKO_MARK, PORT289_FN1), \
+- PINMUX_DATA(MMCCLK1_MARK, PORT289_FN2, MSEL4CR_MSEL15_1),
+- PINMUX_DATA(MCP_D15_MCP_NAF15_MARK, PORT290_FN1),
+- PINMUX_DATA(MCP_D14_MCP_NAF14_MARK, PORT291_FN1),
+- PINMUX_DATA(MCP_D13_MCP_NAF13_MARK, PORT292_FN1),
+- PINMUX_DATA(MCP_D12_MCP_NAF12_MARK, PORT293_FN1),
+- PINMUX_DATA(MCP_D11_MCP_NAF11_MARK, PORT294_FN1),
+- PINMUX_DATA(MCP_D10_MCP_NAF10_MARK, PORT295_FN1),
+- PINMUX_DATA(MCP_D9_MCP_NAF9_MARK, PORT296_FN1),
+- PINMUX_DATA(MCP_D8_MCP_NAF8_MARK, PORT297_FN1), \
+- PINMUX_DATA(MMCCMD1_MARK, PORT297_FN2, MSEL4CR_MSEL15_1),
+- PINMUX_DATA(MCP_D7_MCP_NAF7_MARK, PORT298_FN1), \
+- PINMUX_DATA(MMCD1_7_MARK, PORT298_FN2, MSEL4CR_MSEL15_1),
+-
+- PINMUX_DATA(MCP_D6_MCP_NAF6_MARK, PORT299_FN1), \
+- PINMUX_DATA(MMCD1_6_MARK, PORT299_FN2, MSEL4CR_MSEL15_1),
+- PINMUX_DATA(MCP_D5_MCP_NAF5_MARK, PORT300_FN1), \
+- PINMUX_DATA(MMCD1_5_MARK, PORT300_FN2, MSEL4CR_MSEL15_1),
+- PINMUX_DATA(MCP_D4_MCP_NAF4_MARK, PORT301_FN1), \
+- PINMUX_DATA(MMCD1_4_MARK, PORT301_FN2, MSEL4CR_MSEL15_1),
+- PINMUX_DATA(MCP_D3_MCP_NAF3_MARK, PORT302_FN1), \
+- PINMUX_DATA(MMCD1_3_MARK, PORT302_FN2, MSEL4CR_MSEL15_1),
+- PINMUX_DATA(MCP_D2_MCP_NAF2_MARK, PORT303_FN1), \
+- PINMUX_DATA(MMCD1_2_MARK, PORT303_FN2, MSEL4CR_MSEL15_1),
+- PINMUX_DATA(MCP_D1_MCP_NAF1_MARK, PORT304_FN1), \
+- PINMUX_DATA(MMCD1_1_MARK, PORT304_FN2, MSEL4CR_MSEL15_1),
+- PINMUX_DATA(MCP_D0_MCP_NAF0_MARK, PORT305_FN1), \
+- PINMUX_DATA(MMCD1_0_MARK, PORT305_FN2, MSEL4CR_MSEL15_1),
+- PINMUX_DATA(MCP_NBRSTOUT__MARK, PORT306_FN1),
+- PINMUX_DATA(MCP_WE0__MCP_FWE_MARK, PORT309_FN1), \
+- PINMUX_DATA(MCP_RDWR_MCP_FWE_MARK, PORT309_FN2),
+-
+- /* MSEL2 special cases */
+- PINMUX_DATA(TSIF2_TS_XX1_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0,
+- MSEL2CR_MSEL12_0),
+- PINMUX_DATA(TSIF2_TS_XX2_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0,
+- MSEL2CR_MSEL12_1),
+- PINMUX_DATA(TSIF2_TS_XX3_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1,
+- MSEL2CR_MSEL12_0),
+- PINMUX_DATA(TSIF2_TS_XX4_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1,
+- MSEL2CR_MSEL12_1),
+- PINMUX_DATA(TSIF2_TS_XX5_MARK, MSEL2CR_MSEL14_1, MSEL2CR_MSEL13_0,
+- MSEL2CR_MSEL12_0),
+- PINMUX_DATA(TSIF1_TS_XX1_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0,
+- MSEL2CR_MSEL9_0),
+- PINMUX_DATA(TSIF1_TS_XX2_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0,
+- MSEL2CR_MSEL9_1),
+- PINMUX_DATA(TSIF1_TS_XX3_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1,
+- MSEL2CR_MSEL9_0),
+- PINMUX_DATA(TSIF1_TS_XX4_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1,
+- MSEL2CR_MSEL9_1),
+- PINMUX_DATA(TSIF1_TS_XX5_MARK, MSEL2CR_MSEL11_1, MSEL2CR_MSEL10_0,
+- MSEL2CR_MSEL9_0),
+- PINMUX_DATA(TSIF0_TS_XX1_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0,
+- MSEL2CR_MSEL6_0),
+- PINMUX_DATA(TSIF0_TS_XX2_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0,
+- MSEL2CR_MSEL6_1),
+- PINMUX_DATA(TSIF0_TS_XX3_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1,
+- MSEL2CR_MSEL6_0),
+- PINMUX_DATA(TSIF0_TS_XX4_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1,
+- MSEL2CR_MSEL6_1),
+- PINMUX_DATA(TSIF0_TS_XX5_MARK, MSEL2CR_MSEL8_1, MSEL2CR_MSEL7_0,
+- MSEL2CR_MSEL6_0),
+- PINMUX_DATA(MST1_TS_XX1_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0,
+- MSEL2CR_MSEL3_0),
+- PINMUX_DATA(MST1_TS_XX2_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0,
+- MSEL2CR_MSEL3_1),
+- PINMUX_DATA(MST1_TS_XX3_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_1,
+- MSEL2CR_MSEL3_0),
+- PINMUX_DATA(MST1_TS_XX4_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_1,
+- MSEL2CR_MSEL3_1),
+- PINMUX_DATA(MST1_TS_XX5_MARK, MSEL2CR_MSEL5_1, MSEL2CR_MSEL4_0,
+- MSEL2CR_MSEL3_0),
+- PINMUX_DATA(MST0_TS_XX1_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_0,
+- MSEL2CR_MSEL0_0),
+- PINMUX_DATA(MST0_TS_XX2_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_0,
+- MSEL2CR_MSEL0_1),
+- PINMUX_DATA(MST0_TS_XX3_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_1,
+- MSEL2CR_MSEL0_0),
+- PINMUX_DATA(MST0_TS_XX4_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_1,
+- MSEL2CR_MSEL0_1),
+- PINMUX_DATA(MST0_TS_XX5_MARK, MSEL2CR_MSEL2_1, MSEL2CR_MSEL1_0,
+- MSEL2CR_MSEL0_0),
+-
+- /* MSEL3 special cases */
+- PINMUX_DATA(SDHI0_VCCQ_MC0_ON_MARK, MSEL3CR_MSEL28_1),
+- PINMUX_DATA(SDHI0_VCCQ_MC0_OFF_MARK, MSEL3CR_MSEL28_0),
+- PINMUX_DATA(DEBUG_MON_VIO_MARK, MSEL3CR_MSEL15_0),
+- PINMUX_DATA(DEBUG_MON_LCDD_MARK, MSEL3CR_MSEL15_1),
+- PINMUX_DATA(LCDC_LCDC0_MARK, MSEL3CR_MSEL6_0),
+- PINMUX_DATA(LCDC_LCDC1_MARK, MSEL3CR_MSEL6_1),
+-
+- /* MSEL4 special cases */
+- PINMUX_DATA(IRQ9_MEM_INT_MARK, MSEL4CR_MSEL29_0),
+- PINMUX_DATA(IRQ9_MCP_INT_MARK, MSEL4CR_MSEL29_1),
+- PINMUX_DATA(A11_MARK, MSEL4CR_MSEL13_0, MSEL4CR_MSEL12_0),
+- PINMUX_DATA(KEYOUT8_MARK, MSEL4CR_MSEL13_0, MSEL4CR_MSEL12_1),
+- PINMUX_DATA(TPU4TO3_MARK, MSEL4CR_MSEL13_1, MSEL4CR_MSEL12_0),
+- PINMUX_DATA(RESETA_N_PU_ON_MARK, MSEL4CR_MSEL4_0),
+- PINMUX_DATA(RESETA_N_PU_OFF_MARK, MSEL4CR_MSEL4_1),
+- PINMUX_DATA(EDBGREQ_PD_MARK, MSEL4CR_MSEL1_0),
+- PINMUX_DATA(EDBGREQ_PU_MARK, MSEL4CR_MSEL1_1),
+-
+- /* Functions with pull-ups */
+- PINMUX_DATA(KEYIN0_PU_MARK, PORT66_FN2, PORT66_IN_PU),
+- PINMUX_DATA(KEYIN1_PU_MARK, PORT67_FN2, PORT67_IN_PU),
+- PINMUX_DATA(KEYIN2_PU_MARK, PORT68_FN2, PORT68_IN_PU),
+- PINMUX_DATA(KEYIN3_PU_MARK, PORT69_FN2, PORT69_IN_PU),
+- PINMUX_DATA(KEYIN4_PU_MARK, PORT70_FN2, PORT70_IN_PU),
+- PINMUX_DATA(KEYIN5_PU_MARK, PORT71_FN2, PORT71_IN_PU),
+- PINMUX_DATA(KEYIN6_PU_MARK, PORT72_FN2, PORT72_IN_PU),
+- PINMUX_DATA(KEYIN7_PU_MARK, PORT73_FN2, PORT73_IN_PU),
+-
+- PINMUX_DATA(SDHICD0_PU_MARK, PORT251_FN1, PORT251_IN_PU),
+- PINMUX_DATA(SDHID0_0_PU_MARK, PORT252_FN1, PORT252_IN_PU),
+- PINMUX_DATA(SDHID0_1_PU_MARK, PORT253_FN1, PORT253_IN_PU),
+- PINMUX_DATA(SDHID0_2_PU_MARK, PORT254_FN1, PORT254_IN_PU),
+- PINMUX_DATA(SDHID0_3_PU_MARK, PORT255_FN1, PORT255_IN_PU),
+- PINMUX_DATA(SDHICMD0_PU_MARK, PORT256_FN1, PORT256_IN_PU),
+- PINMUX_DATA(SDHIWP0_PU_MARK, PORT257_FN1, PORT256_IN_PU),
+- PINMUX_DATA(SDHID1_0_PU_MARK, PORT259_FN1, PORT259_IN_PU),
+- PINMUX_DATA(SDHID1_1_PU_MARK, PORT260_FN1, PORT260_IN_PU),
+- PINMUX_DATA(SDHID1_2_PU_MARK, PORT261_FN1, PORT261_IN_PU),
+- PINMUX_DATA(SDHID1_3_PU_MARK, PORT262_FN1, PORT262_IN_PU),
+- PINMUX_DATA(SDHICMD1_PU_MARK, PORT263_FN1, PORT263_IN_PU),
+- PINMUX_DATA(SDHID2_0_PU_MARK, PORT265_FN1, PORT265_IN_PU),
+- PINMUX_DATA(SDHID2_1_PU_MARK, PORT266_FN1, PORT266_IN_PU),
+- PINMUX_DATA(SDHID2_2_PU_MARK, PORT267_FN1, PORT267_IN_PU),
+- PINMUX_DATA(SDHID2_3_PU_MARK, PORT268_FN1, PORT268_IN_PU),
+- PINMUX_DATA(SDHICMD2_PU_MARK, PORT269_FN1, PORT269_IN_PU),
+-
+- PINMUX_DATA(MMCCMD0_PU_MARK, PORT279_FN1, PORT279_IN_PU,
+- MSEL4CR_MSEL15_0),
+- PINMUX_DATA(MMCCMD1_PU_MARK, PORT297_FN2, PORT297_IN_PU,
+- MSEL4CR_MSEL15_1),
+-
+- PINMUX_DATA(MMCD0_0_PU_MARK,
+- PORT271_FN1, PORT271_IN_PU, MSEL4CR_MSEL15_0),
+- PINMUX_DATA(MMCD0_1_PU_MARK,
+- PORT272_FN1, PORT272_IN_PU, MSEL4CR_MSEL15_0),
+- PINMUX_DATA(MMCD0_2_PU_MARK,
+- PORT273_FN1, PORT273_IN_PU, MSEL4CR_MSEL15_0),
+- PINMUX_DATA(MMCD0_3_PU_MARK,
+- PORT274_FN1, PORT274_IN_PU, MSEL4CR_MSEL15_0),
+- PINMUX_DATA(MMCD0_4_PU_MARK,
+- PORT275_FN1, PORT275_IN_PU, MSEL4CR_MSEL15_0),
+- PINMUX_DATA(MMCD0_5_PU_MARK,
+- PORT276_FN1, PORT276_IN_PU, MSEL4CR_MSEL15_0),
+- PINMUX_DATA(MMCD0_6_PU_MARK,
+- PORT277_FN1, PORT277_IN_PU, MSEL4CR_MSEL15_0),
+- PINMUX_DATA(MMCD0_7_PU_MARK,
+- PORT278_FN1, PORT278_IN_PU, MSEL4CR_MSEL15_0),
+-
+- PINMUX_DATA(FSIBISLD_PU_MARK, PORT39_FN1, PORT39_IN_PU),
+- PINMUX_DATA(FSIACK_PU_MARK, PORT49_FN1, PORT49_IN_PU),
+- PINMUX_DATA(FSIAILR_PU_MARK, PORT50_FN5, PORT50_IN_PU),
+- PINMUX_DATA(FSIAIBT_PU_MARK, PORT51_FN5, PORT51_IN_PU),
+- PINMUX_DATA(FSIAISLD_PU_MARK, PORT55_FN1, PORT55_IN_PU),
+-};
+-
+-static struct pinmux_gpio pinmux_gpios[] = {
+- GPIO_PORT_ALL(),
+-
+- /* Table 25-1 (Functions 0-7) */
+- GPIO_FN(VBUS_0),
+- GPIO_FN(GPI0),
+- GPIO_FN(GPI1),
+- GPIO_FN(GPI2),
+- GPIO_FN(GPI3),
+- GPIO_FN(GPI4),
+- GPIO_FN(GPI5),
+- GPIO_FN(GPI6),
+- GPIO_FN(GPI7),
+- GPIO_FN(SCIFA7_RXD),
+- GPIO_FN(SCIFA7_CTS_),
+- GPIO_FN(GPO7), \
+- GPIO_FN(MFG0_OUT2),
+- GPIO_FN(GPO6), \
+- GPIO_FN(MFG1_OUT2),
+- GPIO_FN(GPO5), \
+- GPIO_FN(SCIFA0_SCK), \
+- GPIO_FN(FSICOSLDT3), \
+- GPIO_FN(PORT16_VIO_CKOR),
+- GPIO_FN(SCIFA0_TXD),
+- GPIO_FN(SCIFA7_TXD),
+- GPIO_FN(SCIFA7_RTS_), \
+- GPIO_FN(PORT19_VIO_CKO2),
+- GPIO_FN(GPO0),
+- GPIO_FN(GPO1),
+- GPIO_FN(GPO2), \
+- GPIO_FN(STATUS0),
+- GPIO_FN(GPO3), \
+- GPIO_FN(STATUS1),
+- GPIO_FN(GPO4), \
+- GPIO_FN(STATUS2),
+- GPIO_FN(VINT),
+- GPIO_FN(TCKON),
+- GPIO_FN(XDVFS1), \
+- GPIO_FN(PORT27_I2C_SCL2), \
+- GPIO_FN(PORT27_I2C_SCL3), \
+- GPIO_FN(MFG0_OUT1), \
+- GPIO_FN(PORT27_IROUT),
+- GPIO_FN(XDVFS2), \
+- GPIO_FN(PORT28_I2C_SDA2), \
+- GPIO_FN(PORT28_I2C_SDA3), \
+- GPIO_FN(PORT28_TPU1TO1),
+- GPIO_FN(SIM_RST), \
+- GPIO_FN(PORT29_TPU1TO1),
+- GPIO_FN(SIM_CLK), \
+- GPIO_FN(PORT30_VIO_CKOR),
+- GPIO_FN(SIM_D), \
+- GPIO_FN(PORT31_IROUT),
+- GPIO_FN(SCIFA4_TXD),
+- GPIO_FN(SCIFA4_RXD), \
+- GPIO_FN(XWUP),
+- GPIO_FN(SCIFA4_RTS_),
+- GPIO_FN(SCIFA4_CTS_),
+- GPIO_FN(FSIBOBT), \
+- GPIO_FN(FSIBIBT),
+- GPIO_FN(FSIBOLR), \
+- GPIO_FN(FSIBILR),
+- GPIO_FN(FSIBOSLD),
+- GPIO_FN(FSIBISLD),
+- GPIO_FN(VACK),
+- GPIO_FN(XTAL1L),
+- GPIO_FN(SCIFA0_RTS_), \
+- GPIO_FN(FSICOSLDT2),
+- GPIO_FN(SCIFA0_RXD),
+- GPIO_FN(SCIFA0_CTS_), \
+- GPIO_FN(FSICOSLDT1),
+- GPIO_FN(FSICOBT), \
+- GPIO_FN(FSICIBT), \
+- GPIO_FN(FSIDOBT), \
+- GPIO_FN(FSIDIBT),
+- GPIO_FN(FSICOLR), \
+- GPIO_FN(FSICILR), \
+- GPIO_FN(FSIDOLR), \
+- GPIO_FN(FSIDILR),
+- GPIO_FN(FSICOSLD), \
+- GPIO_FN(PORT47_FSICSPDIF),
+- GPIO_FN(FSICISLD), \
+- GPIO_FN(FSIDISLD),
+- GPIO_FN(FSIACK), \
+- GPIO_FN(PORT49_IRDA_OUT), \
+- GPIO_FN(PORT49_IROUT), \
+- GPIO_FN(FSIAOMC),
+- GPIO_FN(FSIAOLR), \
+- GPIO_FN(BBIF2_TSYNC2), \
+- GPIO_FN(TPU2TO2), \
+- GPIO_FN(FSIAILR),
+-
+- GPIO_FN(FSIAOBT), \
+- GPIO_FN(BBIF2_TSCK2), \
+- GPIO_FN(TPU2TO3), \
+- GPIO_FN(FSIAIBT),
+- GPIO_FN(FSIAOSLD), \
+- GPIO_FN(BBIF2_TXD2),
+- GPIO_FN(FSIASPDIF), \
+- GPIO_FN(PORT53_IRDA_IN), \
+- GPIO_FN(TPU3TO3), \
+- GPIO_FN(FSIBSPDIF), \
+- GPIO_FN(PORT53_FSICSPDIF),
+- GPIO_FN(FSIBCK), \
+- GPIO_FN(PORT54_IRDA_FIRSEL), \
+- GPIO_FN(TPU3TO2), \
+- GPIO_FN(FSIBOMC), \
+- GPIO_FN(FSICCK), \
+- GPIO_FN(FSICOMC),
+- GPIO_FN(FSIAISLD), \
+- GPIO_FN(TPU0TO0),
+- GPIO_FN(A0), \
+- GPIO_FN(BS_),
+- GPIO_FN(A12), \
+- GPIO_FN(PORT58_KEYOUT7), \
+- GPIO_FN(TPU4TO2),
+- GPIO_FN(A13), \
+- GPIO_FN(PORT59_KEYOUT6), \
+- GPIO_FN(TPU0TO1),
+- GPIO_FN(A14), \
+- GPIO_FN(KEYOUT5),
+- GPIO_FN(A15), \
+- GPIO_FN(KEYOUT4),
+- GPIO_FN(A16), \
+- GPIO_FN(KEYOUT3), \
+- GPIO_FN(MSIOF0_SS1),
+- GPIO_FN(A17), \
+- GPIO_FN(KEYOUT2), \
+- GPIO_FN(MSIOF0_TSYNC),
+- GPIO_FN(A18), \
+- GPIO_FN(KEYOUT1), \
+- GPIO_FN(MSIOF0_TSCK),
+- GPIO_FN(A19), \
+- GPIO_FN(KEYOUT0), \
+- GPIO_FN(MSIOF0_TXD),
+- GPIO_FN(A20), \
+- GPIO_FN(KEYIN0), \
+- GPIO_FN(MSIOF0_RSCK),
+- GPIO_FN(A21), \
+- GPIO_FN(KEYIN1), \
+- GPIO_FN(MSIOF0_RSYNC),
+- GPIO_FN(A22), \
+- GPIO_FN(KEYIN2), \
+- GPIO_FN(MSIOF0_MCK0),
+- GPIO_FN(A23), \
+- GPIO_FN(KEYIN3), \
+- GPIO_FN(MSIOF0_MCK1),
+- GPIO_FN(A24), \
+- GPIO_FN(KEYIN4), \
+- GPIO_FN(MSIOF0_RXD),
+- GPIO_FN(A25), \
+- GPIO_FN(KEYIN5), \
+- GPIO_FN(MSIOF0_SS2),
+- GPIO_FN(A26), \
+- GPIO_FN(KEYIN6),
+- GPIO_FN(KEYIN7),
+- GPIO_FN(D0_NAF0),
+- GPIO_FN(D1_NAF1),
+- GPIO_FN(D2_NAF2),
+- GPIO_FN(D3_NAF3),
+- GPIO_FN(D4_NAF4),
+- GPIO_FN(D5_NAF5),
+- GPIO_FN(D6_NAF6),
+- GPIO_FN(D7_NAF7),
+- GPIO_FN(D8_NAF8),
+- GPIO_FN(D9_NAF9),
+- GPIO_FN(D10_NAF10),
+- GPIO_FN(D11_NAF11),
+- GPIO_FN(D12_NAF12),
+- GPIO_FN(D13_NAF13),
+- GPIO_FN(D14_NAF14),
+- GPIO_FN(D15_NAF15),
+- GPIO_FN(CS4_),
+- GPIO_FN(CS5A_), \
+- GPIO_FN(PORT91_RDWR),
+- GPIO_FN(CS5B_), \
+- GPIO_FN(FCE1_),
+- GPIO_FN(CS6B_), \
+- GPIO_FN(DACK0),
+- GPIO_FN(FCE0_), \
+- GPIO_FN(CS6A_),
+- GPIO_FN(WAIT_), \
+- GPIO_FN(DREQ0),
+- GPIO_FN(RD__FSC),
+- GPIO_FN(WE0__FWE), \
+- GPIO_FN(RDWR_FWE),
+- GPIO_FN(WE1_),
+- GPIO_FN(FRB),
+- GPIO_FN(CKO),
+- GPIO_FN(NBRSTOUT_),
+- GPIO_FN(NBRST_),
+- GPIO_FN(BBIF2_TXD),
+- GPIO_FN(BBIF2_RXD),
+- GPIO_FN(BBIF2_SYNC),
+- GPIO_FN(BBIF2_SCK),
+- GPIO_FN(SCIFA3_CTS_), \
+- GPIO_FN(MFG3_IN2),
+- GPIO_FN(SCIFA3_RXD), \
+- GPIO_FN(MFG3_IN1),
+- GPIO_FN(BBIF1_SS2), \
+- GPIO_FN(SCIFA3_RTS_), \
+- GPIO_FN(MFG3_OUT1),
+- GPIO_FN(SCIFA3_TXD),
+- GPIO_FN(HSI_RX_DATA), \
+- GPIO_FN(BBIF1_RXD),
+- GPIO_FN(HSI_TX_WAKE), \
+- GPIO_FN(BBIF1_TSCK),
+- GPIO_FN(HSI_TX_DATA), \
+- GPIO_FN(BBIF1_TSYNC),
+- GPIO_FN(HSI_TX_READY), \
+- GPIO_FN(BBIF1_TXD),
+- GPIO_FN(HSI_RX_READY), \
+- GPIO_FN(BBIF1_RSCK), \
+- GPIO_FN(PORT115_I2C_SCL2), \
+- GPIO_FN(PORT115_I2C_SCL3),
+- GPIO_FN(HSI_RX_WAKE), \
+- GPIO_FN(BBIF1_RSYNC), \
+- GPIO_FN(PORT116_I2C_SDA2), \
+- GPIO_FN(PORT116_I2C_SDA3),
+- GPIO_FN(HSI_RX_FLAG), \
+- GPIO_FN(BBIF1_SS1), \
+- GPIO_FN(BBIF1_FLOW),
+- GPIO_FN(HSI_TX_FLAG),
+- GPIO_FN(VIO_VD), \
+- GPIO_FN(PORT128_LCD2VSYN), \
+- GPIO_FN(VIO2_VD), \
+- GPIO_FN(LCD2D0),
+-
+- GPIO_FN(VIO_HD), \
+- GPIO_FN(PORT129_LCD2HSYN), \
+- GPIO_FN(PORT129_LCD2CS_), \
+- GPIO_FN(VIO2_HD), \
+- GPIO_FN(LCD2D1),
+- GPIO_FN(VIO_D0), \
+- GPIO_FN(PORT130_MSIOF2_RXD), \
+- GPIO_FN(LCD2D10),
+- GPIO_FN(VIO_D1), \
+- GPIO_FN(PORT131_KEYOUT6), \
+- GPIO_FN(PORT131_MSIOF2_SS1), \
+- GPIO_FN(PORT131_KEYOUT11), \
+- GPIO_FN(LCD2D11),
+- GPIO_FN(VIO_D2), \
+- GPIO_FN(PORT132_KEYOUT7), \
+- GPIO_FN(PORT132_MSIOF2_SS2), \
+- GPIO_FN(PORT132_KEYOUT10), \
+- GPIO_FN(LCD2D12),
+- GPIO_FN(VIO_D3), \
+- GPIO_FN(MSIOF2_TSYNC), \
+- GPIO_FN(LCD2D13),
+- GPIO_FN(VIO_D4), \
+- GPIO_FN(MSIOF2_TXD), \
+- GPIO_FN(LCD2D14),
+- GPIO_FN(VIO_D5), \
+- GPIO_FN(MSIOF2_TSCK), \
+- GPIO_FN(LCD2D15),
+- GPIO_FN(VIO_D6), \
+- GPIO_FN(PORT136_KEYOUT8), \
+- GPIO_FN(LCD2D16),
+- GPIO_FN(VIO_D7), \
+- GPIO_FN(PORT137_KEYOUT9), \
+- GPIO_FN(LCD2D17),
+- GPIO_FN(VIO_D8), \
+- GPIO_FN(PORT138_KEYOUT8), \
+- GPIO_FN(VIO2_D0), \
+- GPIO_FN(LCD2D6),
+- GPIO_FN(VIO_D9), \
+- GPIO_FN(PORT139_KEYOUT9), \
+- GPIO_FN(VIO2_D1), \
+- GPIO_FN(LCD2D7),
+- GPIO_FN(VIO_D10), \
+- GPIO_FN(TPU0TO2), \
+- GPIO_FN(VIO2_D2), \
+- GPIO_FN(LCD2D8),
+- GPIO_FN(VIO_D11), \
+- GPIO_FN(TPU0TO3), \
+- GPIO_FN(VIO2_D3), \
+- GPIO_FN(LCD2D9),
+- GPIO_FN(VIO_D12), \
+- GPIO_FN(PORT142_KEYOUT10), \
+- GPIO_FN(VIO2_D4), \
+- GPIO_FN(LCD2D2),
+- GPIO_FN(VIO_D13), \
+- GPIO_FN(PORT143_KEYOUT11), \
+- GPIO_FN(PORT143_KEYOUT6), \
+- GPIO_FN(VIO2_D5), \
+- GPIO_FN(LCD2D3),
+- GPIO_FN(VIO_D14), \
+- GPIO_FN(PORT144_KEYOUT7), \
+- GPIO_FN(VIO2_D6), \
+- GPIO_FN(LCD2D4),
+- GPIO_FN(VIO_D15), \
+- GPIO_FN(TPU1TO3), \
+- GPIO_FN(PORT145_LCD2DISP), \
+- GPIO_FN(PORT145_LCD2RS), \
+- GPIO_FN(VIO2_D7), \
+- GPIO_FN(LCD2D5),
+- GPIO_FN(VIO_CLK), \
+- GPIO_FN(LCD2DCK), \
+- GPIO_FN(PORT146_LCD2WR_), \
+- GPIO_FN(VIO2_CLK), \
+- GPIO_FN(LCD2D18),
+- GPIO_FN(VIO_FIELD), \
+- GPIO_FN(LCD2RD_), \
+- GPIO_FN(VIO2_FIELD), \
+- GPIO_FN(LCD2D19),
+- GPIO_FN(VIO_CKO),
+- GPIO_FN(A27), \
+- GPIO_FN(PORT149_RDWR), \
+- GPIO_FN(MFG0_IN1), \
+- GPIO_FN(PORT149_KEYOUT9),
+- GPIO_FN(MFG0_IN2),
+- GPIO_FN(TS_SPSYNC3), \
+- GPIO_FN(MSIOF2_RSCK),
+- GPIO_FN(TS_SDAT3), \
+- GPIO_FN(MSIOF2_RSYNC),
+- GPIO_FN(TPU1TO2), \
+- GPIO_FN(TS_SDEN3), \
+- GPIO_FN(PORT153_MSIOF2_SS1),
+- GPIO_FN(SCIFA2_TXD1), \
+- GPIO_FN(MSIOF2_MCK0),
+- GPIO_FN(SCIFA2_RXD1), \
+- GPIO_FN(MSIOF2_MCK1),
+- GPIO_FN(SCIFA2_RTS1_), \
+- GPIO_FN(PORT156_MSIOF2_SS2),
+- GPIO_FN(SCIFA2_CTS1_), \
+- GPIO_FN(PORT157_MSIOF2_RXD),
+- GPIO_FN(DINT_), \
+- GPIO_FN(SCIFA2_SCK1), \
+- GPIO_FN(TS_SCK3),
+- GPIO_FN(PORT159_SCIFB_SCK), \
+- GPIO_FN(PORT159_SCIFA5_SCK), \
+- GPIO_FN(NMI),
+- GPIO_FN(PORT160_SCIFB_TXD), \
+- GPIO_FN(PORT160_SCIFA5_TXD),
+- GPIO_FN(PORT161_SCIFB_CTS_), \
+- GPIO_FN(PORT161_SCIFA5_CTS_),
+- GPIO_FN(PORT162_SCIFB_RXD), \
+- GPIO_FN(PORT162_SCIFA5_RXD),
+- GPIO_FN(PORT163_SCIFB_RTS_), \
+- GPIO_FN(PORT163_SCIFA5_RTS_), \
+- GPIO_FN(TPU3TO0),
+- GPIO_FN(LCDD0),
+- GPIO_FN(LCDD1), \
+- GPIO_FN(PORT193_SCIFA5_CTS_), \
+- GPIO_FN(BBIF2_TSYNC1),
+- GPIO_FN(LCDD2), \
+- GPIO_FN(PORT194_SCIFA5_RTS_), \
+- GPIO_FN(BBIF2_TSCK1),
+- GPIO_FN(LCDD3), \
+- GPIO_FN(PORT195_SCIFA5_RXD), \
+- GPIO_FN(BBIF2_TXD1),
+- GPIO_FN(LCDD4), \
+- GPIO_FN(PORT196_SCIFA5_TXD),
+- GPIO_FN(LCDD5), \
+- GPIO_FN(PORT197_SCIFA5_SCK), \
+- GPIO_FN(MFG2_OUT2), \
+- GPIO_FN(TPU2TO1),
+- GPIO_FN(LCDD6),
+- GPIO_FN(LCDD7), \
+- GPIO_FN(TPU4TO1), \
+- GPIO_FN(MFG4_OUT2),
+- GPIO_FN(LCDD8), \
+- GPIO_FN(D16),
+- GPIO_FN(LCDD9), \
+- GPIO_FN(D17),
+- GPIO_FN(LCDD10), \
+- GPIO_FN(D18),
+- GPIO_FN(LCDD11), \
+- GPIO_FN(D19),
+- GPIO_FN(LCDD12), \
+- GPIO_FN(D20),
+- GPIO_FN(LCDD13), \
+- GPIO_FN(D21),
+- GPIO_FN(LCDD14), \
+- GPIO_FN(D22),
+- GPIO_FN(LCDD15), \
+- GPIO_FN(PORT207_MSIOF0L_SS1), \
+- GPIO_FN(D23),
+- GPIO_FN(LCDD16), \
+- GPIO_FN(PORT208_MSIOF0L_SS2), \
+- GPIO_FN(D24),
+- GPIO_FN(LCDD17), \
+- GPIO_FN(D25),
+- GPIO_FN(LCDD18), \
+- GPIO_FN(DREQ2), \
+- GPIO_FN(PORT210_MSIOF0L_SS1), \
+- GPIO_FN(D26),
+- GPIO_FN(LCDD19), \
+- GPIO_FN(PORT211_MSIOF0L_SS2), \
+- GPIO_FN(D27),
+- GPIO_FN(LCDD20), \
+- GPIO_FN(TS_SPSYNC1), \
+- GPIO_FN(MSIOF0L_MCK0), \
+- GPIO_FN(D28),
+- GPIO_FN(LCDD21), \
+- GPIO_FN(TS_SDAT1), \
+- GPIO_FN(MSIOF0L_MCK1), \
+- GPIO_FN(D29),
+- GPIO_FN(LCDD22), \
+- GPIO_FN(TS_SDEN1), \
+- GPIO_FN(MSIOF0L_RSCK), \
+- GPIO_FN(D30),
+- GPIO_FN(LCDD23), \
+- GPIO_FN(TS_SCK1), \
+- GPIO_FN(MSIOF0L_RSYNC), \
+- GPIO_FN(D31),
+- GPIO_FN(LCDDCK), \
+- GPIO_FN(LCDWR_),
+- GPIO_FN(LCDRD_), \
+- GPIO_FN(DACK2), \
+- GPIO_FN(PORT217_LCD2RS), \
+- GPIO_FN(MSIOF0L_TSYNC), \
+- GPIO_FN(VIO2_FIELD3), \
+- GPIO_FN(PORT217_LCD2DISP),
+- GPIO_FN(LCDHSYN), \
+- GPIO_FN(LCDCS_), \
+- GPIO_FN(LCDCS2_), \
+- GPIO_FN(DACK3), \
+- GPIO_FN(PORT218_VIO_CKOR),
+- GPIO_FN(LCDDISP), \
+- GPIO_FN(LCDRS), \
+- GPIO_FN(PORT219_LCD2WR_), \
+- GPIO_FN(DREQ3), \
+- GPIO_FN(MSIOF0L_TSCK), \
+- GPIO_FN(VIO2_CLK3), \
+- GPIO_FN(LCD2DCK_2),
+- GPIO_FN(LCDVSYN), \
+- GPIO_FN(LCDVSYN2),
+- GPIO_FN(LCDLCLK), \
+- GPIO_FN(DREQ1), \
+- GPIO_FN(PORT221_LCD2CS_), \
+- GPIO_FN(PWEN), \
+- GPIO_FN(MSIOF0L_RXD), \
+- GPIO_FN(VIO2_HD3), \
+- GPIO_FN(PORT221_LCD2HSYN),
+- GPIO_FN(LCDDON), \
+- GPIO_FN(LCDDON2), \
+- GPIO_FN(DACK1), \
+- GPIO_FN(OVCN), \
+- GPIO_FN(MSIOF0L_TXD), \
+- GPIO_FN(VIO2_VD3), \
+- GPIO_FN(PORT222_LCD2VSYN),
+-
+- GPIO_FN(SCIFA1_TXD), \
+- GPIO_FN(OVCN2),
+- GPIO_FN(EXTLP), \
+- GPIO_FN(SCIFA1_SCK), \
+- GPIO_FN(PORT226_VIO_CKO2),
+- GPIO_FN(SCIFA1_RTS_), \
+- GPIO_FN(IDIN),
+- GPIO_FN(SCIFA1_RXD),
+- GPIO_FN(SCIFA1_CTS_), \
+- GPIO_FN(MFG1_IN1),
+- GPIO_FN(MSIOF1_TXD), \
+- GPIO_FN(SCIFA2_TXD2),
+- GPIO_FN(MSIOF1_TSYNC), \
+- GPIO_FN(SCIFA2_CTS2_),
+- GPIO_FN(MSIOF1_TSCK), \
+- GPIO_FN(SCIFA2_SCK2),
+- GPIO_FN(MSIOF1_RXD), \
+- GPIO_FN(SCIFA2_RXD2),
+- GPIO_FN(MSIOF1_RSCK), \
+- GPIO_FN(SCIFA2_RTS2_), \
+- GPIO_FN(VIO2_CLK2), \
+- GPIO_FN(LCD2D20),
+- GPIO_FN(MSIOF1_RSYNC), \
+- GPIO_FN(MFG1_IN2), \
+- GPIO_FN(VIO2_VD2), \
+- GPIO_FN(LCD2D21),
+- GPIO_FN(MSIOF1_MCK0), \
+- GPIO_FN(PORT236_I2C_SDA2),
+- GPIO_FN(MSIOF1_MCK1), \
+- GPIO_FN(PORT237_I2C_SCL2),
+- GPIO_FN(MSIOF1_SS1), \
+- GPIO_FN(VIO2_FIELD2), \
+- GPIO_FN(LCD2D22),
+- GPIO_FN(MSIOF1_SS2), \
+- GPIO_FN(VIO2_HD2), \
+- GPIO_FN(LCD2D23),
+- GPIO_FN(SCIFA6_TXD),
+- GPIO_FN(PORT241_IRDA_OUT), \
+- GPIO_FN(PORT241_IROUT), \
+- GPIO_FN(MFG4_OUT1), \
+- GPIO_FN(TPU4TO0),
+- GPIO_FN(PORT242_IRDA_IN), \
+- GPIO_FN(MFG4_IN2),
+- GPIO_FN(PORT243_IRDA_FIRSEL), \
+- GPIO_FN(PORT243_VIO_CKO2),
+- GPIO_FN(PORT244_SCIFA5_CTS_), \
+- GPIO_FN(MFG2_IN1), \
+- GPIO_FN(PORT244_SCIFB_CTS_), \
+- GPIO_FN(MSIOF2R_RXD),
+- GPIO_FN(PORT245_SCIFA5_RTS_), \
+- GPIO_FN(MFG2_IN2), \
+- GPIO_FN(PORT245_SCIFB_RTS_), \
+- GPIO_FN(MSIOF2R_TXD),
+- GPIO_FN(PORT246_SCIFA5_RXD), \
+- GPIO_FN(MFG1_OUT1), \
+- GPIO_FN(PORT246_SCIFB_RXD), \
+- GPIO_FN(TPU1TO0),
+- GPIO_FN(PORT247_SCIFA5_TXD), \
+- GPIO_FN(MFG3_OUT2), \
+- GPIO_FN(PORT247_SCIFB_TXD), \
+- GPIO_FN(TPU3TO1),
+- GPIO_FN(PORT248_SCIFA5_SCK), \
+- GPIO_FN(MFG2_OUT1), \
+- GPIO_FN(PORT248_SCIFB_SCK), \
+- GPIO_FN(TPU2TO0), \
+- GPIO_FN(PORT248_I2C_SCL3), \
+- GPIO_FN(MSIOF2R_TSCK),
+- GPIO_FN(PORT249_IROUT), \
+- GPIO_FN(MFG4_IN1), \
+- GPIO_FN(PORT249_I2C_SDA3), \
+- GPIO_FN(MSIOF2R_TSYNC),
+- GPIO_FN(SDHICLK0),
+- GPIO_FN(SDHICD0),
+- GPIO_FN(SDHID0_0),
+- GPIO_FN(SDHID0_1),
+- GPIO_FN(SDHID0_2),
+- GPIO_FN(SDHID0_3),
+- GPIO_FN(SDHICMD0),
+- GPIO_FN(SDHIWP0),
+- GPIO_FN(SDHICLK1),
+- GPIO_FN(SDHID1_0), \
+- GPIO_FN(TS_SPSYNC2),
+- GPIO_FN(SDHID1_1), \
+- GPIO_FN(TS_SDAT2),
+- GPIO_FN(SDHID1_2), \
+- GPIO_FN(TS_SDEN2),
+- GPIO_FN(SDHID1_3), \
+- GPIO_FN(TS_SCK2),
+- GPIO_FN(SDHICMD1),
+- GPIO_FN(SDHICLK2),
+- GPIO_FN(SDHID2_0), \
+- GPIO_FN(TS_SPSYNC4),
+- GPIO_FN(SDHID2_1), \
+- GPIO_FN(TS_SDAT4),
+- GPIO_FN(SDHID2_2), \
+- GPIO_FN(TS_SDEN4),
+- GPIO_FN(SDHID2_3), \
+- GPIO_FN(TS_SCK4),
+- GPIO_FN(SDHICMD2),
+- GPIO_FN(MMCCLK0),
+- GPIO_FN(MMCD0_0),
+- GPIO_FN(MMCD0_1),
+- GPIO_FN(MMCD0_2),
+- GPIO_FN(MMCD0_3),
+- GPIO_FN(MMCD0_4), \
+- GPIO_FN(TS_SPSYNC5),
+- GPIO_FN(MMCD0_5), \
+- GPIO_FN(TS_SDAT5),
+- GPIO_FN(MMCD0_6), \
+- GPIO_FN(TS_SDEN5),
+- GPIO_FN(MMCD0_7), \
+- GPIO_FN(TS_SCK5),
+- GPIO_FN(MMCCMD0),
+- GPIO_FN(RESETOUTS_), \
+- GPIO_FN(EXTAL2OUT),
+- GPIO_FN(MCP_WAIT__MCP_FRB),
+- GPIO_FN(MCP_CKO), \
+- GPIO_FN(MMCCLK1),
+- GPIO_FN(MCP_D15_MCP_NAF15),
+- GPIO_FN(MCP_D14_MCP_NAF14),
+- GPIO_FN(MCP_D13_MCP_NAF13),
+- GPIO_FN(MCP_D12_MCP_NAF12),
+- GPIO_FN(MCP_D11_MCP_NAF11),
+- GPIO_FN(MCP_D10_MCP_NAF10),
+- GPIO_FN(MCP_D9_MCP_NAF9),
+- GPIO_FN(MCP_D8_MCP_NAF8), \
+- GPIO_FN(MMCCMD1),
+- GPIO_FN(MCP_D7_MCP_NAF7), \
+- GPIO_FN(MMCD1_7),
+-
+- GPIO_FN(MCP_D6_MCP_NAF6), \
+- GPIO_FN(MMCD1_6),
+- GPIO_FN(MCP_D5_MCP_NAF5), \
+- GPIO_FN(MMCD1_5),
+- GPIO_FN(MCP_D4_MCP_NAF4), \
+- GPIO_FN(MMCD1_4),
+- GPIO_FN(MCP_D3_MCP_NAF3), \
+- GPIO_FN(MMCD1_3),
+- GPIO_FN(MCP_D2_MCP_NAF2), \
+- GPIO_FN(MMCD1_2),
+- GPIO_FN(MCP_D1_MCP_NAF1), \
+- GPIO_FN(MMCD1_1),
+- GPIO_FN(MCP_D0_MCP_NAF0), \
+- GPIO_FN(MMCD1_0),
+- GPIO_FN(MCP_NBRSTOUT_),
+- GPIO_FN(MCP_WE0__MCP_FWE), \
+- GPIO_FN(MCP_RDWR_MCP_FWE),
+-
+- /* MSEL2 special cases */
+- GPIO_FN(TSIF2_TS_XX1),
+- GPIO_FN(TSIF2_TS_XX2),
+- GPIO_FN(TSIF2_TS_XX3),
+- GPIO_FN(TSIF2_TS_XX4),
+- GPIO_FN(TSIF2_TS_XX5),
+- GPIO_FN(TSIF1_TS_XX1),
+- GPIO_FN(TSIF1_TS_XX2),
+- GPIO_FN(TSIF1_TS_XX3),
+- GPIO_FN(TSIF1_TS_XX4),
+- GPIO_FN(TSIF1_TS_XX5),
+- GPIO_FN(TSIF0_TS_XX1),
+- GPIO_FN(TSIF0_TS_XX2),
+- GPIO_FN(TSIF0_TS_XX3),
+- GPIO_FN(TSIF0_TS_XX4),
+- GPIO_FN(TSIF0_TS_XX5),
+- GPIO_FN(MST1_TS_XX1),
+- GPIO_FN(MST1_TS_XX2),
+- GPIO_FN(MST1_TS_XX3),
+- GPIO_FN(MST1_TS_XX4),
+- GPIO_FN(MST1_TS_XX5),
+- GPIO_FN(MST0_TS_XX1),
+- GPIO_FN(MST0_TS_XX2),
+- GPIO_FN(MST0_TS_XX3),
+- GPIO_FN(MST0_TS_XX4),
+- GPIO_FN(MST0_TS_XX5),
+-
+- /* MSEL3 special cases */
+- GPIO_FN(SDHI0_VCCQ_MC0_ON),
+- GPIO_FN(SDHI0_VCCQ_MC0_OFF),
+- GPIO_FN(DEBUG_MON_VIO),
+- GPIO_FN(DEBUG_MON_LCDD),
+- GPIO_FN(LCDC_LCDC0),
+- GPIO_FN(LCDC_LCDC1),
+-
+- /* MSEL4 special cases */
+- GPIO_FN(IRQ9_MEM_INT),
+- GPIO_FN(IRQ9_MCP_INT),
+- GPIO_FN(A11),
+- GPIO_FN(KEYOUT8),
+- GPIO_FN(TPU4TO3),
+- GPIO_FN(RESETA_N_PU_ON),
+- GPIO_FN(RESETA_N_PU_OFF),
+- GPIO_FN(EDBGREQ_PD),
+- GPIO_FN(EDBGREQ_PU),
+-
+- /* Functions with pull-ups */
+- GPIO_FN(KEYIN0_PU),
+- GPIO_FN(KEYIN1_PU),
+- GPIO_FN(KEYIN2_PU),
+- GPIO_FN(KEYIN3_PU),
+- GPIO_FN(KEYIN4_PU),
+- GPIO_FN(KEYIN5_PU),
+- GPIO_FN(KEYIN6_PU),
+- GPIO_FN(KEYIN7_PU),
+- GPIO_FN(SDHICD0_PU),
+- GPIO_FN(SDHID0_0_PU),
+- GPIO_FN(SDHID0_1_PU),
+- GPIO_FN(SDHID0_2_PU),
+- GPIO_FN(SDHID0_3_PU),
+- GPIO_FN(SDHICMD0_PU),
+- GPIO_FN(SDHIWP0_PU),
+- GPIO_FN(SDHID1_0_PU),
+- GPIO_FN(SDHID1_1_PU),
+- GPIO_FN(SDHID1_2_PU),
+- GPIO_FN(SDHID1_3_PU),
+- GPIO_FN(SDHICMD1_PU),
+- GPIO_FN(SDHID2_0_PU),
+- GPIO_FN(SDHID2_1_PU),
+- GPIO_FN(SDHID2_2_PU),
+- GPIO_FN(SDHID2_3_PU),
+- GPIO_FN(SDHICMD2_PU),
+- GPIO_FN(MMCCMD0_PU),
+- GPIO_FN(MMCCMD1_PU),
+- GPIO_FN(MMCD0_0_PU),
+- GPIO_FN(MMCD0_1_PU),
+- GPIO_FN(MMCD0_2_PU),
+- GPIO_FN(MMCD0_3_PU),
+- GPIO_FN(MMCD0_4_PU),
+- GPIO_FN(MMCD0_5_PU),
+- GPIO_FN(MMCD0_6_PU),
+- GPIO_FN(MMCD0_7_PU),
+- GPIO_FN(FSIACK_PU),
+- GPIO_FN(FSIAILR_PU),
+- GPIO_FN(FSIAIBT_PU),
+- GPIO_FN(FSIAISLD_PU),
+-};
+-
+-static struct pinmux_cfg_reg pinmux_config_regs[] = {
+- PORTCR(0, 0xe6050000), /* PORT0CR */
+- PORTCR(1, 0xe6050001), /* PORT1CR */
+- PORTCR(2, 0xe6050002), /* PORT2CR */
+- PORTCR(3, 0xe6050003), /* PORT3CR */
+- PORTCR(4, 0xe6050004), /* PORT4CR */
+- PORTCR(5, 0xe6050005), /* PORT5CR */
+- PORTCR(6, 0xe6050006), /* PORT6CR */
+- PORTCR(7, 0xe6050007), /* PORT7CR */
+- PORTCR(8, 0xe6050008), /* PORT8CR */
+- PORTCR(9, 0xe6050009), /* PORT9CR */
+-
+- PORTCR(10, 0xe605000a), /* PORT10CR */
+- PORTCR(11, 0xe605000b), /* PORT11CR */
+- PORTCR(12, 0xe605000c), /* PORT12CR */
+- PORTCR(13, 0xe605000d), /* PORT13CR */
+- PORTCR(14, 0xe605000e), /* PORT14CR */
+- PORTCR(15, 0xe605000f), /* PORT15CR */
+- PORTCR(16, 0xe6050010), /* PORT16CR */
+- PORTCR(17, 0xe6050011), /* PORT17CR */
+- PORTCR(18, 0xe6050012), /* PORT18CR */
+- PORTCR(19, 0xe6050013), /* PORT19CR */
+-
+- PORTCR(20, 0xe6050014), /* PORT20CR */
+- PORTCR(21, 0xe6050015), /* PORT21CR */
+- PORTCR(22, 0xe6050016), /* PORT22CR */
+- PORTCR(23, 0xe6050017), /* PORT23CR */
+- PORTCR(24, 0xe6050018), /* PORT24CR */
+- PORTCR(25, 0xe6050019), /* PORT25CR */
+- PORTCR(26, 0xe605001a), /* PORT26CR */
+- PORTCR(27, 0xe605001b), /* PORT27CR */
+- PORTCR(28, 0xe605001c), /* PORT28CR */
+- PORTCR(29, 0xe605001d), /* PORT29CR */
+-
+- PORTCR(30, 0xe605001e), /* PORT30CR */
+- PORTCR(31, 0xe605001f), /* PORT31CR */
+- PORTCR(32, 0xe6051020), /* PORT32CR */
+- PORTCR(33, 0xe6051021), /* PORT33CR */
+- PORTCR(34, 0xe6051022), /* PORT34CR */
+- PORTCR(35, 0xe6051023), /* PORT35CR */
+- PORTCR(36, 0xe6051024), /* PORT36CR */
+- PORTCR(37, 0xe6051025), /* PORT37CR */
+- PORTCR(38, 0xe6051026), /* PORT38CR */
+- PORTCR(39, 0xe6051027), /* PORT39CR */
+-
+- PORTCR(40, 0xe6051028), /* PORT40CR */
+- PORTCR(41, 0xe6051029), /* PORT41CR */
+- PORTCR(42, 0xe605102a), /* PORT42CR */
+- PORTCR(43, 0xe605102b), /* PORT43CR */
+- PORTCR(44, 0xe605102c), /* PORT44CR */
+- PORTCR(45, 0xe605102d), /* PORT45CR */
+- PORTCR(46, 0xe605102e), /* PORT46CR */
+- PORTCR(47, 0xe605102f), /* PORT47CR */
+- PORTCR(48, 0xe6051030), /* PORT48CR */
+- PORTCR(49, 0xe6051031), /* PORT49CR */
+-
+- PORTCR(50, 0xe6051032), /* PORT50CR */
+- PORTCR(51, 0xe6051033), /* PORT51CR */
+- PORTCR(52, 0xe6051034), /* PORT52CR */
+- PORTCR(53, 0xe6051035), /* PORT53CR */
+- PORTCR(54, 0xe6051036), /* PORT54CR */
+- PORTCR(55, 0xe6051037), /* PORT55CR */
+- PORTCR(56, 0xe6051038), /* PORT56CR */
+- PORTCR(57, 0xe6051039), /* PORT57CR */
+- PORTCR(58, 0xe605103a), /* PORT58CR */
+- PORTCR(59, 0xe605103b), /* PORT59CR */
+-
+- PORTCR(60, 0xe605103c), /* PORT60CR */
+- PORTCR(61, 0xe605103d), /* PORT61CR */
+- PORTCR(62, 0xe605103e), /* PORT62CR */
+- PORTCR(63, 0xe605103f), /* PORT63CR */
+- PORTCR(64, 0xe6051040), /* PORT64CR */
+- PORTCR(65, 0xe6051041), /* PORT65CR */
+- PORTCR(66, 0xe6051042), /* PORT66CR */
+- PORTCR(67, 0xe6051043), /* PORT67CR */
+- PORTCR(68, 0xe6051044), /* PORT68CR */
+- PORTCR(69, 0xe6051045), /* PORT69CR */
+-
+- PORTCR(70, 0xe6051046), /* PORT70CR */
+- PORTCR(71, 0xe6051047), /* PORT71CR */
+- PORTCR(72, 0xe6051048), /* PORT72CR */
+- PORTCR(73, 0xe6051049), /* PORT73CR */
+- PORTCR(74, 0xe605104a), /* PORT74CR */
+- PORTCR(75, 0xe605104b), /* PORT75CR */
+- PORTCR(76, 0xe605104c), /* PORT76CR */
+- PORTCR(77, 0xe605104d), /* PORT77CR */
+- PORTCR(78, 0xe605104e), /* PORT78CR */
+- PORTCR(79, 0xe605104f), /* PORT79CR */
+-
+- PORTCR(80, 0xe6051050), /* PORT80CR */
+- PORTCR(81, 0xe6051051), /* PORT81CR */
+- PORTCR(82, 0xe6051052), /* PORT82CR */
+- PORTCR(83, 0xe6051053), /* PORT83CR */
+- PORTCR(84, 0xe6051054), /* PORT84CR */
+- PORTCR(85, 0xe6051055), /* PORT85CR */
+- PORTCR(86, 0xe6051056), /* PORT86CR */
+- PORTCR(87, 0xe6051057), /* PORT87CR */
+- PORTCR(88, 0xe6051058), /* PORT88CR */
+- PORTCR(89, 0xe6051059), /* PORT89CR */
+-
+- PORTCR(90, 0xe605105a), /* PORT90CR */
+- PORTCR(91, 0xe605105b), /* PORT91CR */
+- PORTCR(92, 0xe605105c), /* PORT92CR */
+- PORTCR(93, 0xe605105d), /* PORT93CR */
+- PORTCR(94, 0xe605105e), /* PORT94CR */
+- PORTCR(95, 0xe605105f), /* PORT95CR */
+- PORTCR(96, 0xe6052060), /* PORT96CR */
+- PORTCR(97, 0xe6052061), /* PORT97CR */
+- PORTCR(98, 0xe6052062), /* PORT98CR */
+- PORTCR(99, 0xe6052063), /* PORT99CR */
+-
+- PORTCR(100, 0xe6052064), /* PORT100CR */
+- PORTCR(101, 0xe6052065), /* PORT101CR */
+- PORTCR(102, 0xe6052066), /* PORT102CR */
+- PORTCR(103, 0xe6052067), /* PORT103CR */
+- PORTCR(104, 0xe6052068), /* PORT104CR */
+- PORTCR(105, 0xe6052069), /* PORT105CR */
+- PORTCR(106, 0xe605206a), /* PORT106CR */
+- PORTCR(107, 0xe605206b), /* PORT107CR */
+- PORTCR(108, 0xe605206c), /* PORT108CR */
+- PORTCR(109, 0xe605206d), /* PORT109CR */
+-
+- PORTCR(110, 0xe605206e), /* PORT110CR */
+- PORTCR(111, 0xe605206f), /* PORT111CR */
+- PORTCR(112, 0xe6052070), /* PORT112CR */
+- PORTCR(113, 0xe6052071), /* PORT113CR */
+- PORTCR(114, 0xe6052072), /* PORT114CR */
+- PORTCR(115, 0xe6052073), /* PORT115CR */
+- PORTCR(116, 0xe6052074), /* PORT116CR */
+- PORTCR(117, 0xe6052075), /* PORT117CR */
+- PORTCR(118, 0xe6052076), /* PORT118CR */
+-
+- PORTCR(128, 0xe6052080), /* PORT128CR */
+- PORTCR(129, 0xe6052081), /* PORT129CR */
+-
+- PORTCR(130, 0xe6052082), /* PORT130CR */
+- PORTCR(131, 0xe6052083), /* PORT131CR */
+- PORTCR(132, 0xe6052084), /* PORT132CR */
+- PORTCR(133, 0xe6052085), /* PORT133CR */
+- PORTCR(134, 0xe6052086), /* PORT134CR */
+- PORTCR(135, 0xe6052087), /* PORT135CR */
+- PORTCR(136, 0xe6052088), /* PORT136CR */
+- PORTCR(137, 0xe6052089), /* PORT137CR */
+- PORTCR(138, 0xe605208a), /* PORT138CR */
+- PORTCR(139, 0xe605208b), /* PORT139CR */
+-
+- PORTCR(140, 0xe605208c), /* PORT140CR */
+- PORTCR(141, 0xe605208d), /* PORT141CR */
+- PORTCR(142, 0xe605208e), /* PORT142CR */
+- PORTCR(143, 0xe605208f), /* PORT143CR */
+- PORTCR(144, 0xe6052090), /* PORT144CR */
+- PORTCR(145, 0xe6052091), /* PORT145CR */
+- PORTCR(146, 0xe6052092), /* PORT146CR */
+- PORTCR(147, 0xe6052093), /* PORT147CR */
+- PORTCR(148, 0xe6052094), /* PORT148CR */
+- PORTCR(149, 0xe6052095), /* PORT149CR */
+-
+- PORTCR(150, 0xe6052096), /* PORT150CR */
+- PORTCR(151, 0xe6052097), /* PORT151CR */
+- PORTCR(152, 0xe6052098), /* PORT152CR */
+- PORTCR(153, 0xe6052099), /* PORT153CR */
+- PORTCR(154, 0xe605209a), /* PORT154CR */
+- PORTCR(155, 0xe605209b), /* PORT155CR */
+- PORTCR(156, 0xe605209c), /* PORT156CR */
+- PORTCR(157, 0xe605209d), /* PORT157CR */
+- PORTCR(158, 0xe605209e), /* PORT158CR */
+- PORTCR(159, 0xe605209f), /* PORT159CR */
+-
+- PORTCR(160, 0xe60520a0), /* PORT160CR */
+- PORTCR(161, 0xe60520a1), /* PORT161CR */
+- PORTCR(162, 0xe60520a2), /* PORT162CR */
+- PORTCR(163, 0xe60520a3), /* PORT163CR */
+- PORTCR(164, 0xe60520a4), /* PORT164CR */
+-
+- PORTCR(192, 0xe60520c0), /* PORT192CR */
+- PORTCR(193, 0xe60520c1), /* PORT193CR */
+- PORTCR(194, 0xe60520c2), /* PORT194CR */
+- PORTCR(195, 0xe60520c3), /* PORT195CR */
+- PORTCR(196, 0xe60520c4), /* PORT196CR */
+- PORTCR(197, 0xe60520c5), /* PORT197CR */
+- PORTCR(198, 0xe60520c6), /* PORT198CR */
+- PORTCR(199, 0xe60520c7), /* PORT199CR */
+-
+- PORTCR(200, 0xe60520c8), /* PORT200CR */
+- PORTCR(201, 0xe60520c9), /* PORT201CR */
+- PORTCR(202, 0xe60520ca), /* PORT202CR */
+- PORTCR(203, 0xe60520cb), /* PORT203CR */
+- PORTCR(204, 0xe60520cc), /* PORT204CR */
+- PORTCR(205, 0xe60520cd), /* PORT205CR */
+- PORTCR(206, 0xe60520ce), /* PORT206CR */
+- PORTCR(207, 0xe60520cf), /* PORT207CR */
+- PORTCR(208, 0xe60520d0), /* PORT208CR */
+- PORTCR(209, 0xe60520d1), /* PORT209CR */
+-
+- PORTCR(210, 0xe60520d2), /* PORT210CR */
+- PORTCR(211, 0xe60520d3), /* PORT211CR */
+- PORTCR(212, 0xe60520d4), /* PORT212CR */
+- PORTCR(213, 0xe60520d5), /* PORT213CR */
+- PORTCR(214, 0xe60520d6), /* PORT214CR */
+- PORTCR(215, 0xe60520d7), /* PORT215CR */
+- PORTCR(216, 0xe60520d8), /* PORT216CR */
+- PORTCR(217, 0xe60520d9), /* PORT217CR */
+- PORTCR(218, 0xe60520da), /* PORT218CR */
+- PORTCR(219, 0xe60520db), /* PORT219CR */
+-
+- PORTCR(220, 0xe60520dc), /* PORT220CR */
+- PORTCR(221, 0xe60520dd), /* PORT221CR */
+- PORTCR(222, 0xe60520de), /* PORT222CR */
+- PORTCR(223, 0xe60520df), /* PORT223CR */
+- PORTCR(224, 0xe60530e0), /* PORT224CR */
+- PORTCR(225, 0xe60530e1), /* PORT225CR */
+- PORTCR(226, 0xe60530e2), /* PORT226CR */
+- PORTCR(227, 0xe60530e3), /* PORT227CR */
+- PORTCR(228, 0xe60530e4), /* PORT228CR */
+- PORTCR(229, 0xe60530e5), /* PORT229CR */
+-
+- PORTCR(230, 0xe60530e6), /* PORT230CR */
+- PORTCR(231, 0xe60530e7), /* PORT231CR */
+- PORTCR(232, 0xe60530e8), /* PORT232CR */
+- PORTCR(233, 0xe60530e9), /* PORT233CR */
+- PORTCR(234, 0xe60530ea), /* PORT234CR */
+- PORTCR(235, 0xe60530eb), /* PORT235CR */
+- PORTCR(236, 0xe60530ec), /* PORT236CR */
+- PORTCR(237, 0xe60530ed), /* PORT237CR */
+- PORTCR(238, 0xe60530ee), /* PORT238CR */
+- PORTCR(239, 0xe60530ef), /* PORT239CR */
+-
+- PORTCR(240, 0xe60530f0), /* PORT240CR */
+- PORTCR(241, 0xe60530f1), /* PORT241CR */
+- PORTCR(242, 0xe60530f2), /* PORT242CR */
+- PORTCR(243, 0xe60530f3), /* PORT243CR */
+- PORTCR(244, 0xe60530f4), /* PORT244CR */
+- PORTCR(245, 0xe60530f5), /* PORT245CR */
+- PORTCR(246, 0xe60530f6), /* PORT246CR */
+- PORTCR(247, 0xe60530f7), /* PORT247CR */
+- PORTCR(248, 0xe60530f8), /* PORT248CR */
+- PORTCR(249, 0xe60530f9), /* PORT249CR */
+-
+- PORTCR(250, 0xe60530fa), /* PORT250CR */
+- PORTCR(251, 0xe60530fb), /* PORT251CR */
+- PORTCR(252, 0xe60530fc), /* PORT252CR */
+- PORTCR(253, 0xe60530fd), /* PORT253CR */
+- PORTCR(254, 0xe60530fe), /* PORT254CR */
+- PORTCR(255, 0xe60530ff), /* PORT255CR */
+- PORTCR(256, 0xe6053100), /* PORT256CR */
+- PORTCR(257, 0xe6053101), /* PORT257CR */
+- PORTCR(258, 0xe6053102), /* PORT258CR */
+- PORTCR(259, 0xe6053103), /* PORT259CR */
+-
+- PORTCR(260, 0xe6053104), /* PORT260CR */
+- PORTCR(261, 0xe6053105), /* PORT261CR */
+- PORTCR(262, 0xe6053106), /* PORT262CR */
+- PORTCR(263, 0xe6053107), /* PORT263CR */
+- PORTCR(264, 0xe6053108), /* PORT264CR */
+- PORTCR(265, 0xe6053109), /* PORT265CR */
+- PORTCR(266, 0xe605310a), /* PORT266CR */
+- PORTCR(267, 0xe605310b), /* PORT267CR */
+- PORTCR(268, 0xe605310c), /* PORT268CR */
+- PORTCR(269, 0xe605310d), /* PORT269CR */
+-
+- PORTCR(270, 0xe605310e), /* PORT270CR */
+- PORTCR(271, 0xe605310f), /* PORT271CR */
+- PORTCR(272, 0xe6053110), /* PORT272CR */
+- PORTCR(273, 0xe6053111), /* PORT273CR */
+- PORTCR(274, 0xe6053112), /* PORT274CR */
+- PORTCR(275, 0xe6053113), /* PORT275CR */
+- PORTCR(276, 0xe6053114), /* PORT276CR */
+- PORTCR(277, 0xe6053115), /* PORT277CR */
+- PORTCR(278, 0xe6053116), /* PORT278CR */
+- PORTCR(279, 0xe6053117), /* PORT279CR */
+-
+- PORTCR(280, 0xe6053118), /* PORT280CR */
+- PORTCR(281, 0xe6053119), /* PORT281CR */
+- PORTCR(282, 0xe605311a), /* PORT282CR */
+-
+- PORTCR(288, 0xe6052120), /* PORT288CR */
+- PORTCR(289, 0xe6052121), /* PORT289CR */
+-
+- PORTCR(290, 0xe6052122), /* PORT290CR */
+- PORTCR(291, 0xe6052123), /* PORT291CR */
+- PORTCR(292, 0xe6052124), /* PORT292CR */
+- PORTCR(293, 0xe6052125), /* PORT293CR */
+- PORTCR(294, 0xe6052126), /* PORT294CR */
+- PORTCR(295, 0xe6052127), /* PORT295CR */
+- PORTCR(296, 0xe6052128), /* PORT296CR */
+- PORTCR(297, 0xe6052129), /* PORT297CR */
+- PORTCR(298, 0xe605212a), /* PORT298CR */
+- PORTCR(299, 0xe605212b), /* PORT299CR */
+-
+- PORTCR(300, 0xe605212c), /* PORT300CR */
+- PORTCR(301, 0xe605212d), /* PORT301CR */
+- PORTCR(302, 0xe605212e), /* PORT302CR */
+- PORTCR(303, 0xe605212f), /* PORT303CR */
+- PORTCR(304, 0xe6052130), /* PORT304CR */
+- PORTCR(305, 0xe6052131), /* PORT305CR */
+- PORTCR(306, 0xe6052132), /* PORT306CR */
+- PORTCR(307, 0xe6052133), /* PORT307CR */
+- PORTCR(308, 0xe6052134), /* PORT308CR */
+- PORTCR(309, 0xe6052135), /* PORT309CR */
+-
+- { PINMUX_CFG_REG("MSEL2CR", 0xe605801c, 32, 1) {
+- 0, 0,
+- 0, 0,
+- 0, 0,
+- 0, 0,
+- 0, 0,
+- 0, 0,
+- 0, 0,
+- 0, 0,
+- 0, 0,
+- 0, 0,
+- 0, 0,
+- 0, 0,
+- MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1,
+- MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1,
+- MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1,
+- MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1,
+- 0, 0,
+- MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1,
+- MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1,
+- MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1,
+- MSEL2CR_MSEL11_0, MSEL2CR_MSEL11_1,
+- MSEL2CR_MSEL10_0, MSEL2CR_MSEL10_1,
+- MSEL2CR_MSEL9_0, MSEL2CR_MSEL9_1,
+- MSEL2CR_MSEL8_0, MSEL2CR_MSEL8_1,
+- MSEL2CR_MSEL7_0, MSEL2CR_MSEL7_1,
+- MSEL2CR_MSEL6_0, MSEL2CR_MSEL6_1,
+- MSEL2CR_MSEL5_0, MSEL2CR_MSEL5_1,
+- MSEL2CR_MSEL4_0, MSEL2CR_MSEL4_1,
+- MSEL2CR_MSEL3_0, MSEL2CR_MSEL3_1,
+- MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1,
+- MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1,
+- MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1,
+- }
+- },
+- { PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1) {
+- 0, 0,
+- 0, 0,
+- 0, 0,
+- MSEL3CR_MSEL28_0, MSEL3CR_MSEL28_1,
+- 0, 0,
+- 0, 0,
+- 0, 0,
+- 0, 0,
+- 0, 0,
+- 0, 0,
+- 0, 0,
+- 0, 0,
+- 0, 0,
+- 0, 0,
+- 0, 0,
+- 0, 0,
+- MSEL3CR_MSEL15_0, MSEL3CR_MSEL15_1,
+- 0, 0,
+- 0, 0,
+- 0, 0,
+- MSEL3CR_MSEL11_0, MSEL3CR_MSEL11_1,
+- 0, 0,
+- MSEL3CR_MSEL9_0, MSEL3CR_MSEL9_1,
+- 0, 0,
+- 0, 0,
+- MSEL3CR_MSEL6_0, MSEL3CR_MSEL6_1,
+- 0, 0,
+- 0, 0,
+- 0, 0,
+- MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1,
+- 0, 0,
+- 0, 0,
+- }
+- },
+- { PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1) {
+- 0, 0,
+- 0, 0,
+- MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1,
+- 0, 0,
+- MSEL4CR_MSEL27_0, MSEL4CR_MSEL27_1,
+- MSEL4CR_MSEL26_0, MSEL4CR_MSEL26_1,
+- 0, 0,
+- 0, 0,
+- 0, 0,
+- MSEL4CR_MSEL22_0, MSEL4CR_MSEL22_1,
+- MSEL4CR_MSEL21_0, MSEL4CR_MSEL21_1,
+- MSEL4CR_MSEL20_0, MSEL4CR_MSEL20_1,
+- MSEL4CR_MSEL19_0, MSEL4CR_MSEL19_1,
+- 0, 0,
+- 0, 0,
+- 0, 0,
+- MSEL4CR_MSEL15_0, MSEL4CR_MSEL15_1,
+- 0, 0,
+- MSEL4CR_MSEL13_0, MSEL4CR_MSEL13_1,
+- MSEL4CR_MSEL12_0, MSEL4CR_MSEL12_1,
+- MSEL4CR_MSEL11_0, MSEL4CR_MSEL11_1,
+- MSEL4CR_MSEL10_0, MSEL4CR_MSEL10_1,
+- MSEL4CR_MSEL9_0, MSEL4CR_MSEL9_1,
+- MSEL4CR_MSEL8_0, MSEL4CR_MSEL8_1,
+- MSEL4CR_MSEL7_0, MSEL4CR_MSEL7_1,
+- 0, 0,
+- 0, 0,
+- MSEL4CR_MSEL4_0, MSEL4CR_MSEL4_1,
+- 0, 0,
+- 0, 0,
+- MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1,
+- 0, 0,
+- }
+- },
+- { },
+-};
+-
+-static struct pinmux_data_reg pinmux_data_regs[] = {
+- { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) {
+- PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
+- PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
+- PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
+- PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
+- PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
+- PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
+- PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
+- PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA }
+- },
+- { PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32) {
+- PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
+- PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
+- PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
+- PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
+- PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
+- PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
+- PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
+- PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA }
+- },
+- { PINMUX_DATA_REG("PORTD095_064DR", 0xe6055004, 32) {
+- PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
+- PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
+- PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
+- PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
+- PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
+- PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
+- PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
+- PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA }
+- },
+- { PINMUX_DATA_REG("PORTR127_096DR", 0xe6056000, 32) {
+- 0, 0, 0, 0,
+- 0, 0, 0, 0,
+- 0, PORT118_DATA, PORT117_DATA, PORT116_DATA,
+- PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
+- PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
+- PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
+- PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
+- PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA }
+- },
+- { PINMUX_DATA_REG("PORTR159_128DR", 0xe6056004, 32) {
+- PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
+- PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
+- PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
+- PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
+- PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
+- PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
+- PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
+- PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA }
+- },
+- { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056008, 32) {
+- 0, 0, 0, 0,
+- 0, 0, 0, 0,
+- 0, 0, 0, 0,
+- 0, 0, 0, 0,
+- 0, 0, 0, 0,
+- 0, 0, 0, 0,
+- 0, 0, 0, PORT164_DATA,
+- PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA }
+- },
+- { PINMUX_DATA_REG("PORTR223_192DR", 0xe605600C, 32) {
+- PORT223_DATA, PORT222_DATA, PORT221_DATA, PORT220_DATA,
+- PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
+- PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
+- PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA,
+- PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
+- PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
+- PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
+- PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA }
+- },
+- { PINMUX_DATA_REG("PORTU255_224DR", 0xe6057000, 32) {
+- PORT255_DATA, PORT254_DATA, PORT253_DATA, PORT252_DATA,
+- PORT251_DATA, PORT250_DATA, PORT249_DATA, PORT248_DATA,
+- PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
+- PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA,
+- PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA,
+- PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
+- PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
+- PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA }
+- },
+- { PINMUX_DATA_REG("PORTU287_256DR", 0xe6057004, 32) {
+- 0, 0, 0, 0,
+- 0, PORT282_DATA, PORT281_DATA, PORT280_DATA,
+- PORT279_DATA, PORT278_DATA, PORT277_DATA, PORT276_DATA,
+- PORT275_DATA, PORT274_DATA, PORT273_DATA, PORT272_DATA,
+- PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA,
+- PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA,
+- PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
+- PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA }
+- },
+- { PINMUX_DATA_REG("PORTR319_288DR", 0xe6056010, 32) {
+- 0, 0, 0, 0,
+- 0, 0, 0, 0,
+- 0, 0, PORT309_DATA, PORT308_DATA,
+- PORT307_DATA, PORT306_DATA, PORT305_DATA, PORT304_DATA,
+- PORT303_DATA, PORT302_DATA, PORT301_DATA, PORT300_DATA,
+- PORT299_DATA, PORT298_DATA, PORT297_DATA, PORT296_DATA,
+- PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA,
+- PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA }
+- },
+- { },
+-};
+-
+-#if 0
+-/* IRQ pins through INTCS with IRQ0->15 from 0x200 and IRQ16-31 from 0x3200 */
+-#define EXT_IRQ16L(n) intcs_evt2irq(0x200 + ((n) << 5))
+-#define EXT_IRQ16H(n) intcs_evt2irq(0x3200 + ((n - 16) << 5))
+-#else
+-#define EXT_IRQ16L(n) (n)
+-#define EXT_IRQ16H(n) (n)
+-#endif
+-
+-static struct pinmux_irq pinmux_irqs[] = {
+- PINMUX_IRQ(EXT_IRQ16H(19), PORT9_FN0),
+- PINMUX_IRQ(EXT_IRQ16L(1), PORT10_FN0),
+- PINMUX_IRQ(EXT_IRQ16L(0), PORT11_FN0),
+- PINMUX_IRQ(EXT_IRQ16H(18), PORT13_FN0),
+- PINMUX_IRQ(EXT_IRQ16H(20), PORT14_FN0),
+- PINMUX_IRQ(EXT_IRQ16H(21), PORT15_FN0),
+- PINMUX_IRQ(EXT_IRQ16H(31), PORT26_FN0),
+- PINMUX_IRQ(EXT_IRQ16H(30), PORT27_FN0),
+- PINMUX_IRQ(EXT_IRQ16H(29), PORT28_FN0),
+- PINMUX_IRQ(EXT_IRQ16H(22), PORT40_FN0),
+- PINMUX_IRQ(EXT_IRQ16H(23), PORT53_FN0),
+- PINMUX_IRQ(EXT_IRQ16L(10), PORT54_FN0),
+- PINMUX_IRQ(EXT_IRQ16L(9), PORT56_FN0),
+- PINMUX_IRQ(EXT_IRQ16H(26), PORT115_FN0),
+- PINMUX_IRQ(EXT_IRQ16H(27), PORT116_FN0),
+- PINMUX_IRQ(EXT_IRQ16H(28), PORT117_FN0),
+- PINMUX_IRQ(EXT_IRQ16H(24), PORT118_FN0),
+- PINMUX_IRQ(EXT_IRQ16L(6), PORT147_FN0),
+- PINMUX_IRQ(EXT_IRQ16L(2), PORT149_FN0),
+- PINMUX_IRQ(EXT_IRQ16L(7), PORT150_FN0),
+- PINMUX_IRQ(EXT_IRQ16L(12), PORT156_FN0),
+- PINMUX_IRQ(EXT_IRQ16L(4), PORT159_FN0),
+- PINMUX_IRQ(EXT_IRQ16H(25), PORT164_FN0),
+- PINMUX_IRQ(EXT_IRQ16L(8), PORT223_FN0),
+- PINMUX_IRQ(EXT_IRQ16L(3), PORT224_FN0),
+- PINMUX_IRQ(EXT_IRQ16L(5), PORT227_FN0),
+- PINMUX_IRQ(EXT_IRQ16H(17), PORT234_FN0),
+- PINMUX_IRQ(EXT_IRQ16L(11), PORT238_FN0),
+- PINMUX_IRQ(EXT_IRQ16L(13), PORT239_FN0),
+- PINMUX_IRQ(EXT_IRQ16H(16), PORT249_FN0),
+- PINMUX_IRQ(EXT_IRQ16L(14), PORT251_FN0),
+- PINMUX_IRQ(EXT_IRQ16L(9), PORT308_FN0),
+-};
+-
+-static struct pinmux_info sh73a0_pinmux_info = {
+- .name = "sh73a0_pfc",
+- .reserved_id = PINMUX_RESERVED,
+- .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
+- .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
+- .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
+- .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
+- .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
+- .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
+- .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+-
+- .first_gpio = GPIO_PORT0,
+- .last_gpio = GPIO_FN_FSIAISLD_PU,
+-
+- .gpios = pinmux_gpios,
+- .cfg_regs = pinmux_config_regs,
+- .data_regs = pinmux_data_regs,
+-
+- .gpio_data = pinmux_data,
+- .gpio_data_size = ARRAY_SIZE(pinmux_data),
+-
+- .gpio_irq = pinmux_irqs,
+- .gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
+-};
+-
+-void sh73a0_pinmux_init(void)
+-{
+- register_pinmux(&sh73a0_pinmux_info);
+-}
+diff --git a/arch/arm/cpu/armv7/rmobile/timer.c b/arch/arm/cpu/armv7/rmobile/timer.c
+deleted file mode 100644
+index 37522dc..0000000
+--- a/arch/arm/cpu/armv7/rmobile/timer.c
++++ /dev/null
+@@ -1,97 +0,0 @@
+-/*
+- * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj at renesas.com>
+- * (C) Copyright 2012 Renesas Solutions Corp.
+- *
+- * See file CREDITS for list of people who contributed to this
+- * project.
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of
+- * the License, or (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+- * MA 02111-1307 USA
+- */
+-
+-#include <common.h>
+-#include <asm/io.h>
+-#include <asm/arch-armv7/globaltimer.h>
+-#include <asm/arch/rmobile.h>
+-
+-static struct globaltimer *global_timer = \
+- (struct globaltimer *)GLOBAL_TIMER_BASE_ADDR;
+-
+-#define CLK2MHZ(clk) (clk / 1000 / 1000)
+-static u64 get_cpu_global_timer(void)
+-{
+- u32 low, high;
+- u64 timer;
+-
+- u32 old = readl(&global_timer->cnt_h);
+- while (1) {
+- low = readl(&global_timer->cnt_l);
+- high = readl(&global_timer->cnt_h);
+- if (old == high)
+- break;
+- else
+- old = high;
+- }
+-
+- timer = high;
+- return (u64)((timer << 32) | low);
+-}
+-
+-static u64 get_time_us(void)
+-{
+- u64 timer = get_cpu_global_timer();
+-
+- timer = ((timer << 2) + (CLK2MHZ(CONFIG_SYS_CPU_CLK) >> 1));
+- timer /= (u64)CLK2MHZ(CONFIG_SYS_CPU_CLK);
+- return timer;
+-}
+-
+-static ulong get_time_ms(void)
+-{
+- return (ulong)(get_time_us() / 1000);
+-}
+-
+-int timer_init(void)
+-{
+- writel(0x01, &global_timer->ctl);
+- return 0;
+-}
+-
+-void __udelay(unsigned long usec)
+-{
+- u64 start, current;
+- u64 wait;
+-
+- start = get_cpu_global_timer();
+- wait = (u64)((usec * CLK2MHZ(CONFIG_SYS_CPU_CLK)) >> 2);
+- do {
+- current = get_cpu_global_timer();
+- } while ((current - start) < wait);
+-}
+-
+-ulong get_timer(ulong base)
+-{
+- return get_time_ms() - base;
+-}
+-
+-unsigned long long get_ticks(void)
+-{
+- return get_cpu_global_timer();
+-}
+-
+-ulong get_tbclk(void)
+-{
+- return (ulong)(CONFIG_SYS_CPU_CLK >> 2);
+-}
+diff --git a/arch/arm/cpu/armv7/socfpga/Makefile b/arch/arm/cpu/armv7/socfpga/Makefile
+deleted file mode 100644
+index 376a4bd..0000000
+--- a/arch/arm/cpu/armv7/socfpga/Makefile
++++ /dev/null
+@@ -1,51 +0,0 @@
+-#
+-# (C) Copyright 2000-2003
+-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+-#
+-# Copyright (C) 2012 Altera Corporation <www.altera.com>
+-#
+-# See file CREDITS for list of people who contributed to this
+-# project.
+-#
+-# This program is free software; you can redistribute it and/or
+-# modify it under the terms of the GNU General Public License as
+-# published by the Free Software Foundation; either version 2 of
+-# the License, or (at your option) any later version.
+-#
+-# This program is distributed in the hope that it will be useful,
+-# but WITHOUT ANY WARRANTY; without even the implied warranty of
+-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-# GNU General Public License for more details.
+-#
+-# You should have received a copy of the GNU General Public License
+-# along with this program; if not, write to the Free Software
+-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+-# MA 02111-1307 USA
+-#
+-
+-
+-include $(TOPDIR)/config.mk
+-
+-LIB = $(obj)lib$(SOC).o
+-
+-SOBJS := lowlevel_init.o
+-COBJS-y := misc.o timer.o
+-COBJS-$(CONFIG_SPL_BUILD) += spl.o
+-
+-COBJS := $(COBJS-y)
+-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+-OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+-
+-all: $(obj).depend $(LIB)
+-
+-$(LIB): $(OBJS)
+- $(call cmd_link_o_target, $(OBJS))
+-
+-#########################################################################
+-
+-# defines $(obj).depend target
+-include $(SRCTREE)/rules.mk
+-
+-sinclude $(obj).depend
+-
+-#########################################################################
+diff --git a/arch/arm/cpu/armv7/socfpga/config.mk b/arch/arm/cpu/armv7/socfpga/config.mk
+deleted file mode 100644
+index b72ed1e..0000000
+--- a/arch/arm/cpu/armv7/socfpga/config.mk
++++ /dev/null
+@@ -1,16 +0,0 @@
+-#
+-# Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+-#
+-# This program is free software; you can redistribute it and/or
+-# modify it under the terms of the GNU General Public License as
+-# published by the Free Software Foundation; either version 2 of
+-# the License, or (at your option) any later version.
+-#
+-# This program is distributed "as is" WITHOUT ANY WARRANTY of any
+-# kind, whether express or implied; without even the implied warranty
+-# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-# GNU General Public License for more details.
+-#
+-ifndef CONFIG_SPL_BUILD
+-ALL-y += $(obj)u-boot.img
+-endif
+diff --git a/arch/arm/cpu/armv7/socfpga/lowlevel_init.S b/arch/arm/cpu/armv7/socfpga/lowlevel_init.S
+deleted file mode 100644
+index 001b37d..0000000
+--- a/arch/arm/cpu/armv7/socfpga/lowlevel_init.S
++++ /dev/null
+@@ -1,77 +0,0 @@
+-/*
+- * Copyright (C) 2012 Altera Corporation <www.altera.com>
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+- */
+-
+-#include <config.h>
+-#include <version.h>
+-
+-/* Save the parameter pass in by previous boot loader */
+-.global save_boot_params
+-save_boot_params:
+- /* save the parameter here */
+-
+- /*
+- * Setup stack for exception, which is located
+- * at the end of on-chip RAM. We don't expect exception prior to
+- * relocation and if that happens, we won't worry -- it will overide
+- * global data region as the code will goto reset. After relocation,
+- * this region won't be used by other part of program.
+- * Hence it is safe.
+- */
+- ldr r0, =(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
+- ldr r1, =IRQ_STACK_START_IN
+- str r0, [r1]
+-
+- bx lr
+-
+-
+-/* Set up the platform, once the cpu has been initialized */
+-.globl lowlevel_init
+-lowlevel_init:
+-
+- /* Remap */
+-#ifdef CONFIG_SPL_BUILD
+- /*
+- * SPL : configure the remap (L3 NIC-301 GPV)
+- * so the on-chip RAM at lower memory instead ROM.
+- */
+- ldr r0, =SOCFPGA_L3REGS_ADDRESS
+- mov r1, #0x19
+- str r1, [r0]
+-#else
+- /*
+- * U-Boot : configure the remap (L3 NIC-301 GPV)
+- * so the SDRAM at lower memory instead on-chip RAM.
+- */
+- ldr r0, =SOCFPGA_L3REGS_ADDRESS
+- mov r1, #0x2
+- str r1, [r0]
+-
+- /* Private components security */
+-
+- /*
+- * U-Boot : configure private timer, global timer and cpu
+- * component access as non secure for kernel stage (as required
+- * by kernel)
+- */
+- mrc p15,4,r0,c15,c0,0
+- add r1, r0, #0x54
+- ldr r2, [r1]
+- orr r2, r2, #0xff
+- orr r2, r2, #0xf00
+- str r2, [r1]
+-#endif /* #ifdef CONFIG_SPL_BUILD */
+- mov pc, lr
+diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c
+deleted file mode 100644
+index fa16424..0000000
+--- a/arch/arm/cpu/armv7/socfpga/misc.c
++++ /dev/null
+@@ -1,54 +0,0 @@
+-/*
+- * Copyright (C) 2012 Altera Corporation <www.altera.com>
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+- */
+-
+-#include <common.h>
+-#include <asm/io.h>
+-#include <asm/arch/reset_manager.h>
+-
+-DECLARE_GLOBAL_DATA_PTR;
+-
+-static const struct socfpga_reset_manager *reset_manager_base =
+- (void *)SOCFPGA_RSTMGR_ADDRESS;
+-
+-/*
+- * Write the reset manager register to cause reset
+- */
+-void reset_cpu(ulong addr)
+-{
+- /* request a warm reset */
+- writel(RSTMGR_CTRL_SWWARMRSTREQ_LSB, &reset_manager_base->ctrl);
+- /*
+- * infinite loop here as watchdog will trigger and reset
+- * the processor
+- */
+- while (1)
+- ;
+-}
+-
+-/*
+- * Release peripherals from reset based on handoff
+- */
+-void reset_deassert_peripherals_handoff(void)
+-{
+- writel(0, &reset_manager_base->per_mod_reset);
+-}
+-
+-int dram_init(void)
+-{
+- gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+- return 0;
+-}
+diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c
+deleted file mode 100644
+index 944238b..0000000
+--- a/arch/arm/cpu/armv7/socfpga/spl.c
++++ /dev/null
+@@ -1,48 +0,0 @@
+-/*
+- * Copyright (C) 2012 Altera Corporation <www.altera.com>
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+- */
+-
+-#include <common.h>
+-#include <asm/io.h>
+-#include <asm/u-boot.h>
+-#include <asm/utils.h>
+-#include <version.h>
+-#include <image.h>
+-#include <malloc.h>
+-#include <asm/arch/reset_manager.h>
+-#include <spl.h>
+-
+-DECLARE_GLOBAL_DATA_PTR;
+-
+-u32 spl_boot_device(void)
+-{
+- return BOOT_DEVICE_RAM;
+-}
+-
+-/*
+- * Board initialization after bss clearance
+- */
+-void spl_board_init(void)
+-{
+- /* init timer for enabling delay function */
+- timer_init();
+-
+- /* de-assert reset for peripherals and bridges based on handoff */
+- reset_deassert_peripherals_handoff();
+-
+- /* enable console uart printing */
+- preloader_console_init();
+-}
+diff --git a/arch/arm/cpu/armv7/socfpga/timer.c b/arch/arm/cpu/armv7/socfpga/timer.c
+deleted file mode 100644
+index 321e9b4..0000000
+--- a/arch/arm/cpu/armv7/socfpga/timer.c
++++ /dev/null
+@@ -1,104 +0,0 @@
+-/*
+- * Copyright (C) 2012 Altera Corporation <www.altera.com>
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+- */
+-
+-#include <common.h>
+-#include <asm/io.h>
+-#include <asm/arch/timer.h>
+-
+-DECLARE_GLOBAL_DATA_PTR;
+-
+-static const struct socfpga_timer *timer_base = (void *)CONFIG_SYS_TIMERBASE;
+-
+-/*
+- * Timer initialization
+- */
+-int timer_init(void)
+-{
+- writel(TIMER_LOAD_VAL, &timer_base->load_val);
+- writel(TIMER_LOAD_VAL, &timer_base->curr_val);
+- writel(readl(&timer_base->ctrl) | 0x3, &timer_base->ctrl);
+- return 0;
+-}
+-
+-static u32 read_timer(void)
+-{
+- return readl(&timer_base->curr_val);
+-}
+-
+-/*
+- * Delay x useconds
+- */
+-void __udelay(unsigned long usec)
+-{
+- unsigned long now, last;
+- /*
+- * get the tmo value based on timer clock speed
+- * tmo = delay required / period of timer clock
+- */
+- long tmo = usec * CONFIG_TIMER_CLOCK_KHZ / 1000;
+-
+- last = read_timer();
+- while (tmo > 0) {
+- now = read_timer();
+- if (last >= now)
+- /* normal mode (non roll) */
+- tmo -= last - now;
+- else
+- /* we have overflow of the count down timer */
+- tmo -= TIMER_LOAD_VAL - last + now;
+- last = now;
+- }
+-}
+-
+-/*
+- * Get the timer value
+- */
+-ulong get_timer(ulong base)
+-{
+- return get_timer_masked() - base;
+-}
+-
+-/*
+- * Timer : get the time difference
+- * Unit of tick is based on the CONFIG_SYS_HZ
+- */
+-ulong get_timer_masked(void)
+-{
+- /* current tick value */
+- ulong now = read_timer() / (CONFIG_TIMER_CLOCK_KHZ/CONFIG_SYS_HZ);
+- if (gd->lastinc >= now) {
+- /* normal mode (non roll) */
+- /* move stamp forward with absolute diff ticks */
+- gd->tbl += gd->lastinc - now;
+- } else {
+- /* we have overflow of the count down timer */
+- gd->tbl += TIMER_LOAD_VAL - gd->lastinc + now;
+- }
+- gd->lastinc = now;
+- return gd->tbl;
+-}
+-
+-/*
+- * Reset the timer
+- */
+-void reset_timer(void)
+-{
+- /* capture current decrementer value time */
+- gd->lastinc = read_timer() / (CONFIG_TIMER_CLOCK_KHZ/CONFIG_SYS_HZ);
+- /* start "advancing" time stamp from 0 */
+- gd->tbl = 0;
+-}
+diff --git a/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds b/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds
+deleted file mode 100644
+index 7cd409c..0000000
+--- a/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds
++++ /dev/null
+@@ -1,60 +0,0 @@
+-/*
+- * Copyright (C) 2012 Altera Corporation <www.altera.com>
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+- */
+-
+-MEMORY { .sdram : ORIGIN = (0), LENGTH = (0xffffffff) }
+-
+-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+-OUTPUT_ARCH(arm)
+-ENTRY(_start)
+-SECTIONS
+-{
+- . = 0x00000000;
+-
+- . = ALIGN(4);
+- .text :
+- {
+- arch/arm/cpu/armv7/start.o (.text)
+- *(.text*)
+- } >.sdram
+-
+- . = ALIGN(4);
+- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } >.sdram
+-
+- . = ALIGN(4);
+- .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sdram
+-
+- . = ALIGN(4);
+- __image_copy_end = .;
+- _end = .;
+-
+- .bss : {
+- . = ALIGN(4);
+- __bss_start = .;
+- *(.bss*)
+- . = ALIGN(4);
+- __bss_end__ = .;
+- } >.sdram
+-
+- . = ALIGN(8);
+- __malloc_start = .;
+- . = . + CONFIG_SPL_MALLOC_SIZE;
+- __malloc_end = .;
+-
+- . = . + CONFIG_SPL_STACK_SIZE;
+- . = ALIGN(8);
+- __stack_start = .;
+-}
+diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
+index 7df97c5..f26308d 100644
+--- a/arch/arm/cpu/armv7/start.S
++++ b/arch/arm/cpu/armv7/start.S
+@@ -360,7 +360,10 @@ ENTRY(cpu_init_crit)
+ * basic memory. Go here to bump up clock rate and handle
+ * wake up conditions.
+ */
+- b lowlevel_init @ go setup pll,mux,memory
++ mov ip, lr @ persevere link reg across call
++ bl lowlevel_init @ go setup pll,mux,memory
++ mov lr, ip @ restore link
++ mov pc, lr @ back to my caller
+ ENDPROC(cpu_init_crit)
+ #endif
+
+diff --git a/arch/arm/cpu/armv7/zynq/Makefile b/arch/arm/cpu/armv7/zynq/Makefile
+deleted file mode 100644
+index 499ace4..0000000
+--- a/arch/arm/cpu/armv7/zynq/Makefile
++++ /dev/null
+@@ -1,51 +0,0 @@
+-#
+-# (C) Copyright 2000-2003
+-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+-#
+-# (C) Copyright 2008
+-# Guennadi Liakhovetki, DENX Software Engineering, <lg at denx.de>
+-#
+-# See file CREDITS for list of people who contributed to this
+-# project.
+-#
+-# This program is free software; you can redistribute it and/or
+-# modify it under the terms of the GNU General Public License as
+-# published by the Free Software Foundation; either version 2 of
+-# the License, or (at your option) any later version.
+-#
+-# This program is distributed in the hope that it will be useful,
+-# but WITHOUT ANY WARRANTY; without even the implied warranty of
+-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-# GNU General Public License for more details.
+-#
+-# You should have received a copy of the GNU General Public License
+-# along with this program; if not, write to the Free Software
+-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+-# MA 02111-1307 USA
+-#
+-
+-include $(TOPDIR)/config.mk
+-
+-LIB = $(obj)lib$(SOC).o
+-
+-COBJS-y := timer.o
+-COBJS-y += cpu.o
+-
+-COBJS := $(COBJS-y)
+-
+-SRCS := $(COBJS:.o=.c)
+-OBJS := $(addprefix $(obj),$(COBJS))
+-
+-all: $(obj).depend $(LIB)
+-
+-$(LIB): $(OBJS)
+- $(call cmd_link_o_target, $(OBJS))
+-
+-#########################################################################
+-
+-# defines $(obj).depend target
+-include $(SRCTREE)/rules.mk
+-
+-sinclude $(obj).depend
+-
+-#########################################################################
+diff --git a/arch/arm/cpu/armv7/zynq/cpu.c b/arch/arm/cpu/armv7/zynq/cpu.c
+deleted file mode 100644
+index ab615cc..0000000
+--- a/arch/arm/cpu/armv7/zynq/cpu.c
++++ /dev/null
+@@ -1,31 +0,0 @@
+-/*
+- * Copyright (C) 2012 Michal Simek <monstr at monstr.eu>
+- * Copyright (C) 2012 Xilinx, Inc. All rights reserved.
+- *
+- * See file CREDITS for list of people who contributed to this
+- * project.
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of
+- * the License, or (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+- * MA 02111-1307 USA
+- */
+-#include <common.h>
+-
+-inline void lowlevel_init(void) {}
+-
+-void reset_cpu(ulong addr)
+-{
+- while (1)
+- ;
+-}
+diff --git a/arch/arm/cpu/armv7/zynq/timer.c b/arch/arm/cpu/armv7/zynq/timer.c
+deleted file mode 100644
+index 323e7b5..0000000
+--- a/arch/arm/cpu/armv7/zynq/timer.c
++++ /dev/null
+@@ -1,150 +0,0 @@
+-/*
+- * Copyright (C) 2012 Michal Simek <monstr at monstr.eu>
+- * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved.
+- *
+- * (C) Copyright 2008
+- * Guennadi Liakhovetki, DENX Software Engineering, <lg at denx.de>
+- *
+- * (C) Copyright 2004
+- * Philippe Robin, ARM Ltd. <philippe.robin at arm.com>
+- *
+- * (C) Copyright 2002-2004
+- * Gary Jennejohn, DENX Software Engineering, <gj at denx.de>
+- *
+- * (C) Copyright 2003
+- * Texas Instruments <www.ti.com>
+- *
+- * (C) Copyright 2002
+- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+- * Marius Groeger <mgroeger at sysgo.de>
+- *
+- * (C) Copyright 2002
+- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+- * Alex Zuepke <azu at sysgo.de>
+- *
+- * See file CREDITS for list of people who contributed to this
+- * project.
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of
+- * the License, or (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+- * MA 02111-1307 USA
+- */
+-
+-#include <common.h>
+-#include <div64.h>
+-#include <asm/io.h>
+-
+-DECLARE_GLOBAL_DATA_PTR;
+-
+-struct scu_timer {
+- u32 load; /* Timer Load Register */
+- u32 counter; /* Timer Counter Register */
+- u32 control; /* Timer Control Register */
+-};
+-
+-static struct scu_timer *timer_base =
+- (struct scu_timer *) CONFIG_SCUTIMER_BASEADDR;
+-
+-#define SCUTIMER_CONTROL_PRESCALER_MASK 0x0000FF00 /* Prescaler */
+-#define SCUTIMER_CONTROL_PRESCALER_SHIFT 8
+-#define SCUTIMER_CONTROL_AUTO_RELOAD_MASK 0x00000002 /* Auto-reload */
+-#define SCUTIMER_CONTROL_ENABLE_MASK 0x00000001 /* Timer enable */
+-
+-#define TIMER_LOAD_VAL 0xFFFFFFFF
+-#define TIMER_PRESCALE 255
+-#define TIMER_TICK_HZ (CONFIG_CPU_FREQ_HZ / 2 / TIMER_PRESCALE)
+-
+-int timer_init(void)
+-{
+- const u32 emask = SCUTIMER_CONTROL_AUTO_RELOAD_MASK |
+- (TIMER_PRESCALE << SCUTIMER_CONTROL_PRESCALER_SHIFT) |
+- SCUTIMER_CONTROL_ENABLE_MASK;
+-
+- /* Load the timer counter register */
+- writel(0xFFFFFFFF, &timer_base->counter);
+-
+- /*
+- * Start the A9Timer device
+- * Enable Auto reload mode, Clear prescaler control bits
+- * Set prescaler value, Enable the decrementer
+- */
+- clrsetbits_le32(&timer_base->control, SCUTIMER_CONTROL_PRESCALER_MASK,
+- emask);
+-
+- /* Reset time */
+- gd->lastinc = readl(&timer_base->counter) /
+- (TIMER_TICK_HZ / CONFIG_SYS_HZ);
+- gd->tbl = 0;
+-
+- return 0;
+-}
+-
+-/*
+- * This function is derived from PowerPC code (read timebase as long long).
+- * On ARM it just returns the timer value.
+- */
+-ulong get_timer_masked(void)
+-{
+- ulong now;
+-
+- now = readl(&timer_base->counter) / (TIMER_TICK_HZ / CONFIG_SYS_HZ);
+-
+- if (gd->lastinc >= now) {
+- /* Normal mode */
+- gd->tbl += gd->lastinc - now;
+- } else {
+- /* We have an overflow ... */
+- gd->tbl += gd->lastinc + TIMER_LOAD_VAL - now;
+- }
+- gd->lastinc = now;
+-
+- return gd->tbl;
+-}
+-
+-void __udelay(unsigned long usec)
+-{
+- unsigned long long tmp;
+- ulong tmo;
+-
+- tmo = usec / (1000000 / CONFIG_SYS_HZ);
+- tmp = get_ticks() + tmo; /* Get current timestamp */
+-
+- while (get_ticks() < tmp) { /* Loop till event */
+- /* NOP */;
+- }
+-}
+-
+-/* Timer without interrupts */
+-ulong get_timer(ulong base)
+-{
+- return get_timer_masked() - base;
+-}
+-
+-/*
+- * This function is derived from PowerPC code (read timebase as long long).
+- * On ARM it just returns the timer value.
+- */
+-unsigned long long get_ticks(void)
+-{
+- return get_timer(0);
+-}
+-
+-/*
+- * This function is derived from PowerPC code (timebase clock frequency).
+- * On ARM it returns the number of timer ticks per second.
+- */
+-ulong get_tbclk(void)
+-{
+- return CONFIG_SYS_HZ;
+-}
+diff --git a/arch/arm/cpu/ixp/start.S b/arch/arm/cpu/ixp/start.S
+index c12f1a7..59c359a 100644
+--- a/arch/arm/cpu/ixp/start.S
++++ b/arch/arm/cpu/ixp/start.S
+@@ -273,7 +273,6 @@ stack_setup:
+
+ adr r0, _start
+ cmp r0, r6
+- moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
+ beq clear_bss /* skip relocation */
+ mov r1, r6 /* r1 <- scratch for copy_loop */
+ ldr r3, _bss_start_ofs
+diff --git a/arch/arm/cpu/lh7a40x/start.S b/arch/arm/cpu/lh7a40x/start.S
+index 33b9269..bd68cd4 100644
+--- a/arch/arm/cpu/lh7a40x/start.S
++++ b/arch/arm/cpu/lh7a40x/start.S
+@@ -184,7 +184,6 @@ stack_setup:
+
+ adr r0, _start
+ cmp r0, r6
+- moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
+ beq clear_bss /* skip relocation */
+ mov r1, r6 /* r1 <- scratch for copy_loop */
+ ldr r3, _bss_start_ofs
+diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S
+index 536cf5c..33c73f6 100644
+--- a/arch/arm/cpu/pxa/start.S
++++ b/arch/arm/cpu/pxa/start.S
+@@ -197,7 +197,6 @@ stack_setup:
+
+ adr r0, _start
+ cmp r0, r6
+- moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
+ beq clear_bss /* skip relocation */
+ mov r1, r6 /* r1 <- scratch for copy_loop */
+ ldr r3, _bss_start_ofs
+diff --git a/arch/arm/cpu/s3c44b0/start.S b/arch/arm/cpu/s3c44b0/start.S
+index 323b923..8daf26c 100644
+--- a/arch/arm/cpu/s3c44b0/start.S
++++ b/arch/arm/cpu/s3c44b0/start.S
+@@ -156,7 +156,6 @@ stack_setup:
+
+ adr r0, _start
+ cmp r0, r6
+- moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
+ beq clear_bss /* skip relocation */
+ mov r1, r6 /* r1 <- scratch for copy_loop */
+ ldr r3, _bss_start_ofs
+diff --git a/arch/arm/cpu/sa1100/start.S b/arch/arm/cpu/sa1100/start.S
+index 1ea92d1..bcea2a8 100644
+--- a/arch/arm/cpu/sa1100/start.S
++++ b/arch/arm/cpu/sa1100/start.S
+@@ -160,7 +160,6 @@ stack_setup:
+
+ adr r0, _start
+ cmp r0, r6
+- moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
+ beq clear_bss /* skip relocation */
+ mov r1, r6 /* r1 <- scratch for copy_loop */
+ ldr r3, _bss_start_ofs
+diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
+index b3e608e..410fb16 100644
+--- a/arch/arm/imx-common/Makefile
++++ b/arch/arm/imx-common/Makefile
+@@ -32,8 +32,9 @@ COBJS-y = iomux-v3.o timer.o cpu.o speed.o
+ COBJS-$(CONFIG_I2C_MXC) += i2c-mxv7.o
+ endif
+ COBJS-$(CONFIG_CMD_BMODE) += cmd_bmode.o
+-COBJS := $(sort $(COBJS-y))
++COBJS-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o
+
++COBJS := $(sort $(COBJS-y))
+ SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+ OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+diff --git a/arch/arm/imx-common/cmd_hdmidet.c b/arch/arm/imx-common/cmd_hdmidet.c
+new file mode 100644
+index 0000000..ede5d88
+--- /dev/null
++++ b/arch/arm/imx-common/cmd_hdmidet.c
+@@ -0,0 +1,37 @@
++/*
++ * Copyright (C) 2012 Boundary Devices Inc.
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++#include <common.h>
++#include <asm/arch/imx-regs.h>
++#include <asm/arch/mxc_hdmi.h>
++#include <asm/io.h>
++
++int do_hdmidet(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
++{
++ u8 reg = __raw_readb(HDMI_ARB_BASE_ADDR+HDMI_PHY_STAT0);
++ return (reg&HDMI_PHY_HPD)
++ ? 0 : 1;
++}
++
++U_BOOT_CMD(hdmidet, 1, 1, do_hdmidet,
++ "detect HDMI monitor",
++ ""
++);
+diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c
+index da093fb..fb797fe 100644
+--- a/arch/arm/imx-common/iomux-v3.c
++++ b/arch/arm/imx-common/iomux-v3.c
+@@ -54,7 +54,8 @@ int imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
+ return 0;
+ }
+
+-int imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count)
++int imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
++ unsigned count)
+ {
+ iomux_v3_cfg_t *p = pad_list;
+ int i;
+diff --git a/arch/arm/imx-common/speed.c b/arch/arm/imx-common/speed.c
+index 80989c4..fbf4de3 100644
+--- a/arch/arm/imx-common/speed.c
++++ b/arch/arm/imx-common/speed.c
+@@ -36,9 +36,25 @@ int get_clocks(void)
+ {
+ #ifdef CONFIG_FSL_ESDHC
+ #ifdef CONFIG_FSL_USDHC
++#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
++ gd->sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
++#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
++ gd->sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
++#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC4_BASE_ADDR
++ gd->sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
++#else
+ gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
++#endif
++#else
++#if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
++ gd->sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
++#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
++ gd->sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
++#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC4_BASE_ADDR
++ gd->sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+ #else
+- gd->sdhc_clk = mxc_get_clock(MXC_IPG_PERCLK);
++ gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
++#endif
+ #endif
+ #endif
+ return 0;
+diff --git a/arch/arm/imx-common/timer.c b/arch/arm/imx-common/timer.c
+index e2725e1..b021903 100644
+--- a/arch/arm/imx-common/timer.c
++++ b/arch/arm/imx-common/timer.c
+@@ -27,6 +27,7 @@
+ #include <asm/io.h>
+ #include <div64.h>
+ #include <asm/arch/imx-regs.h>
++#include <asm/arch/clock.h>
+
+ /* General purpose timers registers */
+ struct mxc_gpt {
+@@ -44,7 +45,6 @@ static struct mxc_gpt *cur_gpt = (struct mxc_gpt *)GPT1_BASE_ADDR;
+ #define GPTCR_FRR (1 << 9) /* Freerun / restart */
+ #define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source */
+ #define GPTCR_TEN 1 /* Timer enable */
+-#define CLK_32KHZ 32768 /* 32Khz input */
+
+ DECLARE_GLOBAL_DATA_PTR;
+
+@@ -54,14 +54,14 @@ DECLARE_GLOBAL_DATA_PTR;
+ static inline unsigned long long tick_to_time(unsigned long long tick)
+ {
+ tick *= CONFIG_SYS_HZ;
+- do_div(tick, CLK_32KHZ);
++ do_div(tick, MXC_CLK32);
+
+ return tick;
+ }
+
+ static inline unsigned long long us_to_tick(unsigned long long usec)
+ {
+- usec = usec * CLK_32KHZ + 999999;
++ usec = usec * MXC_CLK32 + 999999;
+ do_div(usec, 1000000);
+
+ return usec;
+@@ -86,7 +86,7 @@ int timer_init(void)
+ __raw_writel(i | GPTCR_CLKSOURCE_32 | GPTCR_TEN, &cur_gpt->control);
+
+ val = __raw_readl(&cur_gpt->counter);
+- lastinc = val / (CLK_32KHZ / CONFIG_SYS_HZ);
++ lastinc = val / (MXC_CLK32 / CONFIG_SYS_HZ);
+ timestamp = 0;
+
+ return 0;
+@@ -114,7 +114,7 @@ ulong get_timer_masked(void)
+ {
+ /*
+ * get_ticks() returns a long long (64 bit), it wraps in
+- * 2^64 / CONFIG_MX25_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
++ * 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
+ * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
+ * 5 * 10^6 days - long enough.
+ */
+@@ -145,5 +145,5 @@ void __udelay(unsigned long usec)
+ */
+ ulong get_tbclk(void)
+ {
+- return CLK_32KHZ;
++ return MXC_CLK32;
+ }
+diff --git a/arch/arm/include/asm/arch-am33xx/spl.h b/arch/arm/include/asm/arch-am33xx/spl.h
+index 63ed10b..70f521d 100644
+--- a/arch/arm/include/asm/arch-am33xx/spl.h
++++ b/arch/arm/include/asm/arch-am33xx/spl.h
+@@ -23,11 +23,9 @@
+ #ifndef _ASM_ARCH_SPL_H_
+ #define _ASM_SPL_H_
+
+-#define BOOT_DEVICE_XIP 2
+ #define BOOT_DEVICE_NAND 5
+ #define BOOT_DEVICE_MMC1 8
+ #define BOOT_DEVICE_MMC2 9 /* eMMC or daughter card */
+ #define BOOT_DEVICE_UART 65
+-#define BOOT_DEVICE_CPGMAC 70
+ #define BOOT_DEVICE_MMC2_2 0xFF
+ #endif
+diff --git a/arch/arm/include/asm/arch-armv7/globaltimer.h b/arch/arm/include/asm/arch-armv7/globaltimer.h
+deleted file mode 100644
+index 0ac70fd..0000000
+--- a/arch/arm/include/asm/arch-armv7/globaltimer.h
++++ /dev/null
+@@ -1,36 +0,0 @@
+-/*
+- * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj at renesas.com>
+- * (C) Copyright 2012 Renesas Solutions Corp.
+- *
+- * See file CREDITS for list of people who contributed to this
+- * project.
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of
+- * the License, or (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+- * MA 02111-1307 USA
+- */
+-#ifndef _GLOBALTIMER_H_
+-#define _GLOBALTIMER_H_
+-
+-struct globaltimer {
+- u32 cnt_l; /* 0x00 */
+- u32 cnt_h;
+- u32 ctl;
+- u32 stat;
+- u32 cmp_l; /* 0x10 */
+- u32 cmp_h;
+- u32 inc;
+-};
+-
+-#endif /* _GLOBALTIMER_H_ */
+diff --git a/arch/arm/include/asm/arch-kirkwood/cpu.h b/arch/arm/include/asm/arch-kirkwood/cpu.h
+index 57bfe8e..d28c51a 100644
+--- a/arch/arm/include/asm/arch-kirkwood/cpu.h
++++ b/arch/arm/include/asm/arch-kirkwood/cpu.h
+@@ -155,10 +155,10 @@ struct kwgpio_registers {
+ /*
+ * functions
+ */
++void reset_cpu(unsigned long ignored);
+ unsigned char get_random_hex(void);
+ unsigned int kw_sdram_bar(enum memory_bank bank);
+ unsigned int kw_sdram_bs(enum memory_bank bank);
+-void kw_sdram_size_adjust(enum memory_bank bank);
+ int kw_config_adr_windows(void);
+ void kw_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val,
+ unsigned int gpp0_oe, unsigned int gpp1_oe);
+diff --git a/arch/arm/include/asm/arch-kirkwood/mpp.h b/arch/arm/include/asm/arch-kirkwood/mpp.h
+index 8ceea7b..8e50ee7 100644
+--- a/arch/arm/include/asm/arch-kirkwood/mpp.h
++++ b/arch/arm/include/asm/arch-kirkwood/mpp.h
+@@ -85,7 +85,7 @@
+ #define MPP7_SPI_SCn MPP( 7, 0x2, 0, 1, 1, 1, 1, 1 )
+ #define MPP7_PTP_TRIG_GEN MPP( 7, 0x3, 0, 1, 1, 1, 1, 1 )
+
+-#define MPP8_GPIO MPP( 8, 0x0, 1, 1, 1, 1, 1, 1 )
++#define MPP8_GPIO MPP( 8, 0x0, 1, 1, 1, 1, 1, 1 )
+ #define MPP8_TW_SDA MPP( 8, 0x1, 1, 1, 1, 1, 1, 1 )
+ #define MPP8_UART0_RTS MPP( 8, 0x2, 0, 1, 1, 1, 1, 1 )
+ #define MPP8_UART1_RTS MPP( 8, 0x3, 0, 1, 1, 1, 1, 1 )
+diff --git a/arch/arm/include/asm/arch-mx25/clock.h b/arch/arm/include/asm/arch-mx25/clock.h
+index a313b80..efbe038 100644
+--- a/arch/arm/include/asm/arch-mx25/clock.h
++++ b/arch/arm/include/asm/arch-mx25/clock.h
+@@ -41,6 +41,7 @@
+ #endif
+
+ enum mxc_clock {
++ /* PER clocks (do not change order) */
+ MXC_CSI_CLK,
+ MXC_EPIT_CLK,
+ MXC_ESAI_CLK,
+@@ -57,17 +58,18 @@ enum mxc_clock {
+ MXC_SSI1_CLK,
+ MXC_SSI2_CLK,
+ MXC_UART_CLK,
++ /* Other clocks */
+ MXC_ARM_CLK,
++ MXC_AHB_CLK,
++ MXC_IPG_CLK,
++ MXC_CSPI_CLK,
+ MXC_FEC_CLK,
+ MXC_CLK_NUM
+ };
+
+-ulong imx_get_perclk(int clk);
+-ulong imx_get_ahbclk(void);
+-
+-#define imx_get_uartclk() imx_get_perclk(15)
+-#define imx_get_fecclk() (imx_get_ahbclk()/2)
+-
+ unsigned int mxc_get_clock(enum mxc_clock clk);
+
++#define imx_get_uartclk() mxc_get_clock(MXC_UART_CLK)
++#define imx_get_fecclk() mxc_get_clock(MXC_FEC_CLK)
++
+ #endif /* __ASM_ARCH_CLOCK_H */
+diff --git a/arch/arm/include/asm/arch-mx25/macro.h b/arch/arm/include/asm/arch-mx25/macro.h
+index 3b694da..56cae36 100644
+--- a/arch/arm/include/asm/arch-mx25/macro.h
++++ b/arch/arm/include/asm/arch-mx25/macro.h
+@@ -32,32 +32,75 @@
+
+ #include <asm/arch/imx-regs.h>
+ #include <generated/asm-offsets.h>
++#include <asm/macro.h>
+
+-.macro init_aips
+- write32 IMX_AIPS1_BASE + AIPS_MPR_0_7, 0x77777777
+- write32 IMX_AIPS1_BASE + AIPS_MPR_8_15, 0x77777777
+- write32 IMX_AIPS2_BASE + AIPS_MPR_0_7, 0x77777777
+- write32 IMX_AIPS2_BASE + AIPS_MPR_8_15, 0x77777777
++/*
++ * AIPS setup - Only setup MPROTx registers.
++ * The PACR default values are good.
++ *
++ * Default argument values:
++ * - MPR: Set all MPROTx to be non-bufferable, trusted for R/W, not forced to
++ * user-mode.
++ */
++.macro init_aips mpr=0x77777777
++ ldr r0, =IMX_AIPS1_BASE
++ ldr r1, =\mpr
++ str r1, [r0, #AIPS_MPR_0_7]
++ str r1, [r0, #AIPS_MPR_8_15]
++ ldr r2, =IMX_AIPS2_BASE
++ str r1, [r2, #AIPS_MPR_0_7]
++ str r1, [r2, #AIPS_MPR_8_15]
+ .endm
+
+-.macro init_max
+- write32 IMX_MAX_BASE + MAX_MPR0, 0x43210
+- write32 IMX_MAX_BASE + MAX_MPR1, 0x43210
+- write32 IMX_MAX_BASE + MAX_MPR2, 0x43210
+- write32 IMX_MAX_BASE + MAX_MPR3, 0x43210
+- write32 IMX_MAX_BASE + MAX_MPR4, 0x43210
+-
+- write32 IMX_MAX_BASE + MAX_SGPCR0, 0x10
+- write32 IMX_MAX_BASE + MAX_SGPCR1, 0x10
+- write32 IMX_MAX_BASE + MAX_SGPCR2, 0x10
+- write32 IMX_MAX_BASE + MAX_SGPCR3, 0x10
+- write32 IMX_MAX_BASE + MAX_SGPCR4, 0x10
++/*
++ * MAX (Multi-Layer AHB Crossbar Switch) setup
++ *
++ * Default argument values:
++ * - MPR: priority is IAHB > DAHB > USBOTG > RTIC > eSDHC2/SDMA
++ * - SGPCR: always park on last master
++ * - MGPCR: restore default values
++ */
++.macro init_max mpr=0x00043210, sgpcr=0x00000010, mgpcr=0x00000000
++ ldr r0, =IMX_MAX_BASE
++ ldr r1, =\mpr
++ str r1, [r0, #MAX_MPR0] /* for S0 */
++ str r1, [r0, #MAX_MPR1] /* for S1 */
++ str r1, [r0, #MAX_MPR2] /* for S2 */
++ str r1, [r0, #MAX_MPR3] /* for S3 */
++ str r1, [r0, #MAX_MPR4] /* for S4 */
++ ldr r1, =\sgpcr
++ str r1, [r0, #MAX_SGPCR0] /* for S0 */
++ str r1, [r0, #MAX_SGPCR1] /* for S1 */
++ str r1, [r0, #MAX_SGPCR2] /* for S2 */
++ str r1, [r0, #MAX_SGPCR3] /* for S3 */
++ str r1, [r0, #MAX_SGPCR4] /* for S4 */
++ ldr r1, =\mgpcr
++ str r1, [r0, #MAX_MGPCR0] /* for M0 */
++ str r1, [r0, #MAX_MGPCR1] /* for M1 */
++ str r1, [r0, #MAX_MGPCR2] /* for M2 */
++ str r1, [r0, #MAX_MGPCR3] /* for M3 */
++ str r1, [r0, #MAX_MGPCR4] /* for M4 */
++.endm
+
+- write32 IMX_MAX_BASE + MAX_MGPCR0, 0x0
+- write32 IMX_MAX_BASE + MAX_MGPCR1, 0x0
+- write32 IMX_MAX_BASE + MAX_MGPCR2, 0x0
+- write32 IMX_MAX_BASE + MAX_MGPCR3, 0x0
+- write32 IMX_MAX_BASE + MAX_MGPCR4, 0x0
++/*
++ * M3IF setup
++ *
++ * Default argument values:
++ * - CTL:
++ * MRRP[0] = LCDC on priority list (1 << 0) = 0x00000001
++ * MRRP[1] = MAX1 not on priority list (0 << 1) = 0x00000000
++ * MRRP[2] = MAX0 not on priority list (0 << 2) = 0x00000000
++ * MRRP[3] = USBH not on priority list (0 << 3) = 0x00000000
++ * MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000
++ * MRRP[5] = eSDHC1/ATA/FEC not on priority list (0 << 5) = 0x00000000
++ * MRRP[6] = LCDC/SLCDC/MAX2 not on priority list (0 << 6) = 0x00000000
++ * MRRP[7] = CSI not on priority list (0 << 7) = 0x00000000
++ * ------------
++ * 0x00000001
++ */
++.macro init_m3if ctl=0x00000001
++ /* M3IF Control Register (M3IFCTL) */
++ write32 IMX_M3IF_CTRL_BASE, \ctl
+ .endm
+
+ #endif /* __ASSEMBLY__ */
+diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h
+index 1dd952c..8fd3d08 100644
+--- a/arch/arm/include/asm/arch-mx31/imx-regs.h
++++ b/arch/arm/include/asm/arch-mx31/imx-regs.h
+@@ -569,7 +569,8 @@ struct esdc_regs {
+
+ #define MX31_IIM_BASE_ADDR 0x5001C000
+
+-#define PDR0_CSI_PODF(x) (((x) & 0x1ff) << 23)
++#define PDR0_CSI_PODF(x) (((x) & 0x3f) << 26)
++#define PDR0_CSI_PRDF(x) (((x) & 0x7) << 23)
+ #define PDR0_PER_PODF(x) (((x) & 0x1f) << 16)
+ #define PDR0_HSP_PODF(x) (((x) & 0x7) << 11)
+ #define PDR0_NFC_PODF(x) (((x) & 0x7) << 8)
+@@ -577,12 +578,23 @@ struct esdc_regs {
+ #define PDR0_MAX_PODF(x) (((x) & 0x7) << 3)
+ #define PDR0_MCU_PODF(x) ((x) & 0x7)
+
++#define PDR1_USB_PRDF(x) (((x) & 0x3) << 30)
++#define PDR1_USB_PODF(x) (((x) & 0x7) << 27)
++#define PDR1_FIRI_PRDF(x) (((x) & 0x7) << 24)
++#define PDR1_FIRI_PODF(x) (((x) & 0x3f) << 18)
++#define PDR1_SSI2_PRDF(x) (((x) & 0x7) << 15)
++#define PDR1_SSI2_PODF(x) (((x) & 0x3f) << 9)
++#define PDR1_SSI1_PRDF(x) (((x) & 0x7) << 6)
++#define PDR1_SSI1_PODF(x) ((x) & 0x3f)
++
++#define PLL_BRMO(x) (((x) & 0x1) << 31)
+ #define PLL_PD(x) (((x) & 0xf) << 26)
+ #define PLL_MFD(x) (((x) & 0x3ff) << 16)
+ #define PLL_MFI(x) (((x) & 0xf) << 10)
+ #define PLL_MFN(x) (((x) & 0x3ff) << 0)
+
+-#define GET_PDR0_CSI_PODF(x) (((x) >> 23) & 0x1ff)
++#define GET_PDR0_CSI_PODF(x) (((x) >> 26) & 0x3f)
++#define GET_PDR0_CSI_PRDF(x) (((x) >> 23) & 0x7)
+ #define GET_PDR0_PER_PODF(x) (((x) >> 16) & 0x1f)
+ #define GET_PDR0_HSP_PODF(x) (((x) >> 11) & 0x7)
+ #define GET_PDR0_NFC_PODF(x) (((x) >> 8) & 0x7)
+diff --git a/arch/arm/include/asm/arch-mx35/imx-regs.h b/arch/arm/include/asm/arch-mx35/imx-regs.h
+index 2c6e59c..7b09809 100644
+--- a/arch/arm/include/asm/arch-mx35/imx-regs.h
++++ b/arch/arm/include/asm/arch-mx35/imx-regs.h
+@@ -314,6 +314,58 @@ struct esdc_regs {
+ #define ESDC_MISC_DDR_EN (1 << 8)
+ #define ESDC_MISC_DDR2_EN (1 << 9)
+
++/* Multi-Layer AHB Crossbar Switch (MAX) registers */
++struct max_regs {
++ u32 mpr0;
++ u32 pad00[3];
++ u32 sgpcr0;
++ u32 pad01[59];
++ u32 mpr1;
++ u32 pad02[3];
++ u32 sgpcr1;
++ u32 pad03[59];
++ u32 mpr2;
++ u32 pad04[3];
++ u32 sgpcr2;
++ u32 pad05[59];
++ u32 mpr3;
++ u32 pad06[3];
++ u32 sgpcr3;
++ u32 pad07[59];
++ u32 mpr4;
++ u32 pad08[3];
++ u32 sgpcr4;
++ u32 pad09[251];
++ u32 mgpcr0;
++ u32 pad10[63];
++ u32 mgpcr1;
++ u32 pad11[63];
++ u32 mgpcr2;
++ u32 pad12[63];
++ u32 mgpcr3;
++ u32 pad13[63];
++ u32 mgpcr4;
++ u32 pad14[63];
++ u32 mgpcr5;
++};
++
++/* AHB <-> IP-Bus Interface (AIPS) */
++struct aips_regs {
++ u32 mpr_0_7;
++ u32 mpr_8_15;
++ u32 pad0[6];
++ u32 pacr_0_7;
++ u32 pacr_8_15;
++ u32 pacr_16_23;
++ u32 pacr_24_31;
++ u32 pad1[4];
++ u32 opacr_0_7;
++ u32 opacr_8_15;
++ u32 opacr_16_23;
++ u32 opacr_24_31;
++ u32 opacr_32_39;
++};
++
+ /*
+ * NFMS bit in RCSR register for pagesize of nandflash
+ */
+diff --git a/arch/arm/include/asm/arch-mx5/clock.h b/arch/arm/include/asm/arch-mx5/clock.h
+index 21febd8..9cdfb48 100644
+--- a/arch/arm/include/asm/arch-mx5/clock.h
++++ b/arch/arm/include/asm/arch-mx5/clock.h
+@@ -24,6 +24,20 @@
+ #ifndef __ASM_ARCH_CLOCK_H
+ #define __ASM_ARCH_CLOCK_H
+
++#include <common.h>
++
++#ifdef CONFIG_SYS_MX5_HCLK
++#define MXC_HCLK CONFIG_SYS_MX5_HCLK
++#else
++#define MXC_HCLK 24000000
++#endif
++
++#ifdef CONFIG_SYS_MX5_CLK32
++#define MXC_CLK32 CONFIG_SYS_MX5_CLK32
++#else
++#define MXC_CLK32 32768
++#endif
++
+ enum mxc_clock {
+ MXC_ARM_CLK = 0,
+ MXC_AHB_CLK,
+@@ -31,6 +45,10 @@ enum mxc_clock {
+ MXC_IPG_PERCLK,
+ MXC_UART_CLK,
+ MXC_CSPI_CLK,
++ MXC_ESDHC_CLK,
++ MXC_ESDHC2_CLK,
++ MXC_ESDHC3_CLK,
++ MXC_ESDHC4_CLK,
+ MXC_FEC_CLK,
+ MXC_SATA_CLK,
+ MXC_DDR_CLK,
+@@ -43,7 +61,8 @@ u32 imx_get_uartclk(void);
+ u32 imx_get_fecclk(void);
+ unsigned int mxc_get_clock(enum mxc_clock clk);
+ int mxc_set_clock(u32 ref, u32 freq, u32 clk_type);
+-void set_usb_phy2_clk(void);
++void set_usb_phy_clk(void);
++void enable_usb_phy1_clk(unsigned char enable);
+ void enable_usb_phy2_clk(unsigned char enable);
+ void set_usboh3_clk(void);
+ void enable_usboh3_clk(unsigned char enable);
+diff --git a/arch/arm/include/asm/arch-mx5/crm_regs.h b/arch/arm/include/asm/arch-mx5/crm_regs.h
+index 4e0fc1b..ddfab70 100644
+--- a/arch/arm/include/asm/arch-mx5/crm_regs.h
++++ b/arch/arm/include/asm/arch-mx5/crm_regs.h
+@@ -82,129 +82,526 @@ struct mxc_ccm_reg {
+ u32 cmeor;
+ };
+
++/* Define the bits in register CCR */
++#define MXC_CCM_CCR_COSC_EN (0x1 << 12)
++#if defined(CONFIG_MX51)
++#define MXC_CCM_CCR_FPM_MULT (0x1 << 11)
++#endif
++#define MXC_CCM_CCR_CAMP2_EN (0x1 << 10)
++#define MXC_CCM_CCR_CAMP1_EN (0x1 << 9)
++#if defined(CONFIG_MX51)
++#define MXC_CCM_CCR_FPM_EN (0x1 << 8)
++#endif
++#define MXC_CCM_CCR_OSCNT_OFFSET 0
++#define MXC_CCM_CCR_OSCNT_MASK 0xFF
++#define MXC_CCM_CCR_OSCNT(v) ((v) & 0xFF)
++#define MXC_CCM_CCR_OSCNT_RD(r) ((r) & 0xFF)
++
++/* Define the bits in register CCSR */
++#if defined(CONFIG_MX51)
++#define MXC_CCM_CCSR_LP_APM (0x1 << 9)
++#elif defined(CONFIG_MX53)
++#define MXC_CCM_CCSR_LP_APM (0x1 << 10)
++#define MXC_CCM_CCSR_PLL4_SW_CLK_SEL (0x1 << 9)
++#endif
++#define MXC_CCM_CCSR_STEP_SEL_OFFSET 7
++#define MXC_CCM_CCSR_STEP_SEL_MASK (0x3 << 7)
++#define MXC_CCM_CCSR_STEP_SEL(v) (((v) & 0x3) << 7)
++#define MXC_CCM_CCSR_STEP_SEL_RD(r) (((r) >> 7) & 0x3)
++#define MXC_CCM_CCSR_PLL2_DIV_PODF_OFFSET 5
++#define MXC_CCM_CCSR_PLL2_DIV_PODF_MASK (0x3 << 5)
++#define MXC_CCM_CCSR_PLL2_DIV_PODF(v) (((v) & 0x3) << 5)
++#define MXC_CCM_CCSR_PLL2_DIV_PODF_RD(r) (((r) >> 5) & 0x3)
++#define MXC_CCM_CCSR_PLL3_DIV_PODF_OFFSET 3
++#define MXC_CCM_CCSR_PLL3_DIV_PODF_MASK (0x3 << 3)
++#define MXC_CCM_CCSR_PLL3_DIV_PODF(v) (((v) & 0x3) << 3)
++#define MXC_CCM_CCSR_PLL3_DIV_PODF_RD(r) (((r) >> 3) & 0x3)
++#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (0x1 << 2)
++#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (0x1 << 1)
++#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL 0x1
++
+ /* Define the bits in register CACRR */
+ #define MXC_CCM_CACRR_ARM_PODF_OFFSET 0
+ #define MXC_CCM_CACRR_ARM_PODF_MASK 0x7
++#define MXC_CCM_CACRR_ARM_PODF(v) ((v) & 0x7)
++#define MXC_CCM_CACRR_ARM_PODF_RD(r) ((r) & 0x7)
+
+ /* Define the bits in register CBCDR */
+ #define MXC_CCM_CBCDR_DDR_HIFREQ_SEL (0x1 << 30)
+-#define MXC_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27)
+ #define MXC_CCM_CBCDR_DDR_PODF_OFFSET 27
++#define MXC_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27)
++#define MXC_CCM_CBCDR_DDR_PODF(v) (((v) & 0x7) << 27)
++#define MXC_CCM_CBCDR_DDR_PODF_RD(r) (((r) >> 27) & 0x7)
+ #define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26)
+ #define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25)
+ #define MXC_CCM_CBCDR_EMI_PODF_OFFSET 22
+ #define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22)
++#define MXC_CCM_CBCDR_EMI_PODF(v) (((v) & 0x7) << 22)
++#define MXC_CCM_CBCDR_EMI_PODF_RD(r) (((r) >> 22) & 0x7)
+ #define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET 19
+ #define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19)
++#define MXC_CCM_CBCDR_AXI_B_PODF(v) (((v) & 0x7) << 19)
++#define MXC_CCM_CBCDR_AXI_B_PODF_RD(r) (((r) >> 19) & 0x7)
+ #define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET 16
+ #define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16)
++#define MXC_CCM_CBCDR_AXI_A_PODF(v) (((v) & 0x7) << 16)
++#define MXC_CCM_CBCDR_AXI_A_PODF_RD(r) (((r) >> 16) & 0x7)
+ #define MXC_CCM_CBCDR_NFC_PODF_OFFSET 13
+ #define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13)
++#define MXC_CCM_CBCDR_NFC_PODF(v) (((v) & 0x7) << 13)
++#define MXC_CCM_CBCDR_NFC_PODF_RD(r) (((r) >> 13) & 0x7)
+ #define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10
+ #define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
++#define MXC_CCM_CBCDR_AHB_PODF(v) (((v) & 0x7) << 10)
++#define MXC_CCM_CBCDR_AHB_PODF_RD(r) (((r) >> 10) & 0x7)
+ #define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8
+ #define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8)
++#define MXC_CCM_CBCDR_IPG_PODF(v) (((v) & 0x3) << 8)
++#define MXC_CCM_CBCDR_IPG_PODF_RD(r) (((r) >> 8) & 0x3)
+ #define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET 6
+ #define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6)
++#define MXC_CCM_CBCDR_PERCLK_PRED1(v) (((v) & 0x3) << 6)
++#define MXC_CCM_CBCDR_PERCLK_PRED1_RD(r) (((r) >> 6) & 0x3)
+ #define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET 3
+ #define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3)
++#define MXC_CCM_CBCDR_PERCLK_PRED2(v) (((v) & 0x7) << 3)
++#define MXC_CCM_CBCDR_PERCLK_PRED2_RD(r) (((r) >> 3) & 0x7)
+ #define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET 0
+ #define MXC_CCM_CBCDR_PERCLK_PODF_MASK 0x7
++#define MXC_CCM_CBCDR_PERCLK_PODF(v) ((v) & 0x7)
++#define MXC_CCM_CBCDR_PERCLK_PODF_RD(r) ((r) & 0x7)
+
+ /* Define the bits in register CSCMR1 */
+ #define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET 30
+ #define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30)
++#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL(v) (((v) & 0x3) << 30)
++#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_RD(r) (((r) >> 30) & 0x3)
+ #define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET 28
+ #define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28)
+-#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET 26
++#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL(v) (((v) & 0x3) << 28)
++#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_RD(r) (((r) >> 28) & 0x3)
+ #define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26)
+ #define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET 24
+ #define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24)
++#define MXC_CCM_CSCMR1_UART_CLK_SEL(v) (((v) & 0x3) << 24)
++#define MXC_CCM_CSCMR1_UART_CLK_SEL_RD(r) (((r) >> 24) & 0x3)
+ #define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET 22
+ #define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22)
++#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL(v) (((v) & 0x3) << 22)
++#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_RD(r) (((r) >> 22) & 0x3)
+ #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET 20
+ #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20)
++#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL(v) (((v) & 0x3) << 20)
++#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_RD(r) (((r) >> 20) & 0x3)
+ #define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19)
+ #define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18)
+ #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET 16
+ #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16)
++#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL(v) (((v) & 0x3) << 16)
++#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_RD(r) (((r) >> 16) & 0x3)
+ #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 14
+ #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14)
++#define MXC_CCM_CSCMR1_SSI1_CLK_SEL(v) (((v) & 0x3) << 14)
++#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_RD(r) (((r) >> 14) & 0x3)
+ #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12
+ #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12)
++#define MXC_CCM_CSCMR1_SSI2_CLK_SEL(v) (((v) & 0x3) << 12)
++#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_RD(r) (((r) >> 12) & 0x3)
+ #define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11)
+ #define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10)
+ #define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET 8
+ #define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8)
++#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL(v) (((v) & 0x3) << 8)
++#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_RD(r) (((r) >> 8) & 0x3)
+ #define MXC_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7)
+ #define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6)
+ #define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET 4
+ #define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4)
++#define MXC_CCM_CSCMR1_CSPI_CLK_SEL(v) (((v) & 0x3) << 4)
++#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_RD(r) (((r) >> 4) & 0x3)
+ #define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET 2
+ #define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2)
++#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL(v) (((v) & 0x3) << 2)
++#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_RD(r) (((r) >> 2) & 0x3)
+ #define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1)
+ #define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL 0x1
+
+ /* Define the bits in register CSCDR2 */
+ #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET 25
+ #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25)
++#define MXC_CCM_CSCDR2_CSPI_CLK_PRED(v) (((v) & 0x7) << 25)
++#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_RD(r) (((r) >> 25) & 0x7)
+ #define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET 19
+ #define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19)
++#define MXC_CCM_CSCDR2_CSPI_CLK_PODF(v) (((v) & 0x3F) << 19)
++#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_RD(r) (((r) >> 19) & 0x3F)
+ #define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET 16
+ #define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16)
++#define MXC_CCM_CSCDR2_SIM_CLK_PRED(v) (((v) & 0x7) << 16)
++#define MXC_CCM_CSCDR2_SIM_CLK_PRED_RD(r) (((r) >> 16) & 0x7)
+ #define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET 9
+ #define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK (0x3F << 9)
++#define MXC_CCM_CSCDR2_SIM_CLK_PODF(v) (((v) & 0x3F) << 9)
++#define MXC_CCM_CSCDR2_SIM_CLK_PODF_RD(r) (((r) >> 9) & 0x3F)
+ #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET 6
+-#define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK (0x7 << 6)
+-#define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET 0
+-#define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK 0x3F
++#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_MASK (0x7 << 6)
++#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED(v) (((v) & 0x7) << 6)
++#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_RD(r) (((r) >> 6) & 0x7)
++#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_OFFSET 0
++#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_MASK 0x3F
++#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF(v) ((v) & 0x3F)
++#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_RD(r) ((r) & 0x3F)
+
+ /* Define the bits in register CBCMR */
+ #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14
+ #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14)
++#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL(v) (((v) & 0x3) << 14)
++#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_RD(r) (((r) >> 14) & 0x3)
+ #define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET 12
+ #define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12)
++#define MXC_CCM_CBCMR_PERIPH_CLK_SEL(v) (((v) & 0x3) << 12)
++#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(r) (((r) >> 12) & 0x3)
+ #define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET 10
+ #define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10)
++#define MXC_CCM_CBCMR_DDR_CLK_SEL(v) (((v) & 0x3) << 10)
++#define MXC_CCM_CBCMR_DDR_CLK_SEL_RD(r) (((r) >> 10) & 0x3)
+ #define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET 8
+ #define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8)
++#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL(v) (((v) & 0x3) << 8)
++#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_RD(r) (((r) >> 8) & 0x3)
+ #define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET 6
+ #define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6)
++#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL(v) (((v) & 0x3) << 6)
++#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_RD(r) (((r) >> 6) & 0x3)
+ #define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET 4
+ #define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4)
++#define MXC_CCM_CBCMR_GPU_CLK_SEL(v) (((v) & 0x3) << 4)
++#define MXC_CCM_CBCMR_GPU_CLK_SEL_RD(r) (((r) >> 4) & 0x3)
+ #define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1)
+ #define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0)
+
+ /* Define the bits in register CSCDR1 */
+ #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET 22
+ #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22)
++#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED(v) (((v) & 0x7) << 22)
++#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_RD(r) (((r) >> 22) & 0x7)
+ #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET 19
+ #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19)
++#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF(v) (((v) & 0x7) << 19)
++#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_RD(r) (((r) >> 19) & 0x7)
+ #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET 16
+ #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16)
++#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED(v) (((v) & 0x7) << 16)
++#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_RD(r) (((r) >> 16) & 0x7)
+ #define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET 14
+ #define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14)
++#define MXC_CCM_CSCDR1_PGC_CLK_PODF(v) (((v) & 0x3) << 14)
++#define MXC_CCM_CSCDR1_PGC_CLK_PODF_RD(r) (((r) >> 14) & 0x3)
+ #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET 11
+ #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11)
++#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF(v) (((v) & 0x7) << 11)
++#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_RD(r) (((r) >> 11) & 0x7)
+ #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8
+ #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8)
++#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED(v) (((v) & 0x7) << 8)
++#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_RD(r) (((r) >> 8) & 0x7)
+ #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6
+ #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
++#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF(v) (((v) & 0x3) << 6)
++#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_RD(r) (((r) >> 6) & 0x3)
+ #define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET 3
+ #define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3)
++#define MXC_CCM_CSCDR1_UART_CLK_PRED(v) (((v) & 0x7) << 3)
++#define MXC_CCM_CSCDR1_UART_CLK_PRED_RD(r) (((r) >> 3) & 0x7)
+ #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0
+ #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x7
++#define MXC_CCM_CSCDR1_UART_CLK_PODF(v) ((v) & 0x7)
++#define MXC_CCM_CSCDR1_UART_CLK_PODF_RD(r) ((r) & 0x7)
+
+ /* Define the bits in register CCDR */
+ #define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17)
+
+ /* Define the bits in register CCGRx */
+ #define MXC_CCM_CCGR_CG_MASK 0x3
++#define MXC_CCM_CCGR_CG_OFF 0x0
++#define MXC_CCM_CCGR_CG_RUN_ON 0x1
++#define MXC_CCM_CCGR_CG_ON 0x3
++
++#define MXC_CCM_CCGR0_ARM_BUS_OFFSET 0
++#define MXC_CCM_CCGR0_ARM_BUS(v) (((v) & 0x3) << 0)
++#define MXC_CCM_CCGR0_ARM_AXI_OFFSET 2
++#define MXC_CCM_CCGR0_ARM_AXI(v) (((v) & 0x3) << 2)
++#define MXC_CCM_CCGR0_ARM_DEBUG_OFFSET 4
++#define MXC_CCM_CCGR0_ARM_DEBUG(v) (((v) & 0x3) << 4)
++#define MXC_CCM_CCGR0_TZIC_OFFSET 6
++#define MXC_CCM_CCGR0_TZIC(v) (((v) & 0x3) << 6)
++#define MXC_CCM_CCGR0_DAP_OFFSET 8
++#define MXC_CCM_CCGR0_DAP(v) (((v) & 0x3) << 8)
++#define MXC_CCM_CCGR0_TPIU_OFFSET 10
++#define MXC_CCM_CCGR0_TPIU(v) (((v) & 0x3) << 10)
++#define MXC_CCM_CCGR0_CTI2_OFFSET 12
++#define MXC_CCM_CCGR0_CTI2(v) (((v) & 0x3) << 12)
++#define MXC_CCM_CCGR0_CTI3_OFFSET 14
++#define MXC_CCM_CCGR0_CTI3(v) (((v) & 0x3) << 14)
++#define MXC_CCM_CCGR0_AHBMUX1_OFFSET 16
++#define MXC_CCM_CCGR0_AHBMUX1(v) (((v) & 0x3) << 16)
++#define MXC_CCM_CCGR0_AHBMUX2_OFFSET 18
++#define MXC_CCM_CCGR0_AHBMUX2(v) (((v) & 0x3) << 18)
++#define MXC_CCM_CCGR0_ROMCP_OFFSET 20
++#define MXC_CCM_CCGR0_ROMCP(v) (((v) & 0x3) << 20)
++#define MXC_CCM_CCGR0_ROM_OFFSET 22
++#define MXC_CCM_CCGR0_ROM(v) (((v) & 0x3) << 22)
++#define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET 24
++#define MXC_CCM_CCGR0_AIPS_TZ1(v) (((v) & 0x3) << 24)
++#define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET 26
++#define MXC_CCM_CCGR0_AIPS_TZ2(v) (((v) & 0x3) << 26)
++#define MXC_CCM_CCGR0_AHB_MAX_OFFSET 28
++#define MXC_CCM_CCGR0_AHB_MAX(v) (((v) & 0x3) << 28)
++#define MXC_CCM_CCGR0_IIM_OFFSET 30
++#define MXC_CCM_CCGR0_IIM(v) (((v) & 0x3) << 30)
++
++#define MXC_CCM_CCGR1_TMAX1_OFFSET 0
++#define MXC_CCM_CCGR1_TMAX1(v) (((v) & 0x3) << 0)
++#define MXC_CCM_CCGR1_TMAX2_OFFSET 2
++#define MXC_CCM_CCGR1_TMAX2(v) (((v) & 0x3) << 2)
++#define MXC_CCM_CCGR1_TMAX3_OFFSET 4
++#define MXC_CCM_CCGR1_TMAX3(v) (((v) & 0x3) << 4)
++#define MXC_CCM_CCGR1_UART1_IPG_OFFSET 6
++#define MXC_CCM_CCGR1_UART1_IPG(v) (((v) & 0x3) << 6)
++#define MXC_CCM_CCGR1_UART1_PER_OFFSET 8
++#define MXC_CCM_CCGR1_UART1_PER(v) (((v) & 0x3) << 8)
++#define MXC_CCM_CCGR1_UART2_IPG_OFFSET 10
++#define MXC_CCM_CCGR1_UART2_IPG(v) (((v) & 0x3) << 10)
++#define MXC_CCM_CCGR1_UART2_PER_OFFSET 12
++#define MXC_CCM_CCGR1_UART2_PER(v) (((v) & 0x3) << 12)
++#define MXC_CCM_CCGR1_UART3_IPG_OFFSET 14
++#define MXC_CCM_CCGR1_UART3_IPG(v) (((v) & 0x3) << 14)
++#define MXC_CCM_CCGR1_UART3_PER_OFFSET 16
++#define MXC_CCM_CCGR1_UART3_PER(v) (((v) & 0x3) << 16)
++#define MXC_CCM_CCGR1_I2C1_OFFSET 18
++#define MXC_CCM_CCGR1_I2C1(v) (((v) & 0x3) << 18)
++#define MXC_CCM_CCGR1_I2C2_OFFSET 20
++#define MXC_CCM_CCGR1_I2C2(v) (((v) & 0x3) << 20)
++#if defined(CONFIG_MX51)
++#define MXC_CCM_CCGR1_HSI2C_IPG_OFFSET 22
++#define MXC_CCM_CCGR1_HSI2C_IPG(v) (((v) & 0x3) << 22)
++#define MXC_CCM_CCGR1_HSI2C_SERIAL_OFFSET 24
++#define MXC_CCM_CCGR1_HSI2C_SERIAL(v) (((v) & 0x3) << 24)
++#elif defined(CONFIG_MX53)
++#define MXC_CCM_CCGR1_I2C3_OFFSET 22
++#define MXC_CCM_CCGR1_I2C3(v) (((v) & 0x3) << 22)
++#endif
++#define MXC_CCM_CCGR1_FIRI_IPG_OFFSET 26
++#define MXC_CCM_CCGR1_FIRI_IPG(v) (((v) & 0x3) << 26)
++#define MXC_CCM_CCGR1_FIRI_SERIAL_OFFSET 28
++#define MXC_CCM_CCGR1_FIRI_SERIAL(v) (((v) & 0x3) << 28)
++#define MXC_CCM_CCGR1_SCC_OFFSET 30
++#define MXC_CCM_CCGR1_SCC(v) (((v) & 0x3) << 30)
++
++#if defined(CONFIG_MX51)
++#define MXC_CCM_CCGR2_USB_PHY_OFFSET 0
++#define MXC_CCM_CCGR2_USB_PHY(v) (((v) & 0x3) << 0)
++#endif
++#define MXC_CCM_CCGR2_EPIT1_IPG_OFFSET 2
++#define MXC_CCM_CCGR2_EPIT1_IPG(v) (((v) & 0x3) << 2)
++#define MXC_CCM_CCGR2_EPIT1_HF_OFFSET 4
++#define MXC_CCM_CCGR2_EPIT1_HF(v) (((v) & 0x3) << 4)
++#define MXC_CCM_CCGR2_EPIT2_IPG_OFFSET 6
++#define MXC_CCM_CCGR2_EPIT2_IPG(v) (((v) & 0x3) << 6)
++#define MXC_CCM_CCGR2_EPIT2_HF_OFFSET 8
++#define MXC_CCM_CCGR2_EPIT2_HF(v) (((v) & 0x3) << 8)
++#define MXC_CCM_CCGR2_PWM1_IPG_OFFSET 10
++#define MXC_CCM_CCGR2_PWM1_IPG(v) (((v) & 0x3) << 10)
++#define MXC_CCM_CCGR2_PWM1_HF_OFFSET 12
++#define MXC_CCM_CCGR2_PWM1_HF(v) (((v) & 0x3) << 12)
++#define MXC_CCM_CCGR2_PWM2_IPG_OFFSET 14
++#define MXC_CCM_CCGR2_PWM2_IPG(v) (((v) & 0x3) << 14)
++#define MXC_CCM_CCGR2_PWM2_HF_OFFSET 16
++#define MXC_CCM_CCGR2_PWM2_HF(v) (((v) & 0x3) << 16)
++#define MXC_CCM_CCGR2_GPT_IPG_OFFSET 18
++#define MXC_CCM_CCGR2_GPT_IPG(v) (((v) & 0x3) << 18)
++#define MXC_CCM_CCGR2_GPT_HF_OFFSET 20
++#define MXC_CCM_CCGR2_GPT_HF(v) (((v) & 0x3) << 20)
++#define MXC_CCM_CCGR2_OWIRE_OFFSET 22
++#define MXC_CCM_CCGR2_OWIRE(v) (((v) & 0x3) << 22)
++#define MXC_CCM_CCGR2_FEC_OFFSET 24
++#define MXC_CCM_CCGR2_FEC(v) (((v) & 0x3) << 24)
++#define MXC_CCM_CCGR2_USBOH3_IPG_AHB_OFFSET 26
++#define MXC_CCM_CCGR2_USBOH3_IPG_AHB(v) (((v) & 0x3) << 26)
++#define MXC_CCM_CCGR2_USBOH3_60M_OFFSET 28
++#define MXC_CCM_CCGR2_USBOH3_60M(v) (((v) & 0x3) << 28)
++#define MXC_CCM_CCGR2_TVE_OFFSET 30
++#define MXC_CCM_CCGR2_TVE(v) (((v) & 0x3) << 30)
+
+-#define MXC_CCM_CCGR4_CG5_OFFSET 10
+-#define MXC_CCM_CCGR4_CG6_OFFSET 12
+-#define MXC_CCM_CCGR5_CG5_OFFSET 10
+-#define MXC_CCM_CCGR2_CG14_OFFSET 28
++#define MXC_CCM_CCGR3_ESDHC1_IPG_OFFSET 0
++#define MXC_CCM_CCGR3_ESDHC1_IPG(v) (((v) & 0x3) << 0)
++#define MXC_CCM_CCGR3_ESDHC1_PER_OFFSET 2
++#define MXC_CCM_CCGR3_ESDHC1_PER(v) (((v) & 0x3) << 2)
++#define MXC_CCM_CCGR3_ESDHC2_IPG_OFFSET 4
++#define MXC_CCM_CCGR3_ESDHC2_IPG(v) (((v) & 0x3) << 4)
++#define MXC_CCM_CCGR3_ESDHC2_PER_OFFSET 6
++#define MXC_CCM_CCGR3_ESDHC2_PER(v) (((v) & 0x3) << 6)
++#define MXC_CCM_CCGR3_ESDHC3_IPG_OFFSET 8
++#define MXC_CCM_CCGR3_ESDHC3_IPG(v) (((v) & 0x3) << 8)
++#define MXC_CCM_CCGR3_ESDHC3_PER_OFFSET 10
++#define MXC_CCM_CCGR3_ESDHC3_PER(v) (((v) & 0x3) << 10)
++#define MXC_CCM_CCGR3_ESDHC4_IPG_OFFSET 12
++#define MXC_CCM_CCGR3_ESDHC4_IPG(v) (((v) & 0x3) << 12)
++#define MXC_CCM_CCGR3_ESDHC4_PER_OFFSET 14
++#define MXC_CCM_CCGR3_ESDHC4_PER(v) (((v) & 0x3) << 14)
++#define MXC_CCM_CCGR3_SSI1_IPG_OFFSET 16
++#define MXC_CCM_CCGR3_SSI1_IPG(v) (((v) & 0x3) << 16)
++#define MXC_CCM_CCGR3_SSI1_SSI_OFFSET 18
++#define MXC_CCM_CCGR3_SSI1_SSI(v) (((v) & 0x3) << 18)
++#define MXC_CCM_CCGR3_SSI2_IPG_OFFSET 20
++#define MXC_CCM_CCGR3_SSI2_IPG(v) (((v) & 0x3) << 20)
++#define MXC_CCM_CCGR3_SSI2_SSI_OFFSET 22
++#define MXC_CCM_CCGR3_SSI2_SSI(v) (((v) & 0x3) << 22)
++#define MXC_CCM_CCGR3_SSI3_IPG_OFFSET 24
++#define MXC_CCM_CCGR3_SSI3_IPG(v) (((v) & 0x3) << 24)
++#define MXC_CCM_CCGR3_SSI3_SSI_OFFSET 26
++#define MXC_CCM_CCGR3_SSI3_SSI(v) (((v) & 0x3) << 26)
++#define MXC_CCM_CCGR3_SSI_EXT1_OFFSET 28
++#define MXC_CCM_CCGR3_SSI_EXT1(v) (((v) & 0x3) << 28)
++#define MXC_CCM_CCGR3_SSI_EXT2_OFFSET 30
++#define MXC_CCM_CCGR3_SSI_EXT2(v) (((v) & 0x3) << 30)
++
++#define MXC_CCM_CCGR4_PATA_OFFSET 0
++#define MXC_CCM_CCGR4_PATA(v) (((v) & 0x3) << 0)
++#if defined(CONFIG_MX51)
++#define MXC_CCM_CCGR4_SIM_IPG_OFFSET 2
++#define MXC_CCM_CCGR4_SIM_IPG(v) (((v) & 0x3) << 2)
++#define MXC_CCM_CCGR4_SIM_SERIAL_OFFSET 4
++#define MXC_CCM_CCGR4_SIM_SERIAL(v) (((v) & 0x3) << 4)
++#elif defined(CONFIG_MX53)
++#define MXC_CCM_CCGR4_SATA_OFFSET 2
++#define MXC_CCM_CCGR4_SATA(v) (((v) & 0x3) << 2)
++#define MXC_CCM_CCGR4_CAN2_IPG_OFFSET 6
++#define MXC_CCM_CCGR4_CAN2_IPG(v) (((v) & 0x3) << 6)
++#define MXC_CCM_CCGR4_CAN2_SERIAL_OFFSET 8
++#define MXC_CCM_CCGR4_CAN2_SERIAL(v) (((v) & 0x3) << 8)
++#define MXC_CCM_CCGR4_USB_PHY1_OFFSET 10
++#define MXC_CCM_CCGR4_USB_PHY1(v) (((v) & 0x3) << 10)
++#define MXC_CCM_CCGR4_USB_PHY2_OFFSET 12
++#define MXC_CCM_CCGR4_USB_PHY2(v) (((v) & 0x3) << 12)
++#endif
++#define MXC_CCM_CCGR4_SAHARA_OFFSET 14
++#define MXC_CCM_CCGR4_SAHARA(v) (((v) & 0x3) << 14)
++#define MXC_CCM_CCGR4_RTIC_OFFSET 16
++#define MXC_CCM_CCGR4_RTIC(v) (((v) & 0x3) << 16)
++#define MXC_CCM_CCGR4_ECSPI1_IPG_OFFSET 18
++#define MXC_CCM_CCGR4_ECSPI1_IPG(v) (((v) & 0x3) << 18)
++#define MXC_CCM_CCGR4_ECSPI1_PER_OFFSET 20
++#define MXC_CCM_CCGR4_ECSPI1_PER(v) (((v) & 0x3) << 20)
++#define MXC_CCM_CCGR4_ECSPI2_IPG_OFFSET 22
++#define MXC_CCM_CCGR4_ECSPI2_IPG(v) (((v) & 0x3) << 22)
++#define MXC_CCM_CCGR4_ECSPI2_PER_OFFSET 24
++#define MXC_CCM_CCGR4_ECSPI2_PER(v) (((v) & 0x3) << 24)
++#define MXC_CCM_CCGR4_CSPI_IPG_OFFSET 26
++#define MXC_CCM_CCGR4_CSPI_IPG(v) (((v) & 0x3) << 26)
++#define MXC_CCM_CCGR4_SRTC_OFFSET 28
++#define MXC_CCM_CCGR4_SRTC(v) (((v) & 0x3) << 28)
++#define MXC_CCM_CCGR4_SDMA_OFFSET 30
++#define MXC_CCM_CCGR4_SDMA(v) (((v) & 0x3) << 30)
++
++#define MXC_CCM_CCGR5_SPBA_OFFSET 0
++#define MXC_CCM_CCGR5_SPBA(v) (((v) & 0x3) << 0)
++#define MXC_CCM_CCGR5_GPU_OFFSET 2
++#define MXC_CCM_CCGR5_GPU(v) (((v) & 0x3) << 2)
++#define MXC_CCM_CCGR5_GARB_OFFSET 4
++#define MXC_CCM_CCGR5_GARB(v) (((v) & 0x3) << 4)
++#define MXC_CCM_CCGR5_VPU_OFFSET 6
++#define MXC_CCM_CCGR5_VPU(v) (((v) & 0x3) << 6)
++#define MXC_CCM_CCGR5_VPU_REF_OFFSET 8
++#define MXC_CCM_CCGR5_VPU_REF(v) (((v) & 0x3) << 8)
++#define MXC_CCM_CCGR5_IPU_OFFSET 10
++#define MXC_CCM_CCGR5_IPU(v) (((v) & 0x3) << 10)
++#if defined(CONFIG_MX51)
++#define MXC_CCM_CCGR5_IPUMUX12_OFFSET 12
++#define MXC_CCM_CCGR5_IPUMUX12(v) (((v) & 0x3) << 12)
++#elif defined(CONFIG_MX53)
++#define MXC_CCM_CCGR5_IPUMUX1_OFFSET 12
++#define MXC_CCM_CCGR5_IPUMUX1(v) (((v) & 0x3) << 12)
++#endif
++#define MXC_CCM_CCGR5_EMI_FAST_OFFSET 14
++#define MXC_CCM_CCGR5_EMI_FAST(v) (((v) & 0x3) << 14)
++#define MXC_CCM_CCGR5_EMI_SLOW_OFFSET 16
++#define MXC_CCM_CCGR5_EMI_SLOW(v) (((v) & 0x3) << 16)
++#define MXC_CCM_CCGR5_EMI_INT1_OFFSET 18
++#define MXC_CCM_CCGR5_EMI_INT1(v) (((v) & 0x3) << 18)
++#define MXC_CCM_CCGR5_EMI_ENFC_OFFSET 20
++#define MXC_CCM_CCGR5_EMI_ENFC(v) (((v) & 0x3) << 20)
++#define MXC_CCM_CCGR5_EMI_WRCK_OFFSET 22
++#define MXC_CCM_CCGR5_EMI_WRCK(v) (((v) & 0x3) << 22)
++#define MXC_CCM_CCGR5_GPC_IPG_OFFSET 24
++#define MXC_CCM_CCGR5_GPC_IPG(v) (((v) & 0x3) << 24)
++#define MXC_CCM_CCGR5_SPDIF0_OFFSET 26
++#define MXC_CCM_CCGR5_SPDIF0(v) (((v) & 0x3) << 26)
++#if defined(CONFIG_MX51)
++#define MXC_CCM_CCGR5_SPDIF1_OFFSET 28
++#define MXC_CCM_CCGR5_SPDIF1(v) (((v) & 0x3) << 28)
++#endif
++#define MXC_CCM_CCGR5_SPDIF_IPG_OFFSET 30
++#define MXC_CCM_CCGR5_SPDIF_IPG(v) (((v) & 0x3) << 30)
++
++#if defined(CONFIG_MX53)
++#define MXC_CCM_CCGR6_IPUMUX2_OFFSET 0
++#define MXC_CCM_CCGR6_IPUMUX2(v) (((v) & 0x3) << 0)
++#define MXC_CCM_CCGR6_OCRAM_OFFSET 2
++#define MXC_CCM_CCGR6_OCRAM(v) (((v) & 0x3) << 2)
++#endif
++#define MXC_CCM_CCGR6_CSI_MCLK1_OFFSET 4
++#define MXC_CCM_CCGR6_CSI_MCLK1(v) (((v) & 0x3) << 4)
++#if defined(CONFIG_MX51)
++#define MXC_CCM_CCGR6_CSI_MCLK2_OFFSET 6
++#define MXC_CCM_CCGR6_CSI_MCLK2(v) (((v) & 0x3) << 6)
++#define MXC_CCM_CCGR6_EMI_GARB_OFFSET 8
++#define MXC_CCM_CCGR6_EMI_GARB(v) (((v) & 0x3) << 8)
++#elif defined(CONFIG_MX53)
++#define MXC_CCM_CCGR6_EMI_INT2_OFFSET 8
++#define MXC_CCM_CCGR6_EMI_INT2(v) (((v) & 0x3) << 8)
++#endif
++#define MXC_CCM_CCGR6_IPU_DI0_OFFSET 10
++#define MXC_CCM_CCGR6_IPU_DI0(v) (((v) & 0x3) << 10)
++#define MXC_CCM_CCGR6_IPU_DI1_OFFSET 12
++#define MXC_CCM_CCGR6_IPU_DI1(v) (((v) & 0x3) << 12)
++#define MXC_CCM_CCGR6_GPU2D_OFFSET 14
++#define MXC_CCM_CCGR6_GPU2D(v) (((v) & 0x3) << 14)
++#if defined(CONFIG_MX53)
++#define MXC_CCM_CCGR6_ESAI_IPG_OFFSET 16
++#define MXC_CCM_CCGR6_ESAI_IPG(v) (((v) & 0x3) << 16)
++#define MXC_CCM_CCGR6_ESAI_ROOT_OFFSET 18
++#define MXC_CCM_CCGR6_ESAI_ROOT(v) (((v) & 0x3) << 18)
++#define MXC_CCM_CCGR6_CAN1_IPG_OFFSET 20
++#define MXC_CCM_CCGR6_CAN1_IPG(v) (((v) & 0x3) << 20)
++#define MXC_CCM_CCGR6_CAN1_SERIAL_OFFSET 22
++#define MXC_CCM_CCGR6_CAN1_SERIAL(v) (((v) & 0x3) << 22)
++#define MXC_CCM_CCGR6_PL301_4X1_OFFSET 24
++#define MXC_CCM_CCGR6_PL301_4X1(v) (((v) & 0x3) << 24)
++#define MXC_CCM_CCGR6_PL301_2X2_OFFSET 26
++#define MXC_CCM_CCGR6_PL301_2X2(v) (((v) & 0x3) << 26)
++#define MXC_CCM_CCGR6_LDB_DI0_OFFSET 28
++#define MXC_CCM_CCGR6_LDB_DI0(v) (((v) & 0x3) << 28)
++#define MXC_CCM_CCGR6_LDB_DI1_OFFSET 30
++#define MXC_CCM_CCGR6_LDB_DI1(v) (((v) & 0x3) << 30)
++
++#define MXC_CCM_CCGR7_ASRC_IPG_OFFSET 0
++#define MXC_CCM_CCGR7_ASRC_IPG(v) (((v) & 0x3) << 0)
++#define MXC_CCM_CCGR7_ASRC_ASRCK_OFFSET 2
++#define MXC_CCM_CCGR7_ASRC_ASRCK(v) (((v) & 0x3) << 2)
++#define MXC_CCM_CCGR7_MLB_OFFSET 4
++#define MXC_CCM_CCGR7_MLB(v) (((v) & 0x3) << 4)
++#define MXC_CCM_CCGR7_IEEE1588_OFFSET 6
++#define MXC_CCM_CCGR7_IEEE1588(v) (((v) & 0x3) << 6)
++#define MXC_CCM_CCGR7_UART4_IPG_OFFSET 8
++#define MXC_CCM_CCGR7_UART4_IPG(v) (((v) & 0x3) << 8)
++#define MXC_CCM_CCGR7_UART4_PER_OFFSET 10
++#define MXC_CCM_CCGR7_UART4_PER(v) (((v) & 0x3) << 10)
++#define MXC_CCM_CCGR7_UART5_IPG_OFFSET 12
++#define MXC_CCM_CCGR7_UART5_IPG(v) (((v) & 0x3) << 12)
++#define MXC_CCM_CCGR7_UART5_PER_OFFSET 14
++#define MXC_CCM_CCGR7_UART5_PER(v) (((v) & 0x3) << 14)
++#endif
+
+ /* Define the bits in register CLPCR */
+ #define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18)
+@@ -213,8 +610,10 @@ struct mxc_ccm_reg {
+ #define MXC_DPLLC_CTL_DPDCK0_2_EN (1 << 12)
+
+ #define MXC_DPLLC_OP_PDF_MASK 0xf
+-#define MXC_DPLLC_OP_MFI_MASK (0xf << 4)
+ #define MXC_DPLLC_OP_MFI_OFFSET 4
++#define MXC_DPLLC_OP_MFI_MASK (0xf << 4)
++#define MXC_DPLLC_OP_MFI(v) (((v) & 0xf) << 4)
++#define MXC_DPLLC_OP_MFI_RD(r) (((r) >> 4) & 0xf)
+
+ #define MXC_DPLLC_MFD_MFD_MASK 0x7ffffff
+
+diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h
+index 1d060fd..46017f4 100644
+--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
++++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
+@@ -308,10 +308,6 @@
+ #define DP_MFD_400 (3 - 1)
+ #define DP_MFN_400 1
+
+-#define DP_OP_455 ((9 << 4) + ((2 - 1) << 0))
+-#define DP_MFD_455 (48 - 1)
+-#define DP_MFN_455 23
+-
+ #define DP_OP_216 ((6 << 4) + ((3 - 1) << 0))
+ #define DP_MFD_216 (4 - 1)
+ #define DP_MFN_216 3
+diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h
+index 2af04f0..db377cc 100644
+--- a/arch/arm/include/asm/arch-mx6/clock.h
++++ b/arch/arm/include/asm/arch-mx6/clock.h
+@@ -24,6 +24,20 @@
+ #ifndef __ASM_ARCH_CLOCK_H
+ #define __ASM_ARCH_CLOCK_H
+
++#include <common.h>
++
++#ifdef CONFIG_SYS_MX6_HCLK
++#define MXC_HCLK CONFIG_SYS_MX6_HCLK
++#else
++#define MXC_HCLK 24000000
++#endif
++
++#ifdef CONFIG_SYS_MX6_CLK32
++#define MXC_CLK32 CONFIG_SYS_MX6_CLK32
++#else
++#define MXC_CLK32 32768
++#endif
++
+ enum mxc_clock {
+ MXC_ARM_CLK = 0,
+ MXC_PER_CLK,
+diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
+index 0e605c2..d670f30 100644
+--- a/arch/arm/include/asm/arch-mx6/crm_regs.h
++++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
+@@ -34,7 +34,7 @@ struct mxc_ccm_reg {
+ u32 cs1cdr;
+ u32 cs2cdr;
+ u32 cdcdr; /* 0x0030 */
+- u32 chscdr;
++ u32 chsccdr;
+ u32 cscdr2;
+ u32 cscdr3;
+ u32 cscdr4; /* 0x0040 */
+@@ -294,6 +294,10 @@ struct mxc_ccm_reg {
+ #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7)
+ #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0
+
++#define CHSCCDR_CLK_SEL_LDB_DI0 3
++#define CHSCCDR_PODF_DIVIDE_BY_3 2
++#define CHSCCDR_IPU_PRE_CLK_540M_PFD 5
++
+ /* Define the bits in register CSCDR2 */
+ #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << 19)
+ #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19
+@@ -395,185 +399,185 @@ struct mxc_ccm_reg {
+ /* Define the bits in registers CCGRx */
+ #define MXC_CCM_CCGR_CG_MASK 3
+
+-#define MXC_CCM_CCGR0_CG15_OFFSET 30
+-#define MXC_CCM_CCGR0_CG15_MASK (0x3 << 30)
+-#define MXC_CCM_CCGR0_CG14_OFFSET 28
+-#define MXC_CCM_CCGR0_CG14_MASK (0x3 << 28)
+-#define MXC_CCM_CCGR0_CG13_OFFSET 26
+-#define MXC_CCM_CCGR0_CG13_MASK (0x3 << 26)
+-#define MXC_CCM_CCGR0_CG12_OFFSET 24
+-#define MXC_CCM_CCGR0_CG12_MASK (0x3 << 24)
+-#define MXC_CCM_CCGR0_CG11_OFFSET 22
+-#define MXC_CCM_CCGR0_CG11_MASK (0x3 << 22)
+-#define MXC_CCM_CCGR0_CG10_OFFSET 20
+-#define MXC_CCM_CCGR0_CG10_MASK (0x3 << 20)
+-#define MXC_CCM_CCGR0_CG9_OFFSET 18
+-#define MXC_CCM_CCGR0_CG9_MASK (0x3 << 18)
+-#define MXC_CCM_CCGR0_CG8_OFFSET 16
+-#define MXC_CCM_CCGR0_CG8_MASK (0x3 << 16)
+-#define MXC_CCM_CCGR0_CG7_OFFSET 14
+-#define MXC_CCM_CCGR0_CG6_OFFSET 12
+-#define MXC_CCM_CCGR0_CG5_OFFSET 10
+-#define MXC_CCM_CCGR0_CG5_MASK (0x3 << 10)
+-#define MXC_CCM_CCGR0_CG4_OFFSET 8
+-#define MXC_CCM_CCGR0_CG4_MASK (0x3 << 8)
+-#define MXC_CCM_CCGR0_CG3_OFFSET 6
+-#define MXC_CCM_CCGR0_CG3_MASK (0x3 << 6)
+-#define MXC_CCM_CCGR0_CG2_OFFSET 4
+-#define MXC_CCM_CCGR0_CG2_MASK (0x3 << 4)
+-#define MXC_CCM_CCGR0_CG1_OFFSET 2
+-#define MXC_CCM_CCGR0_CG1_MASK (0x3 << 2)
+-#define MXC_CCM_CCGR0_CG0_OFFSET 0
+-#define MXC_CCM_CCGR0_CG0_MASK 3
+-
+-#define MXC_CCM_CCGR1_CG15_OFFSET 30
+-#define MXC_CCM_CCGR1_CG14_OFFSET 28
+-#define MXC_CCM_CCGR1_CG13_OFFSET 26
+-#define MXC_CCM_CCGR1_CG12_OFFSET 24
+-#define MXC_CCM_CCGR1_CG11_OFFSET 22
+-#define MXC_CCM_CCGR1_CG10_OFFSET 20
+-#define MXC_CCM_CCGR1_CG9_OFFSET 18
+-#define MXC_CCM_CCGR1_CG8_OFFSET 16
+-#define MXC_CCM_CCGR1_CG7_OFFSET 14
+-#define MXC_CCM_CCGR1_CG6_OFFSET 12
+-#define MXC_CCM_CCGR1_CG5_OFFSET 10
+-#define MXC_CCM_CCGR1_CG4_OFFSET 8
+-#define MXC_CCM_CCGR1_CG3_OFFSET 6
+-#define MXC_CCM_CCGR1_CG2_OFFSET 4
+-#define MXC_CCM_CCGR1_CG1_OFFSET 2
+-#define MXC_CCM_CCGR1_CG0_OFFSET 0
+-
+-#define MXC_CCM_CCGR2_CG15_OFFSET 30
+-#define MXC_CCM_CCGR2_CG14_OFFSET 28
+-#define MXC_CCM_CCGR2_CG13_OFFSET 26
+-#define MXC_CCM_CCGR2_CG12_OFFSET 24
+-#define MXC_CCM_CCGR2_CG11_OFFSET 22
+-#define MXC_CCM_CCGR2_CG10_OFFSET 20
+-#define MXC_CCM_CCGR2_CG9_OFFSET 18
+-#define MXC_CCM_CCGR2_CG8_OFFSET 16
+-#define MXC_CCM_CCGR2_CG7_OFFSET 14
+-#define MXC_CCM_CCGR2_CG6_OFFSET 12
+-#define MXC_CCM_CCGR2_CG5_OFFSET 10
+-#define MXC_CCM_CCGR2_CG4_OFFSET 8
+-#define MXC_CCM_CCGR2_CG3_OFFSET 6
+-#define MXC_CCM_CCGR2_CG2_OFFSET 4
+-#define MXC_CCM_CCGR2_CG1_OFFSET 2
+-#define MXC_CCM_CCGR2_CG0_OFFSET 0
+-
+-#define MXC_CCM_CCGR3_CG15_OFFSET 30
+-#define MXC_CCM_CCGR3_CG14_OFFSET 28
+-#define MXC_CCM_CCGR3_CG13_OFFSET 26
+-#define MXC_CCM_CCGR3_CG12_OFFSET 24
+-#define MXC_CCM_CCGR3_CG11_OFFSET 22
+-#define MXC_CCM_CCGR3_CG10_OFFSET 20
+-#define MXC_CCM_CCGR3_CG9_OFFSET 18
+-#define MXC_CCM_CCGR3_CG8_OFFSET 16
+-#define MXC_CCM_CCGR3_CG7_OFFSET 14
+-#define MXC_CCM_CCGR3_CG6_OFFSET 12
+-#define MXC_CCM_CCGR3_CG5_OFFSET 10
+-#define MXC_CCM_CCGR3_CG4_OFFSET 8
+-#define MXC_CCM_CCGR3_CG3_OFFSET 6
+-#define MXC_CCM_CCGR3_CG2_OFFSET 4
+-#define MXC_CCM_CCGR3_CG1_OFFSET 2
+-#define MXC_CCM_CCGR3_CG0_OFFSET 0
+-
+-#define MXC_CCM_CCGR4_CG15_OFFSET 30
+-#define MXC_CCM_CCGR4_CG14_OFFSET 28
+-#define MXC_CCM_CCGR4_CG13_OFFSET 26
+-#define MXC_CCM_CCGR4_CG12_OFFSET 24
+-#define MXC_CCM_CCGR4_CG11_OFFSET 22
+-#define MXC_CCM_CCGR4_CG10_OFFSET 20
+-#define MXC_CCM_CCGR4_CG9_OFFSET 18
+-#define MXC_CCM_CCGR4_CG8_OFFSET 16
+-#define MXC_CCM_CCGR4_CG7_OFFSET 14
+-#define MXC_CCM_CCGR4_CG6_OFFSET 12
+-#define MXC_CCM_CCGR4_CG5_OFFSET 10
+-#define MXC_CCM_CCGR4_CG4_OFFSET 8
+-#define MXC_CCM_CCGR4_CG3_OFFSET 6
+-#define MXC_CCM_CCGR4_CG2_OFFSET 4
+-#define MXC_CCM_CCGR4_CG1_OFFSET 2
+-#define MXC_CCM_CCGR4_CG0_OFFSET 0
+-
+-#define MXC_CCM_CCGR5_CG15_OFFSET 30
+-#define MXC_CCM_CCGR5_CG14_OFFSET 28
+-#define MXC_CCM_CCGR5_CG14_MASK (0x3 << 28)
+-#define MXC_CCM_CCGR5_CG13_OFFSET 26
+-#define MXC_CCM_CCGR5_CG13_MASK (0x3 << 26)
+-#define MXC_CCM_CCGR5_CG12_OFFSET 24
+-#define MXC_CCM_CCGR5_CG12_MASK (0x3 << 24)
+-#define MXC_CCM_CCGR5_CG11_OFFSET 22
+-#define MXC_CCM_CCGR5_CG11_MASK (0x3 << 22)
+-#define MXC_CCM_CCGR5_CG10_OFFSET 20
+-#define MXC_CCM_CCGR5_CG10_MASK (0x3 << 20)
+-#define MXC_CCM_CCGR5_CG9_OFFSET 18
+-#define MXC_CCM_CCGR5_CG9_MASK (0x3 << 18)
+-#define MXC_CCM_CCGR5_CG8_OFFSET 16
+-#define MXC_CCM_CCGR5_CG8_MASK (0x3 << 16)
+-#define MXC_CCM_CCGR5_CG7_OFFSET 14
+-#define MXC_CCM_CCGR5_CG7_MASK (0x3 << 14)
+-#define MXC_CCM_CCGR5_CG6_OFFSET 12
+-#define MXC_CCM_CCGR5_CG6_MASK (0x3 << 12)
+-#define MXC_CCM_CCGR5_CG5_OFFSET 10
+-#define MXC_CCM_CCGR5_CG4_OFFSET 8
+-#define MXC_CCM_CCGR5_CG3_OFFSET 6
+-#define MXC_CCM_CCGR5_CG2_OFFSET 4
+-#define MXC_CCM_CCGR5_CG2_MASK (0x3 << 4)
+-#define MXC_CCM_CCGR5_CG1_OFFSET 2
+-#define MXC_CCM_CCGR5_CG0_OFFSET 0
+-
+-#define MXC_CCM_CCGR6_CG15_OFFSET 30
+-#define MXC_CCM_CCGR6_CG14_OFFSET 28
+-#define MXC_CCM_CCGR6_CG14_MASK (0x3 << 28)
+-#define MXC_CCM_CCGR6_CG13_OFFSET 26
+-#define MXC_CCM_CCGR6_CG13_MASK (0x3 << 26)
+-#define MXC_CCM_CCGR6_CG12_OFFSET 24
+-#define MXC_CCM_CCGR6_CG12_MASK (0x3 << 24)
+-#define MXC_CCM_CCGR6_CG11_OFFSET 22
+-#define MXC_CCM_CCGR6_CG11_MASK (0x3 << 22)
+-#define MXC_CCM_CCGR6_CG10_OFFSET 20
+-#define MXC_CCM_CCGR6_CG10_MASK (0x3 << 20)
+-#define MXC_CCM_CCGR6_CG9_OFFSET 18
+-#define MXC_CCM_CCGR6_CG9_MASK (0x3 << 18)
+-#define MXC_CCM_CCGR6_CG8_OFFSET 16
+-#define MXC_CCM_CCGR6_CG8_MASK (0x3 << 16)
+-#define MXC_CCM_CCGR6_CG7_OFFSET 14
+-#define MXC_CCM_CCGR6_CG7_MASK (0x3 << 14)
+-#define MXC_CCM_CCGR6_CG6_OFFSET 12
+-#define MXC_CCM_CCGR6_CG6_MASK (0x3 << 12)
+-#define MXC_CCM_CCGR6_CG5_OFFSET 10
+-#define MXC_CCM_CCGR6_CG4_OFFSET 8
+-#define MXC_CCM_CCGR6_CG3_OFFSET 6
+-#define MXC_CCM_CCGR6_CG2_OFFSET 4
+-#define MXC_CCM_CCGR6_CG2_MASK (0x3 << 4)
+-#define MXC_CCM_CCGR6_CG1_OFFSET 2
+-#define MXC_CCM_CCGR6_CG0_OFFSET 0
+-
+-#define MXC_CCM_CCGR7_CG15_OFFSET 30
+-#define MXC_CCM_CCGR7_CG14_OFFSET 28
+-#define MXC_CCM_CCGR7_CG14_MASK (0x3 << 28)
+-#define MXC_CCM_CCGR7_CG13_OFFSET 26
+-#define MXC_CCM_CCGR7_CG13_MASK (0x3 << 26)
+-#define MXC_CCM_CCGR7_CG12_OFFSET 24
+-#define MXC_CCM_CCGR7_CG12_MASK (0x3 << 24)
+-#define MXC_CCM_CCGR7_CG11_OFFSET 22
+-#define MXC_CCM_CCGR7_CG11_MASK (0x3 << 22)
+-#define MXC_CCM_CCGR7_CG10_OFFSET 20
+-#define MXC_CCM_CCGR7_CG10_MASK (0x3 << 20)
+-#define MXC_CCM_CCGR7_CG9_OFFSET 18
+-#define MXC_CCM_CCGR7_CG9_MASK (0x3 << 18)
+-#define MXC_CCM_CCGR7_CG8_OFFSET 16
+-#define MXC_CCM_CCGR7_CG8_MASK (0x3 << 16)
+-#define MXC_CCM_CCGR7_CG7_OFFSET 14
+-#define MXC_CCM_CCGR7_CG7_MASK (0x3 << 14)
+-#define MXC_CCM_CCGR7_CG6_OFFSET 12
+-#define MXC_CCM_CCGR7_CG6_MASK (0x3 << 12)
+-#define MXC_CCM_CCGR7_CG5_OFFSET 10
+-#define MXC_CCM_CCGR7_CG4_OFFSET 8
+-#define MXC_CCM_CCGR7_CG3_OFFSET 6
+-#define MXC_CCM_CCGR7_CG2_OFFSET 4
+-#define MXC_CCM_CCGR7_CG2_MASK (0x3 << 4)
+-#define MXC_CCM_CCGR7_CG1_OFFSET 2
+-#define MXC_CCM_CCGR7_CG0_OFFSET 0
++#define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET 0
++#define MXC_CCM_CCGR0_AIPS_TZ1_MASK (3<<MXC_CCM_CCGR0_AIPS_TZ1_OFFSET)
++#define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET 2
++#define MXC_CCM_CCGR0_AIPS_TZ2_MASK (3<<MXC_CCM_CCGR0_AIPS_TZ2_OFFSET)
++#define MXC_CCM_CCGR0_APBHDMA HCLK_OFFSET 4
++#define MXC_CCM_CCGR0_AMASK (3<<MXC_CCM_CCGR0_APBHDMA)
++#define MXC_CCM_CCGR0_ASRC_OFFSET 6
++#define MXC_CCM_CCGR0_ASRC_MASK (3<<MXC_CCM_CCGR0_ASRC_OFFSET)
++#define MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET 8
++#define MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK (3<<MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET)
++#define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET 10
++#define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK (3<<MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET)
++#define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET 12
++#define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK (3<<MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET)
++#define MXC_CCM_CCGR0_CAN1_OFFSET 14
++#define MXC_CCM_CCGR0_CAN1_MASK (3<<MXC_CCM_CCGR0_CAN1_OFFSET)
++#define MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET 16
++#define MXC_CCM_CCGR0_CAN1_SERIAL_MASK (3<<MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET)
++#define MXC_CCM_CCGR0_CAN2_OFFSET 18
++#define MXC_CCM_CCGR0_CAN2_MASK (3<<MXC_CCM_CCGR0_CAN2_OFFSET)
++#define MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET 20
++#define MXC_CCM_CCGR0_CAN2_SERIAL_MASK (3<<MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET)
++#define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET 22
++#define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_MASK (3<<MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET)
++#define MXC_CCM_CCGR0_DCIC1_OFFSET 24
++#define MXC_CCM_CCGR0_DCIC1_MASK (3<<MXC_CCM_CCGR0_DCIC1_OFFSET)
++#define MXC_CCM_CCGR0_DCIC2_OFFSET 26
++#define MXC_CCM_CCGR0_DCIC2_MASK (3<<MXC_CCM_CCGR0_DCIC2_OFFSET)
++#define MXC_CCM_CCGR0_DTCP_OFFSET 28
++#define MXC_CCM_CCGR0_DTCP_MASK (3<<MXC_CCM_CCGR0_DTCP_OFFSET)
++
++#define MXC_CCM_CCGR1_ECSPI1S_OFFSET 0
++#define MXC_CCM_CCGR1_ECSPI1S_MASK (3<<MXC_CCM_CCGR1_ECSPI1S_OFFSET)
++#define MXC_CCM_CCGR1_ECSPI2S_OFFSET 2
++#define MXC_CCM_CCGR1_ECSPI2S_MASK (3<<MXC_CCM_CCGR1_ECSPI2S_OFFSET)
++#define MXC_CCM_CCGR1_ECSPI3S_OFFSET 4
++#define MXC_CCM_CCGR1_ECSPI3S_MASK (3<<MXC_CCM_CCGR1_ECSPI3S_OFFSET)
++#define MXC_CCM_CCGR1_ECSPI4S_OFFSET 6
++#define MXC_CCM_CCGR1_ECSPI4S_MASK (3<<MXC_CCM_CCGR1_ECSPI4S_OFFSET)
++#define MXC_CCM_CCGR1_ECSPI5S_OFFSET 8
++#define MXC_CCM_CCGR1_ECSPI5S_MASK (3<<MXC_CCM_CCGR1_ECSPI5S_OFFSET)
++#define MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET 10
++#define MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK (3<<MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET)
++#define MXC_CCM_CCGR1_EPIT1S_OFFSET 12
++#define MXC_CCM_CCGR1_EPIT1S_MASK (3<<MXC_CCM_CCGR1_EPIT1S_OFFSET)
++#define MXC_CCM_CCGR1_EPIT2S_OFFSET 14
++#define MXC_CCM_CCGR1_EPIT2S_MASK (3<<MXC_CCM_CCGR1_EPIT2S_OFFSET)
++#define MXC_CCM_CCGR1_ESAIS_OFFSET 16
++#define MXC_CCM_CCGR1_ESAIS_MASK (3<<MXC_CCM_CCGR1_ESAIS_OFFSET)
++#define MXC_CCM_CCGR1_GPT_BUS_OFFSET 20
++#define MXC_CCM_CCGR1_GPT_BUS_MASK (3<<MXC_CCM_CCGR1_GPT_BUS_OFFSET)
++#define MXC_CCM_CCGR1_GPT_SERIAL_OFFSET 22
++#define MXC_CCM_CCGR1_GPT_SERIAL_MASK (3<<MXC_CCM_CCGR1_GPT_SERIAL_OFFSET)
++#define MXC_CCM_CCGR1_GPU2D_OFFSET 24
++#define MXC_CCM_CCGR1_GPU2D_MASK (3<<MXC_CCM_CCGR1_GPU2D_OFFSET)
++#define MXC_CCM_CCGR1_GPU3D_OFFSET 26
++#define MXC_CCM_CCGR1_GPU3D_MASK (3<<MXC_CCM_CCGR1_GPU3D_OFFSET)
++
++#define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET 0
++#define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK (3<<MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET)
++#define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET 4
++#define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK (3<<MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET)
++#define MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET 6
++#define MXC_CCM_CCGR2_I2C1_SERIAL_MASK (3<<MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET)
++#define MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET 8
++#define MXC_CCM_CCGR2_I2C2_SERIAL_MASK (3<<MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET)
++#define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET 10
++#define MXC_CCM_CCGR2_I2C3_SERIAL_MASK (3<<MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET)
++#define MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET 12
++#define MXC_CCM_CCGR2_OCOTP_CTRL_MASK (3<<MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET)
++#define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET 14
++#define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK (3<<MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET)
++#define MXC_CCM_CCGR2_IPMUX1_OFFSET 16
++#define MXC_CCM_CCGR2_IPMUX1_MASK (3<<MXC_CCM_CCGR2_IPMUX1_OFFSET)
++#define MXC_CCM_CCGR2_IPMUX2_OFFSET 18
++#define MXC_CCM_CCGR2_IPMUX2_MASK (3<<MXC_CCM_CCGR2_IPMUX2_OFFSET)
++#define MXC_CCM_CCGR2_IPMUX3_OFFSET 20
++#define MXC_CCM_CCGR2_IPMUX3_MASK (3<<MXC_CCM_CCGR2_IPMUX3_OFFSET)
++#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET 22
++#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK (3<<MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET)
++#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET 24
++#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK (3<<MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET)
++#define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET 26
++#define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK (3<<MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET)
++
++#define MXC_CCM_CCGR3_IPU1_IPU_OFFSET 0
++#define MXC_CCM_CCGR3_IPU1_IPU_MASK (3<<MXC_CCM_CCGR3_IPU1_IPU_OFFSET)
++#define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET 2
++#define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK (3<<MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET)
++#define MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET 4
++#define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK (3<<MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET)
++#define MXC_CCM_CCGR3_IPU2_IPU_OFFSET 6
++#define MXC_CCM_CCGR3_IPU2_IPU_MASK (3<<MXC_CCM_CCGR3_IPU2_IPU_OFFSET)
++#define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET 8
++#define MXC_CCM_CCGR3_IPU2_IPU_DI0_MASK (3<<MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET)
++#define MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET 10
++#define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK (3<<MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET)
++#define MXC_CCM_CCGR3_LDB_DI0_OFFSET 12
++#define MXC_CCM_CCGR3_LDB_DI0_MASK (3<<MXC_CCM_CCGR3_LDB_DI0_OFFSET)
++#define MXC_CCM_CCGR3_LDB_DI1_OFFSET 14
++#define MXC_CCM_CCGR3_LDB_DI1_MASK (3<<MXC_CCM_CCGR3_LDB_DI1_OFFSET)
++#define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET 16
++#define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK (3<<MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET)
++#define MXC_CCM_CCGR3_MLB_OFFSET 18
++#define MXC_CCM_CCGR3_MLB_MASK (3<<MXC_CCM_CCGR3_MLB_OFFSET)
++#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET 20
++#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK (3<<MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET)
++#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET 22
++#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK (3<<MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET)
++#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET 24
++#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK (3<<MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET)
++#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET 26
++#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK (3<<MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET)
++#define MXC_CCM_CCGR3_OCRAM_OFFSET 28
++#define MXC_CCM_CCGR3_OCRAM_MASK (3<<MXC_CCM_CCGR3_OCRAM_OFFSET)
++#define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET 30
++#define MXC_CCM_CCGR3_OPENVGAXICLK_MASK (3<<MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET)
++
++#define MXC_CCM_CCGR4_PCIE_OFFSET 0
++#define MXC_CCM_CCGR4_PCIE_MASK (3<<MXC_CCM_CCGR4_PCIE_OFFSET)
++#define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET 8
++#define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK (3<<MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET)
++#define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET 12
++#define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK (3<<MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET)
++#define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET 14
++#define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_MASK (3<<MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET)
++#define MXC_CCM_CCGR4_PWM1_OFFSET 16
++#define MXC_CCM_CCGR4_PWM1_MASK (3<<MXC_CCM_CCGR4_PWM1_OFFSET)
++#define MXC_CCM_CCGR4_PWM2_OFFSET 18
++#define MXC_CCM_CCGR4_PWM2_MASK (3<<MXC_CCM_CCGR4_PWM2_OFFSET)
++#define MXC_CCM_CCGR4_PWM3_OFFSET 20
++#define MXC_CCM_CCGR4_PWM3_MASK (3<<MXC_CCM_CCGR4_PWM3_OFFSET)
++#define MXC_CCM_CCGR4_PWM4_OFFSET 22
++#define MXC_CCM_CCGR4_PWM4_MASK (3<<MXC_CCM_CCGR4_PWM4_OFFSET)
++#define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET 24
++#define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK (3<<MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET)
++#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET 26
++#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK (3<<MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET)
++#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET 28
++#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK (3<<MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET)
++#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET 30
++#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK (3<<MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET)
++
++#define MXC_CCM_CCGR5_ROM_OFFSET 0
++#define MXC_CCM_CCGR5_ROM_MASK (3<<MXC_CCM_CCGR5_ROM_OFFSET)
++#define MXC_CCM_CCGR5_SATA_OFFSET 4
++#define MXC_CCM_CCGR5_SATA_MASK (3<<MXC_CCM_CCGR5_SATA_OFFSET)
++#define MXC_CCM_CCGR5_SDMA_OFFSET 6
++#define MXC_CCM_CCGR5_SDMA_MASK (3<<MXC_CCM_CCGR5_SDMA_OFFSET)
++#define MXC_CCM_CCGR5_SPBA_OFFSET 12
++#define MXC_CCM_CCGR5_SPBA_MASK (3<<MXC_CCM_CCGR5_SPBA_OFFSET)
++#define MXC_CCM_CCGR5_SPDIF_OFFSET 14
++#define MXC_CCM_CCGR5_SPDIF_MASK (3<<MXC_CCM_CCGR5_SPDIF_OFFSET)
++#define MXC_CCM_CCGR5_SSI1_OFFSET 18
++#define MXC_CCM_CCGR5_SSI1_MASK (3<<MXC_CCM_CCGR5_SSI1_OFFSET)
++#define MXC_CCM_CCGR5_SSI2_OFFSET 20
++#define MXC_CCM_CCGR5_SSI2_MASK (3<<MXC_CCM_CCGR5_SSI2_OFFSET)
++#define MXC_CCM_CCGR5_SSI3_OFFSET 22
++#define MXC_CCM_CCGR5_SSI3_MASK (3<<MXC_CCM_CCGR5_SSI3_OFFSET)
++#define MXC_CCM_CCGR5_UART_OFFSET 24
++#define MXC_CCM_CCGR5_UART_MASK (3<<MXC_CCM_CCGR5_UART_OFFSET)
++#define MXC_CCM_CCGR5_UART_SERIAL_OFFSET 26
++#define MXC_CCM_CCGR5_UART_SERIAL_MASK (3<<MXC_CCM_CCGR5_UART_SERIAL_OFFSET)
++
++#define MXC_CCM_CCGR6_USBOH3_OFFSET 0
++#define MXC_CCM_CCGR6_USBOH3_MASK (3<<MXC_CCM_CCGR6_USBOH3_OFFSET)
++#define MXC_CCM_CCGR6_USDHC1_OFFSET 2
++#define MXC_CCM_CCGR6_USDHC1_MASK (3<<MXC_CCM_CCGR6_USDHC1_OFFSET)
++#define MXC_CCM_CCGR6_USDHC2_OFFSET 4
++#define MXC_CCM_CCGR6_USDHC2_MASK (3<<MXC_CCM_CCGR6_USDHC2_OFFSET)
++#define MXC_CCM_CCGR6_USDHC3_OFFSET 6
++#define MXC_CCM_CCGR6_USDHC3_MASK (3<<MXC_CCM_CCGR6_USDHC3_OFFSET)
++#define MXC_CCM_CCGR6_USDHC4_OFFSET 8
++#define MXC_CCM_CCGR6_USDHC4_MASK (3<<MXC_CCM_CCGR6_USDHC4_OFFSET)
++#define MXC_CCM_CCGR6_EMI_SLOW_OFFSET 10
++#define MXC_CCM_CCGR6_EMI_SLOW_MASK (3<<MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
++#define MXC_CCM_CCGR6_VDOAXICLK_OFFSET 12
++#define MXC_CCM_CCGR6_VDOAXICLK_MASK (3<<MXC_CCM_CCGR6_VDOAXICLK_OFFSET)
++
+ #define BM_ANADIG_PLL_SYS_LOCK 0x80000000
+ #define BP_ANADIG_PLL_SYS_RSVD0 20
+ #define BM_ANADIG_PLL_SYS_RSVD0 0x7FF00000
+diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
+index 159068e..dc737ba 100644
+--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
++++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
+@@ -200,12 +200,6 @@ struct src {
+ u32 gpr10;
+ };
+
+-/* OCOTP Registers */
+-struct ocotp_regs {
+- u32 reserved[0x198];
+- u32 gp1; /* 0x660 */
+-};
+-
+ /* GPR3 bitfields */
+ #define IOMUXC_GPR3_GPU_DBG_OFFSET 29
+ #define IOMUXC_GPR3_GPU_DBG_MASK (3<<IOMUXC_GPR3_GPU_DBG_OFFSET)
+@@ -566,6 +560,30 @@ struct anatop_regs {
+ u32 digprog; /* 0x260 */
+ };
+
++#define ANATOP_PFD_480_PFD0_FRAC_SHIFT 0
++#define ANATOP_PFD_480_PFD0_FRAC_MASK (0x3f<<ANATOP_PFD_480_PFD0_FRAC_SHIFT)
++#define ANATOP_PFD_480_PFD0_STABLE_SHIFT 6
++#define ANATOP_PFD_480_PFD0_STABLE_MASK (1<<ANATOP_PFD_480_PFD0_STABLE_SHIFT)
++#define ANATOP_PFD_480_PFD0_CLKGATE_SHIFT 7
++#define ANATOP_PFD_480_PFD0_CLKGATE_MASK (1<<ANATOP_PFD_480_PFD0_CLKGATE_SHIFT)
++#define ANATOP_PFD_480_PFD1_FRAC_SHIFT 8
++#define ANATOP_PFD_480_PFD1_FRAC_MASK (0x3f<<ANATOP_PFD_480_PFD1_FRAC_SHIFT)
++#define ANATOP_PFD_480_PFD1_STABLE_SHIFT 14
++#define ANATOP_PFD_480_PFD1_STABLE_MASK (1<<ANATOP_PFD_480_PFD1_STABLE_SHIFT)
++#define ANATOP_PFD_480_PFD1_CLKGATE_SHIFT 15
++#define ANATOP_PFD_480_PFD1_CLKGATE_MASK (0x3f<<ANATOP_PFD_480_PFD1_CLKGATE_SHIFT)
++#define ANATOP_PFD_480_PFD2_FRAC_SHIFT 16
++#define ANATOP_PFD_480_PFD2_FRAC_MASK (1<<ANATOP_PFD_480_PFD2_FRAC_SHIFT)
++#define ANATOP_PFD_480_PFD2_STABLE_SHIFT 22
++#define ANATOP_PFD_480_PFD2_STABLE_MASK (1<<ANATOP_PFD_480_PFD2_STABLE_SHIFT)
++#define ANATOP_PFD_480_PFD2_CLKGATE_SHIFT 23
++#define ANATOP_PFD_480_PFD2_CLKGATE_MASK (0x3f<<ANATOP_PFD_480_PFD2_CLKGATE_SHIFT)
++#define ANATOP_PFD_480_PFD3_FRAC_SHIFT 24
++#define ANATOP_PFD_480_PFD3_FRAC_MASK (1<<ANATOP_PFD_480_PFD3_FRAC_SHIFT)
++#define ANATOP_PFD_480_PFD3_STABLE_SHIFT 30
++#define ANATOP_PFD_480_PFD3_STABLE_MASK (1<<ANATOP_PFD_480_PFD3_STABLE_SHIFT)
++#define ANATOP_PFD_480_PFD3_CLKGATE_SHIFT 31
++
+ struct iomuxc_base_regs {
+ u32 gpr[14]; /* 0x000 */
+ u32 obsrv[5]; /* 0x038 */
+@@ -575,26 +593,5 @@ struct iomuxc_base_regs {
+ u32 daisy[104]; /* 0x7b0..94c */
+ };
+
+-struct src_regs {
+- u32 scr; /* 0x00 */
+- u32 sbmr1; /* 0x04 */
+- u32 srsr; /* 0x08 */
+- u32 reserved1; /* 0x0c */
+- u32 reserved2; /* 0x10 */
+- u32 sisr; /* 0x14 */
+- u32 simr; /* 0x18 */
+- u32 sbmr2; /* 0x1c */
+- u32 gpr1; /* 0x20 */
+- u32 gpr2; /* 0x24 */
+- u32 gpr3; /* 0x28 */
+- u32 gpr4; /* 0x2c */
+- u32 gpr5; /* 0x30 */
+- u32 gpr6; /* 0x34 */
+- u32 gpr7; /* 0x38 */
+- u32 gpr8; /* 0x3c */
+- u32 gpr9; /* 0x40 */
+- u32 gpr10; /* 0x44 */
+-};
+-
+ #endif /* __ASSEMBLER__*/
+ #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */
+diff --git a/arch/arm/include/asm/arch-mx6/mx6x_pins.h b/arch/arm/include/asm/arch-mx6/mx6x_pins.h
+index 3d66d64..3ade8dc 100644
+--- a/arch/arm/include/asm/arch-mx6/mx6x_pins.h
++++ b/arch/arm/include/asm/arch-mx6/mx6x_pins.h
+@@ -530,20 +530,20 @@ enum {
+ MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 = IOMUX_PAD(0x046C, 0x0158, 1, 0x0000, 0, 0),
+ MX6Q_PAD_EIM_BCLK__GPIO_6_31 = IOMUX_PAD(0x046C, 0x0158, 5, 0x0000, 0, 0),
+ MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 = IOMUX_PAD(0x046C, 0x0158, 6, 0x0000, 0, 0),
+- MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x0470, 0x015C, 0, 0x0000, 0, 0),
++ MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x0470, 0x015C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK = IOMUX_PAD(0x0470, 0x015C, 1, 0x0000, 0, 0),
+ MX6Q_PAD_DI0_DISP_CLK__MIPI_CR_DPY_OT28 = IOMUX_PAD(0x0470, 0x015C, 3, 0x0000, 0, 0),
+ MX6Q_PAD_DI0_DISP_CLK__SDMA_DBG_CR_STA0 = IOMUX_PAD(0x0470, 0x015C, 4, 0x0000, 0, 0),
+ MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 = IOMUX_PAD(0x0470, 0x015C, 5, 0x0000, 0, 0),
+ MX6Q_PAD_DI0_DISP_CLK__MMDC_DEBUG_0 = IOMUX_PAD(0x0470, 0x015C, 6, 0x0000, 0, 0),
+- MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 = IOMUX_PAD(0x0474, 0x0160, 0, 0x0000, 0, 0),
++ MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 = IOMUX_PAD(0x0474, 0x0160, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 = IOMUX_PAD(0x0474, 0x0160, 1, 0x0000, 0, 0),
+ MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC = IOMUX_PAD(0x0474, 0x0160, 2, 0x0000, 0, 0),
+ MX6Q_PAD_DI0_PIN15__MIPI_CR_DPHY_OUT_29 = IOMUX_PAD(0x0474, 0x0160, 3, 0x0000, 0, 0),
+ MX6Q_PAD_DI0_PIN15__SDMA_DBG_CORE_STA_1 = IOMUX_PAD(0x0474, 0x0160, 4, 0x0000, 0, 0),
+ MX6Q_PAD_DI0_PIN15__GPIO_4_17 = IOMUX_PAD(0x0474, 0x0160, 5, 0x0000, 0, 0),
+ MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 = IOMUX_PAD(0x0474, 0x0160, 6, 0x0000, 0, 0),
+- MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 = IOMUX_PAD(0x0478, 0x0164, 0, 0x0000, 0, 0),
++ MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 = IOMUX_PAD(0x0478, 0x0164, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 = IOMUX_PAD(0x0478, 0x0164, 1, 0x0000, 0, 0),
+ MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD = IOMUX_PAD(0x0478, 0x0164, 2, 0x0000, 0, 0),
+ MX6Q_PAD_DI0_PIN2__MIPI_CR_DPHY_OUT_30 = IOMUX_PAD(0x0478, 0x0164, 3, 0x0000, 0, 0),
+@@ -551,7 +551,7 @@ enum {
+ MX6Q_PAD_DI0_PIN2__GPIO_4_18 = IOMUX_PAD(0x0478, 0x0164, 5, 0x0000, 0, 0),
+ MX6Q_PAD_DI0_PIN2__MMDC_DEBUG_2 = IOMUX_PAD(0x0478, 0x0164, 6, 0x0000, 0, 0),
+ MX6Q_PAD_DI0_PIN2__PL301_PER1_HADDR_9 = IOMUX_PAD(0x0478, 0x0164, 7, 0x0000, 0, 0),
+- MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 = IOMUX_PAD(0x047C, 0x0168, 0, 0x0000, 0, 0),
++ MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 = IOMUX_PAD(0x047C, 0x0168, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 = IOMUX_PAD(0x047C, 0x0168, 1, 0x0000, 0, 0),
+ MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS = IOMUX_PAD(0x047C, 0x0168, 2, 0x0000, 0, 0),
+ MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_OUT31 = IOMUX_PAD(0x047C, 0x0168, 3, 0x0000, 0, 0),
+@@ -564,17 +564,17 @@ enum {
+ MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD = IOMUX_PAD(0x0480, 0x016C, 2, 0x0000, 0, 0),
+ MX6Q_PAD_DI0_PIN4__USDHC1_WP = IOMUX_PAD(0x0480, 0x016C, 3, 0x094C, 0, 0),
+ MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD = IOMUX_PAD(0x0480, 0x016C, 4, 0x0000, 0, 0),
+- MX6Q_PAD_DI0_PIN4__GPIO_4_20 = IOMUX_PAD(0x0480, 0x016C, 5, 0x0000, 0, 0),
++ MX6Q_PAD_DI0_PIN4__GPIO_4_20 = IOMUX_PAD(0x0480, 0x016C, 5, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 = IOMUX_PAD(0x0480, 0x016C, 6, 0x0000, 0, 0),
+ MX6Q_PAD_DI0_PIN4__PL301_PER1_HADDR_11 = IOMUX_PAD(0x0480, 0x016C, 7, 0x0000, 0, 0),
+- MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 = IOMUX_PAD(0x0484, 0x0170, 0, 0x0000, 0, 0),
++ MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 = IOMUX_PAD(0x0484, 0x0170, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 = IOMUX_PAD(0x0484, 0x0170, 1, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK = IOMUX_PAD(0x0484, 0x0170, 2, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DBG_0 = IOMUX_PAD(0x0484, 0x0170, 3, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT0__SDMA_DBG_CORE_RUN = IOMUX_PAD(0x0484, 0x0170, 4, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT0__GPIO_4_21 = IOMUX_PAD(0x0484, 0x0170, 5, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 = IOMUX_PAD(0x0484, 0x0170, 6, 0x0000, 0, 0),
+- MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 = IOMUX_PAD(0x0488, 0x0174, 0, 0x0000, 0, 0),
++ MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 = IOMUX_PAD(0x0488, 0x0174, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 = IOMUX_PAD(0x0488, 0x0174, 1, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI = IOMUX_PAD(0x0488, 0x0174, 2, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DBG_1 = IOMUX_PAD(0x0488, 0x0174, 3, 0x0000, 0, 0),
+@@ -582,7 +582,7 @@ enum {
+ MX6Q_PAD_DISP0_DAT1__GPIO_4_22 = IOMUX_PAD(0x0488, 0x0174, 5, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT1__MMDC_DEBUG_6 = IOMUX_PAD(0x0488, 0x0174, 6, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT1__PL301_PER1_HADR_12 = IOMUX_PAD(0x0488, 0x0174, 7, 0x0000, 0, 0),
+- MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 = IOMUX_PAD(0x048C, 0x0178, 0, 0x0000, 0, 0),
++ MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 = IOMUX_PAD(0x048C, 0x0178, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 = IOMUX_PAD(0x048C, 0x0178, 1, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO = IOMUX_PAD(0x048C, 0x0178, 2, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DBG_2 = IOMUX_PAD(0x048C, 0x0178, 3, 0x0000, 0, 0),
+@@ -590,7 +590,7 @@ enum {
+ MX6Q_PAD_DISP0_DAT2__GPIO_4_23 = IOMUX_PAD(0x048C, 0x0178, 5, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT2__MMDC_DEBUG_7 = IOMUX_PAD(0x048C, 0x0178, 6, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT2__PL301_PER1_HADR_13 = IOMUX_PAD(0x048C, 0x0178, 7, 0x0000, 0, 0),
+- MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 = IOMUX_PAD(0x0490, 0x017C, 0, 0x0000, 0, 0),
++ MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 = IOMUX_PAD(0x0490, 0x017C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 = IOMUX_PAD(0x0490, 0x017C, 1, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 = IOMUX_PAD(0x0490, 0x017C, 2, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DBG_3 = IOMUX_PAD(0x0490, 0x017C, 3, 0x0000, 0, 0),
+@@ -598,7 +598,7 @@ enum {
+ MX6Q_PAD_DISP0_DAT3__GPIO_4_24 = IOMUX_PAD(0x0490, 0x017C, 5, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DBG_8 = IOMUX_PAD(0x0490, 0x017C, 6, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT3__PL301_PER1_HADR_14 = IOMUX_PAD(0x0490, 0x017C, 7, 0x0000, 0, 0),
+- MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 = IOMUX_PAD(0x0494, 0x0180, 0, 0x0000, 0, 0),
++ MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 = IOMUX_PAD(0x0494, 0x0180, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 = IOMUX_PAD(0x0494, 0x0180, 1, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 = IOMUX_PAD(0x0494, 0x0180, 2, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DBG_4 = IOMUX_PAD(0x0494, 0x0180, 3, 0x0000, 0, 0),
+@@ -606,7 +606,7 @@ enum {
+ MX6Q_PAD_DISP0_DAT4__GPIO_4_25 = IOMUX_PAD(0x0494, 0x0180, 5, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 = IOMUX_PAD(0x0494, 0x0180, 6, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT4__PL301_PER1_HADR_15 = IOMUX_PAD(0x0494, 0x0180, 7, 0x0000, 0, 0),
+- MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 = IOMUX_PAD(0x0498, 0x0184, 0, 0x0000, 0, 0),
++ MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 = IOMUX_PAD(0x0498, 0x0184, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 = IOMUX_PAD(0x0498, 0x0184, 1, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 = IOMUX_PAD(0x0498, 0x0184, 2, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS = IOMUX_PAD(0x0498, 0x0184, 3, 0x0000, 0, 0),
+@@ -614,7 +614,7 @@ enum {
+ MX6Q_PAD_DISP0_DAT5__GPIO_4_26 = IOMUX_PAD(0x0498, 0x0184, 5, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT5__MMDC_DEBUG_10 = IOMUX_PAD(0x0498, 0x0184, 6, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT5__PL301_PER1_HADR_16 = IOMUX_PAD(0x0498, 0x0184, 7, 0x0000, 0, 0),
+- MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 = IOMUX_PAD(0x049C, 0x0188, 0, 0x0000, 0, 0),
++ MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 = IOMUX_PAD(0x049C, 0x0188, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 = IOMUX_PAD(0x049C, 0x0188, 1, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 = IOMUX_PAD(0x049C, 0x0188, 2, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC = IOMUX_PAD(0x049C, 0x0188, 3, 0x0000, 0, 0),
+@@ -622,7 +622,7 @@ enum {
+ MX6Q_PAD_DISP0_DAT6__GPIO_4_27 = IOMUX_PAD(0x049C, 0x0188, 5, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT6__MMDC_DEBUG_11 = IOMUX_PAD(0x049C, 0x0188, 6, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT6__PL301_PER1_HADR_17 = IOMUX_PAD(0x049C, 0x0188, 7, 0x0000, 0, 0),
+- MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 = IOMUX_PAD(0x04A0, 0x018C, 0, 0x0000, 0, 0),
++ MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 = IOMUX_PAD(0x04A0, 0x018C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 = IOMUX_PAD(0x04A0, 0x018C, 1, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY = IOMUX_PAD(0x04A0, 0x018C, 2, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DBG_5 = IOMUX_PAD(0x04A0, 0x018C, 3, 0x0000, 0, 0),
+@@ -630,7 +630,7 @@ enum {
+ MX6Q_PAD_DISP0_DAT7__GPIO_4_28 = IOMUX_PAD(0x04A0, 0x018C, 5, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT7__MMDC_DEBUG_12 = IOMUX_PAD(0x04A0, 0x018C, 6, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT7__PL301_PER1_HADR_18 = IOMUX_PAD(0x04A0, 0x018C, 7, 0x0000, 0, 0),
+- MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 = IOMUX_PAD(0x04A4, 0x0190, 0, 0x0000, 0, 0),
++ MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 = IOMUX_PAD(0x04A4, 0x0190, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 = IOMUX_PAD(0x04A4, 0x0190, 1, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT8__PWM1_PWMO = IOMUX_PAD(0x04A4, 0x0190, 2, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B = IOMUX_PAD(0x04A4, 0x0190, 3, 0x0000, 0, 0),
+@@ -638,7 +638,7 @@ enum {
+ MX6Q_PAD_DISP0_DAT8__GPIO_4_29 = IOMUX_PAD(0x04A4, 0x0190, 5, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT8__MMDC_DEBUG_13 = IOMUX_PAD(0x04A4, 0x0190, 6, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT8__PL301_PER1_HADR_19 = IOMUX_PAD(0x04A4, 0x0190, 7, 0x0000, 0, 0),
+- MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 = IOMUX_PAD(0x04A8, 0x0194, 0, 0x0000, 0, 0),
++ MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 = IOMUX_PAD(0x04A8, 0x0194, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 = IOMUX_PAD(0x04A8, 0x0194, 1, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT9__PWM2_PWMO = IOMUX_PAD(0x04A8, 0x0194, 2, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B = IOMUX_PAD(0x04A8, 0x0194, 3, 0x0000, 0, 0),
+@@ -646,41 +646,41 @@ enum {
+ MX6Q_PAD_DISP0_DAT9__GPIO_4_30 = IOMUX_PAD(0x04A8, 0x0194, 5, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT9__MMDC_DEBUG_14 = IOMUX_PAD(0x04A8, 0x0194, 6, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT9__PL301_PER1_HADR_20 = IOMUX_PAD(0x04A8, 0x0194, 7, 0x0000, 0, 0),
+- MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 = IOMUX_PAD(0x04AC, 0x0198, 0, 0x0000, 0, 0),
++ MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 = IOMUX_PAD(0x04AC, 0x0198, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 = IOMUX_PAD(0x04AC, 0x0198, 1, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT10__USDHC1_DBG_6 = IOMUX_PAD(0x04AC, 0x0198, 3, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT10__SDMA_DBG_EVT_CHN3 = IOMUX_PAD(0x04AC, 0x0198, 4, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT10__GPIO_4_31 = IOMUX_PAD(0x04AC, 0x0198, 5, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT10__MMDC_DEBUG_15 = IOMUX_PAD(0x04AC, 0x0198, 6, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT10__PL301_PER1_HADR21 = IOMUX_PAD(0x04AC, 0x0198, 7, 0x0000, 0, 0),
+- MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 = IOMUX_PAD(0x04B0, 0x019C, 0, 0x0000, 0, 0),
++ MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 = IOMUX_PAD(0x04B0, 0x019C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 = IOMUX_PAD(0x04B0, 0x019C, 1, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DBG7 = IOMUX_PAD(0x04B0, 0x019C, 3, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT11__SDMA_DBG_EVT_CHN4 = IOMUX_PAD(0x04B0, 0x019C, 4, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT11__GPIO_5_5 = IOMUX_PAD(0x04B0, 0x019C, 5, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT11__MMDC_DEBUG_16 = IOMUX_PAD(0x04B0, 0x019C, 6, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT11__PL301_PER1_HADR22 = IOMUX_PAD(0x04B0, 0x019C, 7, 0x0000, 0, 0),
+- MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 = IOMUX_PAD(0x04B4, 0x01A0, 0, 0x0000, 0, 0),
++ MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 = IOMUX_PAD(0x04B4, 0x01A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 = IOMUX_PAD(0x04B4, 0x01A0, 1, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED = IOMUX_PAD(0x04B4, 0x01A0, 3, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT12__SDMA_DBG_EVT_CHN5 = IOMUX_PAD(0x04B4, 0x01A0, 4, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT12__GPIO_5_6 = IOMUX_PAD(0x04B4, 0x01A0, 5, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT12__MMDC_DEBUG_17 = IOMUX_PAD(0x04B4, 0x01A0, 6, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT12__PL301_PER1_HADR23 = IOMUX_PAD(0x04B4, 0x01A0, 7, 0x0000, 0, 0),
+- MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 = IOMUX_PAD(0x04B8, 0x01A4, 0, 0x0000, 0, 0),
++ MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 = IOMUX_PAD(0x04B8, 0x01A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 = IOMUX_PAD(0x04B8, 0x01A4, 1, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x04B8, 0x01A4, 3, 0x07D8, 1, 0),
+ MX6Q_PAD_DISP0_DAT13__SDMA_DBG_EVT_CHN0 = IOMUX_PAD(0x04B8, 0x01A4, 4, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT13__GPIO_5_7 = IOMUX_PAD(0x04B8, 0x01A4, 5, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT13__MMDC_DEBUG_18 = IOMUX_PAD(0x04B8, 0x01A4, 6, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT13__PL301_PER1_HADR24 = IOMUX_PAD(0x04B8, 0x01A4, 7, 0x0000, 0, 0),
+- MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 = IOMUX_PAD(0x04BC, 0x01A8, 0, 0x0000, 0, 0),
++ MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 = IOMUX_PAD(0x04BC, 0x01A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 = IOMUX_PAD(0x04BC, 0x01A8, 1, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC = IOMUX_PAD(0x04BC, 0x01A8, 3, 0x07D4, 1, 0),
+ MX6Q_PAD_DISP0_DAT14__SDMA_DBG_EVT_CHN1 = IOMUX_PAD(0x04BC, 0x01A8, 4, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT14__GPIO_5_8 = IOMUX_PAD(0x04BC, 0x01A8, 5, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT14__MMDC_DEBUG_19 = IOMUX_PAD(0x04BC, 0x01A8, 6, 0x0000, 0, 0),
+- MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 = IOMUX_PAD(0x04C0, 0x01AC, 0, 0x0000, 0, 0),
++ MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 = IOMUX_PAD(0x04C0, 0x01AC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 = IOMUX_PAD(0x04C0, 0x01AC, 1, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 = IOMUX_PAD(0x04C0, 0x01AC, 2, 0x0804, 1, 0),
+ MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 = IOMUX_PAD(0x04C0, 0x01AC, 3, 0x0820, 1, 0),
+@@ -688,7 +688,7 @@ enum {
+ MX6Q_PAD_DISP0_DAT15__GPIO_5_9 = IOMUX_PAD(0x04C0, 0x01AC, 5, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT15__MMDC_DEBUG_20 = IOMUX_PAD(0x04C0, 0x01AC, 6, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT15__PL301_PER1_HADR25 = IOMUX_PAD(0x04C0, 0x01AC, 7, 0x0000, 0, 0),
+- MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 = IOMUX_PAD(0x04C4, 0x01B0, 0, 0x0000, 0, 0),
++ MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 = IOMUX_PAD(0x04C4, 0x01B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 = IOMUX_PAD(0x04C4, 0x01B0, 1, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI = IOMUX_PAD(0x04C4, 0x01B0, 2, 0x0818, 1, 0),
+ MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC = IOMUX_PAD(0x04C4, 0x01B0, 3, 0x07DC, 0, 0),
+@@ -696,7 +696,7 @@ enum {
+ MX6Q_PAD_DISP0_DAT16__GPIO_5_10 = IOMUX_PAD(0x04C4, 0x01B0, 5, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT16__MMDC_DEBUG_21 = IOMUX_PAD(0x04C4, 0x01B0, 6, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT16__PL301_PER1_HADR26 = IOMUX_PAD(0x04C4, 0x01B0, 7, 0x0000, 0, 0),
+- MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 = IOMUX_PAD(0x04C8, 0x01B4, 0, 0x0000, 0, 0),
++ MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 = IOMUX_PAD(0x04C8, 0x01B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 = IOMUX_PAD(0x04C8, 0x01B4, 1, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO = IOMUX_PAD(0x04C8, 0x01B4, 2, 0x0814, 1, 0),
+ MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD = IOMUX_PAD(0x04C8, 0x01B4, 3, 0x07D0, 0, 0),
+@@ -704,7 +704,7 @@ enum {
+ MX6Q_PAD_DISP0_DAT17__GPIO_5_11 = IOMUX_PAD(0x04C8, 0x01B4, 5, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT17__MMDC_DEBUG_22 = IOMUX_PAD(0x04C8, 0x01B4, 6, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT17__PL301_PER1_HADR27 = IOMUX_PAD(0x04C8, 0x01B4, 7, 0x0000, 0, 0),
+- MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 = IOMUX_PAD(0x04CC, 0x01B8, 0, 0x0000, 0, 0),
++ MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 = IOMUX_PAD(0x04CC, 0x01B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 = IOMUX_PAD(0x04CC, 0x01B8, 1, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 = IOMUX_PAD(0x04CC, 0x01B8, 2, 0x081C, 1, 0),
+ MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x04CC, 0x01B8, 3, 0x07E0, 0, 0),
+@@ -712,7 +712,7 @@ enum {
+ MX6Q_PAD_DISP0_DAT18__GPIO_5_12 = IOMUX_PAD(0x04CC, 0x01B8, 5, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT18__MMDC_DEBUG_23 = IOMUX_PAD(0x04CC, 0x01B8, 6, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 = IOMUX_PAD(0x04CC, 0x01B8, 7, 0x0000, 0, 0),
+- MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 = IOMUX_PAD(0x04D0, 0x01BC, 0, 0x0000, 0, 0),
++ MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 = IOMUX_PAD(0x04D0, 0x01BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 = IOMUX_PAD(0x04D0, 0x01BC, 1, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK = IOMUX_PAD(0x04D0, 0x01BC, 2, 0x0810, 1, 0),
+ MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD = IOMUX_PAD(0x04D0, 0x01BC, 3, 0x07CC, 0, 0),
+@@ -720,7 +720,7 @@ enum {
+ MX6Q_PAD_DISP0_DAT19__GPIO_5_13 = IOMUX_PAD(0x04D0, 0x01BC, 5, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT19__MMDC_DEBUG_24 = IOMUX_PAD(0x04D0, 0x01BC, 6, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 = IOMUX_PAD(0x04D0, 0x01BC, 7, 0x0000, 0, 0),
+- MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 = IOMUX_PAD(0x04D4, 0x01C0, 0, 0x0000, 0, 0),
++ MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 = IOMUX_PAD(0x04D4, 0x01C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 = IOMUX_PAD(0x04D4, 0x01C0, 1, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK = IOMUX_PAD(0x04D4, 0x01C0, 2, 0x07F4, 1, 0),
+ MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC = IOMUX_PAD(0x04D4, 0x01C0, 3, 0x07C4, 0, 0),
+@@ -728,7 +728,7 @@ enum {
+ MX6Q_PAD_DISP0_DAT20__GPIO_5_14 = IOMUX_PAD(0x04D4, 0x01C0, 5, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT20__MMDC_DEBUG_25 = IOMUX_PAD(0x04D4, 0x01C0, 6, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT20__PL301_PER1_HADR28 = IOMUX_PAD(0x04D4, 0x01C0, 7, 0x0000, 0, 0),
+- MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 = IOMUX_PAD(0x04D8, 0x01C4, 0, 0x0000, 0, 0),
++ MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 = IOMUX_PAD(0x04D8, 0x01C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 = IOMUX_PAD(0x04D8, 0x01C4, 1, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI = IOMUX_PAD(0x04D8, 0x01C4, 2, 0x07FC, 1, 0),
+ MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD = IOMUX_PAD(0x04D8, 0x01C4, 3, 0x07B8, 1, 0),
+@@ -736,7 +736,7 @@ enum {
+ MX6Q_PAD_DISP0_DAT21__GPIO_5_15 = IOMUX_PAD(0x04D8, 0x01C4, 5, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT21__MMDC_DEBUG_26 = IOMUX_PAD(0x04D8, 0x01C4, 6, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT21__PL301_PER1_HADR29 = IOMUX_PAD(0x04D8, 0x01C4, 7, 0x0000, 0, 0),
+- MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 = IOMUX_PAD(0x04DC, 0x01C8, 0, 0x0000, 0, 0),
++ MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 = IOMUX_PAD(0x04DC, 0x01C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 = IOMUX_PAD(0x04DC, 0x01C8, 1, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO = IOMUX_PAD(0x04DC, 0x01C8, 2, 0x07F8, 1, 0),
+ MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS = IOMUX_PAD(0x04DC, 0x01C8, 3, 0x07C8, 1, 0),
+@@ -744,7 +744,7 @@ enum {
+ MX6Q_PAD_DISP0_DAT22__GPIO_5_16 = IOMUX_PAD(0x04DC, 0x01C8, 5, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT22__MMDC_DEBUG_27 = IOMUX_PAD(0x04DC, 0x01C8, 6, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT22__PL301_PER1_HADR30 = IOMUX_PAD(0x04DC, 0x01C8, 7, 0x0000, 0, 0),
+- MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 = IOMUX_PAD(0x04E0, 0x01CC, 0, 0x0000, 0, 0),
++ MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 = IOMUX_PAD(0x04E0, 0x01CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 = IOMUX_PAD(0x04E0, 0x01CC, 1, 0x0000, 0, 0),
+ MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 = IOMUX_PAD(0x04E0, 0x01CC, 2, 0x0800, 1, 0),
+ MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD = IOMUX_PAD(0x04E0, 0x01CC, 3, 0x07B4, 1, 0),
+diff --git a/arch/arm/include/asm/arch-mx6/mxc_hdmi.h b/arch/arm/include/asm/arch-mx6/mxc_hdmi.h
+new file mode 100644
+index 0000000..02a413f
+--- /dev/null
++++ b/arch/arm/include/asm/arch-mx6/mxc_hdmi.h
+@@ -0,0 +1,1053 @@
++/*
++ * Copyright (C) 2011 Freescale Semiconductor, Inc.
++ */
++
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#ifndef __MXC_HDMI_H__
++#define __MXC_HDMI_H__
++
++/*
++ * Hdmi controller registers
++ */
++
++/* Identification Registers */
++#define HDMI_DESIGN_ID 0x0000
++#define HDMI_REVISION_ID 0x0001
++#define HDMI_PRODUCT_ID0 0x0002
++#define HDMI_PRODUCT_ID1 0x0003
++#define HDMI_CONFIG0_ID 0x0004
++#define HDMI_CONFIG1_ID 0x0005
++#define HDMI_CONFIG2_ID 0x0006
++#define HDMI_CONFIG3_ID 0x0007
++
++/* Interrupt Registers */
++#define HDMI_IH_FC_STAT0 0x0100
++#define HDMI_IH_FC_STAT1 0x0101
++#define HDMI_IH_FC_STAT2 0x0102
++#define HDMI_IH_AS_STAT0 0x0103
++#define HDMI_IH_PHY_STAT0 0x0104
++#define HDMI_IH_I2CM_STAT0 0x0105
++#define HDMI_IH_CEC_STAT0 0x0106
++#define HDMI_IH_VP_STAT0 0x0107
++#define HDMI_IH_I2CMPHY_STAT0 0x0108
++#define HDMI_IH_AHBDMAAUD_STAT0 0x0109
++
++#define HDMI_IH_MUTE_FC_STAT0 0x0180
++#define HDMI_IH_MUTE_FC_STAT1 0x0181
++#define HDMI_IH_MUTE_FC_STAT2 0x0182
++#define HDMI_IH_MUTE_AS_STAT0 0x0183
++#define HDMI_IH_MUTE_PHY_STAT0 0x0184
++#define HDMI_IH_MUTE_I2CM_STAT0 0x0185
++#define HDMI_IH_MUTE_CEC_STAT0 0x0186
++#define HDMI_IH_MUTE_VP_STAT0 0x0187
++#define HDMI_IH_MUTE_I2CMPHY_STAT0 0x0188
++#define HDMI_IH_MUTE_AHBDMAAUD_STAT0 0x0189
++#define HDMI_IH_MUTE 0x01FF
++
++/* Video Sample Registers */
++#define HDMI_TX_INVID0 0x0200
++#define HDMI_TX_INSTUFFING 0x0201
++#define HDMI_TX_GYDATA0 0x0202
++#define HDMI_TX_GYDATA1 0x0203
++#define HDMI_TX_RCRDATA0 0x0204
++#define HDMI_TX_RCRDATA1 0x0205
++#define HDMI_TX_BCBDATA0 0x0206
++#define HDMI_TX_BCBDATA1 0x0207
++
++/* Video Packetizer Registers */
++#define HDMI_VP_STATUS 0x0800
++#define HDMI_VP_PR_CD 0x0801
++#define HDMI_VP_STUFF 0x0802
++#define HDMI_VP_REMAP 0x0803
++#define HDMI_VP_CONF 0x0804
++#define HDMI_VP_STAT 0x0805
++#define HDMI_VP_INT 0x0806
++#define HDMI_VP_MASK 0x0807
++#define HDMI_VP_POL 0x0808
++
++/* Frame Composer Registers */
++#define HDMI_FC_INVIDCONF 0x1000
++#define HDMI_FC_INHACTV0 0x1001
++#define HDMI_FC_INHACTV1 0x1002
++#define HDMI_FC_INHBLANK0 0x1003
++#define HDMI_FC_INHBLANK1 0x1004
++#define HDMI_FC_INVACTV0 0x1005
++#define HDMI_FC_INVACTV1 0x1006
++#define HDMI_FC_INVBLANK 0x1007
++#define HDMI_FC_HSYNCINDELAY0 0x1008
++#define HDMI_FC_HSYNCINDELAY1 0x1009
++#define HDMI_FC_HSYNCINWIDTH0 0x100A
++#define HDMI_FC_HSYNCINWIDTH1 0x100B
++#define HDMI_FC_VSYNCINDELAY 0x100C
++#define HDMI_FC_VSYNCINWIDTH 0x100D
++#define HDMI_FC_INFREQ0 0x100E
++#define HDMI_FC_INFREQ1 0x100F
++#define HDMI_FC_INFREQ2 0x1010
++#define HDMI_FC_CTRLDUR 0x1011
++#define HDMI_FC_EXCTRLDUR 0x1012
++#define HDMI_FC_EXCTRLSPAC 0x1013
++#define HDMI_FC_CH0PREAM 0x1014
++#define HDMI_FC_CH1PREAM 0x1015
++#define HDMI_FC_CH2PREAM 0x1016
++#define HDMI_FC_AVICONF3 0x1017
++#define HDMI_FC_GCP 0x1018
++#define HDMI_FC_AVICONF0 0x1019
++#define HDMI_FC_AVICONF1 0x101A
++#define HDMI_FC_AVICONF2 0x101B
++#define HDMI_FC_AVIVID 0x101C
++#define HDMI_FC_AVIETB0 0x101D
++#define HDMI_FC_AVIETB1 0x101E
++#define HDMI_FC_AVISBB0 0x101F
++#define HDMI_FC_AVISBB1 0x1020
++#define HDMI_FC_AVIELB0 0x1021
++#define HDMI_FC_AVIELB1 0x1022
++#define HDMI_FC_AVISRB0 0x1023
++#define HDMI_FC_AVISRB1 0x1024
++#define HDMI_FC_AUDICONF0 0x1025
++#define HDMI_FC_AUDICONF1 0x1026
++#define HDMI_FC_AUDICONF2 0x1027
++#define HDMI_FC_AUDICONF3 0x1028
++#define HDMI_FC_VSDIEEEID0 0x1029
++#define HDMI_FC_VSDSIZE 0x102A
++#define HDMI_FC_VSDIEEEID1 0x1030
++#define HDMI_FC_VSDIEEEID2 0x1031
++#define HDMI_FC_VSDPAYLOAD0 0x1032
++#define HDMI_FC_VSDPAYLOAD1 0x1033
++#define HDMI_FC_VSDPAYLOAD2 0x1034
++#define HDMI_FC_VSDPAYLOAD3 0x1035
++#define HDMI_FC_VSDPAYLOAD4 0x1036
++#define HDMI_FC_VSDPAYLOAD5 0x1037
++#define HDMI_FC_VSDPAYLOAD6 0x1038
++#define HDMI_FC_VSDPAYLOAD7 0x1039
++#define HDMI_FC_VSDPAYLOAD8 0x103A
++#define HDMI_FC_VSDPAYLOAD9 0x103B
++#define HDMI_FC_VSDPAYLOAD10 0x103C
++#define HDMI_FC_VSDPAYLOAD11 0x103D
++#define HDMI_FC_VSDPAYLOAD12 0x103E
++#define HDMI_FC_VSDPAYLOAD13 0x103F
++#define HDMI_FC_VSDPAYLOAD14 0x1040
++#define HDMI_FC_VSDPAYLOAD15 0x1041
++#define HDMI_FC_VSDPAYLOAD16 0x1042
++#define HDMI_FC_VSDPAYLOAD17 0x1043
++#define HDMI_FC_VSDPAYLOAD18 0x1044
++#define HDMI_FC_VSDPAYLOAD19 0x1045
++#define HDMI_FC_VSDPAYLOAD20 0x1046
++#define HDMI_FC_VSDPAYLOAD21 0x1047
++#define HDMI_FC_VSDPAYLOAD22 0x1048
++#define HDMI_FC_VSDPAYLOAD23 0x1049
++#define HDMI_FC_SPDVENDORNAME0 0x104A
++#define HDMI_FC_SPDVENDORNAME1 0x104B
++#define HDMI_FC_SPDVENDORNAME2 0x104C
++#define HDMI_FC_SPDVENDORNAME3 0x104D
++#define HDMI_FC_SPDVENDORNAME4 0x104E
++#define HDMI_FC_SPDVENDORNAME5 0x104F
++#define HDMI_FC_SPDVENDORNAME6 0x1050
++#define HDMI_FC_SPDVENDORNAME7 0x1051
++#define HDMI_FC_SDPPRODUCTNAME0 0x1052
++#define HDMI_FC_SDPPRODUCTNAME1 0x1053
++#define HDMI_FC_SDPPRODUCTNAME2 0x1054
++#define HDMI_FC_SDPPRODUCTNAME3 0x1055
++#define HDMI_FC_SDPPRODUCTNAME4 0x1056
++#define HDMI_FC_SDPPRODUCTNAME5 0x1057
++#define HDMI_FC_SDPPRODUCTNAME6 0x1058
++#define HDMI_FC_SDPPRODUCTNAME7 0x1059
++#define HDMI_FC_SDPPRODUCTNAME8 0x105A
++#define HDMI_FC_SDPPRODUCTNAME9 0x105B
++#define HDMI_FC_SDPPRODUCTNAME10 0x105C
++#define HDMI_FC_SDPPRODUCTNAME11 0x105D
++#define HDMI_FC_SDPPRODUCTNAME12 0x105E
++#define HDMI_FC_SDPPRODUCTNAME13 0x105F
++#define HDMI_FC_SDPPRODUCTNAME14 0x1060
++#define HDMI_FC_SPDPRODUCTNAME15 0x1061
++#define HDMI_FC_SPDDEVICEINF 0x1062
++#define HDMI_FC_AUDSCONF 0x1063
++#define HDMI_FC_AUDSSTAT 0x1064
++#define HDMI_FC_DATACH0FILL 0x1070
++#define HDMI_FC_DATACH1FILL 0x1071
++#define HDMI_FC_DATACH2FILL 0x1072
++#define HDMI_FC_CTRLQHIGH 0x1073
++#define HDMI_FC_CTRLQLOW 0x1074
++#define HDMI_FC_ACP0 0x1075
++#define HDMI_FC_ACP28 0x1076
++#define HDMI_FC_ACP27 0x1077
++#define HDMI_FC_ACP26 0x1078
++#define HDMI_FC_ACP25 0x1079
++#define HDMI_FC_ACP24 0x107A
++#define HDMI_FC_ACP23 0x107B
++#define HDMI_FC_ACP22 0x107C
++#define HDMI_FC_ACP21 0x107D
++#define HDMI_FC_ACP20 0x107E
++#define HDMI_FC_ACP19 0x107F
++#define HDMI_FC_ACP18 0x1080
++#define HDMI_FC_ACP17 0x1081
++#define HDMI_FC_ACP16 0x1082
++#define HDMI_FC_ACP15 0x1083
++#define HDMI_FC_ACP14 0x1084
++#define HDMI_FC_ACP13 0x1085
++#define HDMI_FC_ACP12 0x1086
++#define HDMI_FC_ACP11 0x1087
++#define HDMI_FC_ACP10 0x1088
++#define HDMI_FC_ACP9 0x1089
++#define HDMI_FC_ACP8 0x108A
++#define HDMI_FC_ACP7 0x108B
++#define HDMI_FC_ACP6 0x108C
++#define HDMI_FC_ACP5 0x108D
++#define HDMI_FC_ACP4 0x108E
++#define HDMI_FC_ACP3 0x108F
++#define HDMI_FC_ACP2 0x1090
++#define HDMI_FC_ACP1 0x1091
++#define HDMI_FC_ISCR1_0 0x1092
++#define HDMI_FC_ISCR1_16 0x1093
++#define HDMI_FC_ISCR1_15 0x1094
++#define HDMI_FC_ISCR1_14 0x1095
++#define HDMI_FC_ISCR1_13 0x1096
++#define HDMI_FC_ISCR1_12 0x1097
++#define HDMI_FC_ISCR1_11 0x1098
++#define HDMI_FC_ISCR1_10 0x1099
++#define HDMI_FC_ISCR1_9 0x109A
++#define HDMI_FC_ISCR1_8 0x109B
++#define HDMI_FC_ISCR1_7 0x109C
++#define HDMI_FC_ISCR1_6 0x109D
++#define HDMI_FC_ISCR1_5 0x109E
++#define HDMI_FC_ISCR1_4 0x109F
++#define HDMI_FC_ISCR1_3 0x10A0
++#define HDMI_FC_ISCR1_2 0x10A1
++#define HDMI_FC_ISCR1_1 0x10A2
++#define HDMI_FC_ISCR2_15 0x10A3
++#define HDMI_FC_ISCR2_14 0x10A4
++#define HDMI_FC_ISCR2_13 0x10A5
++#define HDMI_FC_ISCR2_12 0x10A6
++#define HDMI_FC_ISCR2_11 0x10A7
++#define HDMI_FC_ISCR2_10 0x10A8
++#define HDMI_FC_ISCR2_9 0x10A9
++#define HDMI_FC_ISCR2_8 0x10AA
++#define HDMI_FC_ISCR2_7 0x10AB
++#define HDMI_FC_ISCR2_6 0x10AC
++#define HDMI_FC_ISCR2_5 0x10AD
++#define HDMI_FC_ISCR2_4 0x10AE
++#define HDMI_FC_ISCR2_3 0x10AF
++#define HDMI_FC_ISCR2_2 0x10B0
++#define HDMI_FC_ISCR2_1 0x10B1
++#define HDMI_FC_ISCR2_0 0x10B2
++#define HDMI_FC_DATAUTO0 0x10B3
++#define HDMI_FC_DATAUTO1 0x10B4
++#define HDMI_FC_DATAUTO2 0x10B5
++#define HDMI_FC_DATMAN 0x10B6
++#define HDMI_FC_DATAUTO3 0x10B7
++#define HDMI_FC_RDRB0 0x10B8
++#define HDMI_FC_RDRB1 0x10B9
++#define HDMI_FC_RDRB2 0x10BA
++#define HDMI_FC_RDRB3 0x10BB
++#define HDMI_FC_RDRB4 0x10BC
++#define HDMI_FC_RDRB5 0x10BD
++#define HDMI_FC_RDRB6 0x10BE
++#define HDMI_FC_RDRB7 0x10BF
++#define HDMI_FC_STAT0 0x10D0
++#define HDMI_FC_INT0 0x10D1
++#define HDMI_FC_MASK0 0x10D2
++#define HDMI_FC_POL0 0x10D3
++#define HDMI_FC_STAT1 0x10D4
++#define HDMI_FC_INT1 0x10D5
++#define HDMI_FC_MASK1 0x10D6
++#define HDMI_FC_POL1 0x10D7
++#define HDMI_FC_STAT2 0x10D8
++#define HDMI_FC_INT2 0x10D9
++#define HDMI_FC_MASK2 0x10DA
++#define HDMI_FC_POL2 0x10DB
++#define HDMI_FC_PRCONF 0x10E0
++
++#define HDMI_FC_GMD_STAT 0x1100
++#define HDMI_FC_GMD_EN 0x1101
++#define HDMI_FC_GMD_UP 0x1102
++#define HDMI_FC_GMD_CONF 0x1103
++#define HDMI_FC_GMD_HB 0x1104
++#define HDMI_FC_GMD_PB0 0x1105
++#define HDMI_FC_GMD_PB1 0x1106
++#define HDMI_FC_GMD_PB2 0x1107
++#define HDMI_FC_GMD_PB3 0x1108
++#define HDMI_FC_GMD_PB4 0x1109
++#define HDMI_FC_GMD_PB5 0x110A
++#define HDMI_FC_GMD_PB6 0x110B
++#define HDMI_FC_GMD_PB7 0x110C
++#define HDMI_FC_GMD_PB8 0x110D
++#define HDMI_FC_GMD_PB9 0x110E
++#define HDMI_FC_GMD_PB10 0x110F
++#define HDMI_FC_GMD_PB11 0x1110
++#define HDMI_FC_GMD_PB12 0x1111
++#define HDMI_FC_GMD_PB13 0x1112
++#define HDMI_FC_GMD_PB14 0x1113
++#define HDMI_FC_GMD_PB15 0x1114
++#define HDMI_FC_GMD_PB16 0x1115
++#define HDMI_FC_GMD_PB17 0x1116
++#define HDMI_FC_GMD_PB18 0x1117
++#define HDMI_FC_GMD_PB19 0x1118
++#define HDMI_FC_GMD_PB20 0x1119
++#define HDMI_FC_GMD_PB21 0x111A
++#define HDMI_FC_GMD_PB22 0x111B
++#define HDMI_FC_GMD_PB23 0x111C
++#define HDMI_FC_GMD_PB24 0x111D
++#define HDMI_FC_GMD_PB25 0x111E
++#define HDMI_FC_GMD_PB26 0x111F
++#define HDMI_FC_GMD_PB27 0x1120
++
++#define HDMI_FC_DBGFORCE 0x1200
++#define HDMI_FC_DBGAUD0CH0 0x1201
++#define HDMI_FC_DBGAUD1CH0 0x1202
++#define HDMI_FC_DBGAUD2CH0 0x1203
++#define HDMI_FC_DBGAUD0CH1 0x1204
++#define HDMI_FC_DBGAUD1CH1 0x1205
++#define HDMI_FC_DBGAUD2CH1 0x1206
++#define HDMI_FC_DBGAUD0CH2 0x1207
++#define HDMI_FC_DBGAUD1CH2 0x1208
++#define HDMI_FC_DBGAUD2CH2 0x1209
++#define HDMI_FC_DBGAUD0CH3 0x120A
++#define HDMI_FC_DBGAUD1CH3 0x120B
++#define HDMI_FC_DBGAUD2CH3 0x120C
++#define HDMI_FC_DBGAUD0CH4 0x120D
++#define HDMI_FC_DBGAUD1CH4 0x120E
++#define HDMI_FC_DBGAUD2CH4 0x120F
++#define HDMI_FC_DBGAUD0CH5 0x1210
++#define HDMI_FC_DBGAUD1CH5 0x1211
++#define HDMI_FC_DBGAUD2CH5 0x1212
++#define HDMI_FC_DBGAUD0CH6 0x1213
++#define HDMI_FC_DBGAUD1CH6 0x1214
++#define HDMI_FC_DBGAUD2CH6 0x1215
++#define HDMI_FC_DBGAUD0CH7 0x1216
++#define HDMI_FC_DBGAUD1CH7 0x1217
++#define HDMI_FC_DBGAUD2CH7 0x1218
++#define HDMI_FC_DBGTMDS0 0x1219
++#define HDMI_FC_DBGTMDS1 0x121A
++#define HDMI_FC_DBGTMDS2 0x121B
++
++/* HDMI Source PHY Registers */
++#define HDMI_PHY_CONF0 0x3000
++#define HDMI_PHY_TST0 0x3001
++#define HDMI_PHY_TST1 0x3002
++#define HDMI_PHY_TST2 0x3003
++#define HDMI_PHY_STAT0 0x3004
++#define HDMI_PHY_INT0 0x3005
++#define HDMI_PHY_MASK0 0x3006
++#define HDMI_PHY_POL0 0x3007
++
++/* HDMI Master PHY Registers */
++#define HDMI_PHY_I2CM_SLAVE_ADDR 0x3020
++#define HDMI_PHY_I2CM_ADDRESS_ADDR 0x3021
++#define HDMI_PHY_I2CM_DATAO_1_ADDR 0x3022
++#define HDMI_PHY_I2CM_DATAO_0_ADDR 0x3023
++#define HDMI_PHY_I2CM_DATAI_1_ADDR 0x3024
++#define HDMI_PHY_I2CM_DATAI_0_ADDR 0x3025
++#define HDMI_PHY_I2CM_OPERATION_ADDR 0x3026
++#define HDMI_PHY_I2CM_INT_ADDR 0x3027
++#define HDMI_PHY_I2CM_CTLINT_ADDR 0x3028
++#define HDMI_PHY_I2CM_DIV_ADDR 0x3029
++#define HDMI_PHY_I2CM_SOFTRSTZ_ADDR 0x302a
++#define HDMI_PHY_I2CM_SS_SCL_HCNT_1_ADDR 0x302b
++#define HDMI_PHY_I2CM_SS_SCL_HCNT_0_ADDR 0x302c
++#define HDMI_PHY_I2CM_SS_SCL_LCNT_1_ADDR 0x302d
++#define HDMI_PHY_I2CM_SS_SCL_LCNT_0_ADDR 0x302e
++#define HDMI_PHY_I2CM_FS_SCL_HCNT_1_ADDR 0x302f
++#define HDMI_PHY_I2CM_FS_SCL_HCNT_0_ADDR 0x3030
++#define HDMI_PHY_I2CM_FS_SCL_LCNT_1_ADDR 0x3031
++#define HDMI_PHY_I2CM_FS_SCL_LCNT_0_ADDR 0x3032
++
++/* Audio Sampler Registers */
++#define HDMI_AUD_CONF0 0x3100
++#define HDMI_AUD_CONF1 0x3101
++#define HDMI_AUD_INT 0x3102
++#define HDMI_AUD_CONF2 0x3103
++#define HDMI_AUD_N1 0x3200
++#define HDMI_AUD_N2 0x3201
++#define HDMI_AUD_N3 0x3202
++#define HDMI_AUD_CTS1 0x3203
++#define HDMI_AUD_CTS2 0x3204
++#define HDMI_AUD_CTS3 0x3205
++#define HDMI_AUD_INPUTCLKFS 0x3206
++#define HDMI_AUD_SPDIFINT 0x3302
++#define HDMI_AUD_CONF0_HBR 0x3400
++#define HDMI_AUD_HBR_STATUS 0x3401
++#define HDMI_AUD_HBR_INT 0x3402
++#define HDMI_AUD_HBR_POL 0x3403
++#define HDMI_AUD_HBR_MASK 0x3404
++
++/* Generic Parallel Audio Interface Registers */
++/* Not used as GPAUD interface is not enabled in hw */
++#define HDMI_GP_CONF0 0x3500
++#define HDMI_GP_CONF1 0x3501
++#define HDMI_GP_CONF2 0x3502
++#define HDMI_GP_STAT 0x3503
++#define HDMI_GP_INT 0x3504
++#define HDMI_GP_MASK 0x3505
++#define HDMI_GP_POL 0x3506
++
++/* Audio DMA Registers */
++#define HDMI_AHB_DMA_CONF0 0x3600
++#define HDMI_AHB_DMA_START 0x3601
++#define HDMI_AHB_DMA_STOP 0x3602
++#define HDMI_AHB_DMA_THRSLD 0x3603
++#define HDMI_AHB_DMA_STRADDR0 0x3604
++#define HDMI_AHB_DMA_STRADDR1 0x3605
++#define HDMI_AHB_DMA_STRADDR2 0x3606
++#define HDMI_AHB_DMA_STRADDR3 0x3607
++#define HDMI_AHB_DMA_STPADDR0 0x3608
++#define HDMI_AHB_DMA_STPADDR1 0x3609
++#define HDMI_AHB_DMA_STPADDR2 0x360a
++#define HDMI_AHB_DMA_STPADDR3 0x360b
++#define HDMI_AHB_DMA_BSTADDR0 0x360c
++#define HDMI_AHB_DMA_BSTADDR1 0x360d
++#define HDMI_AHB_DMA_BSTADDR2 0x360e
++#define HDMI_AHB_DMA_BSTADDR3 0x360f
++#define HDMI_AHB_DMA_MBLENGTH0 0x3610
++#define HDMI_AHB_DMA_MBLENGTH1 0x3611
++#define HDMI_AHB_DMA_STAT 0x3612
++#define HDMI_AHB_DMA_INT 0x3613
++#define HDMI_AHB_DMA_MASK 0x3614
++#define HDMI_AHB_DMA_POL 0x3615
++#define HDMI_AHB_DMA_CONF1 0x3616
++#define HDMI_AHB_DMA_BUFFSTAT 0x3617
++#define HDMI_AHB_DMA_BUFFINT 0x3618
++#define HDMI_AHB_DMA_BUFFMASK 0x3619
++#define HDMI_AHB_DMA_BUFFPOL 0x361a
++
++/* Main Controller Registers */
++#define HDMI_MC_SFRDIV 0x4000
++#define HDMI_MC_CLKDIS 0x4001
++#define HDMI_MC_SWRSTZ 0x4002
++#define HDMI_MC_OPCTRL 0x4003
++#define HDMI_MC_FLOWCTRL 0x4004
++#define HDMI_MC_PHYRSTZ 0x4005
++#define HDMI_MC_LOCKONCLOCK 0x4006
++#define HDMI_MC_HEACPHY_RST 0x4007
++
++/* Color Space Converter Registers */
++#define HDMI_CSC_CFG 0x4100
++#define HDMI_CSC_SCALE 0x4101
++#define HDMI_CSC_COEF_A1_MSB 0x4102
++#define HDMI_CSC_COEF_A1_LSB 0x4103
++#define HDMI_CSC_COEF_A2_MSB 0x4104
++#define HDMI_CSC_COEF_A2_LSB 0x4105
++#define HDMI_CSC_COEF_A3_MSB 0x4106
++#define HDMI_CSC_COEF_A3_LSB 0x4107
++#define HDMI_CSC_COEF_A4_MSB 0x4108
++#define HDMI_CSC_COEF_A4_LSB 0x4109
++#define HDMI_CSC_COEF_B1_MSB 0x410A
++#define HDMI_CSC_COEF_B1_LSB 0x410B
++#define HDMI_CSC_COEF_B2_MSB 0x410C
++#define HDMI_CSC_COEF_B2_LSB 0x410D
++#define HDMI_CSC_COEF_B3_MSB 0x410E
++#define HDMI_CSC_COEF_B3_LSB 0x410F
++#define HDMI_CSC_COEF_B4_MSB 0x4110
++#define HDMI_CSC_COEF_B4_LSB 0x4111
++#define HDMI_CSC_COEF_C1_MSB 0x4112
++#define HDMI_CSC_COEF_C1_LSB 0x4113
++#define HDMI_CSC_COEF_C2_MSB 0x4114
++#define HDMI_CSC_COEF_C2_LSB 0x4115
++#define HDMI_CSC_COEF_C3_MSB 0x4116
++#define HDMI_CSC_COEF_C3_LSB 0x4117
++#define HDMI_CSC_COEF_C4_MSB 0x4118
++#define HDMI_CSC_COEF_C4_LSB 0x4119
++
++/* HDCP Encryption Engine Registers */
++#define HDMI_A_HDCPCFG0 0x5000
++#define HDMI_A_HDCPCFG1 0x5001
++#define HDMI_A_HDCPOBS0 0x5002
++#define HDMI_A_HDCPOBS1 0x5003
++#define HDMI_A_HDCPOBS2 0x5004
++#define HDMI_A_HDCPOBS3 0x5005
++#define HDMI_A_APIINTCLR 0x5006
++#define HDMI_A_APIINTSTAT 0x5007
++#define HDMI_A_APIINTMSK 0x5008
++#define HDMI_A_VIDPOLCFG 0x5009
++#define HDMI_A_OESSWCFG 0x500A
++#define HDMI_A_TIMER1SETUP0 0x500B
++#define HDMI_A_TIMER1SETUP1 0x500C
++#define HDMI_A_TIMER2SETUP0 0x500D
++#define HDMI_A_TIMER2SETUP1 0x500E
++#define HDMI_A_100MSCFG 0x500F
++#define HDMI_A_2SCFG0 0x5010
++#define HDMI_A_2SCFG1 0x5011
++#define HDMI_A_5SCFG0 0x5012
++#define HDMI_A_5SCFG1 0x5013
++#define HDMI_A_SRMVERLSB 0x5014
++#define HDMI_A_SRMVERMSB 0x5015
++#define HDMI_A_SRMCTRL 0x5016
++#define HDMI_A_SFRSETUP 0x5017
++#define HDMI_A_I2CHSETUP 0x5018
++#define HDMI_A_INTSETUP 0x5019
++#define HDMI_A_PRESETUP 0x501A
++#define HDMI_A_SRM_BASE 0x5020
++
++/* CEC Engine Registers */
++#define HDMI_CEC_CTRL 0x7D00
++#define HDMI_CEC_STAT 0x7D01
++#define HDMI_CEC_MASK 0x7D02
++#define HDMI_CEC_POLARITY 0x7D03
++#define HDMI_CEC_INT 0x7D04
++#define HDMI_CEC_ADDR_L 0x7D05
++#define HDMI_CEC_ADDR_H 0x7D06
++#define HDMI_CEC_TX_CNT 0x7D07
++#define HDMI_CEC_RX_CNT 0x7D08
++#define HDMI_CEC_TX_DATA0 0x7D10
++#define HDMI_CEC_TX_DATA1 0x7D11
++#define HDMI_CEC_TX_DATA2 0x7D12
++#define HDMI_CEC_TX_DATA3 0x7D13
++#define HDMI_CEC_TX_DATA4 0x7D14
++#define HDMI_CEC_TX_DATA5 0x7D15
++#define HDMI_CEC_TX_DATA6 0x7D16
++#define HDMI_CEC_TX_DATA7 0x7D17
++#define HDMI_CEC_TX_DATA8 0x7D18
++#define HDMI_CEC_TX_DATA9 0x7D19
++#define HDMI_CEC_TX_DATA10 0x7D1a
++#define HDMI_CEC_TX_DATA11 0x7D1b
++#define HDMI_CEC_TX_DATA12 0x7D1c
++#define HDMI_CEC_TX_DATA13 0x7D1d
++#define HDMI_CEC_TX_DATA14 0x7D1e
++#define HDMI_CEC_TX_DATA15 0x7D1f
++#define HDMI_CEC_RX_DATA0 0x7D20
++#define HDMI_CEC_RX_DATA1 0x7D21
++#define HDMI_CEC_RX_DATA2 0x7D22
++#define HDMI_CEC_RX_DATA3 0x7D23
++#define HDMI_CEC_RX_DATA4 0x7D24
++#define HDMI_CEC_RX_DATA5 0x7D25
++#define HDMI_CEC_RX_DATA6 0x7D26
++#define HDMI_CEC_RX_DATA7 0x7D27
++#define HDMI_CEC_RX_DATA8 0x7D28
++#define HDMI_CEC_RX_DATA9 0x7D29
++#define HDMI_CEC_RX_DATA10 0x7D2a
++#define HDMI_CEC_RX_DATA11 0x7D2b
++#define HDMI_CEC_RX_DATA12 0x7D2c
++#define HDMI_CEC_RX_DATA13 0x7D2d
++#define HDMI_CEC_RX_DATA14 0x7D2e
++#define HDMI_CEC_RX_DATA15 0x7D2f
++#define HDMI_CEC_LOCK 0x7D30
++#define HDMI_CEC_WKUPCTRL 0x7D31
++
++/* I2C Master Registers (E-DDC) */
++#define HDMI_I2CM_SLAVE 0x7E00
++#define HDMI_I2CMESS 0x7E01
++#define HDMI_I2CM_DATAO 0x7E02
++#define HDMI_I2CM_DATAI 0x7E03
++#define HDMI_I2CM_OPERATION 0x7E04
++#define HDMI_I2CM_INT 0x7E05
++#define HDMI_I2CM_CTLINT 0x7E06
++#define HDMI_I2CM_DIV 0x7E07
++#define HDMI_I2CM_SEGADDR 0x7E08
++#define HDMI_I2CM_SOFTRSTZ 0x7E09
++#define HDMI_I2CM_SEGPTR 0x7E0A
++#define HDMI_I2CM_SS_SCL_HCNT_1_ADDR 0x7E0B
++#define HDMI_I2CM_SS_SCL_HCNT_0_ADDR 0x7E0C
++#define HDMI_I2CM_SS_SCL_LCNT_1_ADDR 0x7E0D
++#define HDMI_I2CM_SS_SCL_LCNT_0_ADDR 0x7E0E
++#define HDMI_I2CM_FS_SCL_HCNT_1_ADDR 0x7E0F
++#define HDMI_I2CM_FS_SCL_HCNT_0_ADDR 0x7E10
++#define HDMI_I2CM_FS_SCL_LCNT_1_ADDR 0x7E11
++#define HDMI_I2CM_FS_SCL_LCNT_0_ADDR 0x7E12
++
++/* Random Number Generator Registers (RNG) */
++#define HDMI_RNG_BASE 0x8000
++
++
++/*
++ * Register field definitions
++ */
++enum {
++/* IH_FC_INT2 field values */
++ HDMI_IH_FC_INT2_OVERFLOW_MASK = 0x03,
++ HDMI_IH_FC_INT2_LOW_PRIORITY_OVERFLOW = 0x02,
++ HDMI_IH_FC_INT2_HIGH_PRIORITY_OVERFLOW = 0x01,
++
++/* IH_FC_STAT2 field values */
++ HDMI_IH_FC_STAT2_OVERFLOW_MASK = 0x03,
++ HDMI_IH_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02,
++ HDMI_IH_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01,
++
++/* IH_PHY_STAT0 field values */
++ HDMI_IH_PHY_STAT0_RX_SENSE3 = 0x20,
++ HDMI_IH_PHY_STAT0_RX_SENSE2 = 0x10,
++ HDMI_IH_PHY_STAT0_RX_SENSE1 = 0x8,
++ HDMI_IH_PHY_STAT0_RX_SENSE0 = 0x4,
++ HDMI_IH_PHY_STAT0_TX_PHY_LOCK = 0x2,
++ HDMI_IH_PHY_STAT0_HPD = 0x1,
++
++/* IH_MUTE_I2CMPHY_STAT0 field values */
++ HDMI_IH_MUTE_I2CMPHY_STAT0_I2CMPHYDONE = 0x2,
++ HDMI_IH_MUTE_I2CMPHY_STAT0_I2CMPHYERROR = 0x1,
++
++/* IH_AHBDMAAUD_STAT0 field values */
++ HDMI_IH_AHBDMAAUD_STAT0_ERROR = 0x20,
++ HDMI_IH_AHBDMAAUD_STAT0_LOST = 0x10,
++ HDMI_IH_AHBDMAAUD_STAT0_RETRY = 0x08,
++ HDMI_IH_AHBDMAAUD_STAT0_DONE = 0x04,
++ HDMI_IH_AHBDMAAUD_STAT0_BUFFFULL = 0x02,
++ HDMI_IH_AHBDMAAUD_STAT0_BUFFEMPTY = 0x01,
++
++/* IH_MUTE_FC_STAT2 field values */
++ HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK = 0x03,
++ HDMI_IH_MUTE_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02,
++ HDMI_IH_MUTE_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01,
++
++/* IH_MUTE_AHBDMAAUD_STAT0 field values */
++ HDMI_IH_MUTE_AHBDMAAUD_STAT0_ERROR = 0x20,
++ HDMI_IH_MUTE_AHBDMAAUD_STAT0_LOST = 0x10,
++ HDMI_IH_MUTE_AHBDMAAUD_STAT0_RETRY = 0x08,
++ HDMI_IH_MUTE_AHBDMAAUD_STAT0_DONE = 0x04,
++ HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFFULL = 0x02,
++ HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFEMPTY = 0x01,
++
++/* IH_MUTE field values */
++ HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT = 0x2,
++ HDMI_IH_MUTE_MUTE_ALL_INTERRUPT = 0x1,
++
++/* TX_INVID0 field values */
++ HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_MASK = 0x80,
++ HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_ENABLE = 0x80,
++ HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE = 0x00,
++ HDMI_TX_INVID0_VIDEO_MAPPING_MASK = 0x1F,
++ HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET = 0,
++
++/* TX_INSTUFFING field values */
++ HDMI_TX_INSTUFFING_BDBDATA_STUFFING_MASK = 0x4,
++ HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE = 0x4,
++ HDMI_TX_INSTUFFING_BDBDATA_STUFFING_DISABLE = 0x0,
++ HDMI_TX_INSTUFFING_RCRDATA_STUFFING_MASK = 0x2,
++ HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE = 0x2,
++ HDMI_TX_INSTUFFING_RCRDATA_STUFFING_DISABLE = 0x0,
++ HDMI_TX_INSTUFFING_GYDATA_STUFFING_MASK = 0x1,
++ HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE = 0x1,
++ HDMI_TX_INSTUFFING_GYDATA_STUFFING_DISABLE = 0x0,
++
++/* VP_PR_CD field values */
++ HDMI_VP_PR_CD_COLOR_DEPTH_MASK = 0xF0,
++ HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET = 4,
++ HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK = 0x0F,
++ HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET = 0,
++
++/* VP_STUFF field values */
++ HDMI_VP_STUFF_IDEFAULT_PHASE_MASK = 0x20,
++ HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET = 5,
++ HDMI_VP_STUFF_IFIX_PP_TO_LAST_MASK = 0x10,
++ HDMI_VP_STUFF_IFIX_PP_TO_LAST_OFFSET = 4,
++ HDMI_VP_STUFF_ICX_GOTO_P0_ST_MASK = 0x8,
++ HDMI_VP_STUFF_ICX_GOTO_P0_ST_OFFSET = 3,
++ HDMI_VP_STUFF_YCC422_STUFFING_MASK = 0x4,
++ HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE = 0x4,
++ HDMI_VP_STUFF_YCC422_STUFFING_DIRECT_MODE = 0x0,
++ HDMI_VP_STUFF_PP_STUFFING_MASK = 0x2,
++ HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE = 0x2,
++ HDMI_VP_STUFF_PP_STUFFING_DIRECT_MODE = 0x0,
++ HDMI_VP_STUFF_PR_STUFFING_MASK = 0x1,
++ HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE = 0x1,
++ HDMI_VP_STUFF_PR_STUFFING_DIRECT_MODE = 0x0,
++
++/* VP_CONF field values */
++ HDMI_VP_CONF_BYPASS_EN_MASK = 0x40,
++ HDMI_VP_CONF_BYPASS_EN_ENABLE = 0x40,
++ HDMI_VP_CONF_BYPASS_EN_DISABLE = 0x00,
++ HDMI_VP_CONF_PP_EN_ENMASK = 0x20,
++ HDMI_VP_CONF_PP_EN_ENABLE = 0x20,
++ HDMI_VP_CONF_PP_EN_DISABLE = 0x00,
++ HDMI_VP_CONF_PR_EN_MASK = 0x10,
++ HDMI_VP_CONF_PR_EN_ENABLE = 0x10,
++ HDMI_VP_CONF_PR_EN_DISABLE = 0x00,
++ HDMI_VP_CONF_YCC422_EN_MASK = 0x8,
++ HDMI_VP_CONF_YCC422_EN_ENABLE = 0x8,
++ HDMI_VP_CONF_YCC422_EN_DISABLE = 0x0,
++ HDMI_VP_CONF_BYPASS_SELECT_MASK = 0x4,
++ HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER = 0x4,
++ HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER = 0x0,
++ HDMI_VP_CONF_OUTPUT_SELECTOR_MASK = 0x3,
++ HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS = 0x3,
++ HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422 = 0x1,
++ HDMI_VP_CONF_OUTPUT_SELECTOR_PP = 0x0,
++
++/* VP_REMAP field values */
++ HDMI_VP_REMAP_MASK = 0x3,
++ HDMI_VP_REMAP_YCC422_24bit = 0x2,
++ HDMI_VP_REMAP_YCC422_20bit = 0x1,
++ HDMI_VP_REMAP_YCC422_16bit = 0x0,
++
++/* FC_INVIDCONF field values */
++ HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK = 0x80,
++ HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE = 0x80,
++ HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE = 0x00,
++ HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_MASK = 0x40,
++ HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH = 0x40,
++ HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
++ HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_MASK = 0x20,
++ HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH = 0x20,
++ HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
++ HDMI_FC_INVIDCONF_DE_IN_POLARITY_MASK = 0x10,
++ HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH = 0x10,
++ HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW = 0x00,
++ HDMI_FC_INVIDCONF_DVI_MODEZ_MASK = 0x8,
++ HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE = 0x8,
++ HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE = 0x0,
++ HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_MASK = 0x2,
++ HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH = 0x2,
++ HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW = 0x0,
++ HDMI_FC_INVIDCONF_IN_I_P_MASK = 0x1,
++ HDMI_FC_INVIDCONF_IN_I_P_INTERLACED = 0x1,
++ HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE = 0x0,
++
++/* FC_AUDICONF0 field values */
++ HDMI_FC_AUDICONF0_CC_OFFSET = 4,
++ HDMI_FC_AUDICONF0_CC_MASK = 0x70,
++ HDMI_FC_AUDICONF0_CT_OFFSET = 0,
++ HDMI_FC_AUDICONF0_CT_MASK = 0xF,
++
++/* FC_AUDICONF1 field values */
++ HDMI_FC_AUDICONF1_SS_OFFSET = 3,
++ HDMI_FC_AUDICONF1_SS_MASK = 0x18,
++ HDMI_FC_AUDICONF1_SF_OFFSET = 0,
++ HDMI_FC_AUDICONF1_SF_MASK = 0x7,
++
++/* FC_AUDICONF3 field values */
++ HDMI_FC_AUDICONF3_LFEPBL_OFFSET = 5,
++ HDMI_FC_AUDICONF3_LFEPBL_MASK = 0x60,
++ HDMI_FC_AUDICONF3_DM_INH_OFFSET = 4,
++ HDMI_FC_AUDICONF3_DM_INH_MASK = 0x10,
++ HDMI_FC_AUDICONF3_LSV_OFFSET = 0,
++ HDMI_FC_AUDICONF3_LSV_MASK = 0xF,
++
++/* FC_AUDSCHNLS0 field values */
++ HDMI_FC_AUDSCHNLS0_CGMSA_OFFSET = 4,
++ HDMI_FC_AUDSCHNLS0_CGMSA_MASK = 0x30,
++ HDMI_FC_AUDSCHNLS0_COPYRIGHT_OFFSET = 0,
++ HDMI_FC_AUDSCHNLS0_COPYRIGHT_MASK = 0x01,
++
++/* FC_AUDSCHNLS3-6 field values */
++ HDMI_FC_AUDSCHNLS3_OIEC_CH0_OFFSET = 0,
++ HDMI_FC_AUDSCHNLS3_OIEC_CH0_MASK = 0x0f,
++ HDMI_FC_AUDSCHNLS3_OIEC_CH1_OFFSET = 4,
++ HDMI_FC_AUDSCHNLS3_OIEC_CH1_MASK = 0xf0,
++ HDMI_FC_AUDSCHNLS4_OIEC_CH2_OFFSET = 0,
++ HDMI_FC_AUDSCHNLS4_OIEC_CH2_MASK = 0x0f,
++ HDMI_FC_AUDSCHNLS4_OIEC_CH3_OFFSET = 4,
++ HDMI_FC_AUDSCHNLS4_OIEC_CH3_MASK = 0xf0,
++
++ HDMI_FC_AUDSCHNLS5_OIEC_CH0_OFFSET = 0,
++ HDMI_FC_AUDSCHNLS5_OIEC_CH0_MASK = 0x0f,
++ HDMI_FC_AUDSCHNLS5_OIEC_CH1_OFFSET = 4,
++ HDMI_FC_AUDSCHNLS5_OIEC_CH1_MASK = 0xf0,
++ HDMI_FC_AUDSCHNLS6_OIEC_CH2_OFFSET = 0,
++ HDMI_FC_AUDSCHNLS6_OIEC_CH2_MASK = 0x0f,
++ HDMI_FC_AUDSCHNLS6_OIEC_CH3_OFFSET = 4,
++ HDMI_FC_AUDSCHNLS6_OIEC_CH3_MASK = 0xf0,
++
++/* HDMI_FC_AUDSCHNLS7 field values */
++ HDMI_FC_AUDSCHNLS7_ACCURACY_OFFSET = 4,
++ HDMI_FC_AUDSCHNLS7_ACCURACY_MASK = 0x30,
++
++/* HDMI_FC_AUDSCHNLS8 field values */
++ HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_MASK = 0xf0,
++ HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_OFFSET = 4,
++ HDMI_FC_AUDSCHNLS8_WORDLEGNTH_MASK = 0x0f,
++ HDMI_FC_AUDSCHNLS8_WORDLEGNTH_OFFSET = 0,
++
++/* FC_AUDSCONF field values */
++ HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_MASK = 0xF0,
++ HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_OFFSET = 4,
++ HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK = 0x1,
++ HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_OFFSET = 0,
++ HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1 = 0x1,
++ HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0 = 0x0,
++
++/* FC_STAT2 field values */
++ HDMI_FC_STAT2_OVERFLOW_MASK = 0x03,
++ HDMI_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02,
++ HDMI_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01,
++
++/* FC_INT2 field values */
++ HDMI_FC_INT2_OVERFLOW_MASK = 0x03,
++ HDMI_FC_INT2_LOW_PRIORITY_OVERFLOW = 0x02,
++ HDMI_FC_INT2_HIGH_PRIORITY_OVERFLOW = 0x01,
++
++/* FC_MASK2 field values */
++ HDMI_FC_MASK2_OVERFLOW_MASK = 0x03,
++ HDMI_FC_MASK2_LOW_PRIORITY_OVERFLOW = 0x02,
++ HDMI_FC_MASK2_HIGH_PRIORITY_OVERFLOW = 0x01,
++
++/* FC_PRCONF field values */
++ HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK = 0xF0,
++ HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET = 4,
++ HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK = 0x0F,
++ HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET = 0,
++
++/* FC_AVICONF0-FC_AVICONF3 field values */
++ HDMI_FC_AVICONF0_PIX_FMT_MASK = 0x03,
++ HDMI_FC_AVICONF0_PIX_FMT_RGB = 0x00,
++ HDMI_FC_AVICONF0_PIX_FMT_YCBCR422 = 0x01,
++ HDMI_FC_AVICONF0_PIX_FMT_YCBCR444 = 0x02,
++ HDMI_FC_AVICONF0_ACTIVE_FMT_MASK = 0x40,
++ HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT = 0x40,
++ HDMI_FC_AVICONF0_ACTIVE_FMT_NO_INFO = 0x00,
++ HDMI_FC_AVICONF0_BAR_DATA_MASK = 0x0C,
++ HDMI_FC_AVICONF0_BAR_DATA_NO_DATA = 0x00,
++ HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR = 0x04,
++ HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR = 0x08,
++ HDMI_FC_AVICONF0_BAR_DATA_VERT_HORIZ_BAR = 0x0C,
++ HDMI_FC_AVICONF0_SCAN_INFO_MASK = 0x30,
++ HDMI_FC_AVICONF0_SCAN_INFO_OVERSCAN = 0x10,
++ HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN = 0x20,
++ HDMI_FC_AVICONF0_SCAN_INFO_NODATA = 0x00,
++
++ HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_MASK = 0x0F,
++ HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_USE_CODED = 0x08,
++ HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3 = 0x09,
++ HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9 = 0x0A,
++ HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_14_9 = 0x0B,
++ HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_MASK = 0x30,
++ HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_NO_DATA = 0x00,
++ HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3 = 0x10,
++ HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9 = 0x20,
++ HDMI_FC_AVICONF1_COLORIMETRY_MASK = 0xC0,
++ HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA = 0x00,
++ HDMI_FC_AVICONF1_COLORIMETRY_SMPTE = 0x40,
++ HDMI_FC_AVICONF1_COLORIMETRY_ITUR = 0x80,
++ HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO = 0xC0,
++
++ HDMI_FC_AVICONF2_SCALING_MASK = 0x03,
++ HDMI_FC_AVICONF2_SCALING_NONE = 0x00,
++ HDMI_FC_AVICONF2_SCALING_HORIZ = 0x01,
++ HDMI_FC_AVICONF2_SCALING_VERT = 0x02,
++ HDMI_FC_AVICONF2_SCALING_HORIZ_VERT = 0x03,
++ HDMI_FC_AVICONF2_RGB_QUANT_MASK = 0x0C,
++ HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT = 0x00,
++ HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE = 0x04,
++ HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE = 0x08,
++ HDMI_FC_AVICONF2_EXT_COLORIMETRY_MASK = 0x70,
++ HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601 = 0x00,
++ HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709 = 0x10,
++ HDMI_FC_AVICONF2_EXT_COLORIMETRY_SYCC601 = 0x20,
++ HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_YCC601 = 0x30,
++ HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_RGB = 0x40,
++ HDMI_FC_AVICONF2_IT_CONTENT_MASK = 0x80,
++ HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA = 0x00,
++ HDMI_FC_AVICONF2_IT_CONTENT_VALID = 0x80,
++
++ HDMI_FC_AVICONF3_IT_CONTENT_TYPE_MASK = 0x03,
++ HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS = 0x00,
++ HDMI_FC_AVICONF3_IT_CONTENT_TYPE_PHOTO = 0x01,
++ HDMI_FC_AVICONF3_IT_CONTENT_TYPE_CINEMA = 0x02,
++ HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GAME = 0x03,
++ HDMI_FC_AVICONF3_QUANT_RANGE_MASK = 0x0C,
++ HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED = 0x00,
++ HDMI_FC_AVICONF3_QUANT_RANGE_FULL = 0x04,
++
++/* FC_DBGFORCE field values */
++ HDMI_FC_DBGFORCE_FORCEAUDIO = 0x10,
++ HDMI_FC_DBGFORCE_FORCEVIDEO = 0x1,
++
++/* PHY_CONF0 field values */
++ HDMI_PHY_CONF0_PDZ_MASK = 0x80,
++ HDMI_PHY_CONF0_PDZ_OFFSET = 7,
++ HDMI_PHY_CONF0_ENTMDS_MASK = 0x40,
++ HDMI_PHY_CONF0_ENTMDS_OFFSET = 6,
++ HDMI_PHY_CONF0_SPARECTRL = 0x20,
++ HDMI_PHY_CONF0_GEN2_PDDQ_MASK = 0x10,
++ HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET = 4,
++ HDMI_PHY_CONF0_GEN2_TXPWRON_MASK = 0x8,
++ HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET = 3,
++ HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_MASK = 0x4,
++ HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_OFFSET = 2,
++ HDMI_PHY_CONF0_SELDATAENPOL_MASK = 0x2,
++ HDMI_PHY_CONF0_SELDATAENPOL_OFFSET = 1,
++ HDMI_PHY_CONF0_SELDIPIF_MASK = 0x1,
++ HDMI_PHY_CONF0_SELDIPIF_OFFSET = 0,
++
++/* PHY_TST0 field values */
++ HDMI_PHY_TST0_TSTCLR_MASK = 0x20,
++ HDMI_PHY_TST0_TSTCLR_OFFSET = 5,
++ HDMI_PHY_TST0_TSTEN_MASK = 0x10,
++ HDMI_PHY_TST0_TSTEN_OFFSET = 4,
++ HDMI_PHY_TST0_TSTCLK_MASK = 0x1,
++ HDMI_PHY_TST0_TSTCLK_OFFSET = 0,
++
++/* PHY_STAT0 field values */
++ HDMI_PHY_RX_SENSE3 = 0x80,
++ HDMI_PHY_RX_SENSE2 = 0x40,
++ HDMI_PHY_RX_SENSE1 = 0x20,
++ HDMI_PHY_RX_SENSE0 = 0x10,
++ HDMI_PHY_HPD = 0x02,
++ HDMI_PHY_TX_PHY_LOCK = 0x01,
++
++/* PHY_I2CM_SLAVE_ADDR field values */
++ HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69,
++ HDMI_PHY_I2CM_SLAVE_ADDR_HEAC_PHY = 0x49,
++
++/* PHY_I2CM_OPERATION_ADDR field values */
++ HDMI_PHY_I2CM_OPERATION_ADDR_WRITE = 0x10,
++ HDMI_PHY_I2CM_OPERATION_ADDR_READ = 0x1,
++
++/* HDMI_PHY_I2CM_INT_ADDR */
++ HDMI_PHY_I2CM_INT_ADDR_DONE_POL = 0x08,
++ HDMI_PHY_I2CM_INT_ADDR_DONE_MASK = 0x04,
++
++/* HDMI_PHY_I2CM_CTLINT_ADDR */
++ HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL = 0x80,
++ HDMI_PHY_I2CM_CTLINT_ADDR_NAC_MASK = 0x40,
++ HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL = 0x08,
++ HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_MASK = 0x04,
++
++/* AUD_CTS3 field values */
++ HDMI_AUD_CTS3_N_SHIFT_OFFSET = 5,
++ HDMI_AUD_CTS3_N_SHIFT_MASK = 0xe0,
++ HDMI_AUD_CTS3_N_SHIFT_1 = 0,
++ HDMI_AUD_CTS3_N_SHIFT_16 = 0x20,
++ HDMI_AUD_CTS3_N_SHIFT_32 = 0x40,
++ HDMI_AUD_CTS3_N_SHIFT_64 = 0x60,
++ HDMI_AUD_CTS3_N_SHIFT_128 = 0x80,
++ HDMI_AUD_CTS3_N_SHIFT_256 = 0xa0,
++ /* note that the CTS3 MANUAL bit has been removed
++ from our part. Can't set it, will read as 0. */
++ HDMI_AUD_CTS3_CTS_MANUAL = 0x10,
++ HDMI_AUD_CTS3_AUDCTS19_16_MASK = 0x0f,
++
++/* AHB_DMA_CONF0 field values */
++ HDMI_AHB_DMA_CONF0_SW_FIFO_RST_OFFSET = 7,
++ HDMI_AHB_DMA_CONF0_SW_FIFO_RST_MASK = 0x80,
++ HDMI_AHB_DMA_CONF0_HBR = 0x10,
++ HDMI_AHB_DMA_CONF0_EN_HLOCK_OFFSET = 3,
++ HDMI_AHB_DMA_CONF0_EN_HLOCK_MASK = 0x08,
++ HDMI_AHB_DMA_CONF0_INCR_TYPE_OFFSET = 1,
++ HDMI_AHB_DMA_CONF0_INCR_TYPE_MASK = 0x06,
++ HDMI_AHB_DMA_CONF0_INCR4 = 0x0,
++ HDMI_AHB_DMA_CONF0_INCR8 = 0x2,
++ HDMI_AHB_DMA_CONF0_INCR16 = 0x4,
++ HDMI_AHB_DMA_CONF0_BURST_MODE = 0x1,
++
++/* HDMI_AHB_DMA_START field values */
++ HDMI_AHB_DMA_START_START_OFFSET = 0,
++ HDMI_AHB_DMA_START_START_MASK = 0x01,
++
++/* HDMI_AHB_DMA_STOP field values */
++ HDMI_AHB_DMA_STOP_STOP_OFFSET = 0,
++ HDMI_AHB_DMA_STOP_STOP_MASK = 0x01,
++
++/* AHB_DMA_STAT, AHB_DMA_INT, AHB_DMA_MASK, AHB_DMA_POL field values */
++ HDMI_AHB_DMA_DONE = 0x80,
++ HDMI_AHB_DMA_RETRY_SPLIT = 0x40,
++ HDMI_AHB_DMA_LOSTOWNERSHIP = 0x20,
++ HDMI_AHB_DMA_ERROR = 0x10,
++ HDMI_AHB_DMA_FIFO_THREMPTY = 0x04,
++ HDMI_AHB_DMA_FIFO_FULL = 0x02,
++ HDMI_AHB_DMA_FIFO_EMPTY = 0x01,
++
++/* AHB_DMA_BUFFSTAT, AHB_DMA_BUFFINT, AHB_DMA_BUFFMASK, AHB_DMA_BUFFPOL field values */
++ HDMI_AHB_DMA_BUFFSTAT_FULL = 0x02,
++ HDMI_AHB_DMA_BUFFSTAT_EMPTY = 0x01,
++
++/* MC_CLKDIS field values */
++ HDMI_MC_CLKDIS_HDCPCLK_DISABLE = 0x40,
++ HDMI_MC_CLKDIS_CECCLK_DISABLE = 0x20,
++ HDMI_MC_CLKDIS_CSCCLK_DISABLE = 0x10,
++ HDMI_MC_CLKDIS_AUDCLK_DISABLE = 0x8,
++ HDMI_MC_CLKDIS_PREPCLK_DISABLE = 0x4,
++ HDMI_MC_CLKDIS_TMDSCLK_DISABLE = 0x2,
++ HDMI_MC_CLKDIS_PIXELCLK_DISABLE = 0x1,
++
++/* MC_SWRSTZ field values */
++ HDMI_MC_SWRSTZ_TMDSSWRST_REQ = 0x02,
++
++/* MC_FLOWCTRL field values */
++ HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_MASK = 0x1,
++ HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH = 0x1,
++ HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS = 0x0,
++
++/* MC_PHYRSTZ field values */
++ HDMI_MC_PHYRSTZ_ASSERT = 0x0,
++ HDMI_MC_PHYRSTZ_DEASSERT = 0x1,
++
++/* MC_HEACPHY_RST field values */
++ HDMI_MC_HEACPHY_RST_ASSERT = 0x1,
++ HDMI_MC_HEACPHY_RST_DEASSERT = 0x0,
++
++/* CSC_CFG field values */
++ HDMI_CSC_CFG_INTMODE_MASK = 0x30,
++ HDMI_CSC_CFG_INTMODE_OFFSET = 4,
++ HDMI_CSC_CFG_INTMODE_DISABLE = 0x00,
++ HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1 = 0x10,
++ HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA2 = 0x20,
++ HDMI_CSC_CFG_DECMODE_MASK = 0x3,
++ HDMI_CSC_CFG_DECMODE_OFFSET = 0,
++ HDMI_CSC_CFG_DECMODE_DISABLE = 0x0,
++ HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA1 = 0x1,
++ HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA2 = 0x2,
++ HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3 = 0x3,
++
++/* CSC_SCALE field values */
++ HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK = 0xF0,
++ HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP = 0x00,
++ HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP = 0x50,
++ HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP = 0x60,
++ HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP = 0x70,
++ HDMI_CSC_SCALE_CSCSCALE_MASK = 0x03,
++
++/* A_HDCPCFG0 field values */
++ HDMI_A_HDCPCFG0_ELVENA_MASK = 0x80,
++ HDMI_A_HDCPCFG0_ELVENA_ENABLE = 0x80,
++ HDMI_A_HDCPCFG0_ELVENA_DISABLE = 0x00,
++ HDMI_A_HDCPCFG0_I2CFASTMODE_MASK = 0x40,
++ HDMI_A_HDCPCFG0_I2CFASTMODE_ENABLE = 0x40,
++ HDMI_A_HDCPCFG0_I2CFASTMODE_DISABLE = 0x00,
++ HDMI_A_HDCPCFG0_BYPENCRYPTION_MASK = 0x20,
++ HDMI_A_HDCPCFG0_BYPENCRYPTION_ENABLE = 0x20,
++ HDMI_A_HDCPCFG0_BYPENCRYPTION_DISABLE = 0x00,
++ HDMI_A_HDCPCFG0_SYNCRICHECK_MASK = 0x10,
++ HDMI_A_HDCPCFG0_SYNCRICHECK_ENABLE = 0x10,
++ HDMI_A_HDCPCFG0_SYNCRICHECK_DISABLE = 0x00,
++ HDMI_A_HDCPCFG0_AVMUTE_MASK = 0x8,
++ HDMI_A_HDCPCFG0_AVMUTE_ENABLE = 0x8,
++ HDMI_A_HDCPCFG0_AVMUTE_DISABLE = 0x0,
++ HDMI_A_HDCPCFG0_RXDETECT_MASK = 0x4,
++ HDMI_A_HDCPCFG0_RXDETECT_ENABLE = 0x4,
++ HDMI_A_HDCPCFG0_RXDETECT_DISABLE = 0x0,
++ HDMI_A_HDCPCFG0_EN11FEATURE_MASK = 0x2,
++ HDMI_A_HDCPCFG0_EN11FEATURE_ENABLE = 0x2,
++ HDMI_A_HDCPCFG0_EN11FEATURE_DISABLE = 0x0,
++ HDMI_A_HDCPCFG0_HDMIDVI_MASK = 0x1,
++ HDMI_A_HDCPCFG0_HDMIDVI_HDMI = 0x1,
++ HDMI_A_HDCPCFG0_HDMIDVI_DVI = 0x0,
++
++/* A_HDCPCFG1 field values */
++ HDMI_A_HDCPCFG1_DISSHA1CHECK_MASK = 0x8,
++ HDMI_A_HDCPCFG1_DISSHA1CHECK_DISABLE = 0x8,
++ HDMI_A_HDCPCFG1_DISSHA1CHECK_ENABLE = 0x0,
++ HDMI_A_HDCPCFG1_PH2UPSHFTENC_MASK = 0x4,
++ HDMI_A_HDCPCFG1_PH2UPSHFTENC_ENABLE = 0x4,
++ HDMI_A_HDCPCFG1_PH2UPSHFTENC_DISABLE = 0x0,
++ HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK = 0x2,
++ HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE = 0x2,
++ HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_ENABLE = 0x0,
++ HDMI_A_HDCPCFG1_SWRESET_MASK = 0x1,
++ HDMI_A_HDCPCFG1_SWRESET_ASSERT = 0x0,
++
++/* A_VIDPOLCFG field values */
++ HDMI_A_VIDPOLCFG_UNENCRYPTCONF_MASK = 0x60,
++ HDMI_A_VIDPOLCFG_UNENCRYPTCONF_OFFSET = 5,
++ HDMI_A_VIDPOLCFG_DATAENPOL_MASK = 0x10,
++ HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH = 0x10,
++ HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW = 0x0,
++ HDMI_A_VIDPOLCFG_VSYNCPOL_MASK = 0x8,
++ HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_HIGH = 0x8,
++ HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_LOW = 0x0,
++ HDMI_A_VIDPOLCFG_HSYNCPOL_MASK = 0x2,
++ HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_HIGH = 0x2,
++ HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_LOW = 0x0,
++};
++
++#endif /* __MXC_HDMI_H__ */
+diff --git a/arch/arm/include/asm/arch-orion5x/cpu.h b/arch/arm/include/asm/arch-orion5x/cpu.h
+index 17b9b69..2f52ca8 100644
+--- a/arch/arm/include/asm/arch-orion5x/cpu.h
++++ b/arch/arm/include/asm/arch-orion5x/cpu.h
+@@ -251,6 +251,7 @@ struct orion5x_ddr_addr_decode_registers {
+ /*
+ * functions
+ */
++void reset_cpu(unsigned long ignored);
+ u32 orion5x_device_id(void);
+ u32 orion5x_device_rev(void);
+ unsigned int orion5x_winctrl_calcsize(unsigned int sizeval);
+diff --git a/arch/arm/include/asm/arch-rmobile/gpio.h b/arch/arm/include/asm/arch-rmobile/gpio.h
+deleted file mode 100644
+index 6b5e4ed..0000000
+--- a/arch/arm/include/asm/arch-rmobile/gpio.h
++++ /dev/null
+@@ -1,12 +0,0 @@
+-#ifndef __ASM_ARCH_GPIO_H
+-#define __ASM_ARCH_GPIO_H
+-
+-#if defined(CONFIG_SH73A0)
+-#include "sh73a0-gpio.h"
+-void sh73a0_pinmux_init(void);
+-#elif defined(CONFIG_R8A7740)
+-#include "r8a7740-gpio.h"
+-void r8a7740_pinmux_init(void);
+-#endif
+-
+-#endif /* __ASM_ARCH_GPIO_H */
+diff --git a/arch/arm/include/asm/arch-rmobile/irqs.h b/arch/arm/include/asm/arch-rmobile/irqs.h
+deleted file mode 100644
+index dcb714f..0000000
+--- a/arch/arm/include/asm/arch-rmobile/irqs.h
++++ /dev/null
+@@ -1,18 +0,0 @@
+-#ifndef __ASM_MACH_IRQS_H
+-#define __ASM_MACH_IRQS_H
+-
+-#define NR_IRQS 1024
+-
+-/* GIC */
+-#define gic_spi(nr) ((nr) + 32)
+-
+-/* INTCA */
+-#define evt2irq(evt) (((evt) >> 5) - 16)
+-#define irq2evt(irq) (((irq) + 16) << 5)
+-
+-/* INTCS */
+-#define INTCS_VECT_BASE 0x2200
+-#define INTCS_VECT(n, vect) INTC_VECT((n), INTCS_VECT_BASE + (vect))
+-#define intcs_evt2irq(evt) evt2irq(INTCS_VECT_BASE + (evt))
+-
+-#endif /* __ASM_MACH_IRQS_H */
+diff --git a/arch/arm/include/asm/arch-rmobile/r8a7740-gpio.h b/arch/arm/include/asm/arch-rmobile/r8a7740-gpio.h
+deleted file mode 100644
+index 9d447ab..0000000
+--- a/arch/arm/include/asm/arch-rmobile/r8a7740-gpio.h
++++ /dev/null
+@@ -1,584 +0,0 @@
+-/*
+- * Copyright (C) 2011 Renesas Solutions Corp.
+- * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; version 2 of the License.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+- */
+-
+-#ifndef __ASM_R8A7740_H__
+-#define __ASM_R8A7740_H__
+-
+-/*
+- * MD_CKx pin
+- */
+-#define MD_CK2 (1 << 2)
+-#define MD_CK1 (1 << 1)
+-#define MD_CK0 (1 << 0)
+-
+-/*
+- * Pin Function Controller:
+- * GPIO_FN_xx - GPIO used to select pin function
+- * GPIO_PORTxx - GPIO mapped to real I/O pin on CPU
+- */
+-enum {
+- /* PORT */
+- GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4,
+- GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9,
+-
+- GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14,
+- GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19,
+-
+- GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24,
+- GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29,
+-
+- GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34,
+- GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39,
+-
+- GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44,
+- GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49,
+-
+- GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54,
+- GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59,
+-
+- GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64,
+- GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69,
+-
+- GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74,
+- GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79,
+-
+- GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84,
+- GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89,
+-
+- GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94,
+- GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99,
+-
+- GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104,
+- GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109,
+-
+- GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114,
+- GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, GPIO_PORT119,
+-
+- GPIO_PORT120, GPIO_PORT121, GPIO_PORT122, GPIO_PORT123, GPIO_PORT124,
+- GPIO_PORT125, GPIO_PORT126, GPIO_PORT127, GPIO_PORT128, GPIO_PORT129,
+-
+- GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134,
+- GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139,
+-
+- GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144,
+- GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149,
+-
+- GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154,
+- GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159,
+-
+- GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164,
+- GPIO_PORT165, GPIO_PORT166, GPIO_PORT167, GPIO_PORT168, GPIO_PORT169,
+-
+- GPIO_PORT170, GPIO_PORT171, GPIO_PORT172, GPIO_PORT173, GPIO_PORT174,
+- GPIO_PORT175, GPIO_PORT176, GPIO_PORT177, GPIO_PORT178, GPIO_PORT179,
+-
+- GPIO_PORT180, GPIO_PORT181, GPIO_PORT182, GPIO_PORT183, GPIO_PORT184,
+- GPIO_PORT185, GPIO_PORT186, GPIO_PORT187, GPIO_PORT188, GPIO_PORT189,
+-
+- GPIO_PORT190, GPIO_PORT191, GPIO_PORT192, GPIO_PORT193, GPIO_PORT194,
+- GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199,
+-
+- GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204,
+- GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209,
+-
+- GPIO_PORT210, GPIO_PORT211,
+-
+- /* IRQ */
+- GPIO_FN_IRQ0_PORT2, GPIO_FN_IRQ0_PORT13,
+- GPIO_FN_IRQ1,
+- GPIO_FN_IRQ2_PORT11, GPIO_FN_IRQ2_PORT12,
+- GPIO_FN_IRQ3_PORT10, GPIO_FN_IRQ3_PORT14,
+- GPIO_FN_IRQ4_PORT15, GPIO_FN_IRQ4_PORT172,
+- GPIO_FN_IRQ5_PORT0, GPIO_FN_IRQ5_PORT1,
+- GPIO_FN_IRQ6_PORT121, GPIO_FN_IRQ6_PORT173,
+- GPIO_FN_IRQ7_PORT120, GPIO_FN_IRQ7_PORT209,
+- GPIO_FN_IRQ8,
+- GPIO_FN_IRQ9_PORT118, GPIO_FN_IRQ9_PORT210,
+- GPIO_FN_IRQ10,
+- GPIO_FN_IRQ11,
+- GPIO_FN_IRQ12_PORT42, GPIO_FN_IRQ12_PORT97,
+- GPIO_FN_IRQ13_PORT64, GPIO_FN_IRQ13_PORT98,
+- GPIO_FN_IRQ14_PORT63, GPIO_FN_IRQ14_PORT99,
+- GPIO_FN_IRQ15_PORT62, GPIO_FN_IRQ15_PORT100,
+- GPIO_FN_IRQ16_PORT68, GPIO_FN_IRQ16_PORT211,
+- GPIO_FN_IRQ17,
+- GPIO_FN_IRQ18,
+- GPIO_FN_IRQ19,
+- GPIO_FN_IRQ20,
+- GPIO_FN_IRQ21,
+- GPIO_FN_IRQ22,
+- GPIO_FN_IRQ23,
+- GPIO_FN_IRQ24,
+- GPIO_FN_IRQ25,
+- GPIO_FN_IRQ26_PORT58, GPIO_FN_IRQ26_PORT81,
+- GPIO_FN_IRQ27_PORT57, GPIO_FN_IRQ27_PORT168,
+- GPIO_FN_IRQ28_PORT56, GPIO_FN_IRQ28_PORT169,
+- GPIO_FN_IRQ29_PORT50, GPIO_FN_IRQ29_PORT170,
+- GPIO_FN_IRQ30_PORT49, GPIO_FN_IRQ30_PORT171,
+- GPIO_FN_IRQ31_PORT41, GPIO_FN_IRQ31_PORT167,
+-
+- /* Function */
+-
+- /* DBGT */
+- GPIO_FN_DBGMDT2, GPIO_FN_DBGMDT1, GPIO_FN_DBGMDT0,
+- GPIO_FN_DBGMD10, GPIO_FN_DBGMD11, GPIO_FN_DBGMD20,
+- GPIO_FN_DBGMD21,
+-
+- /* FSI */
+- GPIO_FN_FSIAISLD_PORT0, /* FSIAISLD Port 0/5 */
+- GPIO_FN_FSIAISLD_PORT5,
+- GPIO_FN_FSIASPDIF_PORT9, /* FSIASPDIF Port 9/18 */
+- GPIO_FN_FSIASPDIF_PORT18,
+- GPIO_FN_FSIAOSLD1, GPIO_FN_FSIAOSLD2,
+- GPIO_FN_FSIAOLR, GPIO_FN_FSIAOBT,
+- GPIO_FN_FSIAOSLD, GPIO_FN_FSIAOMC,
+- GPIO_FN_FSIACK, GPIO_FN_FSIAILR,
+- GPIO_FN_FSIAIBT,
+-
+- /* FMSI */
+- GPIO_FN_FMSISLD_PORT1, /* FMSISLD Port 1/6 */
+- GPIO_FN_FMSISLD_PORT6,
+- GPIO_FN_FMSIILR, GPIO_FN_FMSIIBT,
+- GPIO_FN_FMSIOLR, GPIO_FN_FMSIOBT,
+- GPIO_FN_FMSICK, GPIO_FN_FMSOILR,
+- GPIO_FN_FMSOIBT, GPIO_FN_FMSOOLR,
+- GPIO_FN_FMSOOBT, GPIO_FN_FMSOSLD,
+- GPIO_FN_FMSOCK,
+-
+- /* SCIFA0 */
+- GPIO_FN_SCIFA0_SCK, GPIO_FN_SCIFA0_CTS,
+- GPIO_FN_SCIFA0_RTS, GPIO_FN_SCIFA0_RXD,
+- GPIO_FN_SCIFA0_TXD,
+-
+- /* SCIFA1 */
+- GPIO_FN_SCIFA1_CTS, GPIO_FN_SCIFA1_SCK,
+- GPIO_FN_SCIFA1_RXD, GPIO_FN_SCIFA1_TXD,
+- GPIO_FN_SCIFA1_RTS,
+-
+- /* SCIFA2 */
+- GPIO_FN_SCIFA2_SCK_PORT22, /* SCIFA2_SCK Port 22/199 */
+- GPIO_FN_SCIFA2_SCK_PORT199,
+- GPIO_FN_SCIFA2_RXD, GPIO_FN_SCIFA2_TXD,
+- GPIO_FN_SCIFA2_CTS, GPIO_FN_SCIFA2_RTS,
+-
+- /* SCIFA3 */
+- GPIO_FN_SCIFA3_RTS_PORT105, /* MSEL5CR_8_0 */
+- GPIO_FN_SCIFA3_SCK_PORT116,
+- GPIO_FN_SCIFA3_CTS_PORT117,
+- GPIO_FN_SCIFA3_RXD_PORT174,
+- GPIO_FN_SCIFA3_TXD_PORT175,
+-
+- GPIO_FN_SCIFA3_RTS_PORT161, /* MSEL5CR_8_1 */
+- GPIO_FN_SCIFA3_SCK_PORT158,
+- GPIO_FN_SCIFA3_CTS_PORT162,
+- GPIO_FN_SCIFA3_RXD_PORT159,
+- GPIO_FN_SCIFA3_TXD_PORT160,
+-
+- /* SCIFA4 */
+- GPIO_FN_SCIFA4_RXD_PORT12, /* MSEL5CR[12:11] = 00 */
+- GPIO_FN_SCIFA4_TXD_PORT13,
+-
+- GPIO_FN_SCIFA4_RXD_PORT204, /* MSEL5CR[12:11] = 01 */
+- GPIO_FN_SCIFA4_TXD_PORT203,
+-
+- GPIO_FN_SCIFA4_RXD_PORT94, /* MSEL5CR[12:11] = 10 */
+- GPIO_FN_SCIFA4_TXD_PORT93,
+-
+- GPIO_FN_SCIFA4_SCK_PORT21, /* SCIFA4_SCK Port 21/205 */
+- GPIO_FN_SCIFA4_SCK_PORT205,
+-
+- /* SCIFA5 */
+- GPIO_FN_SCIFA5_TXD_PORT20, /* MSEL5CR[15:14] = 00 */
+- GPIO_FN_SCIFA5_RXD_PORT10,
+-
+- GPIO_FN_SCIFA5_RXD_PORT207, /* MSEL5CR[15:14] = 01 */
+- GPIO_FN_SCIFA5_TXD_PORT208,
+-
+- GPIO_FN_SCIFA5_TXD_PORT91, /* MSEL5CR[15:14] = 10 */
+- GPIO_FN_SCIFA5_RXD_PORT92,
+-
+- GPIO_FN_SCIFA5_SCK_PORT23, /* SCIFA5_SCK Port 23/206 */
+- GPIO_FN_SCIFA5_SCK_PORT206,
+-
+- /* SCIFA6 */
+- GPIO_FN_SCIFA6_SCK, GPIO_FN_SCIFA6_RXD, GPIO_FN_SCIFA6_TXD,
+-
+- /* SCIFA7 */
+- GPIO_FN_SCIFA7_TXD, GPIO_FN_SCIFA7_RXD,
+-
+- /* SCIFAB */
+- GPIO_FN_SCIFB_SCK_PORT190, /* MSEL5CR_17_0 */
+- GPIO_FN_SCIFB_RXD_PORT191,
+- GPIO_FN_SCIFB_TXD_PORT192,
+- GPIO_FN_SCIFB_RTS_PORT186,
+- GPIO_FN_SCIFB_CTS_PORT187,
+-
+- GPIO_FN_SCIFB_SCK_PORT2, /* MSEL5CR_17_1 */
+- GPIO_FN_SCIFB_RXD_PORT3,
+- GPIO_FN_SCIFB_TXD_PORT4,
+- GPIO_FN_SCIFB_RTS_PORT172,
+- GPIO_FN_SCIFB_CTS_PORT173,
+-
+- /* LCD0 */
+- GPIO_FN_LCDC0_SELECT,
+- GPIO_FN_LCD0_D0, GPIO_FN_LCD0_D1, GPIO_FN_LCD0_D2,
+- GPIO_FN_LCD0_D3, GPIO_FN_LCD0_D4, GPIO_FN_LCD0_D5,
+- GPIO_FN_LCD0_D6, GPIO_FN_LCD0_D7, GPIO_FN_LCD0_D8,
+- GPIO_FN_LCD0_D9, GPIO_FN_LCD0_D10, GPIO_FN_LCD0_D11,
+- GPIO_FN_LCD0_D12, GPIO_FN_LCD0_D13, GPIO_FN_LCD0_D14,
+- GPIO_FN_LCD0_D15, GPIO_FN_LCD0_D16, GPIO_FN_LCD0_D17,
+- GPIO_FN_LCD0_DON, GPIO_FN_LCD0_VCPWC, GPIO_FN_LCD0_VEPWC,
+-
+- GPIO_FN_LCD0_DCK, GPIO_FN_LCD0_VSYN, /* for RGB */
+- GPIO_FN_LCD0_HSYN, GPIO_FN_LCD0_DISP, /* for RGB */
+-
+- GPIO_FN_LCD0_WR, GPIO_FN_LCD0_RD, /* for SYS */
+- GPIO_FN_LCD0_CS, GPIO_FN_LCD0_RS, /* for SYS */
+-
+- GPIO_FN_LCD0_D18_PORT163, GPIO_FN_LCD0_D19_PORT162,
+- GPIO_FN_LCD0_D20_PORT161, GPIO_FN_LCD0_D21_PORT158,
+- GPIO_FN_LCD0_D22_PORT160, GPIO_FN_LCD0_D23_PORT159,
+- GPIO_FN_LCD0_LCLK_PORT165, /* MSEL5CR_6_1 */
+-
+- GPIO_FN_LCD0_D18_PORT40, GPIO_FN_LCD0_D19_PORT4,
+- GPIO_FN_LCD0_D20_PORT3, GPIO_FN_LCD0_D21_PORT2,
+- GPIO_FN_LCD0_D22_PORT0, GPIO_FN_LCD0_D23_PORT1,
+- GPIO_FN_LCD0_LCLK_PORT102, /* MSEL5CR_6_0 */
+-
+- /* LCD1 */
+- GPIO_FN_LCDC1_SELECT,
+- GPIO_FN_LCD1_D0, GPIO_FN_LCD1_D1, GPIO_FN_LCD1_D2,
+- GPIO_FN_LCD1_D3, GPIO_FN_LCD1_D4, GPIO_FN_LCD1_D5,
+- GPIO_FN_LCD1_D6, GPIO_FN_LCD1_D7, GPIO_FN_LCD1_D8,
+- GPIO_FN_LCD1_D9, GPIO_FN_LCD1_D10, GPIO_FN_LCD1_D11,
+- GPIO_FN_LCD1_D12, GPIO_FN_LCD1_D13, GPIO_FN_LCD1_D14,
+- GPIO_FN_LCD1_D15, GPIO_FN_LCD1_D16, GPIO_FN_LCD1_D17,
+- GPIO_FN_LCD1_D18, GPIO_FN_LCD1_D19, GPIO_FN_LCD1_D20,
+- GPIO_FN_LCD1_D21, GPIO_FN_LCD1_D22, GPIO_FN_LCD1_D23,
+- GPIO_FN_LCD1_DON, GPIO_FN_LCD1_VCPWC,
+- GPIO_FN_LCD1_LCLK, GPIO_FN_LCD1_VEPWC,
+-
+- GPIO_FN_LCD1_DCK, GPIO_FN_LCD1_VSYN, /* for RGB */
+- GPIO_FN_LCD1_HSYN, GPIO_FN_LCD1_DISP, /* for RGB */
+-
+- GPIO_FN_LCD1_WR, GPIO_FN_LCD1_RD, /* for SYS */
+- GPIO_FN_LCD1_CS, GPIO_FN_LCD1_RS, /* for SYS */
+-
+- /* RSPI */
+- GPIO_FN_RSPI_SSL0_A, GPIO_FN_RSPI_SSL1_A,
+- GPIO_FN_RSPI_SSL2_A, GPIO_FN_RSPI_SSL3_A,
+- GPIO_FN_RSPI_MOSI_A, GPIO_FN_RSPI_MISO_A,
+- GPIO_FN_RSPI_CK_A,
+-
+- /* VIO CKO */
+- GPIO_FN_VIO_CKO1,
+- GPIO_FN_VIO_CKO2,
+- GPIO_FN_VIO_CKO_1,
+- GPIO_FN_VIO_CKO,
+-
+- /* VIO0 */
+- GPIO_FN_VIO0_D0, GPIO_FN_VIO0_D1, GPIO_FN_VIO0_D2,
+- GPIO_FN_VIO0_D3, GPIO_FN_VIO0_D4, GPIO_FN_VIO0_D5,
+- GPIO_FN_VIO0_D6, GPIO_FN_VIO0_D7, GPIO_FN_VIO0_D8,
+- GPIO_FN_VIO0_D9, GPIO_FN_VIO0_D10, GPIO_FN_VIO0_D11,
+- GPIO_FN_VIO0_D12, GPIO_FN_VIO0_VD, GPIO_FN_VIO0_HD,
+- GPIO_FN_VIO0_CLK, GPIO_FN_VIO0_FIELD,
+-
+- GPIO_FN_VIO0_D13_PORT26, /* MSEL5CR_27_0 */
+- GPIO_FN_VIO0_D14_PORT25,
+- GPIO_FN_VIO0_D15_PORT24,
+-
+- GPIO_FN_VIO0_D13_PORT22, /* MSEL5CR_27_1 */
+- GPIO_FN_VIO0_D14_PORT95,
+- GPIO_FN_VIO0_D15_PORT96,
+-
+- /* VIO1 */
+- GPIO_FN_VIO1_D0, GPIO_FN_VIO1_D1, GPIO_FN_VIO1_D2,
+- GPIO_FN_VIO1_D3, GPIO_FN_VIO1_D4, GPIO_FN_VIO1_D5,
+- GPIO_FN_VIO1_D6, GPIO_FN_VIO1_D7, GPIO_FN_VIO1_VD,
+- GPIO_FN_VIO1_HD, GPIO_FN_VIO1_CLK, GPIO_FN_VIO1_FIELD,
+-
+- /* TPU0 */
+- GPIO_FN_TPU0TO0, GPIO_FN_TPU0TO1,
+- GPIO_FN_TPU0TO3,
+- GPIO_FN_TPU0TO2_PORT66, /* TPU0TO2 Port 66/202 */
+- GPIO_FN_TPU0TO2_PORT202,
+-
+- /* SSP1 0 */
+- GPIO_FN_STP0_IPD0, GPIO_FN_STP0_IPD1, GPIO_FN_STP0_IPD2,
+- GPIO_FN_STP0_IPD3, GPIO_FN_STP0_IPD4, GPIO_FN_STP0_IPD5,
+- GPIO_FN_STP0_IPD6, GPIO_FN_STP0_IPD7, GPIO_FN_STP0_IPEN,
+- GPIO_FN_STP0_IPCLK, GPIO_FN_STP0_IPSYNC,
+-
+- /* SSP1 1 */
+- GPIO_FN_STP1_IPD1, GPIO_FN_STP1_IPD2, GPIO_FN_STP1_IPD3,
+- GPIO_FN_STP1_IPD4, GPIO_FN_STP1_IPD5, GPIO_FN_STP1_IPD6,
+- GPIO_FN_STP1_IPD7, GPIO_FN_STP1_IPCLK, GPIO_FN_STP1_IPSYNC,
+-
+- GPIO_FN_STP1_IPD0_PORT186, /* MSEL5CR_23_0 */
+- GPIO_FN_STP1_IPEN_PORT187,
+-
+- GPIO_FN_STP1_IPD0_PORT194, /* MSEL5CR_23_1 */
+- GPIO_FN_STP1_IPEN_PORT193,
+-
+- /* SIM */
+- GPIO_FN_SIM_RST, GPIO_FN_SIM_CLK,
+- GPIO_FN_SIM_D_PORT22, /* SIM_D Port 22/199 */
+- GPIO_FN_SIM_D_PORT199,
+-
+- /* SDHI0 */
+- GPIO_FN_SDHI0_D0, GPIO_FN_SDHI0_D1, GPIO_FN_SDHI0_D2,
+- GPIO_FN_SDHI0_D3, GPIO_FN_SDHI0_CD, GPIO_FN_SDHI0_WP,
+- GPIO_FN_SDHI0_CMD, GPIO_FN_SDHI0_CLK,
+-
+- /* SDHI1 */
+- GPIO_FN_SDHI1_D0, GPIO_FN_SDHI1_D1, GPIO_FN_SDHI1_D2,
+- GPIO_FN_SDHI1_D3, GPIO_FN_SDHI1_CD, GPIO_FN_SDHI1_WP,
+- GPIO_FN_SDHI1_CMD, GPIO_FN_SDHI1_CLK,
+-
+- /* SDHI2 */
+- GPIO_FN_SDHI2_D0, GPIO_FN_SDHI2_D1, GPIO_FN_SDHI2_D2,
+- GPIO_FN_SDHI2_D3, GPIO_FN_SDHI2_CLK, GPIO_FN_SDHI2_CMD,
+-
+- GPIO_FN_SDHI2_CD_PORT24, /* MSEL5CR_19_0 */
+- GPIO_FN_SDHI2_WP_PORT25,
+-
+- GPIO_FN_SDHI2_WP_PORT177, /* MSEL5CR_19_1 */
+- GPIO_FN_SDHI2_CD_PORT202,
+-
+- /* MSIOF2 */
+- GPIO_FN_MSIOF2_TXD, GPIO_FN_MSIOF2_RXD, GPIO_FN_MSIOF2_TSCK,
+- GPIO_FN_MSIOF2_SS2, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_MSIOF2_SS1,
+- GPIO_FN_MSIOF2_MCK1, GPIO_FN_MSIOF2_MCK0, GPIO_FN_MSIOF2_RSYNC,
+- GPIO_FN_MSIOF2_RSCK,
+-
+- /* KEYSC */
+- GPIO_FN_KEYIN4, GPIO_FN_KEYIN5,
+- GPIO_FN_KEYIN6, GPIO_FN_KEYIN7,
+- GPIO_FN_KEYOUT0, GPIO_FN_KEYOUT1, GPIO_FN_KEYOUT2,
+- GPIO_FN_KEYOUT3, GPIO_FN_KEYOUT4, GPIO_FN_KEYOUT5,
+- GPIO_FN_KEYOUT6, GPIO_FN_KEYOUT7,
+-
+- GPIO_FN_KEYIN0_PORT43, /* MSEL4CR_18_0 */
+- GPIO_FN_KEYIN1_PORT44,
+- GPIO_FN_KEYIN2_PORT45,
+- GPIO_FN_KEYIN3_PORT46,
+-
+- GPIO_FN_KEYIN0_PORT58, /* MSEL4CR_18_1 */
+- GPIO_FN_KEYIN1_PORT57,
+- GPIO_FN_KEYIN2_PORT56,
+- GPIO_FN_KEYIN3_PORT55,
+-
+- /* VOU */
+- GPIO_FN_DV_D0, GPIO_FN_DV_D1, GPIO_FN_DV_D2, GPIO_FN_DV_D3,
+- GPIO_FN_DV_D4, GPIO_FN_DV_D5, GPIO_FN_DV_D6, GPIO_FN_DV_D7,
+- GPIO_FN_DV_D8, GPIO_FN_DV_D9, GPIO_FN_DV_D10, GPIO_FN_DV_D11,
+- GPIO_FN_DV_D12, GPIO_FN_DV_D13, GPIO_FN_DV_D14, GPIO_FN_DV_D15,
+- GPIO_FN_DV_CLK,
+- GPIO_FN_DV_VSYNC,
+- GPIO_FN_DV_HSYNC,
+-
+- /* MEMC */
+- GPIO_FN_MEMC_AD0, GPIO_FN_MEMC_AD1, GPIO_FN_MEMC_AD2,
+- GPIO_FN_MEMC_AD3, GPIO_FN_MEMC_AD4, GPIO_FN_MEMC_AD5,
+- GPIO_FN_MEMC_AD6, GPIO_FN_MEMC_AD7, GPIO_FN_MEMC_AD8,
+- GPIO_FN_MEMC_AD9, GPIO_FN_MEMC_AD10, GPIO_FN_MEMC_AD11,
+- GPIO_FN_MEMC_AD12, GPIO_FN_MEMC_AD13, GPIO_FN_MEMC_AD14,
+- GPIO_FN_MEMC_AD15, GPIO_FN_MEMC_CS0, GPIO_FN_MEMC_INT,
+- GPIO_FN_MEMC_NWE, GPIO_FN_MEMC_NOE,
+-
+- GPIO_FN_MEMC_CS1, /* MSEL4CR_6_0 */
+- GPIO_FN_MEMC_ADV,
+- GPIO_FN_MEMC_WAIT,
+- GPIO_FN_MEMC_BUSCLK,
+-
+- GPIO_FN_MEMC_A1, /* MSEL4CR_6_1 */
+- GPIO_FN_MEMC_DREQ0,
+- GPIO_FN_MEMC_DREQ1,
+- GPIO_FN_MEMC_A0,
+-
+- /* MMC */
+- GPIO_FN_MMC0_D0_PORT68, GPIO_FN_MMC0_D1_PORT69,
+- GPIO_FN_MMC0_D2_PORT70, GPIO_FN_MMC0_D3_PORT71,
+- GPIO_FN_MMC0_D4_PORT72, GPIO_FN_MMC0_D5_PORT73,
+- GPIO_FN_MMC0_D6_PORT74, GPIO_FN_MMC0_D7_PORT75,
+- GPIO_FN_MMC0_CLK_PORT66,
+- GPIO_FN_MMC0_CMD_PORT67, /* MSEL4CR_15_0 */
+-
+- GPIO_FN_MMC1_D0_PORT149, GPIO_FN_MMC1_D1_PORT148,
+- GPIO_FN_MMC1_D2_PORT147, GPIO_FN_MMC1_D3_PORT146,
+- GPIO_FN_MMC1_D4_PORT145, GPIO_FN_MMC1_D5_PORT144,
+- GPIO_FN_MMC1_D6_PORT143, GPIO_FN_MMC1_D7_PORT142,
+- GPIO_FN_MMC1_CLK_PORT103,
+- GPIO_FN_MMC1_CMD_PORT104, /* MSEL4CR_15_1 */
+-
+- /* MSIOF0 */
+- GPIO_FN_MSIOF0_SS1, GPIO_FN_MSIOF0_SS2,
+- GPIO_FN_MSIOF0_RXD, GPIO_FN_MSIOF0_TXD,
+- GPIO_FN_MSIOF0_MCK0, GPIO_FN_MSIOF0_MCK1,
+- GPIO_FN_MSIOF0_RSYNC, GPIO_FN_MSIOF0_RSCK,
+- GPIO_FN_MSIOF0_TSCK, GPIO_FN_MSIOF0_TSYNC,
+-
+- /* MSIOF1 */
+- GPIO_FN_MSIOF1_RSCK, GPIO_FN_MSIOF1_RSYNC,
+- GPIO_FN_MSIOF1_MCK0, GPIO_FN_MSIOF1_MCK1,
+-
+- GPIO_FN_MSIOF1_SS2_PORT116, GPIO_FN_MSIOF1_SS1_PORT117,
+- GPIO_FN_MSIOF1_RXD_PORT118, GPIO_FN_MSIOF1_TXD_PORT119,
+- GPIO_FN_MSIOF1_TSYNC_PORT120,
+- GPIO_FN_MSIOF1_TSCK_PORT121, /* MSEL4CR_10_0 */
+-
+- GPIO_FN_MSIOF1_SS1_PORT67, GPIO_FN_MSIOF1_TSCK_PORT72,
+- GPIO_FN_MSIOF1_TSYNC_PORT73, GPIO_FN_MSIOF1_TXD_PORT74,
+- GPIO_FN_MSIOF1_RXD_PORT75,
+- GPIO_FN_MSIOF1_SS2_PORT202, /* MSEL4CR_10_1 */
+-
+- /* GPIO */
+- GPIO_FN_GPO0, GPIO_FN_GPI0,
+- GPIO_FN_GPO1, GPIO_FN_GPI1,
+-
+- /* USB0 */
+- GPIO_FN_USB0_OCI, GPIO_FN_USB0_PPON, GPIO_FN_VBUS,
+-
+- /* USB1 */
+- GPIO_FN_USB1_OCI, GPIO_FN_USB1_PPON,
+-
+- /* BBIF1 */
+- GPIO_FN_BBIF1_RXD, GPIO_FN_BBIF1_TXD, GPIO_FN_BBIF1_TSYNC,
+- GPIO_FN_BBIF1_TSCK, GPIO_FN_BBIF1_RSCK, GPIO_FN_BBIF1_RSYNC,
+- GPIO_FN_BBIF1_FLOW, GPIO_FN_BBIF1_RX_FLOW_N,
+-
+- /* BBIF2 */
+- GPIO_FN_BBIF2_TXD2_PORT5, /* MSEL5CR_0_0 */
+- GPIO_FN_BBIF2_RXD2_PORT60,
+- GPIO_FN_BBIF2_TSYNC2_PORT6,
+- GPIO_FN_BBIF2_TSCK2_PORT59,
+-
+- GPIO_FN_BBIF2_RXD2_PORT90, /* MSEL5CR_0_1 */
+- GPIO_FN_BBIF2_TXD2_PORT183,
+- GPIO_FN_BBIF2_TSCK2_PORT89,
+- GPIO_FN_BBIF2_TSYNC2_PORT184,
+-
+- /* BSC / FLCTL / PCMCIA */
+- GPIO_FN_CS0, GPIO_FN_CS2, GPIO_FN_CS4,
+- GPIO_FN_CS5B, GPIO_FN_CS6A,
+- GPIO_FN_CS5A_PORT105, /* CS5A PORT 19/105 */
+- GPIO_FN_CS5A_PORT19,
+- GPIO_FN_IOIS16, /* ? */
+-
+- GPIO_FN_A0, GPIO_FN_A1, GPIO_FN_A2, GPIO_FN_A3,
+- GPIO_FN_A4_FOE, /* share with FLCTL */
+- GPIO_FN_A5_FCDE, /* share with FLCTL */
+- GPIO_FN_A6, GPIO_FN_A7, GPIO_FN_A8, GPIO_FN_A9,
+- GPIO_FN_A10, GPIO_FN_A11, GPIO_FN_A12, GPIO_FN_A13,
+- GPIO_FN_A14, GPIO_FN_A15, GPIO_FN_A16, GPIO_FN_A17,
+- GPIO_FN_A18, GPIO_FN_A19, GPIO_FN_A20, GPIO_FN_A21,
+- GPIO_FN_A22, GPIO_FN_A23, GPIO_FN_A24, GPIO_FN_A25,
+- GPIO_FN_A26,
+-
+- GPIO_FN_D0_NAF0, GPIO_FN_D1_NAF1, /* share with FLCTL */
+- GPIO_FN_D2_NAF2, GPIO_FN_D3_NAF3, /* share with FLCTL */
+- GPIO_FN_D4_NAF4, GPIO_FN_D5_NAF5, /* share with FLCTL */
+- GPIO_FN_D6_NAF6, GPIO_FN_D7_NAF7, /* share with FLCTL */
+- GPIO_FN_D8_NAF8, GPIO_FN_D9_NAF9, /* share with FLCTL */
+- GPIO_FN_D10_NAF10, GPIO_FN_D11_NAF11, /* share with FLCTL */
+- GPIO_FN_D12_NAF12, GPIO_FN_D13_NAF13, /* share with FLCTL */
+- GPIO_FN_D14_NAF14, GPIO_FN_D15_NAF15, /* share with FLCTL */
+-
+- GPIO_FN_D16, GPIO_FN_D17, GPIO_FN_D18, GPIO_FN_D19,
+- GPIO_FN_D20, GPIO_FN_D21, GPIO_FN_D22, GPIO_FN_D23,
+- GPIO_FN_D24, GPIO_FN_D25, GPIO_FN_D26, GPIO_FN_D27,
+- GPIO_FN_D28, GPIO_FN_D29, GPIO_FN_D30, GPIO_FN_D31,
+-
+- GPIO_FN_WE0_FWE, /* share with FLCTL */
+- GPIO_FN_WE1,
+- GPIO_FN_WE2_ICIORD, /* share with PCMCIA */
+- GPIO_FN_WE3_ICIOWR, /* share with PCMCIA */
+- GPIO_FN_CKO, GPIO_FN_BS, GPIO_FN_RDWR,
+- GPIO_FN_RD_FSC, /* share with FLCTL */
+- GPIO_FN_WAIT_PORT177, /* WAIT Port 90/177 */
+- GPIO_FN_WAIT_PORT90,
+-
+- GPIO_FN_FCE0, GPIO_FN_FCE1, GPIO_FN_FRB, /* FLCTL */
+-
+- /* IRDA */
+- GPIO_FN_IRDA_FIRSEL, GPIO_FN_IRDA_IN, GPIO_FN_IRDA_OUT,
+-
+- /* ATAPI */
+- GPIO_FN_IDE_D0, GPIO_FN_IDE_D1, GPIO_FN_IDE_D2,
+- GPIO_FN_IDE_D3, GPIO_FN_IDE_D4, GPIO_FN_IDE_D5,
+- GPIO_FN_IDE_D6, GPIO_FN_IDE_D7, GPIO_FN_IDE_D8,
+- GPIO_FN_IDE_D9, GPIO_FN_IDE_D10, GPIO_FN_IDE_D11,
+- GPIO_FN_IDE_D12, GPIO_FN_IDE_D13, GPIO_FN_IDE_D14,
+- GPIO_FN_IDE_D15, GPIO_FN_IDE_A0, GPIO_FN_IDE_A1,
+- GPIO_FN_IDE_A2, GPIO_FN_IDE_CS0, GPIO_FN_IDE_CS1,
+- GPIO_FN_IDE_IOWR, GPIO_FN_IDE_IORD, GPIO_FN_IDE_IORDY,
+- GPIO_FN_IDE_INT, GPIO_FN_IDE_RST, GPIO_FN_IDE_DIRECTION,
+- GPIO_FN_IDE_EXBUF_ENB, GPIO_FN_IDE_IODACK, GPIO_FN_IDE_IODREQ,
+-
+- /* RMII */
+- GPIO_FN_RMII_CRS_DV, GPIO_FN_RMII_RX_ER, GPIO_FN_RMII_RXD0,
+- GPIO_FN_RMII_RXD1, GPIO_FN_RMII_TX_EN, GPIO_FN_RMII_TXD0,
+- GPIO_FN_RMII_MDC, GPIO_FN_RMII_TXD1, GPIO_FN_RMII_MDIO,
+- GPIO_FN_RMII_REF50CK, /* for RMII */
+- GPIO_FN_RMII_REF125CK, /* for GMII */
+-
+- /* GEther */
+- GPIO_FN_ET_TX_CLK, GPIO_FN_ET_TX_EN, GPIO_FN_ET_ETXD0,
+- GPIO_FN_ET_ETXD1, GPIO_FN_ET_ETXD2, GPIO_FN_ET_ETXD3,
+- GPIO_FN_ET_ETXD4, GPIO_FN_ET_ETXD5, /* for GEther */
+- GPIO_FN_ET_ETXD6, GPIO_FN_ET_ETXD7, /* for GEther */
+- GPIO_FN_ET_COL, GPIO_FN_ET_TX_ER,
+- GPIO_FN_ET_RX_CLK, GPIO_FN_ET_RX_DV,
+- GPIO_FN_ET_ERXD0, GPIO_FN_ET_ERXD1,
+- GPIO_FN_ET_ERXD2, GPIO_FN_ET_ERXD3,
+- GPIO_FN_ET_ERXD4, GPIO_FN_ET_ERXD5, /* for GEther */
+- GPIO_FN_ET_ERXD6, GPIO_FN_ET_ERXD7, /* for GEther */
+- GPIO_FN_ET_RX_ER, GPIO_FN_ET_CRS,
+- GPIO_FN_ET_MDC, GPIO_FN_ET_MDIO,
+- GPIO_FN_ET_LINK, GPIO_FN_ET_PHY_INT,
+- GPIO_FN_ET_WOL, GPIO_FN_ET_GTX_CLK,
+-
+- /* DMA0 */
+- GPIO_FN_DREQ0, GPIO_FN_DACK0,
+-
+- /* DMA1 */
+- GPIO_FN_DREQ1, GPIO_FN_DACK1,
+-
+- /* SYSC */
+- GPIO_FN_RESETOUTS,
+- GPIO_FN_RESETP_PULLUP,
+- GPIO_FN_RESETP_PLAIN,
+-
+- /* SDENC */
+- GPIO_FN_SDENC_CPG,
+- GPIO_FN_SDENC_DV_CLKI,
+-
+- /* IRREM */
+- GPIO_FN_IROUT,
+-
+- /* DEBUG */
+- GPIO_FN_EDEBGREQ_PULLDOWN,
+- GPIO_FN_EDEBGREQ_PULLUP,
+-
+- GPIO_FN_TRACEAUD_FROM_VIO,
+- GPIO_FN_TRACEAUD_FROM_LCDC0,
+- GPIO_FN_TRACEAUD_FROM_MEMC,
+-};
+-
+-#endif /* __ASM_R8A7740_H__ */
+diff --git a/arch/arm/include/asm/arch-rmobile/r8a7740.h b/arch/arm/include/asm/arch-rmobile/r8a7740.h
+deleted file mode 100644
+index 8f17950..0000000
+--- a/arch/arm/include/asm/arch-rmobile/r8a7740.h
++++ /dev/null
+@@ -1,287 +0,0 @@
+-/*
+- * Copyright (C) 2012 Renesas Solutions Corp.
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License
+- * version 2 as published by the Free Software Foundation.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+- * MA 02110-1301, USA.
+- */
+-
+-#ifndef __ASM_ARCH_R8A7740_H
+-#define __ASM_ARCH_R8A7740_H
+-
+-/*
+- * R8A7740 I/O Addresses
+- */
+-
+-#define MERAM_BASE 0xE5580000
+-#define DDRP_BASE 0xC12A0000
+-#define HPB_BASE 0xE6000000
+-#define RWDT0_BASE 0xE6020000
+-#define RWDT1_BASE 0xE6030000
+-#define GPIO_BASE 0xE6050000
+-#define CMT1_BASE 0xE6138000
+-#define CPG_BASE 0xE6150000
+-#define SYSC_BASE 0xE6180000
+-#define SDHI0_BASE 0xE6850000
+-#define SDHI1_BASE 0xE6860000
+-#define MMCIF_BASE 0xE6BD0000
+-#define SCIF5_BASE 0xE6CB0000
+-#define SCIF6_BASE 0xE6CC0000
+-#define DBSC_BASE 0xFE400000
+-#define BSC_BASE 0xFEC10000
+-#define I2C0_BASE 0xFFF20000
+-#define I2C1_BASE 0xE6C20000
+-#define TMU_BASE 0xFFF80000
+-
+-#ifndef __ASSEMBLY__
+-#include <asm/types.h>
+-
+-/* RWDT */
+-struct r8a7740_rwdt {
+- u16 rwtcnt0; /* 0x00 */
+- u16 dummy0; /* 0x02 */
+- u16 rwtcsra0; /* 0x04 */
+- u16 dummy1; /* 0x06 */
+- u16 rwtcsrb0; /* 0x08 */
+- u16 dummy2; /* 0x0A */
+-};
+-
+-/* HPB Semaphore Control Registers */
+-struct r8a7740_hpb {
+- u32 hpbctrl0;
+- u32 hpbctrl1;
+- u32 hpbctrl2;
+- u32 cccr;
+- u32 dummy0; /* 0x20 */
+- u32 hpbctrl4;
+- u32 hpbctrl5;
+-};
+-
+-/* CPG */
+-struct r8a7740_cpg {
+- u32 frqcra;
+- u32 frqcrb;
+- u32 vclkcr1;
+- u32 vclkcr2;
+- u32 fmsickcr;
+- u32 fmsockcr;
+- u32 fsiackcr;
+- u32 dummy0; /* 0x1c */
+- u32 rtstbcr;
+- u32 systbcr;
+- u32 pllc01cr;
+- u32 pllc2cr;
+- u32 mstpsr0;
+- u32 dummy1; /* 0x34 */
+- u32 mstpsr1;
+- u32 mstpsr5;
+- u32 mstpsr2;
+- u32 dummy2; /* 0x44 */
+- u32 mstpsr3;
+- u32 mstpsr4;
+- u32 dummy3; /* 0x50 */
+- u32 astat;
+- u32 dummy4[4]; /* 0x58 .. 0x64 */
+- u32 ztrckcr;
+- u32 dummy5[5]; /* 0x6c .. 0x7c */
+- u32 subckcr;
+- u32 spuckcr;
+- u32 vouckcr;
+- u32 usbckcr;
+- u32 dummy6[3]; /* 0x90 .. 0x98 */
+- u32 stprckcr;
+- u32 srcr0;
+- u32 dummy7; /* 0xa4 */
+- u32 srcr1;
+- u32 dummy8; /* 0xac */
+- u32 srcr2;
+- u32 dummy9; /* 0xb4 */
+- u32 srcr3;
+- u32 srcr4;
+- u32 dummy10; /* 0xc0 */
+- u32 srcr5;
+- u32 pllc01stpcr;
+- u32 dummy11[5]; /* 0xcc .. 0xdc */
+- u32 frqcrc;
+- u32 frqcrd;
+- u32 dummy12[10]; /* 0xe8 .. 0x10c */
+- u32 rmstpcr0;
+- u32 rmstpcr1;
+- u32 rmstpcr2;
+- u32 rmstpcr3;
+- u32 rmstpcr4;
+- u32 rmstpcr5;
+- u32 dummy13[2]; /* 0x128 .. 0x12c */
+- u32 smstpcr0;
+- u32 smstpcr1;
+- u32 smstpcr2;
+- u32 smstpcr3;
+- u32 smstpcr4;
+- u32 smstpcr5;
+-};
+-
+-/* BSC */
+-struct r8a7740_bsc {
+- u32 cmncr;
+- u32 cs0bcr;
+- u32 cs2bcr;
+- u32 dummy0; /* 0x0c */
+- u32 cs4bcr;
+- u32 cs5abcr;
+- u32 cs5bbcr;
+- u32 cs6abcr;
+- u32 dummy1; /* 0x20 */
+- u32 cs0wcr;
+- u32 cs2wcr;
+- u32 dummy2; /* 0x2c */
+- u32 cs4wcr;
+- u32 cs5awcr;
+- u32 cs5bwcr;
+- u32 cs6awcr;
+- u32 dummy3[5]; /* 0x40 .. 0x50 */
+- u32 rbwtcnt;
+- u32 busycr;
+- u32 dummy4[5]; /* 0x5c .. 0x6c */
+- u32 bromtimcr;
+- u32 dummy5[7]; /* 0x74 .. 0x8c */
+- u32 bptcr00;
+- u32 bptcr01;
+- u32 bptcr02;
+- u32 bptcr03;
+- u32 bptcr04;
+- u32 bptcr05;
+- u32 bptcr06;
+- u32 bptcr07;
+- u32 bptcr08;
+- u32 bptcr09;
+- u32 bptcr10;
+- u32 bptcr11;
+- u32 bptcr12;
+- u32 bptcr13;
+- u32 bptcr14;
+- u32 bptcr15;
+- u32 bptcr16;
+- u32 bptcr17;
+- u32 bptcr18;
+- u32 bptcr19;
+- u32 bptcr20;
+- u32 bptcr21;
+- u32 bptcr22;
+- u32 bptcr23;
+- u32 bptcr24;
+- u32 bptcr25;
+- u32 bptcr26;
+- u32 bptcr27;
+- u32 bptcr28;
+- u32 bptcr29;
+- u32 bptcr30;
+- u32 bptcr31;
+- u32 bswcr;
+- u32 dummy6[68]; /* 0x114 .. 0x220 */
+- u32 cs0wcr2;
+- u32 cs2wcr2;
+- u32 dummy7; /* 0x22c */
+- u32 cs4wcr2;
+-};
+-
+-#define CS0WCR2 0xFEC10224
+-#define CS2WCR2 0xFEC10228
+-#define CS4WCR2 0xFEC10230
+-
+-/* DDRP */
+-struct r8a7740_ddrp {
+- u32 funcctrl;
+- u32 dllctrl;
+- u32 zqcalctrl;
+- u32 zqodtctrl;
+- u32 rdctrl;
+- u32 rdtmg;
+- u32 fifoinit;
+- u32 outctrl;
+- u32 dummy0[50]; /* 0x20 .. 0xe4 */
+- u32 dqcalofs1;
+- u32 dqcalofs2;
+- u32 dummy1[2]; /* 0xf0 .. 0xf4 */
+- u32 dqcalexp;
+-};
+-
+-#define DDRPNCNT 0xE605803C
+-#define DDRVREFCNT 0xE61500EC
+-
+-/* DBSC */
+-struct r8a7740_dbsc {
+- u32 dummy0;
+- u32 dbsvcr;
+- u32 dbstate0;
+- u32 dbstate1;
+- u32 dbacen;
+- u32 dbrfen;
+- u32 dbcmd;
+- u32 dbwait;
+- u32 dbkind;
+- u32 dbconf0;
+- u32 dummy1[2]; /* 0x28 .. 0x2c */
+- u32 dbphytype;
+- u32 dummy2[3]; /* 0x34 .. 0x3c */
+- u32 dbtr0;
+- u32 dbtr1;
+- u32 dbtr2;
+- u32 dummy3; /* 0x4c */
+- u32 dbtr3;
+- u32 dbtr4;
+- u32 dbtr5;
+- u32 dbtr6;
+- u32 dbtr7;
+- u32 dbtr8;
+- u32 dbtr9;
+- u32 dbtr10;
+- u32 dbtr11;
+- u32 dbtr12;
+- u32 dbtr13;
+- u32 dbtr14;
+- u32 dbtr15;
+- u32 dbtr16;
+- u32 dbtr17;
+- u32 dbtr18;
+- u32 dbtr19;
+- u32 dummy4[7]; /* 0x94 .. 0xac */
+- u32 dbbl;
+- u32 dummy5[3]; /* 0xb4 .. 0xbc */
+- u32 dbadj0;
+- u32 dbadj1;
+- u32 dbadj2;
+- u32 dummy6[5]; /* 0xcc .. 0xdc */
+- u32 dbrfcnf0;
+- u32 dbrfcnf1;
+- u32 dbrfcnf2;
+- u32 dbrfcnf3;
+- u32 dummy7; /* 0xf0 */
+- u32 dbcalcnf;
+- u32 dbcaltr;
+- u32 dummy8; /* 0xfc */;
+- u32 dbrnk0;
+- u32 dummy9[31]; /* 0x104 .. 0x17C */
+- u32 dbpdncnf;
+- u32 dummy10[7]; /* 0x184 .. 0x19C */
+- u32 dbmrrdr;
+- u32 dummy11[39]; /* 0x1A4 .. 0x23C */
+- u32 dbdfistat;
+- u32 dbdficnt;
+- u32 dummy12[46]; /* 0x248 .. 0x2FC */
+- u32 dbbs0cnt0;
+- u32 dbbs0cnt1;
+-};
+-
+-#endif
+-
+-#endif /* __ASM_ARCH_R8A7740_H */
+diff --git a/arch/arm/include/asm/arch-rmobile/rmobile.h b/arch/arm/include/asm/arch-rmobile/rmobile.h
+deleted file mode 100644
+index ac17561..0000000
+--- a/arch/arm/include/asm/arch-rmobile/rmobile.h
++++ /dev/null
+@@ -1,14 +0,0 @@
+-#ifndef __ASM_ARCH_RMOBILE_H
+-#define __ASM_ARCH_RMOBILE_H
+-
+-#if defined(CONFIG_RMOBILE)
+-#if defined(CONFIG_SH73A0)
+-#include <asm/arch/sh73a0.h>
+-#elif defined(CONFIG_R8A7740)
+-#include <asm/arch/r8a7740.h>
+-#else
+-#error "SOC Name not defined"
+-#endif
+-#endif /* CONFIG_RMOBILE */
+-
+-#endif /* __ASM_ARCH_RMOBILE_H */
+diff --git a/arch/arm/include/asm/arch-rmobile/sh73a0-gpio.h b/arch/arm/include/asm/arch-rmobile/sh73a0-gpio.h
+deleted file mode 100644
+index 398e2c1..0000000
+--- a/arch/arm/include/asm/arch-rmobile/sh73a0-gpio.h
++++ /dev/null
+@@ -1,553 +0,0 @@
+-#ifndef __ASM_SH73A0_H__
+-#define __ASM_SH73A0_H__
+-
+-/* Pin Function Controller:
+- * GPIO_FN_xx - GPIO used to select pin function and MSEL switch
+- * GPIO_PORTxx - GPIO mapped to real I/O pin on CPU
+- */
+-enum {
+- /* Hardware manual Table 25-1 (GPIO) */
+- GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4,
+- GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9,
+-
+- GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14,
+- GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19,
+-
+- GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24,
+- GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29,
+-
+- GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34,
+- GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39,
+-
+- GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44,
+- GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49,
+-
+- GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54,
+- GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59,
+-
+- GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64,
+- GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69,
+-
+- GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74,
+- GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79,
+-
+- GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84,
+- GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89,
+-
+- GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94,
+- GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99,
+-
+- GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104,
+- GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109,
+-
+- GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114,
+- GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118,
+-
+- GPIO_PORT128, GPIO_PORT129,
+-
+- GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134,
+- GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139,
+-
+- GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144,
+- GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149,
+-
+- GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154,
+- GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159,
+-
+- GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164,
+-
+- GPIO_PORT192, GPIO_PORT193, GPIO_PORT194,
+- GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199,
+-
+- GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204,
+- GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209,
+-
+- GPIO_PORT210, GPIO_PORT211, GPIO_PORT212, GPIO_PORT213, GPIO_PORT214,
+- GPIO_PORT215, GPIO_PORT216, GPIO_PORT217, GPIO_PORT218, GPIO_PORT219,
+-
+- GPIO_PORT220, GPIO_PORT221, GPIO_PORT222, GPIO_PORT223, GPIO_PORT224,
+- GPIO_PORT225, GPIO_PORT226, GPIO_PORT227, GPIO_PORT228, GPIO_PORT229,
+-
+- GPIO_PORT230, GPIO_PORT231, GPIO_PORT232, GPIO_PORT233, GPIO_PORT234,
+- GPIO_PORT235, GPIO_PORT236, GPIO_PORT237, GPIO_PORT238, GPIO_PORT239,
+-
+- GPIO_PORT240, GPIO_PORT241, GPIO_PORT242, GPIO_PORT243, GPIO_PORT244,
+- GPIO_PORT245, GPIO_PORT246, GPIO_PORT247, GPIO_PORT248, GPIO_PORT249,
+-
+- GPIO_PORT250, GPIO_PORT251, GPIO_PORT252, GPIO_PORT253, GPIO_PORT254,
+- GPIO_PORT255, GPIO_PORT256, GPIO_PORT257, GPIO_PORT258, GPIO_PORT259,
+-
+- GPIO_PORT260, GPIO_PORT261, GPIO_PORT262, GPIO_PORT263, GPIO_PORT264,
+- GPIO_PORT265, GPIO_PORT266, GPIO_PORT267, GPIO_PORT268, GPIO_PORT269,
+-
+- GPIO_PORT270, GPIO_PORT271, GPIO_PORT272, GPIO_PORT273, GPIO_PORT274,
+- GPIO_PORT275, GPIO_PORT276, GPIO_PORT277, GPIO_PORT278, GPIO_PORT279,
+-
+- GPIO_PORT280, GPIO_PORT281, GPIO_PORT282,
+-
+- GPIO_PORT288, GPIO_PORT289,
+-
+- GPIO_PORT290, GPIO_PORT291, GPIO_PORT292, GPIO_PORT293, GPIO_PORT294,
+- GPIO_PORT295, GPIO_PORT296, GPIO_PORT297, GPIO_PORT298, GPIO_PORT299,
+-
+- GPIO_PORT300, GPIO_PORT301, GPIO_PORT302, GPIO_PORT303, GPIO_PORT304,
+- GPIO_PORT305, GPIO_PORT306, GPIO_PORT307, GPIO_PORT308, GPIO_PORT309,
+-
+- /* Table 25-1 (Function 0-7) */
+- GPIO_FN_VBUS_0,
+- GPIO_FN_GPI0,
+- GPIO_FN_GPI1,
+- GPIO_FN_GPI2,
+- GPIO_FN_GPI3,
+- GPIO_FN_GPI4,
+- GPIO_FN_GPI5,
+- GPIO_FN_GPI6,
+- GPIO_FN_GPI7,
+- GPIO_FN_SCIFA7_RXD,
+- GPIO_FN_SCIFA7_CTS_,
+- GPIO_FN_GPO7, GPIO_FN_MFG0_OUT2,
+- GPIO_FN_GPO6, GPIO_FN_MFG1_OUT2,
+- GPIO_FN_GPO5, GPIO_FN_SCIFA0_SCK, GPIO_FN_FSICOSLDT3, \
+- GPIO_FN_PORT16_VIO_CKOR,
+- GPIO_FN_SCIFA0_TXD,
+- GPIO_FN_SCIFA7_TXD,
+- GPIO_FN_SCIFA7_RTS_, GPIO_FN_PORT19_VIO_CKO2,
+- GPIO_FN_GPO0,
+- GPIO_FN_GPO1,
+- GPIO_FN_GPO2, GPIO_FN_STATUS0,
+- GPIO_FN_GPO3, GPIO_FN_STATUS1,
+- GPIO_FN_GPO4, GPIO_FN_STATUS2,
+- GPIO_FN_VINT,
+- GPIO_FN_TCKON,
+- GPIO_FN_XDVFS1, GPIO_FN_PORT27_I2C_SCL2, GPIO_FN_PORT27_I2C_SCL3, \
+- GPIO_FN_MFG0_OUT1, GPIO_FN_PORT27_IROUT,
+- GPIO_FN_XDVFS2, GPIO_FN_PORT28_I2C_SDA2, GPIO_FN_PORT28_I2C_SDA3, \
+- GPIO_FN_PORT28_TPU1TO1,
+- GPIO_FN_SIM_RST, GPIO_FN_PORT29_TPU1TO1,
+- GPIO_FN_SIM_CLK, GPIO_FN_PORT30_VIO_CKOR,
+- GPIO_FN_SIM_D, GPIO_FN_PORT31_IROUT,
+- GPIO_FN_SCIFA4_TXD,
+- GPIO_FN_SCIFA4_RXD, GPIO_FN_XWUP,
+- GPIO_FN_SCIFA4_RTS_,
+- GPIO_FN_SCIFA4_CTS_,
+- GPIO_FN_FSIBOBT, GPIO_FN_FSIBIBT,
+- GPIO_FN_FSIBOLR, GPIO_FN_FSIBILR,
+- GPIO_FN_FSIBOSLD,
+- GPIO_FN_FSIBISLD,
+- GPIO_FN_VACK,
+- GPIO_FN_XTAL1L,
+- GPIO_FN_SCIFA0_RTS_, GPIO_FN_FSICOSLDT2,
+- GPIO_FN_SCIFA0_RXD,
+- GPIO_FN_SCIFA0_CTS_, GPIO_FN_FSICOSLDT1,
+- GPIO_FN_FSICOBT, GPIO_FN_FSICIBT, GPIO_FN_FSIDOBT, GPIO_FN_FSIDIBT,
+- GPIO_FN_FSICOLR, GPIO_FN_FSICILR, GPIO_FN_FSIDOLR, GPIO_FN_FSIDILR,
+- GPIO_FN_FSICOSLD, GPIO_FN_PORT47_FSICSPDIF,
+- GPIO_FN_FSICISLD, GPIO_FN_FSIDISLD,
+- GPIO_FN_FSIACK, GPIO_FN_PORT49_IRDA_OUT, GPIO_FN_PORT49_IROUT, \
+- GPIO_FN_FSIAOMC,
+- GPIO_FN_FSIAOLR, GPIO_FN_BBIF2_TSYNC2, GPIO_FN_TPU2TO2, GPIO_FN_FSIAILR,
+-
+- GPIO_FN_FSIAOBT, GPIO_FN_BBIF2_TSCK2, GPIO_FN_TPU2TO3, GPIO_FN_FSIAIBT,
+- GPIO_FN_FSIAOSLD, GPIO_FN_BBIF2_TXD2,
+- GPIO_FN_FSIASPDIF, GPIO_FN_PORT53_IRDA_IN, GPIO_FN_TPU3TO3, \
+- GPIO_FN_FSIBSPDIF, GPIO_FN_PORT53_FSICSPDIF,
+- GPIO_FN_FSIBCK, GPIO_FN_PORT54_IRDA_FIRSEL, GPIO_FN_TPU3TO2, \
+- GPIO_FN_FSIBOMC, GPIO_FN_FSICCK, GPIO_FN_FSICOMC,
+- GPIO_FN_FSIAISLD, GPIO_FN_TPU0TO0,
+- GPIO_FN_A0, GPIO_FN_BS_,
+- GPIO_FN_A12, GPIO_FN_PORT58_KEYOUT7, GPIO_FN_TPU4TO2,
+- GPIO_FN_A13, GPIO_FN_PORT59_KEYOUT6, GPIO_FN_TPU0TO1,
+- GPIO_FN_A14, GPIO_FN_KEYOUT5,
+- GPIO_FN_A15, GPIO_FN_KEYOUT4,
+- GPIO_FN_A16, GPIO_FN_KEYOUT3, GPIO_FN_MSIOF0_SS1,
+- GPIO_FN_A17, GPIO_FN_KEYOUT2, GPIO_FN_MSIOF0_TSYNC,
+- GPIO_FN_A18, GPIO_FN_KEYOUT1, GPIO_FN_MSIOF0_TSCK,
+- GPIO_FN_A19, GPIO_FN_KEYOUT0, GPIO_FN_MSIOF0_TXD,
+- GPIO_FN_A20, GPIO_FN_KEYIN0, GPIO_FN_MSIOF0_RSCK,
+- GPIO_FN_A21, GPIO_FN_KEYIN1, GPIO_FN_MSIOF0_RSYNC,
+- GPIO_FN_A22, GPIO_FN_KEYIN2, GPIO_FN_MSIOF0_MCK0,
+- GPIO_FN_A23, GPIO_FN_KEYIN3, GPIO_FN_MSIOF0_MCK1,
+- GPIO_FN_A24, GPIO_FN_KEYIN4, GPIO_FN_MSIOF0_RXD,
+- GPIO_FN_A25, GPIO_FN_KEYIN5, GPIO_FN_MSIOF0_SS2,
+- GPIO_FN_A26, GPIO_FN_KEYIN6,
+- GPIO_FN_KEYIN7,
+- GPIO_FN_D0_NAF0,
+- GPIO_FN_D1_NAF1,
+- GPIO_FN_D2_NAF2,
+- GPIO_FN_D3_NAF3,
+- GPIO_FN_D4_NAF4,
+- GPIO_FN_D5_NAF5,
+- GPIO_FN_D6_NAF6,
+- GPIO_FN_D7_NAF7,
+- GPIO_FN_D8_NAF8,
+- GPIO_FN_D9_NAF9,
+- GPIO_FN_D10_NAF10,
+- GPIO_FN_D11_NAF11,
+- GPIO_FN_D12_NAF12,
+- GPIO_FN_D13_NAF13,
+- GPIO_FN_D14_NAF14,
+- GPIO_FN_D15_NAF15,
+- GPIO_FN_CS4_,
+- GPIO_FN_CS5A_, GPIO_FN_PORT91_RDWR,
+- GPIO_FN_CS5B_, GPIO_FN_FCE1_,
+- GPIO_FN_CS6B_, GPIO_FN_DACK0,
+- GPIO_FN_FCE0_, GPIO_FN_CS6A_,
+- GPIO_FN_WAIT_, GPIO_FN_DREQ0,
+- GPIO_FN_RD__FSC,
+- GPIO_FN_WE0__FWE, GPIO_FN_RDWR_FWE,
+- GPIO_FN_WE1_,
+- GPIO_FN_FRB,
+- GPIO_FN_CKO,
+- GPIO_FN_NBRSTOUT_,
+- GPIO_FN_NBRST_,
+- GPIO_FN_BBIF2_TXD,
+- GPIO_FN_BBIF2_RXD,
+- GPIO_FN_BBIF2_SYNC,
+- GPIO_FN_BBIF2_SCK,
+- GPIO_FN_SCIFA3_CTS_, GPIO_FN_MFG3_IN2,
+- GPIO_FN_SCIFA3_RXD, GPIO_FN_MFG3_IN1,
+- GPIO_FN_BBIF1_SS2, GPIO_FN_SCIFA3_RTS_, GPIO_FN_MFG3_OUT1,
+- GPIO_FN_SCIFA3_TXD,
+- GPIO_FN_HSI_RX_DATA, GPIO_FN_BBIF1_RXD,
+- GPIO_FN_HSI_TX_WAKE, GPIO_FN_BBIF1_TSCK,
+- GPIO_FN_HSI_TX_DATA, GPIO_FN_BBIF1_TSYNC,
+- GPIO_FN_HSI_TX_READY, GPIO_FN_BBIF1_TXD,
+- GPIO_FN_HSI_RX_READY, GPIO_FN_BBIF1_RSCK, GPIO_FN_PORT115_I2C_SCL2, \
+- GPIO_FN_PORT115_I2C_SCL3,
+- GPIO_FN_HSI_RX_WAKE, GPIO_FN_BBIF1_RSYNC, GPIO_FN_PORT116_I2C_SDA2, \
+- GPIO_FN_PORT116_I2C_SDA3,
+- GPIO_FN_HSI_RX_FLAG, GPIO_FN_BBIF1_SS1, GPIO_FN_BBIF1_FLOW,
+- GPIO_FN_HSI_TX_FLAG,
+- GPIO_FN_VIO_VD, GPIO_FN_PORT128_LCD2VSYN, GPIO_FN_VIO2_VD, \
+- GPIO_FN_LCD2D0,
+-
+- GPIO_FN_VIO_HD, GPIO_FN_PORT129_LCD2HSYN, GPIO_FN_PORT129_LCD2CS_, \
+- GPIO_FN_VIO2_HD, GPIO_FN_LCD2D1,
+- GPIO_FN_VIO_D0, GPIO_FN_PORT130_MSIOF2_RXD, GPIO_FN_LCD2D10,
+- GPIO_FN_VIO_D1, GPIO_FN_PORT131_KEYOUT6, GPIO_FN_PORT131_MSIOF2_SS1, \
+- GPIO_FN_PORT131_KEYOUT11, GPIO_FN_LCD2D11,
+- GPIO_FN_VIO_D2, GPIO_FN_PORT132_KEYOUT7, GPIO_FN_PORT132_MSIOF2_SS2, \
+- GPIO_FN_PORT132_KEYOUT10, GPIO_FN_LCD2D12,
+- GPIO_FN_VIO_D3, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_LCD2D13,
+- GPIO_FN_VIO_D4, GPIO_FN_MSIOF2_TXD, GPIO_FN_LCD2D14,
+- GPIO_FN_VIO_D5, GPIO_FN_MSIOF2_TSCK, GPIO_FN_LCD2D15,
+- GPIO_FN_VIO_D6, GPIO_FN_PORT136_KEYOUT8, GPIO_FN_LCD2D16,
+- GPIO_FN_VIO_D7, GPIO_FN_PORT137_KEYOUT9, GPIO_FN_LCD2D17,
+- GPIO_FN_VIO_D8, GPIO_FN_PORT138_KEYOUT8, GPIO_FN_VIO2_D0, \
+- GPIO_FN_LCD2D6,
+- GPIO_FN_VIO_D9, GPIO_FN_PORT139_KEYOUT9, GPIO_FN_VIO2_D1, \
+- GPIO_FN_LCD2D7,
+- GPIO_FN_VIO_D10, GPIO_FN_TPU0TO2, GPIO_FN_VIO2_D2, GPIO_FN_LCD2D8,
+- GPIO_FN_VIO_D11, GPIO_FN_TPU0TO3, GPIO_FN_VIO2_D3, GPIO_FN_LCD2D9,
+- GPIO_FN_VIO_D12, GPIO_FN_PORT142_KEYOUT10, GPIO_FN_VIO2_D4, \
+- GPIO_FN_LCD2D2,
+- GPIO_FN_VIO_D13, GPIO_FN_PORT143_KEYOUT11, GPIO_FN_PORT143_KEYOUT6, \
+- GPIO_FN_VIO2_D5, GPIO_FN_LCD2D3,
+- GPIO_FN_VIO_D14, GPIO_FN_PORT144_KEYOUT7, GPIO_FN_VIO2_D6, \
+- GPIO_FN_LCD2D4,
+- GPIO_FN_VIO_D15, GPIO_FN_TPU1TO3, GPIO_FN_PORT145_LCD2DISP, \
+- GPIO_FN_PORT145_LCD2RS, GPIO_FN_VIO2_D7, GPIO_FN_LCD2D5,
+- GPIO_FN_VIO_CLK, GPIO_FN_LCD2DCK, GPIO_FN_PORT146_LCD2WR_, \
+- GPIO_FN_VIO2_CLK, GPIO_FN_LCD2D18,
+- GPIO_FN_VIO_FIELD, GPIO_FN_LCD2RD_, GPIO_FN_VIO2_FIELD, GPIO_FN_LCD2D19,
+- GPIO_FN_VIO_CKO,
+- GPIO_FN_A27, GPIO_FN_PORT149_RDWR, GPIO_FN_MFG0_IN1, \
+- GPIO_FN_PORT149_KEYOUT9,
+- GPIO_FN_MFG0_IN2,
+- GPIO_FN_TS_SPSYNC3, GPIO_FN_MSIOF2_RSCK,
+- GPIO_FN_TS_SDAT3, GPIO_FN_MSIOF2_RSYNC,
+- GPIO_FN_TPU1TO2, GPIO_FN_TS_SDEN3, GPIO_FN_PORT153_MSIOF2_SS1,
+- GPIO_FN_SCIFA2_TXD1, GPIO_FN_MSIOF2_MCK0,
+- GPIO_FN_SCIFA2_RXD1, GPIO_FN_MSIOF2_MCK1,
+- GPIO_FN_SCIFA2_RTS1_, GPIO_FN_PORT156_MSIOF2_SS2,
+- GPIO_FN_SCIFA2_CTS1_, GPIO_FN_PORT157_MSIOF2_RXD,
+- GPIO_FN_DINT_, GPIO_FN_SCIFA2_SCK1, GPIO_FN_TS_SCK3,
+- GPIO_FN_PORT159_SCIFB_SCK, GPIO_FN_PORT159_SCIFA5_SCK, GPIO_FN_NMI,
+- GPIO_FN_PORT160_SCIFB_TXD, GPIO_FN_PORT160_SCIFA5_TXD,
+- GPIO_FN_PORT161_SCIFB_CTS_, GPIO_FN_PORT161_SCIFA5_CTS_,
+- GPIO_FN_PORT162_SCIFB_RXD, GPIO_FN_PORT162_SCIFA5_RXD,
+- GPIO_FN_PORT163_SCIFB_RTS_, GPIO_FN_PORT163_SCIFA5_RTS_, \
+- GPIO_FN_TPU3TO0,
+- GPIO_FN_LCDD0,
+- GPIO_FN_LCDD1, GPIO_FN_PORT193_SCIFA5_CTS_, GPIO_FN_BBIF2_TSYNC1,
+- GPIO_FN_LCDD2, GPIO_FN_PORT194_SCIFA5_RTS_, GPIO_FN_BBIF2_TSCK1,
+- GPIO_FN_LCDD3, GPIO_FN_PORT195_SCIFA5_RXD, GPIO_FN_BBIF2_TXD1,
+- GPIO_FN_LCDD4, GPIO_FN_PORT196_SCIFA5_TXD,
+- GPIO_FN_LCDD5, GPIO_FN_PORT197_SCIFA5_SCK, GPIO_FN_MFG2_OUT2, \
+- GPIO_FN_TPU2TO1,
+- GPIO_FN_LCDD6,
+- GPIO_FN_LCDD7, GPIO_FN_TPU4TO1, GPIO_FN_MFG4_OUT2,
+- GPIO_FN_LCDD8, GPIO_FN_D16,
+- GPIO_FN_LCDD9, GPIO_FN_D17,
+- GPIO_FN_LCDD10, GPIO_FN_D18,
+- GPIO_FN_LCDD11, GPIO_FN_D19,
+- GPIO_FN_LCDD12, GPIO_FN_D20,
+- GPIO_FN_LCDD13, GPIO_FN_D21,
+- GPIO_FN_LCDD14, GPIO_FN_D22,
+- GPIO_FN_LCDD15, GPIO_FN_PORT207_MSIOF0L_SS1, GPIO_FN_D23,
+- GPIO_FN_LCDD16, GPIO_FN_PORT208_MSIOF0L_SS2, GPIO_FN_D24,
+- GPIO_FN_LCDD17, GPIO_FN_D25,
+- GPIO_FN_LCDD18, GPIO_FN_DREQ2, GPIO_FN_PORT210_MSIOF0L_SS1, GPIO_FN_D26,
+- GPIO_FN_LCDD19, GPIO_FN_PORT211_MSIOF0L_SS2, GPIO_FN_D27,
+- GPIO_FN_LCDD20, GPIO_FN_TS_SPSYNC1, GPIO_FN_MSIOF0L_MCK0, GPIO_FN_D28,
+- GPIO_FN_LCDD21, GPIO_FN_TS_SDAT1, GPIO_FN_MSIOF0L_MCK1, GPIO_FN_D29,
+- GPIO_FN_LCDD22, GPIO_FN_TS_SDEN1, GPIO_FN_MSIOF0L_RSCK, GPIO_FN_D30,
+- GPIO_FN_LCDD23, GPIO_FN_TS_SCK1, GPIO_FN_MSIOF0L_RSYNC, GPIO_FN_D31,
+- GPIO_FN_LCDDCK, GPIO_FN_LCDWR_,
+- GPIO_FN_LCDRD_, GPIO_FN_DACK2, GPIO_FN_PORT217_LCD2RS, \
+- GPIO_FN_MSIOF0L_TSYNC, GPIO_FN_VIO2_FIELD3, GPIO_FN_PORT217_LCD2DISP,
+- GPIO_FN_LCDHSYN, GPIO_FN_LCDCS_, GPIO_FN_LCDCS2_, GPIO_FN_DACK3, \
+- GPIO_FN_PORT218_VIO_CKOR,
+- GPIO_FN_LCDDISP, GPIO_FN_LCDRS, GPIO_FN_PORT219_LCD2WR_, \
+- GPIO_FN_DREQ3, GPIO_FN_MSIOF0L_TSCK, GPIO_FN_VIO2_CLK3, \
+- GPIO_FN_LCD2DCK_2,
+- GPIO_FN_LCDVSYN, GPIO_FN_LCDVSYN2,
+- GPIO_FN_LCDLCLK, GPIO_FN_DREQ1, GPIO_FN_PORT221_LCD2CS_, \
+- GPIO_FN_PWEN, GPIO_FN_MSIOF0L_RXD, GPIO_FN_VIO2_HD3, \
+- GPIO_FN_PORT221_LCD2HSYN,
+- GPIO_FN_LCDDON, GPIO_FN_LCDDON2, GPIO_FN_DACK1, GPIO_FN_OVCN, \
+- GPIO_FN_MSIOF0L_TXD, GPIO_FN_VIO2_VD3, GPIO_FN_PORT222_LCD2VSYN,
+-
+- GPIO_FN_SCIFA1_TXD, GPIO_FN_OVCN2,
+- GPIO_FN_EXTLP, GPIO_FN_SCIFA1_SCK, GPIO_FN_PORT226_VIO_CKO2,
+- GPIO_FN_SCIFA1_RTS_, GPIO_FN_IDIN,
+- GPIO_FN_SCIFA1_RXD,
+- GPIO_FN_SCIFA1_CTS_, GPIO_FN_MFG1_IN1,
+- GPIO_FN_MSIOF1_TXD, GPIO_FN_SCIFA2_TXD2,
+- GPIO_FN_MSIOF1_TSYNC, GPIO_FN_SCIFA2_CTS2_,
+- GPIO_FN_MSIOF1_TSCK, GPIO_FN_SCIFA2_SCK2,
+- GPIO_FN_MSIOF1_RXD, GPIO_FN_SCIFA2_RXD2,
+- GPIO_FN_MSIOF1_RSCK, GPIO_FN_SCIFA2_RTS2_, GPIO_FN_VIO2_CLK2, \
+- GPIO_FN_LCD2D20,
+- GPIO_FN_MSIOF1_RSYNC, GPIO_FN_MFG1_IN2, GPIO_FN_VIO2_VD2, \
+- GPIO_FN_LCD2D21,
+- GPIO_FN_MSIOF1_MCK0, GPIO_FN_PORT236_I2C_SDA2,
+- GPIO_FN_MSIOF1_MCK1, GPIO_FN_PORT237_I2C_SCL2,
+- GPIO_FN_MSIOF1_SS1, GPIO_FN_VIO2_FIELD2, GPIO_FN_LCD2D22,
+- GPIO_FN_MSIOF1_SS2, GPIO_FN_VIO2_HD2, GPIO_FN_LCD2D23,
+- GPIO_FN_SCIFA6_TXD,
+- GPIO_FN_PORT241_IRDA_OUT, GPIO_FN_PORT241_IROUT, GPIO_FN_MFG4_OUT1, \
+- GPIO_FN_TPU4TO0,
+- GPIO_FN_PORT242_IRDA_IN, GPIO_FN_MFG4_IN2,
+- GPIO_FN_PORT243_IRDA_FIRSEL, GPIO_FN_PORT243_VIO_CKO2,
+- GPIO_FN_PORT244_SCIFA5_CTS_, GPIO_FN_MFG2_IN1, \
+- GPIO_FN_PORT244_SCIFB_CTS_, GPIO_FN_MSIOF2R_RXD,
+- GPIO_FN_PORT245_SCIFA5_RTS_, GPIO_FN_MFG2_IN2, \
+- GPIO_FN_PORT245_SCIFB_RTS_, GPIO_FN_MSIOF2R_TXD,
+- GPIO_FN_PORT246_SCIFA5_RXD, GPIO_FN_MFG1_OUT1, \
+- GPIO_FN_PORT246_SCIFB_RXD, GPIO_FN_TPU1TO0,
+- GPIO_FN_PORT247_SCIFA5_TXD, GPIO_FN_MFG3_OUT2, \
+- GPIO_FN_PORT247_SCIFB_TXD, GPIO_FN_TPU3TO1,
+- GPIO_FN_PORT248_SCIFA5_SCK, GPIO_FN_MFG2_OUT1, \
+- GPIO_FN_PORT248_SCIFB_SCK, GPIO_FN_TPU2TO0, \
+- GPIO_FN_PORT248_I2C_SCL3, GPIO_FN_MSIOF2R_TSCK,
+- GPIO_FN_PORT249_IROUT, GPIO_FN_MFG4_IN1, \
+- GPIO_FN_PORT249_I2C_SDA3, GPIO_FN_MSIOF2R_TSYNC,
+- GPIO_FN_SDHICLK0,
+- GPIO_FN_SDHICD0,
+- GPIO_FN_SDHID0_0,
+- GPIO_FN_SDHID0_1,
+- GPIO_FN_SDHID0_2,
+- GPIO_FN_SDHID0_3,
+- GPIO_FN_SDHICMD0,
+- GPIO_FN_SDHIWP0,
+- GPIO_FN_SDHICLK1,
+- GPIO_FN_SDHID1_0, GPIO_FN_TS_SPSYNC2,
+- GPIO_FN_SDHID1_1, GPIO_FN_TS_SDAT2,
+- GPIO_FN_SDHID1_2, GPIO_FN_TS_SDEN2,
+- GPIO_FN_SDHID1_3, GPIO_FN_TS_SCK2,
+- GPIO_FN_SDHICMD1,
+- GPIO_FN_SDHICLK2,
+- GPIO_FN_SDHID2_0, GPIO_FN_TS_SPSYNC4,
+- GPIO_FN_SDHID2_1, GPIO_FN_TS_SDAT4,
+- GPIO_FN_SDHID2_2, GPIO_FN_TS_SDEN4,
+- GPIO_FN_SDHID2_3, GPIO_FN_TS_SCK4,
+- GPIO_FN_SDHICMD2,
+- GPIO_FN_MMCCLK0,
+- GPIO_FN_MMCD0_0,
+- GPIO_FN_MMCD0_1,
+- GPIO_FN_MMCD0_2,
+- GPIO_FN_MMCD0_3,
+- GPIO_FN_MMCD0_4, GPIO_FN_TS_SPSYNC5,
+- GPIO_FN_MMCD0_5, GPIO_FN_TS_SDAT5,
+- GPIO_FN_MMCD0_6, GPIO_FN_TS_SDEN5,
+- GPIO_FN_MMCD0_7, GPIO_FN_TS_SCK5,
+- GPIO_FN_MMCCMD0,
+- GPIO_FN_RESETOUTS_, GPIO_FN_EXTAL2OUT,
+- GPIO_FN_MCP_WAIT__MCP_FRB,
+- GPIO_FN_MCP_CKO, GPIO_FN_MMCCLK1,
+- GPIO_FN_MCP_D15_MCP_NAF15,
+- GPIO_FN_MCP_D14_MCP_NAF14,
+- GPIO_FN_MCP_D13_MCP_NAF13,
+- GPIO_FN_MCP_D12_MCP_NAF12,
+- GPIO_FN_MCP_D11_MCP_NAF11,
+- GPIO_FN_MCP_D10_MCP_NAF10,
+- GPIO_FN_MCP_D9_MCP_NAF9,
+- GPIO_FN_MCP_D8_MCP_NAF8, GPIO_FN_MMCCMD1,
+- GPIO_FN_MCP_D7_MCP_NAF7, GPIO_FN_MMCD1_7,
+-
+- GPIO_FN_MCP_D6_MCP_NAF6, GPIO_FN_MMCD1_6,
+- GPIO_FN_MCP_D5_MCP_NAF5, GPIO_FN_MMCD1_5,
+- GPIO_FN_MCP_D4_MCP_NAF4, GPIO_FN_MMCD1_4,
+- GPIO_FN_MCP_D3_MCP_NAF3, GPIO_FN_MMCD1_3,
+- GPIO_FN_MCP_D2_MCP_NAF2, GPIO_FN_MMCD1_2,
+- GPIO_FN_MCP_D1_MCP_NAF1, GPIO_FN_MMCD1_1,
+- GPIO_FN_MCP_D0_MCP_NAF0, GPIO_FN_MMCD1_0,
+- GPIO_FN_MCP_NBRSTOUT_,
+- GPIO_FN_MCP_WE0__MCP_FWE, GPIO_FN_MCP_RDWR_MCP_FWE,
+-
+- /* MSEL2 special case */
+- GPIO_FN_TSIF2_TS_XX1,
+- GPIO_FN_TSIF2_TS_XX2,
+- GPIO_FN_TSIF2_TS_XX3,
+- GPIO_FN_TSIF2_TS_XX4,
+- GPIO_FN_TSIF2_TS_XX5,
+- GPIO_FN_TSIF1_TS_XX1,
+- GPIO_FN_TSIF1_TS_XX2,
+- GPIO_FN_TSIF1_TS_XX3,
+- GPIO_FN_TSIF1_TS_XX4,
+- GPIO_FN_TSIF1_TS_XX5,
+- GPIO_FN_TSIF0_TS_XX1,
+- GPIO_FN_TSIF0_TS_XX2,
+- GPIO_FN_TSIF0_TS_XX3,
+- GPIO_FN_TSIF0_TS_XX4,
+- GPIO_FN_TSIF0_TS_XX5,
+- GPIO_FN_MST1_TS_XX1,
+- GPIO_FN_MST1_TS_XX2,
+- GPIO_FN_MST1_TS_XX3,
+- GPIO_FN_MST1_TS_XX4,
+- GPIO_FN_MST1_TS_XX5,
+- GPIO_FN_MST0_TS_XX1,
+- GPIO_FN_MST0_TS_XX2,
+- GPIO_FN_MST0_TS_XX3,
+- GPIO_FN_MST0_TS_XX4,
+- GPIO_FN_MST0_TS_XX5,
+-
+- /* MSEL3 special cases */
+- GPIO_FN_SDHI0_VCCQ_MC0_ON,
+- GPIO_FN_SDHI0_VCCQ_MC0_OFF,
+- GPIO_FN_DEBUG_MON_VIO,
+- GPIO_FN_DEBUG_MON_LCDD,
+- GPIO_FN_LCDC_LCDC0,
+- GPIO_FN_LCDC_LCDC1,
+-
+- /* MSEL4 special cases */
+- GPIO_FN_IRQ9_MEM_INT,
+- GPIO_FN_IRQ9_MCP_INT,
+- GPIO_FN_A11,
+- GPIO_FN_KEYOUT8,
+- GPIO_FN_TPU4TO3,
+- GPIO_FN_RESETA_N_PU_ON,
+- GPIO_FN_RESETA_N_PU_OFF,
+- GPIO_FN_EDBGREQ_PD,
+- GPIO_FN_EDBGREQ_PU,
+-
+- /* Functions with pull-ups */
+- GPIO_FN_KEYIN0_PU,
+- GPIO_FN_KEYIN1_PU,
+- GPIO_FN_KEYIN2_PU,
+- GPIO_FN_KEYIN3_PU,
+- GPIO_FN_KEYIN4_PU,
+- GPIO_FN_KEYIN5_PU,
+- GPIO_FN_KEYIN6_PU,
+- GPIO_FN_KEYIN7_PU,
+- GPIO_FN_SDHICD0_PU,
+- GPIO_FN_SDHID0_0_PU,
+- GPIO_FN_SDHID0_1_PU,
+- GPIO_FN_SDHID0_2_PU,
+- GPIO_FN_SDHID0_3_PU,
+- GPIO_FN_SDHICMD0_PU,
+- GPIO_FN_SDHIWP0_PU,
+- GPIO_FN_SDHID1_0_PU,
+- GPIO_FN_SDHID1_1_PU,
+- GPIO_FN_SDHID1_2_PU,
+- GPIO_FN_SDHID1_3_PU,
+- GPIO_FN_SDHICMD1_PU,
+- GPIO_FN_SDHID2_0_PU,
+- GPIO_FN_SDHID2_1_PU,
+- GPIO_FN_SDHID2_2_PU,
+- GPIO_FN_SDHID2_3_PU,
+- GPIO_FN_SDHICMD2_PU,
+- GPIO_FN_MMCCMD0_PU,
+- GPIO_FN_MMCCMD1_PU,
+- GPIO_FN_MMCD0_0_PU,
+- GPIO_FN_MMCD0_1_PU,
+- GPIO_FN_MMCD0_2_PU,
+- GPIO_FN_MMCD0_3_PU,
+- GPIO_FN_MMCD0_4_PU,
+- GPIO_FN_MMCD0_5_PU,
+- GPIO_FN_MMCD0_6_PU,
+- GPIO_FN_MMCD0_7_PU,
+- GPIO_FN_FSIACK_PU,
+- GPIO_FN_FSIAILR_PU,
+- GPIO_FN_FSIAIBT_PU,
+- GPIO_FN_FSIAISLD_PU,
+-
+- /* end of GPIO */
+- GPIO_NR,
+-};
+-
+-/* DMA slave IDs */
+-enum {
+- SHDMA_SLAVE_INVALID,
+- SHDMA_SLAVE_SCIF0_TX,
+- SHDMA_SLAVE_SCIF0_RX,
+- SHDMA_SLAVE_SCIF1_TX,
+- SHDMA_SLAVE_SCIF1_RX,
+- SHDMA_SLAVE_SCIF2_TX,
+- SHDMA_SLAVE_SCIF2_RX,
+- SHDMA_SLAVE_SCIF3_TX,
+- SHDMA_SLAVE_SCIF3_RX,
+- SHDMA_SLAVE_SCIF4_TX,
+- SHDMA_SLAVE_SCIF4_RX,
+- SHDMA_SLAVE_SCIF5_TX,
+- SHDMA_SLAVE_SCIF5_RX,
+- SHDMA_SLAVE_SCIF6_TX,
+- SHDMA_SLAVE_SCIF6_RX,
+- SHDMA_SLAVE_SCIF7_TX,
+- SHDMA_SLAVE_SCIF7_RX,
+- SHDMA_SLAVE_SCIF8_TX,
+- SHDMA_SLAVE_SCIF8_RX,
+- SHDMA_SLAVE_SDHI0_TX,
+- SHDMA_SLAVE_SDHI0_RX,
+- SHDMA_SLAVE_SDHI1_TX,
+- SHDMA_SLAVE_SDHI1_RX,
+- SHDMA_SLAVE_SDHI2_TX,
+- SHDMA_SLAVE_SDHI2_RX,
+- SHDMA_SLAVE_MMCIF_TX,
+- SHDMA_SLAVE_MMCIF_RX,
+-};
+-
+-/*
+- * SH73A0 IRQ LOCATION TABLE
+- *
+- * 416 -----------------------------------------
+- * IRQ0-IRQ15
+- * 431 -----------------------------------------
+- * ...
+- * 448 -----------------------------------------
+- * sh73a0-intcs
+- * sh73a0-intca-irq-pins
+- * 680 -----------------------------------------
+- * ...
+- * 700 -----------------------------------------
+- * sh73a0-pint0
+- * 731 -----------------------------------------
+- * 732 -----------------------------------------
+- * sh73a0-pint1
+- * 739 -----------------------------------------
+- * ...
+- * 800 -----------------------------------------
+- * IRQ16-IRQ31
+- * 815 -----------------------------------------
+- * ...
+- * 928 -----------------------------------------
+- * sh73a0-intca-irq-pins
+- * 943 -----------------------------------------
+- */
+-
+-/* PINT interrupts are located at Linux IRQ 700 and up */
+-#define SH73A0_PINT0_IRQ(irq) ((irq) + 700)
+-#define SH73A0_PINT1_IRQ(irq) ((irq) + 732)
+-
+-#endif /* __ASM_SH73A0_H__ */
+diff --git a/arch/arm/include/asm/arch-rmobile/sh73a0.h b/arch/arm/include/asm/arch-rmobile/sh73a0.h
+deleted file mode 100644
+index bdbb408..0000000
+--- a/arch/arm/include/asm/arch-rmobile/sh73a0.h
++++ /dev/null
+@@ -1,289 +0,0 @@
+-#ifndef __ASM_ARCH_RMOBILE_SH73A0_H
+-#define __ASM_ARCH_RMOBILE_SH73A0_H
+-
+-/* Global Timer */
+-#define GLOBAL_TIMER_BASE_ADDR (0xF0000200)
+-#define MERAM_BASE (0xE5580000)
+-
+-/* GIC */
+-#define GIC_BASE (0xF0000100)
+-#define ICCICR GIC_BASE
+-
+-/* Secure control register */
+-#define LIFEC_SEC_SRC (0xE6110008)
+-
+-/* RWDT */
+-#define RWDT_BASE (0xE6020000)
+-
+-/* HPB Semaphore Control Registers */
+-#define HPB_BASE (0xE6001010)
+-
+-/* Bus Semaphore Control Registers */
+-#define HPBSCR_BASE (0xE6001600)
+-
+-/* SBSC1 */
+-#define SBSC1_BASE (0xFE400000)
+-#define SDMRA1A (SBSC1_BASE + 0x100000)
+-#define SDMRA2A (SBSC1_BASE + 0x1C0000)
+-#define SDMRA3A (SBSC1_BASE + 0x104000)
+-
+-/* SBSC2 */
+-#define SBSC2_BASE (0xFB400000)
+-#define SDMRA1B (SBSC2_BASE + 0x100000)
+-#define SDMRA2B (SBSC2_BASE + 0x1C0000)
+-#define SDMRA3B (SBSC2_BASE + 0x104000)
+-
+-/* CPG */
+-#define CPG_BASE (0xE6150000)
+-#define CPG_SRCR_BASE (CPG_BASE + 0x80A0)
+-#define WUPCR (CPG_BASE + 0x1010)
+-#define SRESCR (CPG_BASE + 0x1018)
+-#define PCLKCR (CPG_BASE + 0x1020)
+-
+-/* SYSC */
+-#define SYSC_BASE (0xE6180000)
+-#define RESCNT2 (SYSC_BASE + 0x8020)
+-
+-/* BSC */
+-#define BSC_BASE (0xFEC10000)
+-
+-/* SCIF */
+-#define SCIF0_BASE (0xE6C40000)
+-#define SCIF1_BASE (0xE6C50000)
+-#define SCIF2_BASE (0xE6C60000)
+-#define SCIF3_BASE (0xE6C70000)
+-#define SCIF4_BASE (0xE6C80000)
+-#define SCIF5_BASE (0xE6CB0000)
+-#define SCIF6_BASE (0xE6CC0000)
+-#define SCIF7_BASE (0xE6CD0000)
+-
+-#ifndef __ASSEMBLY__
+-#include <asm/types.h>
+-
+-/* RWDT */
+-struct sh73a0_rwdt {
+- u16 rwtcnt0; /* 0x00 */
+- u16 dummy0; /* 0x02 */
+- u16 rwtcsra0; /* 0x04 */
+- u16 dummy1; /* 0x06 */
+- u16 rwtcsrb0; /* 0x08 */
+-};
+-
+-/* HPB Semaphore Control Registers */
+-struct sh73a0_hpb {
+- u32 hpbctrl0;
+- u32 hpbctrl1;
+- u32 hpbctrl2;
+- u32 cccr;
+- u32 dummy0; /* 0x20 */
+- u32 hpbctrl4;
+- u32 hpbctrl5;
+- u32 dummy1; /* 0x2C */
+- u32 hpbctrl6;
+-};
+-
+-/* Bus Semaphore Control Registers */
+-struct sh73a0_hpb_bscr {
+- u32 mpsrc; /* 0x00 */
+- u32 mpacctl; /* 0x04 */
+- u32 dummy0[6];
+- u32 smgpiosrc; /* 0x20 */
+- u32 smgpioerr;
+- u32 smgpiotime;
+- u32 smgpiocnt;
+- u32 dummy1[4]; /* 0x30 .. 0x3C */
+- u32 smcmt2src;
+- u32 smcmt2err;
+- u32 smcmt2time;
+- u32 smcmt2cnt;
+- u32 smcpgsrc;
+- u32 smcpgerr;
+- u32 smcpgtime;
+- u32 smcpgcnt;
+- u32 dummy2[4]; /* 0x60 - 0x6C */
+- u32 smsyscsrc;
+- u32 smsyscerr;
+- u32 smsysctime;
+- u32 smsysccnt;
+-};
+-
+-/* SBSC */
+-struct sh73a0_sbsc {
+- u32 dummy0[2]; /* 0x00, 0x04 */
+- u32 sdcr0;
+- u32 sdcr1;
+- u32 sdpcr;
+- u32 dummy1; /* 0x14 */
+- u32 sdcr0s;
+- u32 sdcr1s;
+- u32 rtcsr;
+- u32 dummy2; /* 0x24 */
+- u32 rtcor;
+- u32 rtcorh;
+- u32 rtcors;
+- u32 rtcorsh;
+- u32 dummy3[2]; /* 0x38, 0x3C */
+- u32 sdwcrc0;
+- u32 sdwcrc1;
+- u32 sdwcr00;
+- u32 sdwcr01;
+- u32 sdwcr10;
+- u32 sdwcr11;
+- u32 sdpdcr0;
+- u32 dummy4; /* 0x5C */
+- u32 sdwcr2;
+- u32 sdwcrc2;
+- u32 zqccr;
+- u32 dummy5[6]; /* 0x6C .. 0x80 */
+- u32 sdmracr0;
+- u32 dummy6; /* 0x88 */
+- u32 sdmrtmpcr;
+- u32 dummy7; /* 0x90 */
+- u32 sdmrtmpmsk;
+- u32 dummy8; /* 0x98 */
+- u32 sdgencnt;
+- u32 dphycnt0;
+- u32 dphycnt1;
+- u32 dphycnt2;
+- u32 dummy9[2]; /* 0xAC .. 0xB0 */
+- u32 sddrvcr0;
+- u32 dummy10[14]; /* 0xB8 .. 0xEC */
+- u32 dptdivcr0;
+- u32 dptdivcr1;
+- u32 dptdivcr2;
+- u32 dummy11; /* 0xFC */
+- u32 sdptcr0;
+- u32 sdptcr1;
+- u32 sdptcr2;
+- u32 sdptcr3; /* 0x10C */
+- u32 dummy12[145]; /* 0x110 .. 0x350 */
+- u32 dllcnt0; /* 0x354 */
+- u32 sbscmon0;
+-};
+-
+-/* CPG */
+-struct sh73a0_sbsc_cpg {
+- u32 frqcra; /* 0x00 */
+- u32 frqcrb;
+- u32 vclkcr1;
+- u32 vclkcr2;
+- u32 zbckcr;
+- u32 flckcr;
+- u32 fsiackcr;
+- u32 vclkcr3;
+- u32 rtstbcr;
+- u32 systbcr;
+- u32 pll1cr;
+- u32 pll2cr;
+- u32 mstpsr0;
+- u32 dummy0; /* 0x34 */
+- u32 mstpsr1;
+- u32 mstpsr5;
+- u32 mstpsr2;
+- u32 dummy1; /* 0x44 */
+- u32 mstpsr3;
+- u32 mstpsr4;
+- u32 dummy2; /* 0x50 */
+- u32 astat;
+- u32 dvfscr0;
+- u32 dvfscr1;
+- u32 dsitckcr;
+- u32 dsi0pckcr;
+- u32 dsi1pckcr;
+- u32 dsi0phycr;
+- u32 dsi1phycr;
+- u32 sd0ckcr;
+- u32 sd1ckcr;
+- u32 sd2ckcr;
+- u32 subckcr;
+- u32 spuackcr;
+- u32 msuckcr;
+- u32 hsickcr;
+- u32 fsibckcr;
+- u32 spuvckcr;
+- u32 mfck1cr;
+- u32 mfck2cr;
+- u32 dummy3[8]; /* 0xA0 .. 0xBC */
+- u32 ckscr;
+- u32 dummy4; /* 0xC4 */
+- u32 pll1stpcr;
+- u32 mpmode;
+- u32 pllecr;
+- u32 dummy5; /* 0xD4 */
+- u32 pll0cr;
+- u32 pll3cr;
+- u32 dummy6; /* 0xE0 */
+- u32 frqcrd;
+- u32 dummyi7; /* 0xE8 */
+- u32 vrefcr;
+- u32 pll0stpcr;
+- u32 dummy8; /* 0xF4 */
+- u32 pll2stpcr;
+- u32 pll3stpcr;
+- u32 dummy9[4]; /* 0x100 .. 0x10c */
+- u32 rmstpcr0;
+- u32 rmstpcr1;
+- u32 rmstpcr2;
+- u32 rmstpcr3;
+- u32 rmstpcr4;
+- u32 rmstpcr5;
+- u32 dummy10[2]; /* 0x128 .. 0x12c */
+- u32 smstpcr0;
+- u32 smstpcr1;
+- u32 smstpcr2;
+- u32 smstpcr3;
+- u32 smstpcr4;
+- u32 smstpcr5;
+- u32 dummy11[2]; /* 0x148 .. 0x14c */
+- u32 cpgxxcs4;
+- u32 dummy12[7]; /* 0x154 .. 0x16c */
+- u32 dvfscr2;
+- u32 dvfscr3;
+- u32 dvfscr4;
+- u32 dvfscr5; /* 0x17C */
+-};
+-
+-/* CPG SRCR part OK */
+-struct sh73a0_sbsc_cpg_srcr {
+- u32 srcr0;
+- u32 dummy0; /* 0xA4 */
+- u32 srcr1;
+- u32 dummy1; /* 0xAC */
+- u32 srcr2;
+- u32 dummy2; /* 0xB4 */
+- u32 srcr3;
+- u32 srcr4;
+- u32 dummy3; /* 0xC0 */
+- u32 srcr5;
+-};
+-
+-/* BSC */
+-struct sh73a0_bsc {
+- u32 cmncr;
+- u32 cs0bcr;
+- u32 cs2bcr;
+- u32 dummy0; /* 0x0C */
+- u32 cs4bcr;
+- u32 cs5abcr;
+- u32 cs5bbcr;
+- u32 cs6abcr;
+- u32 cs6bbcr;
+- u32 cs0wcr;
+- u32 cs2wcr;
+- u32 dummy1; /* 0x2C */
+- u32 cs4wcr;
+- u32 cs5awcr;
+- u32 cs5bwcr;
+- u32 cs6awcr;
+- u32 cs6bwcr;
+- u32 rbwtcnt;
+- u32 busycr;
+- u32 dummy2; /* 0x5c */
+- u32 cs7abcr;
+- u32 cs7awcr;
+- u32 dummy3[2]; /* 0x68, 0x6C */
+- u32 bromtimcr;
+-};
+-#endif /* __ASSEMBLY__ */
+-
+-#endif /* __ASM_ARCH_RMOBILE_SH73A0_H */
+diff --git a/arch/arm/include/asm/arch-rmobile/sys_proto.h b/arch/arm/include/asm/arch-rmobile/sys_proto.h
+deleted file mode 100644
+index fad4e4e..0000000
+--- a/arch/arm/include/asm/arch-rmobile/sys_proto.h
++++ /dev/null
+@@ -1,29 +0,0 @@
+-/*
+- * (C) Copyright 2010
+- * Texas Instruments, <www.ti.com>
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of
+- * the License, or (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+- * MA 02111-1307 USA
+- */
+-
+-#ifndef _SYS_PROTO_H_
+-#define _SYS_PROTO_H_
+-
+-struct rmobile_sysinfo {
+- char *board_string;
+-};
+-extern const struct rmobile_sysinfo sysinfo;
+-
+-#endif
+diff --git a/arch/arm/include/asm/arch-s3c24x0/gpio.h b/arch/arm/include/asm/arch-s3c24x0/gpio.h
+deleted file mode 100644
+index 76bc52c..0000000
+--- a/arch/arm/include/asm/arch-s3c24x0/gpio.h
++++ /dev/null
+@@ -1,171 +0,0 @@
+-/*
+- * Copyright (c) 2012.
+- *
+- * Gabriel Huau <contact at huau-gabriel.fr>
+- *
+- * See file CREDITS for list of people who contributed to this
+- * project.
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of
+- * the License, or (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+- * MA 02111-1307 USA
+- */
+-
+-#ifndef _S3C24X0_GPIO_H_
+-#define _S3C24X0_GPIO_H_
+-
+-enum s3c2440_gpio {
+- GPA0,
+- GPA1,
+- GPA2,
+- GPA3,
+- GPA4,
+- GPA5,
+- GPA6,
+- GPA7,
+- GPA8,
+- GPA9,
+- GPA10,
+- GPA11,
+- GPA12,
+- GPA13,
+- GPA14,
+- GPA15,
+- GPA16,
+- GPA17,
+- GPA18,
+- GPA19,
+- GPA20,
+- GPA21,
+- GPA22,
+- GPA23,
+- GPA24,
+-
+- GPB0 = 32,
+- GPB1,
+- GPB2,
+- GPB3,
+- GPB4,
+- GPB5,
+- GPB6,
+- GPB7,
+- GPB8,
+- GPB9,
+- GPB10,
+-
+- GPC0 = 64,
+- GPC1,
+- GPC2,
+- GPC3,
+- GPC4,
+- GPC5,
+- GPC6,
+- GPC7,
+- GPC8,
+- GPC9,
+- GPC10,
+- GPC11,
+- GPC12,
+- GPC13,
+- GPC14,
+- GPC15,
+-
+- GPD0 = 96,
+- GPD1,
+- GPD2,
+- GPD3,
+- GPD4,
+- GPD5,
+- GPD6,
+- GPD7,
+- GPD8,
+- GPD9,
+- GPD10,
+- GPD11,
+- GPD12,
+- GPD13,
+- GPD14,
+- GPD15,
+-
+- GPE0 = 128,
+- GPE1,
+- GPE2,
+- GPE3,
+- GPE4,
+- GPE5,
+- GPE6,
+- GPE7,
+- GPE8,
+- GPE9,
+- GPE10,
+- GPE11,
+- GPE12,
+- GPE13,
+- GPE14,
+- GPE15,
+-
+- GPF0 = 160,
+- GPF1,
+- GPF2,
+- GPF3,
+- GPF4,
+- GPF5,
+- GPF6,
+- GPF7,
+-
+- GPG0 = 192,
+- GPG1,
+- GPG2,
+- GPG3,
+- GPG4,
+- GPG5,
+- GPG6,
+- GPG7,
+- GPG8,
+- GPG9,
+- GPG10,
+- GPG11,
+- GPG12,
+- GPG13,
+- GPG14,
+- GPG15,
+-
+- GPH0 = 224,
+- GPH1,
+- GPH2,
+- GPH3,
+- GPH4,
+- GPH5,
+- GPH6,
+- GPH7,
+- GPH8,
+- GPH9,
+- GPH10,
+-
+- GPJ0 = 256,
+- GPJ1,
+- GPJ2,
+- GPJ3,
+- GPJ4,
+- GPJ5,
+- GPJ6,
+- GPJ7,
+- GPJ8,
+- GPJ9,
+- GPJ10,
+- GPJ11,
+- GPJ12,
+-};
+-
+-#endif
+diff --git a/arch/arm/include/asm/arch-s3c24x0/iomux.h b/arch/arm/include/asm/arch-s3c24x0/iomux.h
+deleted file mode 100644
+index cc22de7..0000000
+--- a/arch/arm/include/asm/arch-s3c24x0/iomux.h
++++ /dev/null
+@@ -1,200 +0,0 @@
+-/*
+- * Copyright (c) 2012
+- *
+- * Gabriel Huau <contact at huau-gabriel.fr>
+- *
+- * See file CREDITS for list of people who contributed to this
+- * project.
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of
+- * the License, or (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+- * MA 02111-1307 USA
+- */
+-
+-#ifndef _S3C24X0_IOMUX_H_
+-#define _S3C24X0_IOMUX_H_
+-
+-enum s3c2440_iomux_func {
+- /* PORT A */
+- IOMUXA_ADDR0 = 1,
+- IOMUXA_ADDR16 = (1 << 1),
+- IOMUXA_ADDR17 = (1 << 2),
+- IOMUXA_ADDR18 = (1 << 3),
+- IOMUXA_ADDR19 = (1 << 4),
+- IOMUXA_ADDR20 = (1 << 5),
+- IOMUXA_ADDR21 = (1 << 6),
+- IOMUXA_ADDR22 = (1 << 7),
+- IOMUXA_ADDR23 = (1 << 8),
+- IOMUXA_ADDR24 = (1 << 9),
+- IOMUXA_ADDR25 = (1 << 10),
+- IOMUXA_ADDR26 = (1 << 11),
+- IOMUXA_nGCS1 = (1 << 12),
+- IOMUXA_nGCS2 = (1 << 13),
+- IOMUXA_nGCS3 = (1 << 14),
+- IOMUXA_nGCS4 = (1 << 15),
+- IOMUXA_nGCS5 = (1 << 16),
+- IOMUXA_CLE = (1 << 17),
+- IOMUXA_ALE = (1 << 18),
+- IOMUXA_nFWE = (1 << 19),
+- IOMUXA_nFRE = (1 << 20),
+- IOMUXA_nRSTOUT = (1 << 21),
+- IOMUXA_nFCE = (1 << 22),
+-
+- /* PORT B */
+- IOMUXB_nXDREQ0 = (2 << 20),
+- IOMUXB_nXDACK0 = (2 << 18),
+- IOMUXB_nXDREQ1 = (2 << 16),
+- IOMUXB_nXDACK1 = (2 << 14),
+- IOMUXB_nXBREQ = (2 << 12),
+- IOMUXB_nXBACK = (2 << 10),
+- IOMUXB_TCLK0 = (2 << 8),
+- IOMUXB_TOUT3 = (2 << 6),
+- IOMUXB_TOUT2 = (2 << 4),
+- IOMUXB_TOUT1 = (2 << 2),
+- IOMUXB_TOUT0 = 2,
+-
+- /* PORT C */
+- IOMUXC_VS7 = (2 << 30),
+- IOMUXC_VS6 = (2 << 28),
+- IOMUXC_VS5 = (2 << 26),
+- IOMUXC_VS4 = (2 << 24),
+- IOMUXC_VS3 = (2 << 22),
+- IOMUXC_VS2 = (2 << 20),
+- IOMUXC_VS1 = (2 << 18),
+- IOMUXC_VS0 = (2 << 16),
+- IOMUXC_LCD_LPCREVB = (2 << 14),
+- IOMUXC_LCD_LPCREV = (2 << 12),
+- IOMUXC_LCD_LPCOE = (2 << 10),
+- IOMUXC_VM = (2 << 8),
+- IOMUXC_VFRAME = (2 << 6),
+- IOMUXC_VLINE = (2 << 4),
+- IOMUXC_VCLK = (2 << 2),
+- IOMUXC_LEND = 2,
+- IOMUXC_I2SSDI = (3 << 8),
+-
+- /* PORT D */
+- IOMUXD_VS23 = (2 << 30),
+- IOMUXD_VS22 = (2 << 28),
+- IOMUXD_VS21 = (2 << 26),
+- IOMUXD_VS20 = (2 << 24),
+- IOMUXD_VS19 = (2 << 22),
+- IOMUXD_VS18 = (2 << 20),
+- IOMUXD_VS17 = (2 << 18),
+- IOMUXD_VS16 = (2 << 16),
+- IOMUXD_VS15 = (2 << 14),
+- IOMUXD_VS14 = (2 << 12),
+- IOMUXD_VS13 = (2 << 10),
+- IOMUXD_VS12 = (2 << 8),
+- IOMUXD_VS11 = (2 << 6),
+- IOMUXD_VS10 = (2 << 4),
+- IOMUXD_VS9 = (2 << 2),
+- IOMUXD_VS8 = 2,
+- IOMUXD_nSS0 = (3 << 30),
+- IOMUXD_nSS1 = (3 << 28),
+- IOMUXD_SPICLK1 = (3 << 20),
+- IOMUXD_SPIMOSI1 = (3 << 18),
+- IOMUXD_SPIMISO1 = (3 << 16),
+-
+- /* PORT E */
+- IOMUXE_IICSDA = (2 << 30),
+- IOMUXE_IICSCL = (2 << 28),
+- IOMUXE_SPICLK0 = (2 << 26),
+- IOMUXE_SPIMOSI0 = (2 << 24),
+- IOMUXE_SPIMISO0 = (2 << 22),
+- IOMUXE_SDDAT3 = (2 << 20),
+- IOMUXE_SDDAT2 = (2 << 18),
+- IOMUXE_SDDAT1 = (2 << 16),
+- IOMUXE_SDDAT0 = (2 << 14),
+- IOMUXE_SDCMD = (2 << 12),
+- IOMUXE_SDCLK = (2 << 10),
+- IOMUXE_I2SDO = (2 << 8),
+- IOMUXE_I2SDI = (2 << 6),
+- IOMUXE_CDCLK = (2 << 4),
+- IOMUXE_I2SSCLK = (2 << 2),
+- IOMUXE_I2SLRCK = 2,
+- IOMUXE_AC_SDATA_OUT = (3 << 8),
+- IOMUXE_AC_SDATA_IN = (3 << 6),
+- IOMUXE_AC_nRESET = (3 << 4),
+- IOMUXE_AC_BIT_CLK = (3 << 2),
+- IOMUXE_AC_SYNC = 3,
+-
+- /* PORT F */
+- IOMUXF_EINT7 = (2 << 14),
+- IOMUXF_EINT6 = (2 << 12),
+- IOMUXF_EINT5 = (2 << 10),
+- IOMUXF_EINT4 = (2 << 8),
+- IOMUXF_EINT3 = (2 << 6),
+- IOMUXF_EINT2 = (2 << 4),
+- IOMUXF_EINT1 = (2 << 2),
+- IOMUXF_EINT0 = 2,
+-
+- /* PORT G */
+- IOMUXG_EINT23 = (2 << 30),
+- IOMUXG_EINT22 = (2 << 28),
+- IOMUXG_EINT21 = (2 << 26),
+- IOMUXG_EINT20 = (2 << 24),
+- IOMUXG_EINT19 = (2 << 22),
+- IOMUXG_EINT18 = (2 << 20),
+- IOMUXG_EINT17 = (2 << 18),
+- IOMUXG_EINT16 = (2 << 16),
+- IOMUXG_EINT15 = (2 << 14),
+- IOMUXG_EINT14 = (2 << 12),
+- IOMUXG_EINT13 = (2 << 10),
+- IOMUXG_EINT12 = (2 << 8),
+- IOMUXG_EINT11 = (2 << 6),
+- IOMUXG_EINT10 = (2 << 4),
+- IOMUXG_EINT9 = (2 << 2),
+- IOMUXG_EINT8 = 2,
+- IOMUXG_TCLK1 = (3 << 22),
+- IOMUXG_nCTS1 = (3 << 20),
+- IOMUXG_nRTS1 = (3 << 18),
+- IOMUXG_SPICLK1 = (3 << 14),
+- IOMUXG_SPIMOSI1 = (3 << 12),
+- IOMUXG_SPIMISO1 = (3 << 10),
+- IOMUXG_LCD_PWRDN = (3 << 8),
+- IOMUXG_nSS1 = (3 << 6),
+- IOMUXG_nSS0 = (3 << 4),
+-
+- /* PORT H */
+- IOMUXH_CLKOUT1 = (2 << 20),
+- IOMUXH_CLKOUT0 = (2 << 18),
+- IOMUXH_UEXTCLK = (2 << 16),
+- IOMUXH_RXD2 = (2 << 14),
+- IOMUXH_TXD2 = (2 << 12),
+- IOMUXH_RXD1 = (2 << 10),
+- IOMUXH_TXD1 = (2 << 8),
+- IOMUXH_RXD0 = (2 << 6),
+- IOMUXH_TXD0 = (2 << 4),
+- IOMUXH_nRTS0 = (2 << 2),
+- IOMUXH_nCTS0 = 2,
+- IOMUXH_nCTS1 = (3 << 14),
+- IOMUXH_nRTS1 = (3 << 12),
+-
+- /* PORT J */
+- IOMUXJ_CAMRESET = (2 << 24),
+- IOMUXJ_CAMCLKOUT = (2 << 22),
+- IOMUXJ_CAMHREF = (2 << 20),
+- IOMUXJ_CAMVSYNC = (2 << 18),
+- IOMUXJ_CAMPCLK = (2 << 16),
+- IOMUXJ_CAMDATA7 = (2 << 14),
+- IOMUXJ_CAMDATA6 = (2 << 12),
+- IOMUXJ_CAMDATA5 = (2 << 10),
+- IOMUXJ_CAMDATA4 = (2 << 8),
+- IOMUXJ_CAMDATA3 = (2 << 6),
+- IOMUXJ_CAMDATA2 = (2 << 4),
+- IOMUXJ_CAMDATA1 = (2 << 2),
+- IOMUXJ_CAMDATA0 = 2
+-};
+-
+-#endif
+diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h b/arch/arm/include/asm/arch-socfpga/reset_manager.h
+deleted file mode 100644
+index d9d2c1c..0000000
+--- a/arch/arm/include/asm/arch-socfpga/reset_manager.h
++++ /dev/null
+@@ -1,37 +0,0 @@
+-/*
+- * Copyright (C) 2012 Altera Corporation <www.altera.com>
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+- */
+-
+-#ifndef _RESET_MANAGER_H_
+-#define _RESET_MANAGER_H_
+-
+-void reset_cpu(ulong addr);
+-void reset_deassert_peripherals_handoff(void);
+-
+-struct socfpga_reset_manager {
+- u32 padding1;
+- u32 ctrl;
+- u32 padding2;
+- u32 padding3;
+- u32 mpu_mod_reset;
+- u32 per_mod_reset;
+- u32 per2_mod_reset;
+- u32 brg_mod_reset;
+-};
+-
+-#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
+-
+-#endif /* _RESET_MANAGER_H_ */
+diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
+deleted file mode 100644
+index f353eb2..0000000
+--- a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
++++ /dev/null
+@@ -1,27 +0,0 @@
+-/*
+- * Copyright (C) 2012 Altera Corporation <www.altera.com>
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+- */
+-
+-#ifndef _SOCFPGA_BASE_ADDRS_H_
+-#define _SOCFPGA_BASE_ADDRS_H_
+-
+-#define SOCFPGA_L3REGS_ADDRESS 0xff800000
+-#define SOCFPGA_UART0_ADDRESS 0xffc02000
+-#define SOCFPGA_UART1_ADDRESS 0xffc03000
+-#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000
+-#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
+-
+-#endif /* _SOCFPGA_BASE_ADDRS_H_ */
+diff --git a/arch/arm/include/asm/arch-socfpga/spl.h b/arch/arm/include/asm/arch-socfpga/spl.h
+deleted file mode 100644
+index efd0c06..0000000
+--- a/arch/arm/include/asm/arch-socfpga/spl.h
++++ /dev/null
+@@ -1,26 +0,0 @@
+-/*
+- * Copyright (C) 2012 Pavel Machek <pavel at denx.de>
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+- */
+-
+-#ifndef _SOCFPGA_SPL_H_
+-#define _SOCFPGA_SPL_H_
+-
+-/* Symbols from linker script */
+-extern char __malloc_start, __malloc_end, __stack_start;
+-
+-#define BOOT_DEVICE_RAM 1
+-
+-#endif
+diff --git a/arch/arm/include/asm/arch-socfpga/timer.h b/arch/arm/include/asm/arch-socfpga/timer.h
+deleted file mode 100644
+index 830c94a..0000000
+--- a/arch/arm/include/asm/arch-socfpga/timer.h
++++ /dev/null
+@@ -1,29 +0,0 @@
+-/*
+- * Copyright (C) 2012 Altera Corporation <www.altera.com>
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+- */
+-
+-#ifndef _SOCFPGA_TIMER_H_
+-#define _SOCFPGA_TIMER_H_
+-
+-struct socfpga_timer {
+- u32 load_val;
+- u32 curr_val;
+- u32 ctrl;
+- u32 eoi;
+- u32 int_stat;
+-};
+-
+-#endif
+diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h
+index 4558f4f..c34bb76 100644
+--- a/arch/arm/include/asm/imx-common/iomux-v3.h
++++ b/arch/arm/include/asm/imx-common/iomux-v3.h
+@@ -98,6 +98,7 @@ typedef u64 iomux_v3_cfg_t;
+ #define MUX_CONFIG_SION (0x1 << 4)
+
+ int imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
+-int imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count);
++int imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
++ unsigned count);
+
+ #endif /* __MACH_IOMUX_V3_H__*/
+diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h
+index a676b6d..2d5c3bc 100644
+--- a/arch/arm/include/asm/mach-types.h
++++ b/arch/arm/include/asm/mach-types.h
+@@ -1105,8 +1105,6 @@ extern unsigned int __machine_arch_type;
+ #define MACH_TYPE_UBISYS_P9D_EVP 3493
+ #define MACH_TYPE_ATDGP318 3494
+ #define MACH_TYPE_OMAP5_SEVM 3777
+-#define MACH_TYPE_ARMADILLO_800EVA 3863
+-#define MACH_TYPE_KZM9G 4140
+
+ #ifdef CONFIG_ARCH_EBSA110
+ # ifdef machine_arch_type
+@@ -14224,30 +14222,6 @@ extern unsigned int __machine_arch_type;
+ # define machine_is_omap5_sevm() (0)
+ #endif
+
+-#ifdef CONFIG_MACH_ARMADILLO800EVA
+-# ifdef machine_arch_type
+-# undef machine_arch_type
+-# define machine_arch_type __machine_arch_type
+-# else
+-# define machine_arch_type MACH_TYPE_ARMADILLO800EVA
+-# endif
+-# define machine_is_armadillo800eva() (machine_arch_type == MACH_TYPE_ARMADILLO800EVA)
+-#else
+-# define machine_is_armadillo800eva() (0)
+-#endif
+-
+-#ifdef CONFIG_MACH_KZM9G
+-# ifdef machine_arch_type
+-# undef machine_arch_type
+-# define machine_arch_type __machine_arch_type
+-# else
+-# define machine_arch_type MACH_TYPE_KZM9G
+-# endif
+-# define machine_is_kzm9g() (machine_arch_type == MACH_TYPE_KZM9G)
+-#else
+-# define machine_is_kzm9g() (0)
+-#endif
+-
+ /*
+ * These have not yet been registered
+ */
+diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
+index a9070d5..599547d 100644
+--- a/arch/arm/lib/bootm.c
++++ b/arch/arm/lib/bootm.c
+@@ -69,8 +69,8 @@ void arch_lmb_reserve(struct lmb *lmb)
+ sp = get_sp();
+ debug("## Current stack ends at 0x%08lx ", sp);
+
+- /* adjust sp by 4K to be safe */
+- sp -= 4096;
++ /* adjust sp by 1K to be safe */
++ sp -= 1024;
+ lmb_reserve(lmb, sp,
+ gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size - sp);
+ }
+@@ -258,9 +258,6 @@ static int create_fdt(bootm_headers_t *images)
+ fixup_memory_node(*of_flat_tree);
+ fdt_fixup_ethernet(*of_flat_tree);
+ fdt_initrd(*of_flat_tree, *initrd_start, *initrd_end, 1);
+-#ifdef CONFIG_OF_BOARD_SETUP
+- ft_board_setup(*of_flat_tree, gd->bd);
+-#endif
+
+ return 0;
+ }
+diff --git a/arch/openrisc/include/asm/bitops.h b/arch/openrisc/include/asm/bitops.h
+index c76a409..c001a5d 100644
+--- a/arch/openrisc/include/asm/bitops.h
++++ b/arch/openrisc/include/asm/bitops.h
+@@ -25,8 +25,4 @@
+ #define PLATFORM_FFS
+ #include <asm/bitops/ffs.h>
+
+-#define hweight32(x) generic_hweight32(x)
+-#define hweight16(x) generic_hweight16(x)
+-#define hweight8(x) generic_hweight8(x)
+-
+ #endif /* __ASM_GENERIC_BITOPS_H */
+diff --git a/arch/openrisc/lib/timer.c b/arch/openrisc/lib/timer.c
+index 89e644b..4e92a31 100644
+--- a/arch/openrisc/lib/timer.c
++++ b/arch/openrisc/lib/timer.c
+@@ -86,16 +86,6 @@ void set_timer(ulong t)
+ timestamp = t;
+ }
+
+-unsigned long long get_ticks(void)
+-{
+- return get_timer(0);
+-}
+-
+-ulong get_tbclk(void)
+-{
+- return CONFIG_SYS_HZ;
+-}
+-
+ void __udelay(ulong usec)
+ {
+ ulong elapsed = 0;
+diff --git a/board/LaCie/common/common.c b/board/LaCie/common/common.c
+index a62bf9f..78d0edc 100644
+--- a/board/LaCie/common/common.c
++++ b/board/LaCie/common/common.c
+@@ -13,11 +13,10 @@
+
+ #if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
+
+-#define MII_MARVELL_PHY_PAGE 22
+-
+ #define MV88E1116_LED_FCTRL_REG 10
+ #define MV88E1116_CPRSP_CR3_REG 21
+ #define MV88E1116_MAC_CTRL_REG 21
++#define MV88E1116_PGADR_REG 22
+ #define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
+ #define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
+
+@@ -32,44 +31,15 @@ void mv_phy_88e1116_init(const char *name, u16 phyaddr)
+ * Enable RGMII delay on Tx and Rx for CPU port
+ * Ref: sec 4.7.2 of chip datasheet
+ */
+- miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 2);
++ miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 2);
+ miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, ®);
+ reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
+ miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg);
+- miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 0);
++ miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 0);
+
+ if (miiphy_reset(name, phyaddr) == 0)
+ printf("88E1116 Initialized on %s\n", name);
+ }
+-
+-void mv_phy_88e1318_init(const char *name, u16 phyaddr)
+-{
+- u16 reg;
+-
+- if (miiphy_set_current_dev(name))
+- return;
+-
+- /*
+- * Set control mode 4 for LED[0].
+- */
+- miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 3);
+- miiphy_read(name, phyaddr, 16, ®);
+- reg |= 0xf;
+- miiphy_write(name, phyaddr, 16, reg);
+-
+- /*
+- * Enable RGMII delay on Tx and Rx for CPU port
+- * Ref: sec 4.7.2 of chip datasheet
+- */
+- miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 2);
+- miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, ®);
+- reg |= (MV88E1116_RGMII_TXTM_CTRL | MV88E1116_RGMII_RXTM_CTRL);
+- miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg);
+- miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 0);
+-
+- if (miiphy_reset(name, phyaddr) == 0)
+- printf("88E1318 Initialized on %s\n", name);
+-}
+ #endif /* CONFIG_CMD_NET && CONFIG_RESET_PHY_R */
+
+ #if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
+diff --git a/board/LaCie/common/common.h b/board/LaCie/common/common.h
+index 85e433c..2edd5ab 100644
+--- a/board/LaCie/common/common.h
++++ b/board/LaCie/common/common.h
+@@ -12,7 +12,6 @@
+
+ #if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
+ void mv_phy_88e1116_init(const char *name, u16 phyaddr);
+-void mv_phy_88e1318_init(const char *name, u16 phyaddr);
+ #endif
+ #if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
+ int lacie_read_mac_address(uchar *mac);
+diff --git a/board/LaCie/netspace_v2/kwbimage-ns2l.cfg b/board/LaCie/netspace_v2/kwbimage-ns2l.cfg
+deleted file mode 100644
+index d008eb0..0000000
+--- a/board/LaCie/netspace_v2/kwbimage-ns2l.cfg
++++ /dev/null
+@@ -1,162 +0,0 @@
+-#
+-# Copyright (C) 2011 Simon Guinot <sguinot at lacie.com>
+-#
+-# Based on Kirkwood support:
+-# (C) Copyright 2009
+-# Marvell Semiconductor <www.marvell.com>
+-# Written-by: Prafulla Wadaskar <prafulla at marvell.com>
+-#
+-# See file CREDITS for list of people who contributed to this
+-# project.
+-#
+-# This program is free software; you can redistribute it and/or
+-# modify it under the terms of the GNU General Public License as
+-# published by the Free Software Foundation; either version 2 of
+-# the License, or (at your option) any later version.
+-#
+-# This program is distributed in the hope that it will be useful,
+-# but WITHOUT ANY WARRANTY; without even the implied warranty of
+-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-# GNU General Public License for more details.
+-#
+-# Refer docs/README.kwimage for more details about how-to configure
+-# and create kirkwood boot image
+-#
+-
+-# Boot Media configurations
+-BOOT_FROM spi # Boot from SPI flash
+-
+-# SOC registers configuration using bootrom header extension
+-# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+-
+-# Configure RGMII-0 interface pad voltage to 1.8V
+-DATA 0xFFD100e0 0x1B1B1B9B
+-
+-#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+-DATA 0xFFD01400 0x43000618 # DDR Configuration register
+-# bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
+-# bit23-14: zero
+-# bit24: 1= enable exit self refresh mode on DDR access
+-# bit25: 1 required
+-# bit29-26: zero
+-# bit31-30: 01
+-
+-DATA 0xFFD01404 0x34143000 # DDR Controller Control Low
+-# bit 4: 0=addr/cmd in smame cycle
+-# bit 5: 0=clk is driven during self refresh, we don't care for APX
+-# bit 6: 0=use recommended falling edge of clk for addr/cmd
+-# bit14: 0=input buffer always powered up
+-# bit18: 1=cpu lock transaction enabled
+-# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+-# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+-# bit30-28: 3 required
+-# bit31: 0=no additional STARTBURST delay
+-
+-DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1)
+-# bit7-4: TRCD
+-# bit11- 8: TRP
+-# bit15-12: TWR
+-# bit19-16: TWTR
+-# bit20: TRAS msb
+-# bit23-21: 0x0
+-# bit27-24: TRRD
+-# bit31-28: TRTP
+-
+-DATA 0xFFD0140C 0x00000A19 # DDR Timing (High)
+-# bit6-0: TRFC
+-# bit8-7: TR2R
+-# bit10-9: TR2W
+-# bit12-11: TW2W
+-# bit31-13: zero required
+-
+-DATA 0xFFD01410 0x0000DDDD # DDR Address Control
+-# bit1-0: 00, Cs0width=x8
+-# bit3-2: 10, Cs0size=512Mb
+-# bit5-4: 00, Cs2width=nonexistent
+-# bit7-6: 00, Cs1size =nonexistent
+-# bit9-8: 00, Cs2width=nonexistent
+-# bit11-10: 00, Cs2size =nonexistent
+-# bit13-12: 00, Cs3width=nonexistent
+-# bit15-14: 00, Cs3size =nonexistent
+-# bit16: 0, Cs0AddrSel
+-# bit17: 0, Cs1AddrSel
+-# bit18: 0, Cs2AddrSel
+-# bit19: 0, Cs3AddrSel
+-# bit31-20: 0 required
+-
+-DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
+-# bit0: 0, OpenPage enabled
+-# bit31-1: 0 required
+-
+-DATA 0xFFD01418 0x00000000 # DDR Operation
+-# bit3-0: 0x0, DDR cmd
+-# bit31-4: 0 required
+-
+-DATA 0xFFD0141C 0x00000632 # DDR Mode
+-# bit2-0: 2, BurstLen=2 required
+-# bit3: 0, BurstType=0 required
+-# bit6-4: 4, CL=5
+-# bit7: 0, TestMode=0 normal
+-# bit8: 0, DLL reset=0 normal
+-# bit11-9: 6, auto-precharge write recovery ????????????
+-# bit12: 0, PD must be zero
+-# bit31-13: 0 required
+-
+-DATA 0xFFD01420 0x00000004 # DDR Extended Mode
+-# bit0: 0, DDR DLL enabled
+-# bit1: 1, DDR drive strenght reduced
+-# bit2: 1, DDR ODT control lsd enabled
+-# bit5-3: 000, required
+-# bit6: 1, DDR ODT control msb, enabled
+-# bit9-7: 000, required
+-# bit10: 0, differential DQS enabled
+-# bit11: 0, required
+-# bit12: 0, DDR output buffer enabled
+-# bit31-13: 0 required
+-
+-DATA 0xFFD01424 0x0000F07F # DDR Controller Control High
+-# bit2-0: 111, required
+-# bit3 : 1 , MBUS Burst Chop disabled
+-# bit6-4: 111, required
+-# bit7 : 1 , D2P Latency enabled
+-# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+-# bit9 : 0 , no half clock cycle addition to dataout
+-# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
+-# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
+-# bit15-12: 1111 required
+-# bit31-16: 0 required
+-
+-DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
+-DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
+-
+-DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
+-DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size
+-# bit0: 1, Window enabled
+-# bit1: 0, Write Protect disabled
+-# bit3-2: 00, CS0 hit selected
+-# bit23-4: ones, required
+-# bit31-24: 0x07, Size (i.e. 128MB)
+-
+-DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
+-DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
+-DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
+-
+-DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
+-# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
+-# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+-
+-DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
+-# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
+-# bit3-2: 01, ODT1 active NEVER!
+-# bit31-4: zero, required
+-
+-DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
+-# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
+-# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
+-# bit11-10:1, DQ_ODTSel. ODT select turned on
+-
+-DATA 0xFFD01480 0x00000001 # DDR Initialization Control
+-#bit0=1, enable DDR init upon this register write
+-
+-# End of Header extension
+-DATA 0x0 0x0
+diff --git a/board/LaCie/netspace_v2/netspace_v2.c b/board/LaCie/netspace_v2/netspace_v2.c
+index 101a80a..68e8a77 100644
+--- a/board/LaCie/netspace_v2/netspace_v2.c
++++ b/board/LaCie/netspace_v2/netspace_v2.c
+@@ -107,11 +107,7 @@ int misc_init_r(void)
+ /* Configure and initialize PHY */
+ void reset_phy(void)
+ {
+-#if defined(CONFIG_NETSPACE_LITE_V2) || defined(CONFIG_NETSPACE_MINI_V2)
+- mv_phy_88e1318_init("egiga0", 0);
+-#else
+ mv_phy_88e1116_init("egiga0", 8);
+-#endif
+ }
+ #endif
+
+diff --git a/board/alphaproject/ap_sh4a_4a/lowlevel_init.S b/board/alphaproject/ap_sh4a_4a/lowlevel_init.S
+index cf9c225..f04b36b 100644
+--- a/board/alphaproject/ap_sh4a_4a/lowlevel_init.S
++++ b/board/alphaproject/ap_sh4a_4a/lowlevel_init.S
+@@ -330,7 +330,7 @@ init_dbsc3_ctrl_533:
+ DBKIND_A: .long 0xFE800020
+ DBKIND_D: .long 0x00000005
+ DBCONF_A: .long 0xFE800024
+-DBCONF_D: .long 0x0D020A01
++DBCONF_D: .long 0x0D020901
+
+ DBTR0_A: .long 0xFE800040
+ DBTR0_D_533:.long 0x00000004
+diff --git a/board/altera/socfpga_cyclone5/Makefile b/board/altera/socfpga_cyclone5/Makefile
+deleted file mode 100644
+index 43bbc37..0000000
+--- a/board/altera/socfpga_cyclone5/Makefile
++++ /dev/null
+@@ -1,50 +0,0 @@
+-#
+-# (C) Copyright 2001-2006
+-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+-# (C) Copyright 2010, Thomas Chou <thomas at wytron.com.tw>
+-#
+-# See file CREDITS for list of people who contributed to this
+-# project.
+-#
+-# This program is free software; you can redistribute it and/or
+-# modify it under the terms of the GNU General Public License as
+-# published by the Free Software Foundation; either version 2 of
+-# the License, or (at your option) any later version.
+-#
+-# This program is distributed in the hope that it will be useful,
+-# but WITHOUT ANY WARRANTY; without even the implied warranty of
+-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-# GNU General Public License for more details.
+-#
+-# You should have received a copy of the GNU General Public License
+-# along with this program; if not, write to the Free Software
+-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+-# MA 02111-1307 USA
+-#
+-
+-include $(TOPDIR)/config.mk
+-
+-LIB = $(obj)lib$(BOARD).o
+-
+-COBJS := socfpga_cyclone5.o
+-
+-SRCS := $(COBJS:.o=.c)
+-OBJS := $(addprefix $(obj),$(COBJS))
+-
+-$(LIB): $(obj).depend $(OBJS)
+- $(call cmd_link_o_target, $(OBJS))
+-
+-clean:
+- rm -f $(OBJS)
+-
+-distclean: clean
+- rm -f $(LIB) core *.bak $(obj).depend
+-
+-#########################################################################
+-
+-# defines $(obj).depend target
+-include $(SRCTREE)/rules.mk
+-
+-sinclude $(obj).depend
+-
+-#########################################################################
+diff --git a/board/altera/socfpga_cyclone5/socfpga_cyclone5.c b/board/altera/socfpga_cyclone5/socfpga_cyclone5.c
+deleted file mode 100644
+index 7725be1..0000000
+--- a/board/altera/socfpga_cyclone5/socfpga_cyclone5.c
++++ /dev/null
+@@ -1,80 +0,0 @@
+-/*
+- * Copyright (C) 2012 Altera Corporation <www.altera.com>
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+- */
+-
+-#include <common.h>
+-#include <asm/arch/reset_manager.h>
+-#include <asm/io.h>
+-
+-#include <netdev.h>
+-
+-DECLARE_GLOBAL_DATA_PTR;
+-
+-/*
+- * Print CPU information
+- */
+-int print_cpuinfo(void)
+-{
+- puts("CPU : Altera SOCFPGA Platform\n");
+- return 0;
+-}
+-
+-/*
+- * Print Board information
+- */
+-int checkboard(void)
+-{
+- puts("BOARD : Altera SOCFPGA Cyclone5 Board\n");
+- return 0;
+-}
+-
+-/*
+- * Initialization function which happen at early stage of c code
+- */
+-int board_early_init_f(void)
+-{
+- return 0;
+-}
+-
+-/*
+- * Miscellaneous platform dependent initialisations
+- */
+-int board_init(void)
+-{
+- icache_enable();
+- return 0;
+-}
+-
+-int misc_init_r(void)
+-{
+- return 0;
+-}
+-
+-#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
+-int overwrite_console(void)
+-{
+- return 0;
+-}
+-#endif
+-
+-/*
+- * DesignWare Ethernet initialization
+- */
+-/* We know all the init functions have been run now */
+-int board_eth_init(bd_t *bis)
+-{
+- return 0;
+-}
+diff --git a/board/amirix/ap1000/ap1000.c b/board/amirix/ap1000/ap1000.c
+index dbcb34b..64de04c 100644
+--- a/board/amirix/ap1000/ap1000.c
++++ b/board/amirix/ap1000/ap1000.c
+@@ -43,13 +43,11 @@ int checkboard (void)
+ /* After a loadace command, the SystemAce control register is left in a wonky state. */
+ /* this code did not work in board_pre_init */
+ unsigned char *p = (unsigned char *) AP1000_SYSACE_REGBASE;
+- unsigned int *revision_reg_ptr = (unsigned int *) AP1xx_FPGA_REV_ADDR;
+- unsigned int device = (*revision_reg_ptr & AP1xx_TARGET_MASK);
+
+ p[SYSACE_CTRLREG0] = 0x0;
+
+ /* add platform and device to banner */
+- switch (device) {
++ switch (get_device ()) {
+ case AP1xx_AP107_TARGET:
+ puts (AP1xx_AP107_TARGET_STR);
+ break;
+@@ -162,6 +160,13 @@ unsigned int get_platform (void)
+ return (*revision_reg_ptr & AP1xx_PLATFORM_MASK);
+ }
+
++unsigned int get_device (void)
++{
++ unsigned int *revision_reg_ptr = (unsigned int *) AP1xx_FPGA_REV_ADDR;
++
++ return (*revision_reg_ptr & AP1xx_TARGET_MASK);
++}
++
+ #if 0 /* loadace is not working; it appears to be a hardware issue with the system ace. */
+ /*
+ This function loads FPGA configurations from the SystemACE CompactFlash
+diff --git a/board/amirix/ap1000/ap1000.h b/board/amirix/ap1000/ap1000.h
+index d294816..118c4d1 100644
+--- a/board/amirix/ap1000/ap1000.h
++++ b/board/amirix/ap1000/ap1000.h
+@@ -164,6 +164,7 @@
+ void set_eat_machine_checks(int a_flag);
+ int get_eat_machine_checks(void);
+ unsigned int get_platform(void);
++unsigned int get_device(void);
+ void* memcpyb(void * dest,const void *src,size_t count);
+ int process_bootflag(ulong bootflag);
+ void user_led_on(void);
+diff --git a/board/atmark-techno/armadillo-800eva/Makefile b/board/atmark-techno/armadillo-800eva/Makefile
+deleted file mode 100644
+index 9f9618b..0000000
+--- a/board/atmark-techno/armadillo-800eva/Makefile
++++ /dev/null
+@@ -1,46 +0,0 @@
+-#
+-# Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj at renesas.com>
+-#
+-# This program is free software; you can redistribute it and/or
+-# modify it under the terms of the GNU General Public License as
+-# published by the Free Software Foundation; either version 2 of
+-# the License.
+-#
+-# This program is distributed in the hope that it will be useful,
+-# but WITHOUT ANY WARRANTY; without even the implied warranty of
+-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-# GNU General Public License for more details.
+-#
+-# You should have received a copy of the GNU General Public License
+-# along with this program; if not, write to the Free Software
+-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+-# MA 02111-1307 USA
+-
+-include $(TOPDIR)/config.mk
+-
+-LIB = $(obj)lib$(BOARD).o
+-
+-COBJS-y += armadillo-800eva.o
+-COBJS := $(COBJS-y)
+-
+-SRCS := $(COBJS:.o=.c)
+-OBJS := $(addprefix $(obj),$(COBJS))
+-
+-$(LIB): $(obj).depend $(OBJS)
+- $(call cmd_link_o_target, $(OBJS))
+-
+-clean:
+- rm -f $(OBJS)
+-
+-distclean: clean
+- rm -f $(LIB) core *.bak $(obj).depend
+-
+-#########################################################################
+-
+-# defines $(obj).depend target
+-include $(SRCTREE)/rules.mk
+-
+-sinclude $(obj).depend
+-
+-#########################################################################
+-
+diff --git a/board/atmark-techno/armadillo-800eva/armadillo-800eva.c b/board/atmark-techno/armadillo-800eva/armadillo-800eva.c
+deleted file mode 100644
+index 0e9c222..0000000
+--- a/board/atmark-techno/armadillo-800eva/armadillo-800eva.c
++++ /dev/null
+@@ -1,328 +0,0 @@
+-/*
+- * Copyright (C) 2012 Renesas Solutions Corp.
+- *
+- * See file CREDITS for list of people who contributed to this
+- * project.
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of
+- * the License.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+- * MA 02111-1307 USA
+- */
+-
+-#include <common.h>
+-#include <malloc.h>
+-#include <asm/processor.h>
+-#include <asm/mach-types.h>
+-#include <asm/io.h>
+-#include <asm/arch/sys_proto.h>
+-#include <asm/gpio.h>
+-#include <asm/arch/rmobile.h>
+-
+-#define s_init_wait(cnt) \
+- ({ \
+- volatile u32 i = 0x10000 * cnt; \
+- while (i > 0) \
+- i--; \
+- })
+-
+-#define USBCR1 0xE605810A
+-
+-void s_init(void)
+-{
+- struct r8a7740_rwdt *rwdt0 = (struct r8a7740_rwdt *)RWDT0_BASE;
+- struct r8a7740_rwdt *rwdt1 = (struct r8a7740_rwdt *)RWDT1_BASE;
+- struct r8a7740_cpg *cpg = (struct r8a7740_cpg *)CPG_BASE;
+- struct r8a7740_bsc *bsc = (struct r8a7740_bsc *)BSC_BASE;
+- struct r8a7740_ddrp *ddrp = (struct r8a7740_ddrp *)DDRP_BASE;
+- struct r8a7740_dbsc *dbsc = (struct r8a7740_dbsc *)DBSC_BASE;
+-
+- /* Watchdog init */
+- writew(0xA500, &rwdt0->rwtcsra0);
+- writew(0xA500, &rwdt1->rwtcsra0);
+-
+- /* CPG */
+- writel(0xFF800080, &cpg->rmstpcr4);
+- writel(0xFF800080, &cpg->smstpcr4);
+-
+- /* USB clock */
+- writel(0x00000080, &cpg->usbckcr);
+- s_init_wait(1);
+-
+- /* USBCR1 */
+- writew(0x0710, USBCR1);
+-
+- /* FRQCR */
+- writel(0x00000000, &cpg->frqcrb);
+- writel(0x62030533, &cpg->frqcra);
+- writel(0x208A354E, &cpg->frqcrc);
+- writel(0x80331050, &cpg->frqcrb);
+- s_init_wait(1);
+-
+- writel(0x00000000, &cpg->frqcrd);
+- s_init_wait(1);
+-
+- /* SUBClk */
+- writel(0x0000010B, &cpg->subckcr);
+-
+- /* PLL */
+- writel(0x00004004, &cpg->pllc01cr);
+- s_init_wait(1);
+-
+- writel(0xa0000000, &cpg->pllc2cr);
+- s_init_wait(2);
+-
+- /* BSC */
+- writel(0x0000001B, &bsc->cmncr);
+-
+- writel(0x20000000, &dbsc->dbcmd);
+- writel(0x10009C40, &dbsc->dbcmd);
+- s_init_wait(1);
+-
+- writel(0x00000007, &dbsc->dbkind);
+- writel(0x0E030A02, &dbsc->dbconf0);
+- writel(0x00000001, &dbsc->dbphytype);
+- writel(0x00000000, &dbsc->dbbl);
+- writel(0x00000006, &dbsc->dbtr0);
+- writel(0x00000005, &dbsc->dbtr1);
+- writel(0x00000000, &dbsc->dbtr2);
+- writel(0x00000006, &dbsc->dbtr3);
+- writel(0x00080006, &dbsc->dbtr4);
+- writel(0x00000015, &dbsc->dbtr5);
+- writel(0x0000000f, &dbsc->dbtr6);
+- writel(0x00000004, &dbsc->dbtr7);
+- writel(0x00000018, &dbsc->dbtr8);
+- writel(0x00000006, &dbsc->dbtr9);
+- writel(0x00000006, &dbsc->dbtr10);
+- writel(0x0000000F, &dbsc->dbtr11);
+- writel(0x0000000D, &dbsc->dbtr12);
+- writel(0x000000A0, &dbsc->dbtr13);
+- writel(0x000A0003, &dbsc->dbtr14);
+- writel(0x00000003, &dbsc->dbtr15);
+- writel(0x40005005, &dbsc->dbtr16);
+- writel(0x0C0C0000, &dbsc->dbtr17);
+- writel(0x00000200, &dbsc->dbtr18);
+- writel(0x00000040, &dbsc->dbtr19);
+- writel(0x00000001, &dbsc->dbrnk0);
+- writel(0x00000110, &dbsc->dbdficnt);
+- writel(0x00000101, &ddrp->funcctrl);
+- writel(0x00000001, &ddrp->dllctrl);
+- writel(0x00000186, &ddrp->zqcalctrl);
+- writel(0xB3440051, &ddrp->zqodtctrl);
+- writel(0x94449443, &ddrp->rdctrl);
+- writel(0x000000C0, &ddrp->rdtmg);
+- writel(0x00000101, &ddrp->fifoinit);
+- writel(0x02060506, &ddrp->outctrl);
+- writel(0x00004646, &ddrp->dqcalofs1);
+- writel(0x00004646, &ddrp->dqcalofs2);
+- writel(0x800000aa, &ddrp->dqcalexp);
+- writel(0x00000000, &ddrp->dllctrl);
+- writel(0x00000000, DDRPNCNT);
+-
+- writel(0x0000000C, &dbsc->dbcmd);
+- readl(&dbsc->dbwait);
+- s_init_wait(1);
+-
+- writel(0x00000002, DDRPNCNT);
+-
+- writel(0x0000000C, &dbsc->dbcmd);
+- readl(&dbsc->dbwait);
+- s_init_wait(1);
+-
+- writel(0x00000187, &ddrp->zqcalctrl);
+-
+- writel(0x00009C40, &dbsc->dbcmd);
+- readl(&dbsc->dbwait);
+- s_init_wait(1);
+-
+- writel(0x00009C40, &dbsc->dbcmd);
+- readl(&dbsc->dbwait);
+- s_init_wait(1);
+-
+- writel(0x00000010, &dbsc->dbdficnt);
+- writel(0x02060507, &ddrp->outctrl);
+-
+- writel(0x00009C40, &dbsc->dbcmd);
+- readl(&dbsc->dbwait);
+- s_init_wait(1);
+-
+- writel(0x21009C40, &dbsc->dbcmd);
+- readl(&dbsc->dbwait);
+- s_init_wait(1);
+-
+- writel(0x00009C40, &dbsc->dbcmd);
+- readl(&dbsc->dbwait);
+- s_init_wait(1);
+-
+- writel(0x00009C40, &dbsc->dbcmd);
+- readl(&dbsc->dbwait);
+- s_init_wait(1);
+-
+- writel(0x00009C40, &dbsc->dbcmd);
+- readl(&dbsc->dbwait);
+- s_init_wait(1);
+-
+- writel(0x00009C40, &dbsc->dbcmd);
+- readl(&dbsc->dbwait);
+- s_init_wait(1);
+-
+- writel(0x11000044, &dbsc->dbcmd);
+- readl(&dbsc->dbwait);
+- s_init_wait(1);
+-
+- writel(0x2A000000, &dbsc->dbcmd);
+- readl(&dbsc->dbwait);
+- s_init_wait(1);
+-
+- writel(0x2B000000, &dbsc->dbcmd);
+- readl(&dbsc->dbwait);
+-
+- writel(0x29000004, &dbsc->dbcmd);
+- readl(&dbsc->dbwait);
+-
+- writel(0x28001520, &dbsc->dbcmd);
+- readl(&dbsc->dbwait);
+- s_init_wait(1);
+-
+- writel(0x03000200, &dbsc->dbcmd);
+- readl(&dbsc->dbwait);
+- s_init_wait(1);
+-
+- writel(0x000001FF, &dbsc->dbrfcnf0);
+- writel(0x00010C30, &dbsc->dbrfcnf1);
+- writel(0x00000000, &dbsc->dbrfcnf2);
+-
+- writel(0x00000001, &dbsc->dbrfen);
+- writel(0x00000001, &dbsc->dbacen);
+-
+- /* BSC */
+- writel(0x00410400, &bsc->cs0bcr);
+- writel(0x00410400, &bsc->cs2bcr);
+- writel(0x00410400, &bsc->cs5bbcr);
+- writel(0x02CB0400, &bsc->cs6abcr);
+-
+- writel(0x00000440, &bsc->cs0wcr);
+- writel(0x00000440, &bsc->cs2wcr);
+- writel(0x00000240, &bsc->cs5bwcr);
+- writel(0x00000240, &bsc->cs6awcr);
+-
+- writel(0x00000005, &bsc->rbwtcnt);
+- writel(0x00000002, &bsc->cs0wcr2);
+- writel(0x00000002, &bsc->cs2wcr2);
+- writel(0x00000002, &bsc->cs4wcr2);
+-}
+-
+-#define GPIO_ICCR (0xE60581A0)
+-#define ICCR_15BIT (1 << 15) /* any time 1 */
+-#define IIC0_CONTA (1 << 7)
+-#define IIC0_CONTB (1 << 6)
+-#define IIC1_CONTA (1 << 5)
+-#define IIC1_CONTB (1 << 4)
+-#define IIC0_PS33E (1 << 1)
+-#define IIC1_PS33E (1 << 0)
+-#define GPIO_ICCR_DATA \
+- (ICCR_15BIT | \
+- IIC0_CONTA | IIC0_CONTB | IIC1_CONTA | \
+- IIC1_CONTB | IIC0_PS33E | IIC1_PS33E)
+-
+-#define MSTPCR1 0xE6150134
+-#define TMU0_MSTP125 (1 << 25)
+-#define I2C0_MSTP116 (1 << 16)
+-
+-#define MSTPCR3 0xE615013C
+-#define I2C1_MSTP323 (1 << 23)
+-#define GETHER_MSTP309 (1 << 9)
+-
+-#define GPIO_SCIFA1_TXD (0xE60520C4)
+-#define GPIO_SCIFA1_RXD (0xE60520C3)
+-
+-int board_early_init_f(void)
+-{
+- /* TMU */
+- clrbits_le32(MSTPCR1, TMU0_MSTP125);
+-
+- /* GETHER */
+- clrbits_le32(MSTPCR3, GETHER_MSTP309);
+-
+- /* I2C 0/1 */
+- clrbits_le32(MSTPCR1, I2C0_MSTP116);
+- clrbits_le32(MSTPCR3, I2C1_MSTP323);
+-
+- /* SCIFA1 */
+- writeb(1, GPIO_SCIFA1_TXD); /* SCIFA1_TXD */
+- writeb(1, GPIO_SCIFA1_RXD); /* SCIFA1_RXD */
+-
+- /* IICCR */
+- writew(GPIO_ICCR_DATA, GPIO_ICCR);
+-
+- return 0;
+-}
+-
+-DECLARE_GLOBAL_DATA_PTR;
+-int board_init(void)
+-{
+- /* board id for linux */
+- gd->bd->bi_arch_number = MACH_TYPE_ARMADILLO_800EVA;
+- /* adress of boot parameters */
+- gd->bd->bi_boot_params = ARMADILLO_800EVA_SDRAM_BASE + 0x100;
+-
+- /* Init PFC controller */
+- r8a7740_pinmux_init();
+-
+- /* GETHER Enable */
+- gpio_request(GPIO_FN_ET_CRS, NULL);
+- gpio_request(GPIO_FN_ET_MDC, NULL);
+- gpio_request(GPIO_FN_ET_MDIO, NULL);
+- gpio_request(GPIO_FN_ET_TX_ER, NULL);
+- gpio_request(GPIO_FN_ET_RX_ER, NULL);
+- gpio_request(GPIO_FN_ET_ERXD0, NULL);
+- gpio_request(GPIO_FN_ET_ERXD1, NULL);
+- gpio_request(GPIO_FN_ET_ERXD2, NULL);
+- gpio_request(GPIO_FN_ET_ERXD3, NULL);
+- gpio_request(GPIO_FN_ET_TX_CLK, NULL);
+- gpio_request(GPIO_FN_ET_TX_EN, NULL);
+- gpio_request(GPIO_FN_ET_ETXD0, NULL);
+- gpio_request(GPIO_FN_ET_ETXD1, NULL);
+- gpio_request(GPIO_FN_ET_ETXD2, NULL);
+- gpio_request(GPIO_FN_ET_ETXD3, NULL);
+- gpio_request(GPIO_FN_ET_PHY_INT, NULL);
+- gpio_request(GPIO_FN_ET_COL, NULL);
+- gpio_request(GPIO_FN_ET_RX_DV, NULL);
+- gpio_request(GPIO_FN_ET_RX_CLK, NULL);
+-
+- gpio_request(GPIO_PORT18, NULL); /* PHY_RST */
+- gpio_direction_output(GPIO_PORT18, 1);
+-
+- return 0;
+-}
+-
+-int dram_init(void)
+-{
+- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+-
+- return 0;
+-}
+-
+-const struct rmobile_sysinfo sysinfo = {
+- CONFIG_RMOBILE_BOARD_STRING
+-};
+-
+-int board_late_init(void)
+-{
+- return 0;
+-}
+-
+-void reset_cpu(ulong addr)
+-{
+-}
+diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
+index 06028aa..ae408bc 100644
+--- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c
++++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
+@@ -62,10 +62,6 @@ static void at91sam9x5ek_nand_hw_init(void)
+ csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
+ /* NAND flash on D16 */
+ csa |= AT91_MATRIX_NFD0_ON_D16;
+-
+- /* Configure IO drive */
+- csa &= ~AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
+-
+ writel(csa, &matrix->ebicsa);
+
+ /* Configure SMC CS3 for NAND/SmartMedia */
+diff --git a/board/boundary/nitrogen6x/Makefile b/board/boundary/nitrogen6x/Makefile
+new file mode 100644
+index 0000000..63da7d0
+--- /dev/null
++++ b/board/boundary/nitrogen6x/Makefile
+@@ -0,0 +1,41 @@
++#
++# Copyright (C) 2012, Guennadi Liakhovetski <lg at denx.de>
++#
++# (C) Copyright 2012 Freescale Semiconductor, Inc.
++#
++# This program is free software; you can redistribute it and/or
++# modify it under the terms of the GNU General Public License as
++# published by the Free Software Foundation; either version 2 of
++# the License, or (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++# MA 02111-1307 USA
++#
++
++include $(TOPDIR)/config.mk
++
++LIB = $(obj)lib$(BOARD).o
++
++COBJS := nitrogen6x.o
++
++SRCS := $(COBJS:.o=.c)
++OBJS := $(addprefix $(obj),$(COBJS))
++
++$(LIB): $(obj).depend $(OBJS)
++ $(call cmd_link_o_target, $(OBJS))
++
++#########################################################################
++
++# defines $(obj).depend target
++include $(SRCTREE)/rules.mk
++
++sinclude $(obj).depend
++
++#########################################################################
+diff --git a/board/boundary/nitrogen6x/README b/board/boundary/nitrogen6x/README
+new file mode 100644
+index 0000000..d67cdf0
+--- /dev/null
++++ b/board/boundary/nitrogen6x/README
+@@ -0,0 +1,77 @@
++U-Boot for the Boundary Devices Nitrogen6X and
++Freescale i.MX6q SabreLite boards
++
++This file contains information for the port of
++U-Boot to the Boundary Devices Nitrogen6X and
++Freescale i.MX6q SabreLite boards.
++
++1. Boot source, boot from SPI NOR
++---------------------------------
++The configuration in this directory supports both the
++Nitrogen6X and Freescale SabreLite board, but in a
++different fashion from Freescale's implementation in
++board/freescale/mx6qsabrelite.
++
++In particular, this image supports booting from SPI NOR
++and saving the environment to SPI NOR.
++
++It does not support 'boot from SD' at offset 0x400
++except through the 'bmode' command.
++ http://lists.denx.de/pipermail/u-boot/2012-August/131151.html
++
++2. Boots using 6q_bootscript on SATA or SD card
++-----------------------------------------------
++The default bootcmd for these boards is configured
++to look for and source a boot script named '6q_bootscript'
++in the root of the first partition of the following
++devices:
++
++ sata 0
++ mmc 0
++ mmc 1
++
++They're searched in the order listed above, trying both the
++ext2 and fat filesystems.
++
++2. Maintaining the SPI NOR
++--------------------------
++A couple of convenience commands
++
++ clearenv - clear environment to factory default
++ upgradeu - look and source a boot script named
++ '6q_upgrade' to upgrade the U-Boot version
++ in SPI NOR. The search is the same as for
++ 6q_bootscript described above.
++
++3. Display support
++------------------
++U-Boot support for the following displays is configured by
++default:
++
++ HDMI - 1024 x 768 for maximum compatibility
++ Hannstar-XGA - 1024 x 768 LVDS (Freescale part number MCIMX-LVDS1)
++ wsvga-lvds - 1024 x 600 LVDS (Boundary p/n Nit6X_1024x600)
++ wvga-rgb - 800 x 480 RGB (Boundary p/n Nit6X_800x480)
++
++Since the ipuv3_fb display driver currently supports only a single display,
++this code auto-detects panel by probing the HDMI Phy for Hot Plug Detect
++or the I2C touch controller of the LVDS and RGB displays in the priority
++listed above.
++
++Setting 'panel' environment variable to one of the names above will
++override auto-detection and force activation of the specified panel.
++
++4. Building
++------------
++
++To build U-Boot for the Nitrogen6x or SabreLite board:
++
++ make nitrogen6x_config
++ make u-boot.imx
++
++If you place the u-boot.imx into a single-partition SD card
++along with a binary version of the boot script 6q_upgrade.txt,
++you can program it using 'upgradeu':
++
++ U-Boot> run upgradeu
++
+diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c
+new file mode 100644
+index 0000000..16469b7
+--- /dev/null
++++ b/board/boundary/nitrogen6x/nitrogen6x.c
+@@ -0,0 +1,875 @@
++/*
++ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <common.h>
++#include <asm/io.h>
++#include <asm/arch/clock.h>
++#include <asm/arch/imx-regs.h>
++#include <asm/arch/iomux.h>
++#include <asm/arch/mx6x_pins.h>
++#include <asm/errno.h>
++#include <asm/gpio.h>
++#include <asm/imx-common/iomux-v3.h>
++#include <asm/imx-common/mxc_i2c.h>
++#include <asm/imx-common/boot_mode.h>
++#include <mmc.h>
++#include <fsl_esdhc.h>
++#include <micrel.h>
++#include <miiphy.h>
++#include <netdev.h>
++#include <linux/fb.h>
++#include <ipu_pixfmt.h>
++#include <asm/arch/crm_regs.h>
++#include <asm/arch/mxc_hdmi.h>
++#include <i2c.h>
++
++DECLARE_GLOBAL_DATA_PTR;
++
++#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
++ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
++ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
++
++#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
++ PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
++ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
++
++#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
++ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
++ PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
++
++#define SPI_PAD_CTRL (PAD_CTL_HYS | \
++ PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
++ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
++
++#define BUTTON_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
++ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
++ PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
++
++#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
++ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
++ PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
++ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
++
++#define WEAK_PULLUP (PAD_CTL_PKE | PAD_CTL_PUE | \
++ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
++ PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
++ PAD_CTL_SRE_SLOW)
++
++#define WEAK_PULLDOWN (PAD_CTL_PKE | PAD_CTL_PUE | \
++ PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
++ PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
++ PAD_CTL_SRE_SLOW)
++
++#define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
++
++int dram_init(void)
++{
++ gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
++
++ return 0;
++}
++
++iomux_v3_cfg_t const uart1_pads[] = {
++ MX6Q_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
++ MX6Q_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
++};
++
++iomux_v3_cfg_t const uart2_pads[] = {
++ MX6Q_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
++ MX6Q_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
++};
++
++#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
++
++/* I2C1, SGTL5000 */
++struct i2c_pads_info i2c_pad_info0 = {
++ .scl = {
++ .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
++ .gpio_mode = MX6Q_PAD_EIM_D21__GPIO_3_21 | PC,
++ .gp = IMX_GPIO_NR(3, 21)
++ },
++ .sda = {
++ .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
++ .gpio_mode = MX6Q_PAD_EIM_D28__GPIO_3_28 | PC,
++ .gp = IMX_GPIO_NR(3, 28)
++ }
++};
++
++/* I2C2 Camera, MIPI */
++struct i2c_pads_info i2c_pad_info1 = {
++ .scl = {
++ .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
++ .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO_4_12 | PC,
++ .gp = IMX_GPIO_NR(4, 12)
++ },
++ .sda = {
++ .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
++ .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO_4_13 | PC,
++ .gp = IMX_GPIO_NR(4, 13)
++ }
++};
++
++/* I2C3, J15 - RGB connector */
++struct i2c_pads_info i2c_pad_info2 = {
++ .scl = {
++ .i2c_mode = MX6Q_PAD_GPIO_5__I2C3_SCL | PC,
++ .gpio_mode = MX6Q_PAD_GPIO_5__GPIO_1_5 | PC,
++ .gp = IMX_GPIO_NR(1, 5)
++ },
++ .sda = {
++ .i2c_mode = MX6Q_PAD_GPIO_16__I2C3_SDA | PC,
++ .gpio_mode = MX6Q_PAD_GPIO_16__GPIO_7_11 | PC,
++ .gp = IMX_GPIO_NR(7, 11)
++ }
++};
++
++iomux_v3_cfg_t const usdhc3_pads[] = {
++ MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
++ MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
++ MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
++ MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
++ MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
++ MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
++ MX6Q_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
++};
++
++iomux_v3_cfg_t const usdhc4_pads[] = {
++ MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
++ MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
++ MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
++ MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
++ MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
++ MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
++ MX6Q_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
++};
++
++iomux_v3_cfg_t const enet_pads1[] = {
++ MX6Q_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
++ MX6Q_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
++ MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
++ MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
++ MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
++ MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
++ MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
++ MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
++ MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
++ /* pin 35 - 1 (PHY_AD2) on reset */
++ MX6Q_PAD_RGMII_RXC__GPIO_6_30 | MUX_PAD_CTRL(NO_PAD_CTRL),
++ /* pin 32 - 1 - (MODE0) all */
++ MX6Q_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL),
++ /* pin 31 - 1 - (MODE1) all */
++ MX6Q_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL),
++ /* pin 28 - 1 - (MODE2) all */
++ MX6Q_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL),
++ /* pin 27 - 1 - (MODE3) all */
++ MX6Q_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL),
++ /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
++ MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL),
++ /* pin 42 PHY nRST */
++ MX6Q_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL),
++ MX6Q_PAD_ENET_RXD0__GPIO_1_27 | MUX_PAD_CTRL(NO_PAD_CTRL),
++};
++
++iomux_v3_cfg_t const enet_pads2[] = {
++ MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
++ MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
++ MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
++ MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
++ MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
++ MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
++};
++
++/* wl1271 pads on nitrogen6x */
++iomux_v3_cfg_t const wl12xx_pads[] = {
++ (MX6Q_PAD_NANDF_CS1__GPIO_6_14 & ~MUX_PAD_CTRL_MASK) | MUX_PAD_CTRL(WEAK_PULLDOWN),
++ (MX6Q_PAD_NANDF_CS2__GPIO_6_15 & ~MUX_PAD_CTRL_MASK) | MUX_PAD_CTRL(OUTPUT_40OHM),
++ (MX6Q_PAD_NANDF_CS3__GPIO_6_16 & ~MUX_PAD_CTRL_MASK) | MUX_PAD_CTRL(OUTPUT_40OHM),
++};
++#define WL12XX_WL_IRQ_GP IMX_GPIO_NR(6,14)
++#define WL12XX_WL_ENABLE_GP IMX_GPIO_NR(6,15)
++#define WL12XX_BT_ENABLE_GP IMX_GPIO_NR(6,16)
++
++/* Button assignments for J14 */
++static iomux_v3_cfg_t const button_pads[] = {
++ /* Menu */
++ MX6Q_PAD_NANDF_D1__GPIO_2_1 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
++ /* Back */
++ MX6Q_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
++ /* Labelled Search (mapped to Power under Android) */
++ MX6Q_PAD_NANDF_D3__GPIO_2_3 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
++ /* Home */
++ MX6Q_PAD_NANDF_D4__GPIO_2_4 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
++ /* Volume Down */
++ MX6Q_PAD_GPIO_19__GPIO_4_5 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
++ /* Volume Up */
++ MX6Q_PAD_GPIO_18__GPIO_7_13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
++};
++
++static void setup_iomux_enet(void)
++{
++ gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* SABRE Lite PHY rst */
++ gpio_direction_output(IMX_GPIO_NR(1, 27), 0); /* Nitrogen6X PHY rst */
++ gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
++ gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
++ gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
++ gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
++ gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
++ imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
++ gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
++
++ /* Need delay 10ms according to KSZ9021 spec */
++ udelay(1000 * 10);
++ gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* SABRE Lite PHY reset */
++ gpio_set_value(IMX_GPIO_NR(1, 27), 1); /* Nitrogen6X PHY reset */
++
++ imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
++}
++
++iomux_v3_cfg_t const usb_pads[] = {
++ MX6Q_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL),
++};
++
++static void setup_iomux_uart(void)
++{
++ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
++ imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
++}
++
++#ifdef CONFIG_USB_EHCI_MX6
++int board_ehci_hcd_init(int port)
++{
++ imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
++
++ /* Reset USB hub */
++ gpio_direction_output(IMX_GPIO_NR(7, 12), 0);
++ mdelay(2);
++ gpio_set_value(IMX_GPIO_NR(7, 12), 1);
++
++ return 0;
++}
++#endif
++
++#ifdef CONFIG_FSL_ESDHC
++struct fsl_esdhc_cfg usdhc_cfg[2] = {
++ {USDHC3_BASE_ADDR},
++ {USDHC4_BASE_ADDR},
++};
++
++int board_mmc_getcd(struct mmc *mmc)
++{
++ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
++ int ret;
++
++ if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
++ gpio_direction_input(IMX_GPIO_NR(7, 0));
++ ret = !gpio_get_value(IMX_GPIO_NR(7, 0));
++ } else {
++ gpio_direction_input(IMX_GPIO_NR(2, 6));
++ ret = !gpio_get_value(IMX_GPIO_NR(2, 6));
++ }
++
++ return ret;
++}
++
++int board_mmc_init(bd_t *bis)
++{
++ s32 status = 0;
++ u32 index = 0;
++
++ for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
++ switch (index) {
++ case 0:
++ imx_iomux_v3_setup_multiple_pads(
++ usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
++ break;
++ case 1:
++ imx_iomux_v3_setup_multiple_pads(
++ usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
++ break;
++ default:
++ printf("Warning: you configured more USDHC controllers"
++ "(%d) then supported by the board (%d)\n",
++ index + 1, CONFIG_SYS_FSL_USDHC_NUM);
++ return status;
++ }
++
++ status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
++ }
++
++ return status;
++}
++#endif
++
++u32 get_board_rev(void)
++{
++ return 0x63000 ;
++}
++
++#ifdef CONFIG_MXC_SPI
++iomux_v3_cfg_t const ecspi1_pads[] = {
++ /* SS1 */
++ MX6Q_PAD_EIM_D19__GPIO_3_19 | MUX_PAD_CTRL(SPI_PAD_CTRL),
++ MX6Q_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
++ MX6Q_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
++ MX6Q_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
++};
++
++void setup_spi(void)
++{
++ gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1);
++ imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
++ ARRAY_SIZE(ecspi1_pads));
++}
++#endif
++
++int board_phy_config(struct phy_device *phydev)
++{
++ /* min rx data delay */
++ ksz9021_phy_extended_write(phydev,
++ MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
++ /* min tx data delay */
++ ksz9021_phy_extended_write(phydev,
++ MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
++ /* max rx/tx clock delay, min rx/tx control */
++ ksz9021_phy_extended_write(phydev,
++ MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
++ if (phydev->drv->config)
++ phydev->drv->config(phydev);
++
++ return 0;
++}
++
++int board_eth_init(bd_t *bis)
++{
++ int ret;
++
++ setup_iomux_enet();
++
++ ret = cpu_eth_init(bis);
++ if (ret)
++ printf("FEC MXC: %s:failed\n", __func__);
++
++ return 0;
++}
++
++static void setup_buttons(void)
++{
++ imx_iomux_v3_setup_multiple_pads(button_pads,
++ ARRAY_SIZE(button_pads));
++}
++
++#ifdef CONFIG_CMD_SATA
++
++int setup_sata(void)
++{
++ struct iomuxc_base_regs *const iomuxc_regs
++ = (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR;
++ int ret = enable_sata_clock();
++ if (ret)
++ return ret;
++
++ clrsetbits_le32(&iomuxc_regs->gpr[13],
++ IOMUXC_GPR13_SATA_MASK,
++ IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
++ |IOMUXC_GPR13_SATA_PHY_7_SATA2M
++ |IOMUXC_GPR13_SATA_SPEED_3G
++ |(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
++ |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
++ |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16
++ |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB
++ |IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
++ |IOMUXC_GPR13_SATA_PHY_1_SLOW);
++
++ return 0;
++}
++#endif
++
++#if defined(CONFIG_VIDEO_IPUV3)
++
++static iomux_v3_cfg_t const backlight_pads[] = {
++ /* Backlight on RGB connector: J15 */
++ MX6Q_PAD_SD1_DAT3__GPIO_1_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
++#define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21)
++
++ /* Backlight on LVDS connector: J6 */
++ MX6Q_PAD_SD1_CMD__GPIO_1_18 | MUX_PAD_CTRL(NO_PAD_CTRL),
++#define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18)
++};
++
++static iomux_v3_cfg_t const rgb_pads[] = {
++ MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
++ MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15,
++ MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2,
++ MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3,
++ MX6Q_PAD_DI0_PIN4__GPIO_4_20,
++ MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
++ MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
++ MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
++ MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
++ MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
++ MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
++ MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
++ MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
++ MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
++ MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
++ MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
++ MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
++ MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
++ MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
++ MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
++ MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
++ MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
++ MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
++ MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
++ MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
++ MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
++ MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
++ MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
++ MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
++};
++
++struct display_info_t {
++ int bus;
++ int addr;
++ int pixfmt;
++ int (*detect)(struct display_info_t const *dev);
++ void (*enable)(struct display_info_t const *dev);
++ struct fb_videomode mode;
++};
++
++
++static int detect_hdmi(struct display_info_t const *dev)
++{
++ return __raw_readb(HDMI_ARB_BASE_ADDR+HDMI_PHY_STAT0) & HDMI_PHY_HPD;
++}
++
++static void enable_hdmi(struct display_info_t const *dev)
++{
++ u8 reg;
++ printf("%s: setup HDMI monitor\n", __func__);
++ reg = __raw_readb(
++ HDMI_ARB_BASE_ADDR
++ +HDMI_PHY_CONF0);
++ reg |= HDMI_PHY_CONF0_PDZ_MASK;
++ __raw_writeb(reg,
++ HDMI_ARB_BASE_ADDR
++ +HDMI_PHY_CONF0);
++ udelay(3000);
++ reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
++ __raw_writeb(reg,
++ HDMI_ARB_BASE_ADDR
++ +HDMI_PHY_CONF0);
++ udelay(3000);
++ reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
++ __raw_writeb(reg,
++ HDMI_ARB_BASE_ADDR
++ +HDMI_PHY_CONF0);
++ __raw_writeb(HDMI_MC_PHYRSTZ_ASSERT,
++ HDMI_ARB_BASE_ADDR+HDMI_MC_PHYRSTZ);
++}
++
++static int detect_i2c(struct display_info_t const *dev)
++{
++ return ((0 == i2c_set_bus_num(dev->bus))
++ &&
++ (0 == i2c_probe(dev->addr)));
++}
++
++static void enable_lvds(struct display_info_t const *dev)
++{
++ struct iomuxc *iomux = (struct iomuxc *)
++ IOMUXC_BASE_ADDR;
++ u32 reg = readl(&iomux->gpr[2]);
++ reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
++ writel(reg, &iomux->gpr[2]);
++ gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
++}
++
++static void enable_rgb(struct display_info_t const *dev)
++{
++ imx_iomux_v3_setup_multiple_pads(
++ rgb_pads,
++ ARRAY_SIZE(rgb_pads));
++ gpio_direction_output(RGB_BACKLIGHT_GP, 1);
++}
++
++static struct display_info_t const displays[] = {{
++ .bus = -1,
++ .addr = 0,
++ .pixfmt = IPU_PIX_FMT_RGB24,
++ .detect = detect_hdmi,
++ .enable = enable_hdmi,
++ .mode = {
++ .name = "HDMI",
++ .refresh = 60,
++ .xres = 1024,
++ .yres = 768,
++ .pixclock = 15385,
++ .left_margin = 220,
++ .right_margin = 40,
++ .upper_margin = 21,
++ .lower_margin = 7,
++ .hsync_len = 60,
++ .vsync_len = 10,
++ .sync = FB_SYNC_EXT,
++ .vmode = FB_VMODE_NONINTERLACED
++} }, {
++ .bus = 2,
++ .addr = 0x4,
++ .pixfmt = IPU_PIX_FMT_LVDS666,
++ .detect = detect_i2c,
++ .enable = enable_lvds,
++ .mode = {
++ .name = "Hannstar-XGA",
++ .refresh = 60,
++ .xres = 1024,
++ .yres = 768,
++ .pixclock = 15385,
++ .left_margin = 220,
++ .right_margin = 40,
++ .upper_margin = 21,
++ .lower_margin = 7,
++ .hsync_len = 60,
++ .vsync_len = 10,
++ .sync = FB_SYNC_EXT,
++ .vmode = FB_VMODE_NONINTERLACED
++} }, {
++ .bus = 2,
++ .addr = 0x38,
++ .pixfmt = IPU_PIX_FMT_LVDS666,
++ .detect = detect_i2c,
++ .enable = enable_lvds,
++ .mode = {
++ .name = "wsvga-lvds",
++ .refresh = 60,
++ .xres = 1024,
++ .yres = 600,
++ .pixclock = 15385,
++ .left_margin = 220,
++ .right_margin = 40,
++ .upper_margin = 21,
++ .lower_margin = 7,
++ .hsync_len = 60,
++ .vsync_len = 10,
++ .sync = FB_SYNC_EXT,
++ .vmode = FB_VMODE_NONINTERLACED
++} }, {
++ .bus = 2,
++ .addr = 0x48,
++ .pixfmt = IPU_PIX_FMT_RGB666,
++ .detect = detect_i2c,
++ .enable = enable_rgb,
++ .mode = {
++ .name = "wvga-rgb",
++ .refresh = 57,
++ .xres = 800,
++ .yres = 480,
++ .pixclock = 37037,
++ .left_margin = 40,
++ .right_margin = 60,
++ .upper_margin = 10,
++ .lower_margin = 10,
++ .hsync_len = 20,
++ .vsync_len = 10,
++ .sync = 0,
++ .vmode = FB_VMODE_NONINTERLACED
++} } };
++
++int board_video_skip(void)
++{
++ int i;
++ int ret;
++ char const *panel = getenv("panel");
++ if (!panel) {
++ for (i = 0; i < ARRAY_SIZE(displays); i++) {
++ struct display_info_t const *dev = displays+i;
++ if (dev->detect(dev)) {
++ panel = dev->mode.name;
++ printf("auto-detected panel %s\n", panel);
++ break;
++ }
++ }
++ if (!panel) {
++ panel = displays[0].mode.name;
++ printf("No panel detected: default to %s\n", panel);
++ }
++ } else {
++ for (i = 0; i < ARRAY_SIZE(displays); i++) {
++ if (!strcmp(panel, displays[i].mode.name))
++ break;
++ }
++ }
++ if (i < ARRAY_SIZE(displays)) {
++ ret = ipuv3_fb_init(&displays[i].mode, 0,
++ displays[i].pixfmt);
++ if (!ret) {
++ displays[i].enable(displays+i);
++ printf("Display: %s (%ux%u)\n",
++ displays[i].mode.name,
++ displays[i].mode.xres,
++ displays[i].mode.yres);
++ } else
++ printf("LCD %s cannot be configured: %d\n",
++ displays[i].mode.name, ret);
++ } else {
++ printf("unsupported panel %s\n", panel);
++ ret = -EINVAL;
++ }
++ return (0 != ret);
++}
++
++static void setup_display(void)
++{
++ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
++ struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
++ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
++
++ int reg;
++
++ /* Turn on LDB0,IPU,IPU DI0 clocks */
++ reg = __raw_readl(&mxc_ccm->CCGR3);
++ reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET
++ |MXC_CCM_CCGR3_LDB_DI0_MASK;
++ writel(reg, &mxc_ccm->CCGR3);
++
++ /* Turn on HDMI PHY clock */
++ reg = __raw_readl(&mxc_ccm->CCGR2);
++ reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK
++ |MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
++ writel(reg, &mxc_ccm->CCGR2);
++
++ /* clear HDMI PHY reset */
++ __raw_writeb(HDMI_MC_PHYRSTZ_DEASSERT,
++ HDMI_ARB_BASE_ADDR+HDMI_MC_PHYRSTZ);
++
++ /* set PFD1_FRAC to 0x13 == 455 MHz (480*18)/0x13 */
++ writel(ANATOP_PFD_480_PFD1_FRAC_MASK, &anatop->pfd_480_clr);
++ writel(0x13<<ANATOP_PFD_480_PFD1_FRAC_SHIFT, &anatop->pfd_480_set);
++
++ /* set LDB0, LDB1 clk select to 011/011 */
++ reg = readl(&mxc_ccm->cs2cdr);
++ reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
++ |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
++ reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
++ |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
++ writel(reg, &mxc_ccm->cs2cdr);
++
++ reg = readl(&mxc_ccm->cscmr2);
++ reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
++ writel(reg, &mxc_ccm->cscmr2);
++
++ reg = readl(&mxc_ccm->chsccdr);
++ reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK
++ |MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK
++ |MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
++ reg |= (CHSCCDR_CLK_SEL_LDB_DI0
++ <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
++ |(CHSCCDR_PODF_DIVIDE_BY_3
++ <<MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
++ |(CHSCCDR_IPU_PRE_CLK_540M_PFD
++ <<MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
++ writel(reg, &mxc_ccm->chsccdr);
++
++ reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
++ |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
++ |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
++ |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
++ |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
++ |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
++ |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
++ |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
++ |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
++ writel(reg, &iomux->gpr[2]);
++
++ reg = readl(&iomux->gpr[3]);
++ reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
++ | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
++ <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
++ writel(reg, &iomux->gpr[3]);
++
++ /* backlights off until needed */
++ imx_iomux_v3_setup_multiple_pads(backlight_pads,
++ ARRAY_SIZE(backlight_pads));
++ gpio_direction_input(LVDS_BACKLIGHT_GP);
++ gpio_direction_input(RGB_BACKLIGHT_GP);
++}
++#endif
++
++int board_early_init_f(void)
++{
++ setup_iomux_uart();
++
++ /* Disable wl1271 For Nitrogen6w */
++ gpio_direction_input(WL12XX_WL_IRQ_GP);
++ gpio_direction_output(WL12XX_WL_ENABLE_GP,0);
++ gpio_direction_output(WL12XX_BT_ENABLE_GP,0);
++
++ imx_iomux_v3_setup_multiple_pads(wl12xx_pads, ARRAY_SIZE(wl12xx_pads));
++ setup_buttons();
++
++#if defined(CONFIG_VIDEO_IPUV3)
++ setup_display();
++#endif
++ return 0;
++}
++
++/*
++ * Do not overwrite the console
++ * Use always serial for U-Boot console
++ */
++int overwrite_console(void)
++{
++ return 1;
++}
++
++int board_init(void)
++{
++ /* address of boot parameters */
++ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
++
++#ifdef CONFIG_MXC_SPI
++ setup_spi();
++#endif
++ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
++ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
++ setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
++
++#ifdef CONFIG_CMD_SATA
++ setup_sata();
++#endif
++
++ return 0;
++}
++
++int checkboard(void)
++{
++ if (gpio_get_value(WL12XX_WL_IRQ_GP)) {
++ puts("Board: Nitrogen6X\n");
++ } else
++ puts("Board: SABRE Lite\n");
++
++ return 0;
++}
++
++struct button_key {
++ char const *name;
++ unsigned gpnum;
++ char ident;
++};
++
++static struct button_key const buttons[] = {
++ {"back", IMX_GPIO_NR(2, 2), 'B'},
++ {"home", IMX_GPIO_NR(2, 4), 'H'},
++ {"menu", IMX_GPIO_NR(2, 1), 'M'},
++ {"search", IMX_GPIO_NR(2, 3), 'S'},
++ {"volup", IMX_GPIO_NR(7, 13), 'V'},
++ {"voldown", IMX_GPIO_NR(4, 5), 'v'},
++};
++
++/*
++ * generate a null-terminated string containing the buttons pressed
++ * returns number of keys pressed
++ */
++static int read_keys(char *buf)
++{
++ int i, numpressed = 0;
++ for (i = 0; i < ARRAY_SIZE(buttons); i++) {
++ if (!gpio_get_value(buttons[i].gpnum))
++ buf[numpressed++] = buttons[i].ident;
++ }
++ buf[numpressed] = '\0';
++ return numpressed;
++}
++
++static int do_kbd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
++{
++ char envvalue[ARRAY_SIZE(buttons)+1];
++ int numpressed = read_keys(envvalue);
++ setenv("keybd", envvalue);
++ return numpressed == 0;
++}
++
++U_BOOT_CMD(
++ kbd, 1, 1, do_kbd,
++ "Tests for keypresses, sets 'keybd' environment variable",
++ "Returns 0 (true) to shell if key is pressed."
++);
++
++#ifdef CONFIG_PREBOOT
++static char const kbd_magic_prefix[] = "key_magic";
++static char const kbd_command_prefix[] = "key_cmd";
++
++static void preboot_keys(void)
++{
++ int numpressed;
++ char keypress[ARRAY_SIZE(buttons)+1];
++ numpressed = read_keys(keypress);
++ if (numpressed) {
++ char *kbd_magic_keys = getenv("magic_keys");
++ char *suffix;
++ /*
++ * loop over all magic keys
++ */
++ for (suffix = kbd_magic_keys; *suffix; ++suffix) {
++ char *keys;
++ char magic[sizeof(kbd_magic_prefix) + 1];
++ sprintf(magic, "%s%c", kbd_magic_prefix, *suffix);
++ keys = getenv(magic);
++ if (keys) {
++ if (!strcmp(keys, keypress))
++ break;
++ }
++ }
++ if (*suffix) {
++ char cmd_name[sizeof(kbd_command_prefix) + 1];
++ char *cmd;
++ sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix);
++ cmd = getenv(cmd_name);
++ if (cmd) {
++ setenv("preboot", cmd);
++ return;
++ }
++ }
++ }
++}
++#endif
++
++#ifdef CONFIG_CMD_BMODE
++static const struct boot_mode board_boot_modes[] = {
++ /* 4 bit bus width */
++ {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
++ {"mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
++ {NULL, 0},
++};
++#endif
++
++int misc_init_r(void)
++{
++#ifdef CONFIG_PREBOOT
++ preboot_keys();
++#endif
++
++#ifdef CONFIG_CMD_BMODE
++ add_board_boot_modes(board_boot_modes);
++#endif
++ return 0;
++}
+diff --git a/board/buffalo/lsxl/lsxl.c b/board/buffalo/lsxl/lsxl.c
+index 57776fb..b3f31d6 100644
+--- a/board/buffalo/lsxl/lsxl.c
++++ b/board/buffalo/lsxl/lsxl.c
+@@ -195,11 +195,9 @@ int board_init(void)
+ static void check_power_switch(void)
+ {
+ if (kw_gpio_get_value(GPIO_POWER_SWITCH)) {
+- /* turn off fan, HDD and USB power */
++ /* turn off HDD and USB power */
+ kw_gpio_set_value(GPIO_HDD_POWER, 0);
+ kw_gpio_set_value(GPIO_USB_VBUS, 0);
+- kw_gpio_set_value(GPIO_FAN_HIGH, 1);
+- kw_gpio_set_value(GPIO_FAN_LOW, 1);
+ set_led(LED_OFF);
+
+ /* loop until released */
+@@ -209,8 +207,6 @@ static void check_power_switch(void)
+ /* turn power on again */
+ kw_gpio_set_value(GPIO_HDD_POWER, 1);
+ kw_gpio_set_value(GPIO_USB_VBUS, 1);
+- kw_gpio_set_value(GPIO_FAN_HIGH, 0);
+- kw_gpio_set_value(GPIO_FAN_LOW, 0);
+ set_led(LED_POWER_BLINKING);
+ }
+ }
+diff --git a/board/davinci/ea20/ea20.c b/board/davinci/ea20/ea20.c
+index 0edd910..7e00040 100644
+--- a/board/davinci/ea20/ea20.c
++++ b/board/davinci/ea20/ea20.c
+@@ -176,9 +176,6 @@ int board_early_init_f(void)
+ if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0)
+ return 1;
+
+- /* Set DISP_ON high to enable LCD output*/
+- gpio_direction_output(97, 1);
+-
+ /* Set the RESETOUTn low */
+ gpio_direction_output(111, 0);
+
+@@ -191,6 +188,9 @@ int board_early_init_f(void)
+ /* Set LCD_B_PWR low to power down LCD Backlight*/
+ gpio_direction_output(102, 0);
+
++ /* Set DISP_ON low to disable LCD output*/
++ gpio_direction_output(97, 0);
++
+ #ifndef CONFIG_USE_IRQ
+ irq_init();
+ #endif
+@@ -250,17 +250,13 @@ int board_early_init_f(void)
+ writel(readl(&davinci_syscfg_regs->mstpri[2]) & 0x0fffffff,
+ &davinci_syscfg_regs->mstpri[2]);
+
++ /* Set LCD_B_PWR low to power up LCD Backlight*/
++ gpio_set_value(102, 1);
+
+- return 0;
+-}
++ /* Set DISP_ON low to disable LCD output*/
++ gpio_set_value(97, 1);
+
+-/*
+- * Do not overwrite the console
+- * Use always serial for U-Boot console
+- */
+-int overwrite_console(void)
+-{
+- return 1;
++ return 0;
+ }
+
+ int board_init(void)
+@@ -280,9 +276,6 @@ int board_init(void)
+
+ int board_late_init(void)
+ {
+- unsigned char buf[2];
+- int ret;
+-
+ /* PinMux for HALTEN */
+ if (davinci_configure_pin_mux(halten_pin, ARRAY_SIZE(halten_pin)) != 0)
+ return 1;
+@@ -290,15 +283,8 @@ int board_late_init(void)
+ /* Set HALTEN to high */
+ gpio_direction_output(134, 1);
+
+- /* Set fixed contrast settings for LCD via I2C potentiometer */
+- buf[0] = 0x00;
+- buf[1] = 0xd7;
+- ret = i2c_write(0x2e, 6, 1, buf, 2);
+- if (ret)
+- puts("\nContrast Settings FAILED\n");
++ setenv("stdout", "serial");
+
+- /* Set LCD_B_PWR high to power up LCD Backlight*/
+- gpio_set_value(102, 1);
+ return 0;
+ }
+ #endif /* CONFIG_BOARD_LATE_INIT */
+diff --git a/board/freescale/mx31ads/lowlevel_init.S b/board/freescale/mx31ads/lowlevel_init.S
+index 5c18bc1..2972065 100644
+--- a/board/freescale/mx31ads/lowlevel_init.S
++++ b/board/freescale/mx31ads/lowlevel_init.S
+@@ -246,8 +246,8 @@ lowlevel_init:
+ /* COSR */
+ str r1, [r0, #0x1c]
+
+- /* RedBoot sets 0x1ff, 7, 3, 5, 1, 3, 0 */
+-/* REG CCM_PDR0, PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0)*/
++ /* RedBoot sets 0x3f, 7, 7, 3, 5, 1, 3, 0 */
++/* REG CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0)*/
+
+ /* Redboot: 0, 51, 10, 12 / 0, 14, 9, 13 */
+ /* REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0x33) | PLL_MFI(7) | PLL_MFN(0x23)*/
+diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c
+index a94701c..3c4f814 100644
+--- a/board/freescale/mx51evk/mx51evk.c
++++ b/board/freescale/mx51evk/mx51evk.c
+@@ -467,7 +467,7 @@ int board_mmc_init(bd_t *bis)
+ }
+ #endif
+
+-static struct fb_videomode claa_wvga = {
++static struct fb_videomode const claa_wvga = {
+ .name = "CLAA07LC0ACW",
+ .refresh = 57,
+ .xres = 800,
+diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c
+index 8f82125..6fcaa0b 100644
+--- a/board/freescale/mx53loco/mx53loco.c
++++ b/board/freescale/mx53loco/mx53loco.c
+@@ -394,7 +394,7 @@ static int power_init(void)
+ static void clock_1GHz(void)
+ {
+ int ret;
+- u32 ref_clk = CONFIG_SYS_MX5_HCLK;
++ u32 ref_clk = MXC_HCLK;
+ /*
+ * After increasing voltage to 1.25V, we can switch
+ * CPU clock to 1GHz and DDR to 400MHz safely
+@@ -409,7 +409,7 @@ static void clock_1GHz(void)
+ printf("CPU: Switch DDR clock to 400MHz failed\n");
+ }
+
+-static struct fb_videomode claa_wvga = {
++static struct fb_videomode const claa_wvga = {
+ .name = "CLAA07LC0ACW",
+ .refresh = 57,
+ .xres = 800,
+diff --git a/board/freescale/mx6qarm2/mx6qarm2.c b/board/freescale/mx6qarm2/mx6qarm2.c
+index d43b327..b6b3542 100644
+--- a/board/freescale/mx6qarm2/mx6qarm2.c
++++ b/board/freescale/mx6qarm2/mx6qarm2.c
+@@ -53,12 +53,12 @@ int dram_init(void)
+ return 0;
+ }
+
+-iomux_v3_cfg_t uart4_pads[] = {
++iomux_v3_cfg_t const uart4_pads[] = {
+ MX6Q_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6Q_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+ };
+
+-iomux_v3_cfg_t usdhc3_pads[] = {
++iomux_v3_cfg_t const usdhc3_pads[] = {
+ MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+@@ -72,7 +72,7 @@ iomux_v3_cfg_t usdhc3_pads[] = {
+ MX6Q_PAD_NANDF_CS0__GPIO_6_11 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+ };
+
+-iomux_v3_cfg_t usdhc4_pads[] = {
++iomux_v3_cfg_t const usdhc4_pads[] = {
+ MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+@@ -85,7 +85,7 @@ iomux_v3_cfg_t usdhc4_pads[] = {
+ MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ };
+
+-iomux_v3_cfg_t enet_pads[] = {
++iomux_v3_cfg_t const enet_pads[] = {
+ MX6Q_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
+index 8ca1ae7..25d8fe5 100644
+--- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c
++++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
+@@ -30,8 +30,6 @@
+ #include <fsl_esdhc.h>
+ #include <miiphy.h>
+ #include <netdev.h>
+-#include <asm/arch/sys_proto.h>
+-
+ DECLARE_GLOBAL_DATA_PTR;
+
+ #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+@@ -53,12 +51,12 @@ int dram_init(void)
+ return 0;
+ }
+
+-iomux_v3_cfg_t uart4_pads[] = {
++iomux_v3_cfg_t const uart4_pads[] = {
+ MX6Q_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6Q_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+ };
+
+-iomux_v3_cfg_t enet_pads[] = {
++iomux_v3_cfg_t const enet_pads[] = {
+ MX6Q_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+@@ -81,7 +79,7 @@ static void setup_iomux_enet(void)
+ imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
+ }
+
+-iomux_v3_cfg_t usdhc3_pads[] = {
++iomux_v3_cfg_t const usdhc3_pads[] = {
+ MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+@@ -166,38 +164,9 @@ int board_eth_init(bd_t *bis)
+ return 0;
+ }
+
+-#define BOARD_REV_B 0x200
+-#define BOARD_REV_A 0x100
+-
+-static int mx6sabre_rev(void)
+-{
+- /*
+- * Get Board ID information from OCOTP_GP1[15:8]
+- * i.MX6Q ARD RevA: 0x01
+- * i.MX6Q ARD RevB: 0x02
+- */
+- struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+- int reg = readl(&ocotp->gp1);
+- int ret;
+-
+- switch (reg >> 8 & 0x0F) {
+- case 0x02:
+- ret = BOARD_REV_B;
+- break;
+- case 0x01:
+- default:
+- ret = BOARD_REV_A;
+- break;
+- }
+-
+- return ret;
+-}
+-
+ u32 get_board_rev(void)
+ {
+- int rev = mx6sabre_rev();
+-
+- return (get_cpu_rev() & ~(0xF << 8)) | rev;
++ return 0x63000;
+ }
+
+ int board_early_init_f(void)
+@@ -217,20 +186,7 @@ int board_init(void)
+
+ int checkboard(void)
+ {
+- int rev = mx6sabre_rev();
+- char *revname;
+-
+- switch (rev) {
+- case BOARD_REV_B:
+- revname = "B";
+- break;
+- case BOARD_REV_A:
+- default:
+- revname = "A";
+- break;
+- }
+-
+- printf("Board: MX6Q-Sabreauto rev%s\n", revname);
++ puts("Board: MX6Q-Sabreauto\n");
+
+ return 0;
+ }
+diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
+index 4b4e89b..3635cdb 100644
+--- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
++++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
+@@ -36,6 +36,12 @@
+ #include <micrel.h>
+ #include <miiphy.h>
+ #include <netdev.h>
++#include <linux/fb.h>
++#include <ipu_pixfmt.h>
++#include <asm/arch/crm_regs.h>
++#include <asm/arch/mxc_hdmi.h>
++#include <i2c.h>
++
+ DECLARE_GLOBAL_DATA_PTR;
+
+ #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+@@ -70,12 +76,12 @@ int dram_init(void)
+ return 0;
+ }
+
+-iomux_v3_cfg_t uart1_pads[] = {
++iomux_v3_cfg_t const uart1_pads[] = {
+ MX6Q_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6Q_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+ };
+
+-iomux_v3_cfg_t uart2_pads[] = {
++iomux_v3_cfg_t const uart2_pads[] = {
+ MX6Q_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6Q_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+ };
+@@ -124,7 +130,7 @@ struct i2c_pads_info i2c_pad_info2 = {
+ }
+ };
+
+-iomux_v3_cfg_t usdhc3_pads[] = {
++iomux_v3_cfg_t const usdhc3_pads[] = {
+ MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+@@ -134,7 +140,7 @@ iomux_v3_cfg_t usdhc3_pads[] = {
+ MX6Q_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+ };
+
+-iomux_v3_cfg_t usdhc4_pads[] = {
++iomux_v3_cfg_t const usdhc4_pads[] = {
+ MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+@@ -144,7 +150,7 @@ iomux_v3_cfg_t usdhc4_pads[] = {
+ MX6Q_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+ };
+
+-iomux_v3_cfg_t enet_pads1[] = {
++iomux_v3_cfg_t const enet_pads1[] = {
+ MX6Q_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+@@ -170,7 +176,7 @@ iomux_v3_cfg_t enet_pads1[] = {
+ MX6Q_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ };
+
+-iomux_v3_cfg_t enet_pads2[] = {
++iomux_v3_cfg_t const enet_pads2[] = {
+ MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+@@ -180,7 +186,7 @@ iomux_v3_cfg_t enet_pads2[] = {
+ };
+
+ /* Button assignments for J14 */
+-static iomux_v3_cfg_t button_pads[] = {
++static iomux_v3_cfg_t const button_pads[] = {
+ /* Menu */
+ MX6Q_PAD_NANDF_D1__GPIO_2_1 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+ /* Back */
+@@ -213,7 +219,7 @@ static void setup_iomux_enet(void)
+ imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
+ }
+
+-iomux_v3_cfg_t usb_pads[] = {
++iomux_v3_cfg_t const usb_pads[] = {
+ MX6Q_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ };
+
+@@ -294,7 +300,7 @@ u32 get_board_rev(void)
+ }
+
+ #ifdef CONFIG_MXC_SPI
+-iomux_v3_cfg_t ecspi1_pads[] = {
++iomux_v3_cfg_t const ecspi1_pads[] = {
+ /* SS1 */
+ MX6Q_PAD_EIM_D19__GPIO_3_19 | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6Q_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+@@ -372,14 +378,337 @@ int setup_sata(void)
+ }
+ #endif
+
++#if defined(CONFIG_VIDEO_IPUV3)
++
++static iomux_v3_cfg_t const backlight_pads[] = {
++ /* Backlight on RGB connector: J15 */
++ MX6Q_PAD_SD1_DAT3__GPIO_1_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
++#define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21)
++
++ /* Backlight on LVDS connector: J6 */
++ MX6Q_PAD_SD1_CMD__GPIO_1_18 | MUX_PAD_CTRL(NO_PAD_CTRL),
++#define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18)
++};
++
++static iomux_v3_cfg_t const rgb_pads[] = {
++ MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
++ MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15,
++ MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2,
++ MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3,
++ MX6Q_PAD_DI0_PIN4__GPIO_4_20,
++ MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
++ MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
++ MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
++ MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
++ MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
++ MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
++ MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
++ MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
++ MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
++ MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
++ MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
++ MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
++ MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
++ MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
++ MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
++ MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
++ MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
++ MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
++ MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
++ MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
++ MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
++ MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
++ MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
++ MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
++};
++
++struct display_info_t {
++ int bus;
++ int addr;
++ int pixfmt;
++ int (*detect)(struct display_info_t const *dev);
++ void (*enable)(struct display_info_t const *dev);
++ struct fb_videomode mode;
++};
++
++
++static int detect_hdmi(struct display_info_t const *dev)
++{
++ return __raw_readb(HDMI_ARB_BASE_ADDR+HDMI_PHY_STAT0) & HDMI_PHY_HPD;
++}
++
++static void enable_hdmi(struct display_info_t const *dev)
++{
++ u8 reg;
++ printf("%s: setup HDMI monitor\n", __func__);
++ reg = __raw_readb(
++ HDMI_ARB_BASE_ADDR
++ +HDMI_PHY_CONF0);
++ reg |= HDMI_PHY_CONF0_PDZ_MASK;
++ __raw_writeb(reg,
++ HDMI_ARB_BASE_ADDR
++ +HDMI_PHY_CONF0);
++ udelay(3000);
++ reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
++ __raw_writeb(reg,
++ HDMI_ARB_BASE_ADDR
++ +HDMI_PHY_CONF0);
++ udelay(3000);
++ reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
++ __raw_writeb(reg,
++ HDMI_ARB_BASE_ADDR
++ +HDMI_PHY_CONF0);
++ __raw_writeb(HDMI_MC_PHYRSTZ_ASSERT,
++ HDMI_ARB_BASE_ADDR+HDMI_MC_PHYRSTZ);
++}
++
++static int detect_i2c(struct display_info_t const *dev)
++{
++ return ((0 == i2c_set_bus_num(dev->bus))
++ &&
++ (0 == i2c_probe(dev->addr)));
++}
++
++static void enable_lvds(struct display_info_t const *dev)
++{
++ struct iomuxc *iomux = (struct iomuxc *)
++ IOMUXC_BASE_ADDR;
++ u32 reg = readl(&iomux->gpr[2]);
++ reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
++ writel(reg, &iomux->gpr[2]);
++ gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
++}
++
++static void enable_rgb(struct display_info_t const *dev)
++{
++ imx_iomux_v3_setup_multiple_pads(
++ rgb_pads,
++ ARRAY_SIZE(rgb_pads));
++ gpio_direction_output(RGB_BACKLIGHT_GP, 1);
++}
++
++static struct display_info_t const displays[] = {{
++ .bus = -1,
++ .addr = 0,
++ .pixfmt = IPU_PIX_FMT_RGB24,
++ .detect = detect_hdmi,
++ .enable = enable_hdmi,
++ .mode = {
++ .name = "HDMI",
++ .refresh = 60,
++ .xres = 1024,
++ .yres = 768,
++ .pixclock = 15385,
++ .left_margin = 220,
++ .right_margin = 40,
++ .upper_margin = 21,
++ .lower_margin = 7,
++ .hsync_len = 60,
++ .vsync_len = 10,
++ .sync = FB_SYNC_EXT,
++ .vmode = FB_VMODE_NONINTERLACED
++} }, {
++ .bus = 2,
++ .addr = 0x4,
++ .pixfmt = IPU_PIX_FMT_LVDS666,
++ .detect = detect_i2c,
++ .enable = enable_lvds,
++ .mode = {
++ .name = "Hannstar-XGA",
++ .refresh = 60,
++ .xres = 1024,
++ .yres = 768,
++ .pixclock = 15385,
++ .left_margin = 220,
++ .right_margin = 40,
++ .upper_margin = 21,
++ .lower_margin = 7,
++ .hsync_len = 60,
++ .vsync_len = 10,
++ .sync = FB_SYNC_EXT,
++ .vmode = FB_VMODE_NONINTERLACED
++} }, {
++ .bus = 2,
++ .addr = 0x38,
++ .pixfmt = IPU_PIX_FMT_LVDS666,
++ .detect = detect_i2c,
++ .enable = enable_lvds,
++ .mode = {
++ .name = "wsvga-lvds",
++ .refresh = 60,
++ .xres = 1024,
++ .yres = 600,
++ .pixclock = 15385,
++ .left_margin = 220,
++ .right_margin = 40,
++ .upper_margin = 21,
++ .lower_margin = 7,
++ .hsync_len = 60,
++ .vsync_len = 10,
++ .sync = FB_SYNC_EXT,
++ .vmode = FB_VMODE_NONINTERLACED
++} }, {
++ .bus = 2,
++ .addr = 0x48,
++ .pixfmt = IPU_PIX_FMT_RGB666,
++ .detect = detect_i2c,
++ .enable = enable_rgb,
++ .mode = {
++ .name = "wvga-rgb",
++ .refresh = 57,
++ .xres = 800,
++ .yres = 480,
++ .pixclock = 37037,
++ .left_margin = 40,
++ .right_margin = 60,
++ .upper_margin = 10,
++ .lower_margin = 10,
++ .hsync_len = 20,
++ .vsync_len = 10,
++ .sync = 0,
++ .vmode = FB_VMODE_NONINTERLACED
++} } };
++
++int board_video_skip(void)
++{
++ int i;
++ int ret;
++ char const *panel = getenv("panel");
++ if (!panel) {
++ for (i = 0; i < ARRAY_SIZE(displays); i++) {
++ struct display_info_t const *dev = displays+i;
++ if (dev->detect(dev)) {
++ panel = dev->mode.name;
++ printf("auto-detected panel %s\n", panel);
++ break;
++ }
++ }
++ if (!panel) {
++ panel = displays[0].mode.name;
++ printf("No panel detected: default to %s\n", panel);
++ }
++ } else {
++ for (i = 0; i < ARRAY_SIZE(displays); i++) {
++ if (!strcmp(panel, displays[i].mode.name))
++ break;
++ }
++ }
++ if (i < ARRAY_SIZE(displays)) {
++ ret = ipuv3_fb_init(&displays[i].mode, 0,
++ displays[i].pixfmt);
++ if (!ret) {
++ displays[i].enable(displays+i);
++ printf("Display: %s (%ux%u)\n",
++ displays[i].mode.name,
++ displays[i].mode.xres,
++ displays[i].mode.yres);
++ } else
++ printf("LCD %s cannot be configured: %d\n",
++ displays[i].mode.name, ret);
++ } else {
++ printf("unsupported panel %s\n", panel);
++ ret = -EINVAL;
++ }
++ return (0 != ret);
++}
++
++static void setup_display(void)
++{
++ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
++ struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
++ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
++
++ int reg;
++
++ /* Turn on LDB0,IPU,IPU DI0 clocks */
++ reg = __raw_readl(&mxc_ccm->CCGR3);
++ reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET
++ |MXC_CCM_CCGR3_LDB_DI0_MASK;
++ writel(reg, &mxc_ccm->CCGR3);
++
++ /* Turn on HDMI PHY clock */
++ reg = __raw_readl(&mxc_ccm->CCGR2);
++ reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK
++ |MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
++ writel(reg, &mxc_ccm->CCGR2);
++
++ /* clear HDMI PHY reset */
++ __raw_writeb(HDMI_MC_PHYRSTZ_DEASSERT,
++ HDMI_ARB_BASE_ADDR+HDMI_MC_PHYRSTZ);
++
++ /* set PFD1_FRAC to 0x13 == 455 MHz (480*18)/0x13 */
++ writel(ANATOP_PFD_480_PFD1_FRAC_MASK, &anatop->pfd_480_clr);
++ writel(0x13<<ANATOP_PFD_480_PFD1_FRAC_SHIFT, &anatop->pfd_480_set);
++
++ /* set LDB0, LDB1 clk select to 011/011 */
++ reg = readl(&mxc_ccm->cs2cdr);
++ reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
++ |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
++ reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
++ |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
++ writel(reg, &mxc_ccm->cs2cdr);
++
++ reg = readl(&mxc_ccm->cscmr2);
++ reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
++ writel(reg, &mxc_ccm->cscmr2);
++
++ reg = readl(&mxc_ccm->chsccdr);
++ reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK
++ |MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK
++ |MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
++ reg |= (CHSCCDR_CLK_SEL_LDB_DI0
++ <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
++ |(CHSCCDR_PODF_DIVIDE_BY_3
++ <<MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
++ |(CHSCCDR_IPU_PRE_CLK_540M_PFD
++ <<MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
++ writel(reg, &mxc_ccm->chsccdr);
++
++ reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
++ |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
++ |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
++ |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
++ |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
++ |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
++ |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
++ |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
++ |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
++ writel(reg, &iomux->gpr[2]);
++
++ reg = readl(&iomux->gpr[3]);
++ reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
++ | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
++ <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
++ writel(reg, &iomux->gpr[3]);
++
++ /* backlights off until needed */
++ imx_iomux_v3_setup_multiple_pads(backlight_pads,
++ ARRAY_SIZE(backlight_pads));
++ gpio_direction_input(LVDS_BACKLIGHT_GP);
++ gpio_direction_input(RGB_BACKLIGHT_GP);
++}
++#endif
++
+ int board_early_init_f(void)
+ {
+ setup_iomux_uart();
+ setup_buttons();
+
++#if defined(CONFIG_VIDEO_IPUV3)
++ setup_display();
++#endif
+ return 0;
+ }
+
++/*
++ * Do not overwrite the console
++ * Use always serial for U-Boot console
++ */
++int overwrite_console(void)
++{
++ return 1;
++}
++
+ int board_init(void)
+ {
+ /* address of boot parameters */
+diff --git a/board/freescale/mx6qsabresd/mx6qsabresd.c b/board/freescale/mx6qsabresd/mx6qsabresd.c
+index 03a6857..745d398 100644
+--- a/board/freescale/mx6qsabresd/mx6qsabresd.c
++++ b/board/freescale/mx6qsabresd/mx6qsabresd.c
+@@ -51,12 +51,12 @@ int dram_init(void)
+ return 0;
+ }
+
+-iomux_v3_cfg_t uart1_pads[] = {
++iomux_v3_cfg_t const uart1_pads[] = {
+ MX6Q_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6Q_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+ };
+
+-iomux_v3_cfg_t enet_pads[] = {
++iomux_v3_cfg_t const enet_pads[] = {
+ MX6Q_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+@@ -86,7 +86,7 @@ static void setup_iomux_enet(void)
+ gpio_set_value(IMX_GPIO_NR(1, 25), 1);
+ }
+
+-iomux_v3_cfg_t usdhc3_pads[] = {
++iomux_v3_cfg_t const usdhc3_pads[] = {
+ MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+diff --git a/board/friendlyarm/mini2440/Makefile b/board/friendlyarm/mini2440/Makefile
+deleted file mode 100644
+index b88e569..0000000
+--- a/board/friendlyarm/mini2440/Makefile
++++ /dev/null
+@@ -1,44 +0,0 @@
+-#
+-# (C) Copyright 2012
+-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+-#
+-# See file CREDITS for list of people who contributed to this
+-# project.
+-#
+-# This program is free software; you can redistribute it and/or
+-# modify it under the terms of the GNU General Public License as
+-# published by the Free Software Foundation; either version 2 of
+-# the License, or (at your option) any later version.
+-#
+-# This program is distributed in the hope that it will be useful,
+-# but WITHOUT ANY WARRANTY; without even the implied warranty of
+-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-# GNU General Public License for more details.
+-#
+-# You should have received a copy of the GNU General Public License
+-# along with this program; if not, write to the Free Software
+-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+-# MA 02111-1307 USA
+-#
+-
+-include $(TOPDIR)/config.mk
+-
+-LIB = $(obj)lib$(BOARD).o
+-
+-COBJS := mini2440.o
+-
+-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+-OBJS := $(addprefix $(obj),$(COBJS))
+-SOBJS := $(addprefix $(obj),$(SOBJS))
+-
+-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+- $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+-
+-#########################################################################
+-
+-# defines $(obj).depend target
+-include $(SRCTREE)/rules.mk
+-
+-sinclude $(obj).depend
+-
+-#########################################################################
+diff --git a/board/friendlyarm/mini2440/mini2440.c b/board/friendlyarm/mini2440/mini2440.c
+deleted file mode 100644
+index e97d981..0000000
+--- a/board/friendlyarm/mini2440/mini2440.c
++++ /dev/null
+@@ -1,134 +0,0 @@
+-/*
+- * (C) Copyright 2002
+- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+- * Marius Groeger <mgroeger at sysgo.de>
+- *
+- * (C) Copyright 2002
+- * David Mueller, ELSOFT AG, <d.mueller at elsoft.ch>
+- *
+- * (C) Copyright 2009
+- * Michel Pollet <buserror at gmail.com>
+- *
+- * (C) Copyright 2012
+- * Gabriel Huau <contact at huau-gabriel.fr>
+- *
+- * See file CREDITS for list of people who contributed to this
+- * project.
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of
+- * the License, or (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+- * MA 02111-1307 USA
+- */
+-
+-#include <common.h>
+-#include <asm/arch/s3c2440.h>
+-#include <asm/arch/iomux.h>
+-#include <asm/arch/gpio.h>
+-#include <asm/io.h>
+-#include <asm/gpio.h>
+-#include <netdev.h>
+-#include "mini2440.h"
+-
+-DECLARE_GLOBAL_DATA_PTR;
+-
+-static inline void pll_delay(unsigned long loops)
+-{
+- __asm__ volatile ("1:\n"
+- "subs %0, %1, #1\n"
+- "bne 1b" : "=r" (loops) : "0" (loops));
+-}
+-
+-int board_early_init_f(void)
+-{
+- struct s3c24x0_clock_power * const clk_power =
+- s3c24x0_get_base_clock_power();
+-
+- /* to reduce PLL lock time, adjust the LOCKTIME register */
+- clk_power->locktime = 0xFFFFFF; /* Max PLL Lock time count */
+- clk_power->clkdivn = CLKDIVN_VAL;
+-
+- /* configure UPLL */
+- clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
+- /* some delay between MPLL and UPLL */
+- pll_delay(100);
+-
+- /* configure MPLL */
+- clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
+-
+- /* some delay between MPLL and UPLL */
+- pll_delay(10000);
+-
+- return 0;
+-}
+-
+-/*
+- * Miscellaneous platform dependent initialisations
+- */
+-int board_init(void)
+-{
+- struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
+-
+- /* IOMUX Port H : UART Configuration */
+- gpio->gphcon = IOMUXH_nCTS0 | IOMUXH_nRTS0 | IOMUXH_TXD0 | IOMUXH_RXD0 |
+- IOMUXH_TXD1 | IOMUXH_RXD1 | IOMUXH_TXD2 | IOMUXH_RXD2;
+-
+- gpio_direction_output(GPH8, 0);
+- gpio_direction_output(GPH9, 0);
+- gpio_direction_output(GPH10, 0);
+-
+- /* adress of boot parameters */
+- gd->bd->bi_boot_params = CONFIG_BOOT_PARAM_ADDR;
+-
+- return 0;
+-}
+-
+-int dram_init(void)
+-{
+- struct s3c24x0_memctl *memctl = s3c24x0_get_base_memctl();
+-
+- /*
+- * Configuring bus width and timing
+- * Initialize clocks for each bank 0..5
+- * Bank 3 and 4 are used for DM9000
+- */
+- writel(BANK_CONF, &memctl->bwscon);
+- writel(B0_CONF, &memctl->bankcon[0]);
+- writel(B1_CONF, &memctl->bankcon[1]);
+- writel(B2_CONF, &memctl->bankcon[2]);
+- writel(B3_CONF, &memctl->bankcon[3]);
+- writel(B4_CONF, &memctl->bankcon[4]);
+- writel(B5_CONF, &memctl->bankcon[5]);
+-
+- /* Bank 6 and 7 are used for DRAM */
+- writel(SDRAM_64MB, &memctl->bankcon[6]);
+- writel(SDRAM_64MB, &memctl->bankcon[7]);
+-
+- writel(MEM_TIMING, &memctl->refresh);
+- writel(BANKSIZE_CONF, &memctl->banksize);
+- writel(B6_MRSR, &memctl->mrsrb6);
+- writel(B7_MRSR, &memctl->mrsrb7);
+-
+- gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
+- PHYS_SDRAM_SIZE);
+- return 0;
+-}
+-
+-int board_eth_init(bd_t *bis)
+-{
+-#ifdef CONFIG_DRIVER_DM9000
+- return dm9000_initialize(bis);
+-#else
+- return 0;
+-#endif
+-}
+diff --git a/board/friendlyarm/mini2440/mini2440.h b/board/friendlyarm/mini2440/mini2440.h
+deleted file mode 100644
+index db386ea..0000000
+--- a/board/friendlyarm/mini2440/mini2440.h
++++ /dev/null
+@@ -1,144 +0,0 @@
+-#ifndef __MINI2440_BOARD_CONF_H__
+-#define __MINI2440_BOARD_CONF_H__
+-
+-/* PLL Parameters */
+-#define CLKDIVN_VAL 7
+-#define M_MDIV 0x7f
+-#define M_PDIV 0x2
+-#define M_SDIV 0x1
+-
+-#define U_M_MDIV 0x38
+-#define U_M_PDIV 0x2
+-#define U_M_SDIV 0x2
+-
+-/* BWSCON */
+-#define DW8 0x0
+-#define DW16 0x1
+-#define DW32 0x2
+-#define WAIT (0x1<<2)
+-#define UBLB (0x1<<3)
+-
+-#define B1_BWSCON (DW32)
+-#define B2_BWSCON (DW16)
+-#define B3_BWSCON (DW16 + WAIT + UBLB)
+-#define B4_BWSCON (DW16 + WAIT + UBLB)
+-#define B5_BWSCON (DW16)
+-#define B6_BWSCON (DW32)
+-#define B7_BWSCON (DW32)
+-
+-/*
+- * Bank Configuration
+- */
+-#define B0_Tacs 0x0 /* 0clk */
+-#define B0_Tcos 0x0 /* 0clk */
+-#define B0_Tacc 0x7 /* 14clk */
+-#define B0_Tcoh 0x0 /* 0clk */
+-#define B0_Tah 0x0 /* 0clk */
+-#define B0_Tacp 0x0 /* 0clk */
+-#define B0_PMC 0x0 /* normal */
+-
+-#define B1_Tacs 0x0
+-#define B1_Tcos 0x0
+-#define B1_Tacc 0x7
+-#define B1_Tcoh 0x0
+-#define B1_Tah 0x0
+-#define B1_Tacp 0x0
+-#define B1_PMC 0x0
+-
+-#define B2_Tacs 0x0
+-#define B2_Tcos 0x0
+-#define B2_Tacc 0x7
+-#define B2_Tcoh 0x0
+-#define B2_Tah 0x0
+-#define B2_Tacp 0x0
+-#define B2_PMC 0x0
+-
+-#define B3_Tacs 0x0
+-#define B3_Tcos 0x3 /* 4clk */
+-#define B3_Tacc 0x7
+-#define B3_Tcoh 0x1 /* 1clk */
+-#define B3_Tah 0x3 /* 4clk */
+-#define B3_Tacp 0x0
+-#define B3_PMC 0x0
+-
+-#define B4_Tacs 0x0
+-#define B4_Tcos 0x3
+-#define B4_Tacc 0x7
+-#define B4_Tcoh 0x1
+-#define B4_Tah 0x3
+-#define B4_Tacp 0x0
+-#define B4_PMC 0x0
+-
+-#define B5_Tacs 0x0
+-#define B5_Tcos 0x0
+-#define B5_Tacc 0x7
+-#define B5_Tcoh 0x0
+-#define B5_Tah 0x0
+-#define B5_Tacp 0x0
+-#define B5_PMC 0x0
+-
+-/*
+- * SDRAM Configuration
+- */
+-#define SDRAM_MT 0x3 /* SDRAM */
+-#define SDRAM_Trcd 0x0 /* 2clk */
+-#define SDRAM_SCAN_9 0x1 /* 9bit */
+-#define SDRAM_SCAN_10 0x2 /* 10bit */
+-
+-#define SDRAM_64MB ((SDRAM_MT<<15) + (SDRAM_Trcd<<2) + (SDRAM_SCAN_9))
+-
+-/*
+- * Refresh Parameter
+- */
+-#define REFEN 0x1 /* Refresh enable */
+-#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
+-#define Trp 0x1 /* 3clk */
+-#define Trc 0x3 /* 7clk */
+-#define Tchr 0x0 /* unused */
+-#define REFCNT 1012 /* period=10.37us, HCLK=100Mhz, (2048 + 1-10.37*100) */
+-
+-/*
+- * MRSR Parameter
+- */
+-#define BL 0x0
+-#define BT 0x0
+-#define CL 0x3 /* 3 clocks */
+-#define TM 0x0
+-#define WBL 0x0
+-
+-/*
+- * BankSize Parameter
+- */
+-#define BK76MAP 0x2 /* 128MB/128MB */
+-#define SCLK_EN 0x1 /* SCLK active */
+-#define SCKE_EN 0x1 /* SDRAM power down mode enable */
+-#define BURST_EN 0x1 /* Burst enable */
+-
+-/*
+- * Register values
+- */
+-#define BANK_CONF ((0 + (B1_BWSCON<<4) + (B2_BWSCON<<8) + (B3_BWSCON<<12) + \
+- (B4_BWSCON<<16) + (B5_BWSCON<<20) + (B6_BWSCON<<24) + \
+- (B7_BWSCON<<28)))
+-
+-#define B0_CONF ((B0_Tacs<<13) + (B0_Tcos<<11) + (B0_Tacc<<8) + \
+- (B0_Tcoh<<6) + (B0_Tah<<4) + (B0_Tacp<<2) + (B0_PMC))
+-#define B1_CONF ((B1_Tacs<<13) + (B1_Tcos<<11) + (B1_Tacc<<8) + \
+- (B1_Tcoh<<6) + (B1_Tah<<4) + (B1_Tacp<<2) + (B1_PMC))
+-#define B2_CONF ((B2_Tacs<<13) + (B2_Tcos<<11) + (B2_Tacc<<8) + \
+- (B2_Tcoh<<6) + (B2_Tah<<4) + (B2_Tacp<<2) + (B2_PMC))
+-#define B3_CONF ((B3_Tacs<<13) + (B3_Tcos<<11) + (B3_Tacc<<8) + \
+- (B3_Tcoh<<6) + (B3_Tah<<4) + (B3_Tacp<<2) + (B3_PMC))
+-#define B4_CONF ((B4_Tacs<<13) + (B4_Tcos<<11) + (B4_Tacc<<8) + \
+- (B4_Tcoh<<6) + (B4_Tah<<4) + (B4_Tacp<<2) + (B4_PMC))
+-#define B5_CONF ((B5_Tacs<<13) + (B5_Tcos<<11) + (B5_Tacc<<8) + \
+- (B5_Tcoh<<6) + (B5_Tah<<4) + (B5_Tacp<<2) + (B5_PMC))
+-
+-#define MEM_TIMING (REFEN<<23) + (TREFMD<<22) + (Trp<<20) + \
+- (Trc<<18) + (Tchr<<16) + REFCNT
+-
+-#define BANKSIZE_CONF (BK76MAP) + (SCLK_EN<<4) + (SCKE_EN<<5) + (BURST_EN<<7)
+-#define B6_MRSR (CL<<4)
+-#define B7_MRSR (CL<<4)
+-
+-#endif
+diff --git a/board/genesi/mx51_efikamx/efikamx.c b/board/genesi/mx51_efikamx/efikamx.c
+index cfd2e93..f7c87b5 100644
+--- a/board/genesi/mx51_efikamx/efikamx.c
++++ b/board/genesi/mx51_efikamx/efikamx.c
+@@ -93,7 +93,7 @@ static u32 get_mx_rev(void)
+ return (~rev & 0x7) + 1;
+ }
+
+-static iomux_v3_cfg_t efikasb_revision_pads[] = {
++static iomux_v3_cfg_t const efikasb_revision_pads[] = {
+ MX51_PAD_EIM_CS3__GPIO2_28,
+ MX51_PAD_EIM_CS4__GPIO2_29,
+ };
+@@ -140,7 +140,7 @@ int dram_init(void)
+ /*
+ * UART configuration
+ */
+-static iomux_v3_cfg_t efikamx_uart_pads[] = {
++static iomux_v3_cfg_t const efikamx_uart_pads[] = {
+ MX51_PAD_UART1_RXD__UART1_RXD,
+ MX51_PAD_UART1_TXD__UART1_TXD,
+ MX51_PAD_UART1_RTS__UART1_RTS,
+@@ -150,7 +150,7 @@ static iomux_v3_cfg_t efikamx_uart_pads[] = {
+ /*
+ * SPI configuration
+ */
+-static iomux_v3_cfg_t efikamx_spi_pads[] = {
++static iomux_v3_cfg_t const efikamx_spi_pads[] = {
+ MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
+ MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
+ MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
+@@ -272,7 +272,7 @@ struct fsl_esdhc_cfg esdhc_cfg[2] = {
+ {MMC_SDHC2_BASE_ADDR},
+ };
+
+-static iomux_v3_cfg_t efikamx_sdhc1_pads[] = {
++static iomux_v3_cfg_t const efikamx_sdhc1_pads[] = {
+ MX51_PAD_SD1_CMD__SD1_CMD,
+ MX51_PAD_SD1_CLK__SD1_CLK,
+ MX51_PAD_SD1_DATA0__SD1_DATA0,
+@@ -284,7 +284,7 @@ static iomux_v3_cfg_t efikamx_sdhc1_pads[] = {
+
+ #define EFIKAMX_SDHC1_WP IMX_GPIO_NR(1, 1)
+
+-static iomux_v3_cfg_t efikamx_sdhc1_cd_pads[] = {
++static iomux_v3_cfg_t const efikamx_sdhc1_cd_pads[] = {
+ MX51_PAD_GPIO1_0__SD1_CD,
+ MX51_PAD_EIM_CS2__SD1_CD,
+ };
+@@ -292,7 +292,7 @@ static iomux_v3_cfg_t efikamx_sdhc1_cd_pads[] = {
+ #define EFIKAMX_SDHC1_CD IMX_GPIO_NR(1, 0)
+ #define EFIKASB_SDHC1_CD IMX_GPIO_NR(2, 27)
+
+-static iomux_v3_cfg_t efikasb_sdhc2_pads[] = {
++static iomux_v3_cfg_t const efikasb_sdhc2_pads[] = {
+ MX51_PAD_SD2_CMD__SD2_CMD,
+ MX51_PAD_SD2_CLK__SD2_CLK,
+ MX51_PAD_SD2_DATA0__SD2_DATA0,
+@@ -368,7 +368,7 @@ int board_mmc_init(bd_t *bis)
+ /*
+ * PATA
+ */
+-static iomux_v3_cfg_t efikamx_pata_pads[] = {
++static iomux_v3_cfg_t const efikamx_pata_pads[] = {
+ MX51_PAD_NANDF_WE_B__PATA_DIOW,
+ MX51_PAD_NANDF_RE_B__PATA_DIOR,
+ MX51_PAD_NANDF_ALE__PATA_BUFFER_EN,
+@@ -419,7 +419,7 @@ static inline void setup_iomux_usb(void) { }
+ #define EFIKAMX_LED_GREEN IMX_GPIO_NR(3, 14)
+ #define EFIKAMX_LED_RED IMX_GPIO_NR(3, 15)
+
+-static iomux_v3_cfg_t efikasb_led_pads[] = {
++static iomux_v3_cfg_t const efikasb_led_pads[] = {
+ MX51_PAD_GPIO1_3__GPIO1_3,
+ MX51_PAD_EIM_CS0__GPIO2_25,
+ };
+diff --git a/board/hale/tt01/tt01.c b/board/hale/tt01/tt01.c
+index 02e75ed..143fcef 100644
+--- a/board/hale/tt01/tt01.c
++++ b/board/hale/tt01/tt01.c
+@@ -52,7 +52,7 @@ static void board_setup_clocks(void)
+ writel((CCM_CCMR_SETUP | CCMR_MPE) & ~CCMR_MDS, &ccm->ccmr);
+
+ /* Set up clock to 532MHz */
+- writel(PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) |
++ writel(PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) |
+ PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) |
+ PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) |
+ PDR0_MCU_PODF(0), &ccm->pdr0);
+diff --git a/board/imx31_phycore/lowlevel_init.S b/board/imx31_phycore/lowlevel_init.S
+index c47137d..4dd78b6 100644
+--- a/board/imx31_phycore/lowlevel_init.S
++++ b/board/imx31_phycore/lowlevel_init.S
+@@ -54,7 +54,7 @@ lowlevel_init:
+ REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE
+ REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
+
+- REG CCM_PDR0, PDR0_CSI_PODF(0xff1) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0)
++ REG CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0)
+
+ REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0xe) | PLL_MFI(9) | PLL_MFN(0xd)
+
+diff --git a/board/iomega/iconnect/Makefile b/board/iomega/iconnect/Makefile
+deleted file mode 100644
+index f77fcfb..0000000
+--- a/board/iomega/iconnect/Makefile
++++ /dev/null
+@@ -1,43 +0,0 @@
+-#
+-# (C) Copyright 2009
+-# Marvell Semiconductor <www.marvell.com>
+-# Written-by: Prafulla Wadaskar <prafulla at marvell.com>
+-#
+-# See file CREDITS for list of people who contributed to this
+-# project.
+-#
+-# This program is free software; you can redistribute it and/or
+-# modify it under the terms of the GNU General Public License as
+-# published by the Free Software Foundation; either version 2 of
+-# the License, or (at your option) any later version.
+-#
+-# This program is distributed in the hope that it will be useful,
+-# but WITHOUT ANY WARRANTY; without even the implied warranty of
+-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-# GNU General Public License for more details.
+-#
+-# You should have received a copy of the GNU General Public License
+-# along with this program. If not, see <http://www.gnu.org/licenses/>.
+-#
+-
+-include $(TOPDIR)/config.mk
+-
+-LIB = $(obj)lib$(BOARD).o
+-
+-COBJS := iconnect.o
+-
+-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+-OBJS := $(addprefix $(obj),$(COBJS))
+-SOBJS := $(addprefix $(obj),$(SOBJS))
+-
+-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+- $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+-
+-#########################################################################
+-
+-# defines $(obj).depend target
+-include $(SRCTREE)/rules.mk
+-
+-sinclude $(obj).depend
+-
+-#########################################################################
+diff --git a/board/iomega/iconnect/iconnect.c b/board/iomega/iconnect/iconnect.c
+deleted file mode 100644
+index 6ee2128..0000000
+--- a/board/iomega/iconnect/iconnect.c
++++ /dev/null
+@@ -1,107 +0,0 @@
+-/*
+- * Copyright (C) 2009-2012
+- * Wojciech Dubowik <wojciech.dubowik at neratec.com>
+- * Luka Perkov <uboot at lukaperkov.net>
+- *
+- * See file CREDITS for list of people who contributed to this
+- * project.
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of
+- * the License, or (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+- */
+-
+-#include <common.h>
+-#include <miiphy.h>
+-#include <asm/arch/cpu.h>
+-#include <asm/arch/kirkwood.h>
+-#include <asm/arch/mpp.h>
+-#include "iconnect.h"
+-
+-DECLARE_GLOBAL_DATA_PTR;
+-
+-int board_early_init_f(void)
+-{
+- /*
+- * default gpio configuration
+- * There are maximum 64 gpios controlled through 2 sets of registers
+- * the below configuration configures mainly initial LED status
+- */
+- kw_config_gpio(ICONNECT_OE_VAL_LOW,
+- ICONNECT_OE_VAL_HIGH,
+- ICONNECT_OE_LOW, ICONNECT_OE_HIGH);
+-
+- /* Multi-Purpose Pins Functionality configuration */
+- u32 kwmpp_config[] = {
+- MPP0_NF_IO2,
+- MPP1_NF_IO3,
+- MPP2_NF_IO4,
+- MPP3_NF_IO5,
+- MPP4_NF_IO6,
+- MPP5_NF_IO7,
+- MPP6_SYSRST_OUTn, /* Reset signal */
+- MPP7_GPO,
+- MPP8_TW_SDA, /* I2C */
+- MPP9_TW_SCK, /* I2C */
+- MPP10_UART0_TXD,
+- MPP11_UART0_RXD,
+- MPP12_GPO, /* Reset button */
+- MPP13_SD_CMD,
+- MPP14_SD_D0,
+- MPP15_SD_D1,
+- MPP16_SD_D2,
+- MPP17_SD_D3,
+- MPP18_NF_IO0,
+- MPP19_NF_IO1,
+- MPP20_GE1_0,
+- MPP21_GE1_1,
+- MPP22_GE1_2,
+- MPP23_GE1_3,
+- MPP24_GE1_4,
+- MPP25_GE1_5,
+- MPP26_GE1_6,
+- MPP27_GE1_7,
+- MPP28_GPIO,
+- MPP29_GPIO,
+- MPP30_GE1_10,
+- MPP31_GE1_11,
+- MPP32_GE1_12,
+- MPP33_GE1_13,
+- MPP34_GE1_14,
+- MPP35_GPIO, /* OTB button */
+- MPP36_AUDIO_SPDIFI,
+- MPP37_AUDIO_SPDIFO,
+- MPP38_GPIO,
+- MPP39_TDM_SPI_CS0,
+- MPP40_TDM_SPI_SCK,
+- MPP41_GPIO, /* LED brightness */
+- MPP42_GPIO, /* LED power (blue) */
+- MPP43_GPIO, /* LED power (red) */
+- MPP44_GPIO, /* LED USB 1 */
+- MPP45_GPIO, /* LED USB 2 */
+- MPP46_GPIO, /* LED USB 3 */
+- MPP47_GPIO, /* LED USB 4 */
+- MPP48_GPIO, /* LED OTB */
+- MPP49_GPIO,
+- 0
+- };
+- kirkwood_mpp_conf(kwmpp_config, NULL);
+- return 0;
+-}
+-
+-int board_init(void)
+-{
+- /* adress of boot parameters */
+- gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+-
+- return 0;
+-}
+diff --git a/board/iomega/iconnect/iconnect.h b/board/iomega/iconnect/iconnect.h
+deleted file mode 100644
+index 2fb3e5e..0000000
+--- a/board/iomega/iconnect/iconnect.h
++++ /dev/null
+@@ -1,39 +0,0 @@
+-/*
+- * Copyright (C) 2009-2012
+- * Wojciech Dubowik <wojciech.dubowik at neratec.com>
+- * Luka Perkov <uboot at lukaperkov.net>
+- *
+- * See file CREDITS for list of people who contributed to this
+- * project.
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of
+- * the License, or (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+- */
+-
+-#ifndef __ICONNECT_H
+-#define __ICONNECT_H
+-
+-#define ICONNECT_OE_LOW (~(1 << 7))
+-#define ICONNECT_OE_HIGH (~(1 << 10))
+-#define ICONNECT_OE_VAL_LOW (0)
+-#define ICONNECT_OE_VAL_HIGH (1 << 10)
+-
+-/* PHY related */
+-#define MV88E1116_LED_FCTRL_REG 10
+-#define MV88E1116_CPRSP_CR3_REG 21
+-#define MV88E1116_MAC_CTRL_REG 21
+-#define MV88E1116_PGADR_REG 22
+-#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
+-#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
+-
+-#endif /* __ICONNECT_H */
+diff --git a/board/iomega/iconnect/kwbimage.cfg b/board/iomega/iconnect/kwbimage.cfg
+deleted file mode 100644
+index 6c9dfe3..0000000
+--- a/board/iomega/iconnect/kwbimage.cfg
++++ /dev/null
+@@ -1,165 +0,0 @@
+-#
+-# (C) Copyright 2009-2012
+-# Wojciech Dubowik <wojciech.dubowik at neratec.com>
+-# Luka Perkov <uboot at lukaperkov.net>
+-#
+-# See file CREDITS for list of people who contributed to this
+-# project.
+-#
+-# This program is free software; you can redistribute it and/or
+-# modify it under the terms of the GNU General Public License as
+-# published by the Free Software Foundation; either version 2 of
+-# the License, or (at your option) any later version.
+-#
+-# This program is distributed in the hope that it will be useful,
+-# but WITHOUT ANY WARRANTY; without even the implied warranty of
+-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-# GNU General Public License for more details.
+-#
+-# You should have received a copy of the GNU General Public License
+-# along with this program. If not, see <http://www.gnu.org/licenses/>.
+-#
+-# Refer docs/README.kwimage for more details about how-to configure
+-# and create kirkwood boot image
+-#
+-
+-# Boot Media configurations
+-BOOT_FROM nand
+-NAND_ECC_MODE default
+-NAND_PAGE_SIZE 0x0800
+-
+-# SOC registers configuration using bootrom header extension
+-# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+-
+-# Configure RGMII-0 interface pad voltage to 1.8V
+-DATA 0xffd100e0 0x1b1b1b9b
+-
+-#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+-DATA 0xffd01400 0x43000c30 # DDR Configuration register
+-# bit13-0: 0xc30, (3120 DDR2 clks refresh rate)
+-# bit23-14: 0x0,
+-# bit24: 0x1, enable exit self refresh mode on DDR access
+-# bit25: 0x1, required
+-# bit29-26: 0x0,
+-# bit31-30: 0x1,
+-
+-DATA 0xffd01404 0x37543000 # DDR Controller Control Low
+-# bit4: 0x0, addr/cmd in smame cycle
+-# bit5: 0x0, clk is driven during self refresh, we don't care for APX
+-# bit6: 0x0, use recommended falling edge of clk for addr/cmd
+-# bit14: 0x0, input buffer always powered up
+-# bit18: 0x1, cpu lock transaction enabled
+-# bit23-20: 0x5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+-# bit27-24: 0x7, CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+-# bit30-28: 0x3, required
+-# bit31: 0x0, no additional STARTBURST delay
+-
+-DATA 0xffd01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
+-# bit3-0: TRAS lsbs
+-# bit7-4: TRCD
+-# bit11-8: TRP
+-# bit15-12: TWR
+-# bit19-16: TWTR
+-# bit20: TRAS msb
+-# bit23-21: 0x0
+-# bit27-24: TRRD
+-# bit31-28: TRTP
+-
+-DATA 0xffd0140c 0x00000a33 # DDR Timing (High)
+-# bit6-0: TRFC
+-# bit8-7: TR2R
+-# bit10-9: TR2W
+-# bit12-11: TW2W
+-# bit31-13: 0x0, required
+-
+-DATA 0xffd01410 0x000000cc # DDR Address Control
+-# bit1-0: 00, Cs0width (x8)
+-# bit3-2: 11, Cs0size (1Gb)
+-# bit5-4: 00, Cs1width (x8)
+-# bit7-6: 11, Cs1size (1Gb)
+-# bit9-8: 00, Cs2width (nonexistent)
+-# bit11-10: 00, Cs2size (nonexistent)
+-# bit13-12: 00, Cs3width (nonexistent)
+-# bit15-14: 00, Cs3size (nonexistent)
+-# bit16: 0, Cs0AddrSel
+-# bit17: 0, Cs1AddrSel
+-# bit18: 0, Cs2AddrSel
+-# bit19: 0, Cs3AddrSel
+-# bit31-20: 0x0, required
+-
+-DATA 0xffd01414 0x00000000 # DDR Open Pages Control
+-# bit0: 0, OpenPage enabled
+-# bit31-1: 0x0, required
+-
+-DATA 0xffd01418 0x00000000 # DDR Operation
+-# bit3-0: 0x0, DDR cmd
+-# bit31-4: 0x0, required
+-
+-DATA 0xffd0141c 0x00000c52 # DDR Mode
+-# bit2-0: 0x2, BurstLen=2 required
+-# bit3: 0x0, BurstType=0 required
+-# bit6-4: 0x4, CL=5
+-# bit7: 0x0, TestMode=0 normal
+-# bit8: 0x0, DLL reset=0 normal
+-# bit11-9: 0x6, auto-precharge write recovery ????????????
+-# bit12: 0x0, PD must be zero
+-# bit31-13: 0x0, required
+-
+-DATA 0xffd01420 0x00000040 # DDR Extended Mode
+-# bit0: 0, DDR DLL enabled
+-# bit1: 0, DDR drive strenght normal
+-# bit2: 0, DDR ODT control lsd (disabled)
+-# bit5-3: 0x0, required
+-# bit6: 1, DDR ODT control msb, (disabled)
+-# bit9-7: 0x0, required
+-# bit10: 0, differential DQS enabled
+-# bit11: 0, required
+-# bit12: 0, DDR output buffer enabled
+-# bit31-13: 0x0, required
+-
+-DATA 0xffd01424 0x0000f17f # DDR Controller Control High
+-# bit2-0: 0x7, required
+-# bit3: 0x1, MBUS Burst Chop disabled
+-# bit6-4: 0x7, required
+-# bit7: 0x0,
+-# bit8: 0x1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
+-# bit9: 0x0, no half clock cycle addition to dataout
+-# bit10: 0x0, 1/4 clock cycle skew enabled for addr/ctl signals
+-# bit11: 0x0, 1/4 clock cycle skew disabled for write mesh
+-# bit15-12: 0xf, required
+-# bit31-16: 0x0, required
+-
+-DATA 0xffd01428 0x00085520 # DDR2 ODT Read Timing (default values)
+-DATA 0xffd0147c 0x00008552 # DDR2 ODT Write Timing (default values)
+-
+-DATA 0xffd01500 0x00000000 # CS[0]n Base address to 0x0
+-DATA 0xffd01504 0x0ffffff1 # CS[0]n Size
+-# bit0: 0x1, Window enabled
+-# bit1: 0x0, Write Protect disabled
+-# bit3-2: 0x0, CS0 hit selected
+-# bit23-4: 0xfffff, required
+-# bit31-24: 0x0f, Size (i.e. 256MB)
+-
+-DATA 0xffd01508 0x00000000 # CS[1]n Base address to 256Mb
+-DATA 0xffd0150c 0x00000000 # CS[1]n Size, window disabled
+-
+-DATA 0xffd01514 0x00000000 # CS[2]n Size, window disabled
+-DATA 0xffd0151c 0x00000000 # CS[3]n Size, window disabled
+-
+-DATA 0xffd01494 0x00030000 # DDR ODT Control (Low)
+-# bit3-0: ODT0Rd, MODT[0] asserted during read from DRAM CS1
+-# bit7-4: ODT0Rd, MODT[0] asserted during read from DRAM CS0
+-# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1
+-# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+-
+-DATA 0xffd01498 0x00000000 # DDR ODT Control (High)
+-# bit1-0: 0x0, ODT0 controlled by ODT Control (low) register above
+-# bit3-2: 0x1, ODT1 active NEVER!
+-# bit31-4: 0x0, required
+-
+-DATA 0xffd0149c 0x0000e803 # CPU ODT Control
+-DATA 0xffd01480 0x00000001 # DDR Initialization Control
+-# bit0: 0x1, enable DDR init upon this register write
+-
+-# End of Header extension
+-DATA 0x0 0x0
+diff --git a/board/karo/tx25/lowlevel_init.S b/board/karo/tx25/lowlevel_init.S
+index eb3f187..3e46ed9 100644
+--- a/board/karo/tx25/lowlevel_init.S
++++ b/board/karo/tx25/lowlevel_init.S
+@@ -22,37 +22,7 @@
+ */
+
+ #include <asm/macro.h>
+-
+-.macro init_aips
+- write32 0x43f00000, 0x77777777
+- write32 0x43f00004, 0x77777777
+- write32 0x43f00000, 0x77777777
+- write32 0x53f00004, 0x77777777
+-.endm
+-
+-.macro init_max
+- write32 0x43f04000, 0x43210
+- write32 0x43f04100, 0x43210
+- write32 0x43f04200, 0x43210
+- write32 0x43f04300, 0x43210
+- write32 0x43f04400, 0x43210
+-
+- write32 0x43f04010, 0x10
+- write32 0x43f04110, 0x10
+- write32 0x43f04210, 0x10
+- write32 0x43f04310, 0x10
+- write32 0x43f04410, 0x10
+-
+- write32 0x43f04800, 0x0
+- write32 0x43f04900, 0x0
+- write32 0x43f04a00, 0x0
+- write32 0x43f04b00, 0x0
+- write32 0x43f04c00, 0x0
+-.endm
+-
+-.macro init_m3if
+- write32 0xb8003000, 0x1
+-.endm
++#include <asm/arch/macro.h>
+
+ .macro init_clocks
+ /*
+@@ -64,6 +34,8 @@
+ * 0x00600000 makes CLKO parent clk the USB clk
+ */
+ write32 0x53f80064, 0x45600000
++
++ /* CCTL: ARM = 399 MHz, AHB = 133 MHz */
+ write32 0x53f80008, 0x20034000
+
+ /*
+diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
+index 0c4dddc..be8f51c 100644
+--- a/board/keymile/km_arm/km_arm.c
++++ b/board/keymile/km_arm/km_arm.c
+@@ -250,8 +250,7 @@ int board_early_init_f(void)
+ tmp = readl(KW_GPIO0_BASE + 4);
+ writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , KW_GPIO0_BASE + 4);
+ #endif
+- /* adjust SDRAM size for bank 0 */
+- kw_sdram_size_adjust(0);
++
+ kirkwood_mpp_conf(kwmpp_config, NULL);
+ return 0;
+ }
+@@ -366,71 +365,6 @@ void reset_phy(void)
+ /* reset the phy */
+ miiphy_reset(name, CONFIG_PHY_BASE_ADR);
+ }
+-#elif defined(CONFIG_KM_PIGGY4_88E6352)
+-
+-#include <mv88e6352.h>
+-
+-#if defined(CONFIG_KM_NUSA)
+-struct mv88e_sw_reg extsw_conf[] = {
+- /*
+- * port 0, PIGGY4, autoneg
+- * first the fix for the 1000Mbits Autoneg, this is from
+- * a Marvell errata, the regs are undocumented
+- */
+- { PHY(0), PHY_PAGE, AN1000FIX_PAGE },
+- { PHY(0), PHY_STATUS, AN1000FIX },
+- { PHY(0), PHY_PAGE, 0 },
+- /* now the real port and phy configuration */
+- { PORT(0), PORT_PHY, NO_SPEED_FOR },
+- { PORT(0), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
+- { PHY(0), PHY_1000_CTRL, NO_ADV },
+- { PHY(0), PHY_SPEC_CTRL, AUTO_MDIX_EN },
+- { PHY(0), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST |
+- FULL_DUPLEX },
+- /* port 1, unused */
+- { PORT(1), PORT_CTRL, PORT_DIS },
+- { PHY(1), PHY_CTRL, PHY_PWR_DOWN },
+- { PHY(1), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
+- /* port 2, unused */
+- { PORT(2), PORT_CTRL, PORT_DIS },
+- { PHY(2), PHY_CTRL, PHY_PWR_DOWN },
+- { PHY(2), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
+- /* port 3, unused */
+- { PORT(3), PORT_CTRL, PORT_DIS },
+- { PHY(3), PHY_CTRL, PHY_PWR_DOWN },
+- { PHY(3), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
+- /* port 4, ICNEV, SerDes, SGMII */
+- { PORT(4), PORT_STATUS, NO_PHY_DETECT },
+- { PORT(4), PORT_PHY, SPEED_1000_FOR },
+- { PORT(4), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
+- { PHY(4), PHY_CTRL, PHY_PWR_DOWN },
+- { PHY(4), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
+- /* port 5, CPU_RGMII */
+- { PORT(5), PORT_PHY, RX_RGMII_TIM | TX_RGMII_TIM | FLOW_CTRL_EN |
+- FLOW_CTRL_FOR | LINK_VAL | LINK_FOR | FULL_DPX |
+- FULL_DPX_FOR | SPEED_1000_FOR },
+- { PORT(5), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
+- /* port 6, unused, this port has no phy */
+- { PORT(6), PORT_CTRL, PORT_DIS },
+-};
+-#else
+-struct mv88e_sw_reg extsw_conf[] = {};
+-#endif
+-
+-void reset_phy(void)
+-{
+-#if defined(CONFIG_KM_MVEXTSW_ADDR)
+- char *name = "egiga0";
+-
+- if (miiphy_set_current_dev(name))
+- return;
+-
+- mv88e_sw_program(name, CONFIG_KM_MVEXTSW_ADDR, extsw_conf,
+- ARRAY_SIZE(extsw_conf));
+- mv88e_sw_reset(name, CONFIG_KM_MVEXTSW_ADDR);
+-#endif
+-}
+-
+ #else
+ /* Configure and enable MV88E1118 PHY on the piggy*/
+ void reset_phy(void)
+diff --git a/board/kmc/kzm9g/Makefile b/board/kmc/kzm9g/Makefile
+deleted file mode 100644
+index bae79f5..0000000
+--- a/board/kmc/kzm9g/Makefile
++++ /dev/null
+@@ -1,50 +0,0 @@
+-#
+-# (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj at renesas.com>
+-# (C) Copyright 2012 Renesas Solutions Corp.
+-#
+-# See file CREDITS for list of people who contributed to this
+-# project.
+-#
+-# This program is free software; you can redistribute it and/or
+-# modify it under the terms of the GNU General Public License as
+-# published by the Free Software Foundation; either version 2 of
+-# the License, or (at your option) any later version.
+-#
+-# This program is distributed in the hope that it will be useful,
+-# but WITHOUT ANY WARRANTY; without even the implied warranty of
+-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-# GNU General Public License for more details.
+-#
+-# You should have received a copy of the GNU General Public License
+-# along with this program; if not, write to the Free Software
+-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+-# MA 02111-1307 USA
+-#
+-
+-include $(TOPDIR)/config.mk
+-
+-LIB = $(obj)lib$(BOARD).o
+-
+-COBJS := kzm9g.o
+-
+-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+-OBJS := $(addprefix $(obj),$(COBJS))
+-SOBJS := $(addprefix $(obj),$(SOBJS))
+-
+-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+- $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+-
+-clean:
+- rm -f $(SOBJS) $(OBJS)
+-
+-distclean: clean
+- rm -f $(LIB) core *.bak $(obj) .depend
+-
+-#########################################################################
+-
+-# defines $(obj).depend target
+-include $(SRCTREE)/rules.mk
+-
+-sinclude $(obj).depend
+-
+-#########################################################################
+diff --git a/board/kmc/kzm9g/kzm9g.c b/board/kmc/kzm9g/kzm9g.c
+deleted file mode 100644
+index 525c97a..0000000
+--- a/board/kmc/kzm9g/kzm9g.c
++++ /dev/null
+@@ -1,377 +0,0 @@
+-/*
+- * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj at renesas.com>
+- * (C) Copyright 2012 Renesas Solutions Corp.
+- *
+- * See file CREDITS for list of people who contributed to this
+- * project.
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of
+- * the License, or (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+- * MA 02111-1307 USA
+- */
+-
+-#include <common.h>
+-#include <asm/io.h>
+-#include <asm/arch/sys_proto.h>
+-#include <asm/gpio.h>
+-#include <netdev.h>
+-#include <i2c.h>
+-
+-DECLARE_GLOBAL_DATA_PTR;
+-
+-#define CS0BCR_D (0x06C00400)
+-#define CS4BCR_D (0x16c90400)
+-#define CS0WCR_D (0x55062C42)
+-#define CS4WCR_D (0x1e071dc3)
+-
+-#define CMNCR_BROMMD0 (1 << 21)
+-#define CMNCR_BROMMD1 (1 << 22)
+-#define CMNCR_BROMMD (CMNCR_BROMMD0|CMNCR_BROMMD1)
+-#define VCLKCR1_D (0x27)
+-
+-#define SMSTPCR1_CMT0 (1 << 24)
+-#define SMSTPCR1_I2C0 (1 << 16)
+-#define SMSTPCR3_USB (1 << 22)
+-
+-#define PORT32CR (0xE6051020)
+-#define PORT33CR (0xE6051021)
+-#define PORT34CR (0xE6051022)
+-#define PORT35CR (0xE6051023)
+-
+-static int cmp_loop(u32 *addr, u32 data, u32 cmp)
+-{
+- int err = -1;
+- int timeout = 100;
+- u32 value;
+-
+- while (timeout > 0) {
+- value = readl(addr);
+- if ((value & data) == cmp) {
+- err = 0;
+- break;
+- }
+- timeout--;
+- }
+-
+- return err;
+-}
+-
+-/* SBSC Init function */
+-static void sbsc_init(struct sh73a0_sbsc *sbsc)
+-{
+- writel(readl(&sbsc->dllcnt0)|0x2, &sbsc->dllcnt0);
+- writel(0x5, &sbsc->sdgencnt);
+- cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0);
+-
+- writel(0xacc90159, &sbsc->sdcr0);
+- writel(0x00010059, &sbsc->sdcr1);
+- writel(0x50874114, &sbsc->sdwcrc0);
+- writel(0x33199b37, &sbsc->sdwcrc1);
+- writel(0x008f2313, &sbsc->sdwcrc2);
+- writel(0x31020707, &sbsc->sdwcr00);
+- writel(0x0017040a, &sbsc->sdwcr01);
+- writel(0x31020707, &sbsc->sdwcr10);
+- writel(0x0017040a, &sbsc->sdwcr11);
+- writel(0x05555555, &sbsc->sddrvcr0);
+- writel(0x30000000, &sbsc->sdwcr2);
+-
+- writel(readl(&sbsc->sdpcr) | 0x80, &sbsc->sdpcr);
+- cmp_loop(&sbsc->sdpcr, 0x80, 0x80);
+-
+- writel(0x00002710, &sbsc->sdgencnt);
+- cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0);
+-
+- writel(0x0000003f, &sbsc->sdmracr0);
+- writel(0x0, SDMRA1A);
+- writel(0x000001f4, &sbsc->sdgencnt);
+- cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0);
+-
+- writel(0x0000ff0a, &sbsc->sdmracr0);
+- if (sbsc == (struct sh73a0_sbsc *)SBSC1_BASE)
+- writel(0x0, SDMRA3A);
+- else
+- writel(0x0, SDMRA3B);
+-
+- writel(0x00000032, &sbsc->sdgencnt);
+- cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0);
+-
+- if (sbsc == (struct sh73a0_sbsc *)SBSC1_BASE) {
+- writel(0x00002201, &sbsc->sdmracr0);
+- writel(0x0, SDMRA1A);
+- writel(0x00000402, &sbsc->sdmracr0);
+- writel(0x0, SDMRA1A);
+- writel(0x00000403, &sbsc->sdmracr0);
+- writel(0x0, SDMRA1A);
+- writel(0x0, SDMRA2A);
+- } else {
+- writel(0x00002201, &sbsc->sdmracr0);
+- writel(0x0, SDMRA1B);
+- writel(0x00000402, &sbsc->sdmracr0);
+- writel(0x0, SDMRA1B);
+- writel(0x00000403, &sbsc->sdmracr0);
+- writel(0x0, SDMRA1B);
+- writel(0x0, SDMRA2B);
+- }
+-
+- writel(0x88800004, &sbsc->sdmrtmpcr);
+- writel(0x00000004, &sbsc->sdmrtmpmsk);
+- writel(0xa55a0032, &sbsc->rtcor);
+- writel(0xa55a000c, &sbsc->rtcorh);
+- writel(0xa55a2048, &sbsc->rtcsr);
+- writel(readl(&sbsc->sdcr0)|0x800, &sbsc->sdcr0);
+- writel(readl(&sbsc->sdcr1)|0x400, &sbsc->sdcr1);
+- writel(0xfff20000, &sbsc->zqccr);
+-
+- /* SCBS2 only */
+- if (sbsc == (struct sh73a0_sbsc *)SBSC2_BASE) {
+- writel(readl(&sbsc->sdpdcr0)|0x00030000, &sbsc->sdpdcr0);
+- writel(0xa5390000, &sbsc->dphycnt1);
+- writel(0x00001200, &sbsc->dphycnt0);
+- writel(0x07ce0000, &sbsc->dphycnt1);
+- writel(0x00001247, &sbsc->dphycnt0);
+- cmp_loop(&sbsc->dphycnt2, 0xffffffff, 0x07ce0000);
+- writel(readl(&sbsc->sdpdcr0) & 0xfffcffff, &sbsc->sdpdcr0);
+- }
+-}
+-
+-void s_init(void)
+-{
+- struct sh73a0_rwdt *rwdt = (struct sh73a0_rwdt *)RWDT_BASE;
+- struct sh73a0_sbsc_cpg *cpg = (struct sh73a0_sbsc_cpg *)CPG_BASE;
+- struct sh73a0_sbsc_cpg_srcr *cpg_srcr =
+- (struct sh73a0_sbsc_cpg_srcr *)CPG_SRCR_BASE;
+- struct sh73a0_sbsc *sbsc1 = (struct sh73a0_sbsc *)SBSC1_BASE;
+- struct sh73a0_sbsc *sbsc2 = (struct sh73a0_sbsc *)SBSC2_BASE;
+- struct sh73a0_hpb *hpb = (struct sh73a0_hpb *)HPB_BASE;
+- struct sh73a0_hpb_bscr *hpb_bscr =
+- (struct sh73a0_hpb_bscr *)HPBSCR_BASE;
+-
+- /* Watchdog init */
+- writew(0xA507, &rwdt->rwtcsra0);
+-
+- /* Secure control register Init */
+- #define LIFEC_SEC_SRC_BIT (1 << 15)
+- writel(readl(LIFEC_SEC_SRC) & ~LIFEC_SEC_SRC_BIT, LIFEC_SEC_SRC);
+-
+- clrbits_le32(&cpg->smstpcr3, (1 << 15));
+- clrbits_le32(&cpg_srcr->srcr3, (1 << 15));
+- clrbits_le32(&cpg->smstpcr2, (1 << 18));
+- clrbits_le32(&cpg_srcr->srcr2, (1 << 18));
+- writel(0x0, &cpg->pllecr);
+-
+- cmp_loop(&cpg->pllecr, 0x00000F00, 0x0);
+- cmp_loop(&cpg->frqcrb, 0x80000000, 0x0);
+-
+- writel(0x2D000000, &cpg->pll0cr);
+- writel(0x17100000, &cpg->pll1cr);
+- writel(0x96235880, &cpg->frqcrb);
+- cmp_loop(&cpg->frqcrb, 0x80000000, 0x0);
+-
+- writel(0xB, &cpg->flckcr);
+- clrbits_le32(&cpg->smstpcr0, (1 << 1));
+-
+- clrbits_le32(&cpg_srcr->srcr0, (1 << 1));
+- writel(0x0514, &hpb_bscr->smgpiotime);
+- writel(0x0514, &hpb_bscr->smcmt2time);
+- writel(0x0514, &hpb_bscr->smcpgtime);
+- writel(0x0514, &hpb_bscr->smsysctime);
+-
+- writel(0x00092000, &cpg->dvfscr4);
+- writel(0x000000DC, &cpg->dvfscr5);
+- writel(0x0, &cpg->pllecr);
+- cmp_loop(&cpg->pllecr, 0x00000F00, 0x0);
+-
+- /* FRQCR Init */
+- writel(0x0012453C, &cpg->frqcra);
+- writel(0x80331350, &cpg->frqcrb);
+- cmp_loop(&cpg->frqcrb, 0x80000000, 0x0);
+- writel(0x00000B0B, &cpg->frqcrd);
+- cmp_loop(&cpg->frqcrd, 0x80000000, 0x0);
+-
+- /* Clock Init */
+- writel(0x00000003, PCLKCR);
+- writel(0x0000012F, &cpg->vclkcr1);
+- writel(0x00000119, &cpg->vclkcr2);
+- writel(0x00000119, &cpg->vclkcr3);
+- writel(0x00000002, &cpg->zbckcr);
+- writel(0x00000005, &cpg->flckcr);
+- writel(0x00000080, &cpg->sd0ckcr);
+- writel(0x00000080, &cpg->sd1ckcr);
+- writel(0x00000080, &cpg->sd2ckcr);
+- writel(0x0000003F, &cpg->fsiackcr);
+- writel(0x0000003F, &cpg->fsibckcr);
+- writel(0x00000080, &cpg->subckcr);
+- writel(0x0000000B, &cpg->spuackcr);
+- writel(0x0000000B, &cpg->spuvckcr);
+- writel(0x0000013F, &cpg->msuckcr);
+- writel(0x00000080, &cpg->hsickcr);
+- writel(0x0000003F, &cpg->mfck1cr);
+- writel(0x0000003F, &cpg->mfck2cr);
+- writel(0x00000107, &cpg->dsitckcr);
+- writel(0x00000313, &cpg->dsi0pckcr);
+- writel(0x0000130D, &cpg->dsi1pckcr);
+- writel(0x2A800E0E, &cpg->dsi0phycr);
+- writel(0x1E000000, &cpg->pll0cr);
+- writel(0x2D000000, &cpg->pll0cr);
+- writel(0x17100000, &cpg->pll1cr);
+- writel(0x27000080, &cpg->pll2cr);
+- writel(0x1D000000, &cpg->pll3cr);
+- writel(0x00080000, &cpg->pll0stpcr);
+- writel(0x000120C0, &cpg->pll1stpcr);
+- writel(0x00012000, &cpg->pll2stpcr);
+- writel(0x00000030, &cpg->pll3stpcr);
+-
+- writel(0x0000000B, &cpg->pllecr);
+- cmp_loop(&cpg->pllecr, 0x00000B00, 0x00000B00);
+-
+- writel(0x000120F0, &cpg->dvfscr3);
+- writel(0x00000020, &cpg->mpmode);
+- writel(0x0000028A, &cpg->vrefcr);
+- writel(0xE4628087, &cpg->rmstpcr0);
+- writel(0xFFFFFFFF, &cpg->rmstpcr1);
+- writel(0x53FFFFFF, &cpg->rmstpcr2);
+- writel(0xFFFFFFFF, &cpg->rmstpcr3);
+- writel(0x00800D3D, &cpg->rmstpcr4);
+- writel(0xFFFFF3FF, &cpg->rmstpcr5);
+- writel(0x00000000, &cpg->smstpcr2);
+- writel(0x00040000, &cpg_srcr->srcr2);
+-
+- clrbits_le32(&cpg->pllecr, (1 << 3));
+- cmp_loop(&cpg->pllecr, 0x00000800, 0x0);
+-
+- writel(0x00000001, &hpb->hpbctrl6);
+- cmp_loop(&hpb->hpbctrl6, 0x1, 0x1);
+-
+- writel(0x00001414, &cpg->frqcrd);
+- cmp_loop(&cpg->frqcrd, 0x80000000, 0x0);
+-
+- writel(0x1d000000, &cpg->pll3cr);
+- setbits_le32(&cpg->pllecr, (1 << 3));
+- cmp_loop(&cpg->pllecr, 0x800, 0x800);
+-
+- /* SBSC1 Init*/
+- sbsc_init(sbsc1);
+-
+- /* SBSC2 Init*/
+- sbsc_init(sbsc2);
+-
+- writel(0x00000b0b, &cpg->frqcrd);
+- cmp_loop(&cpg->frqcrd, 0x80000000, 0x0);
+- writel(0xfffffffc, &cpg->cpgxxcs4);
+-}
+-
+-int board_early_init_f(void)
+-{
+- struct sh73a0_sbsc_cpg *cpg = (struct sh73a0_sbsc_cpg *)CPG_BASE;
+- struct sh73a0_bsc *bsc = (struct sh73a0_bsc *)BSC_BASE;
+- struct sh73a0_sbsc_cpg_srcr *cpg_srcr =
+- (struct sh73a0_sbsc_cpg_srcr *)CPG_SRCR_BASE;
+-
+- writel(CS0BCR_D, &bsc->cs0bcr);
+- writel(CS4BCR_D, &bsc->cs4bcr);
+- writel(CS0WCR_D, &bsc->cs0wcr);
+- writel(CS4WCR_D, &bsc->cs4wcr);
+-
+- clrsetbits_le32(&bsc->cmncr, ~CMNCR_BROMMD, CMNCR_BROMMD);
+-
+- clrbits_le32(&cpg->smstpcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0));
+- clrbits_le32(&cpg_srcr->srcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0));
+- clrbits_le32(&cpg->smstpcr3, SMSTPCR3_USB);
+- clrbits_le32(&cpg_srcr->srcr3, SMSTPCR3_USB);
+- writel(VCLKCR1_D, &cpg->vclkcr1);
+-
+- /* Setup SCIF4 / workaround */
+- writeb(0x12, PORT32CR);
+- writeb(0x22, PORT33CR);
+- writeb(0x12, PORT34CR);
+- writeb(0x22, PORT35CR);
+-
+- return 0;
+-}
+-
+-int board_init(void)
+-{
+- sh73a0_pinmux_init();
+-
+- /* SCIFA 4 */
+- gpio_request(GPIO_FN_SCIFA4_TXD, NULL);
+- gpio_request(GPIO_FN_SCIFA4_RXD, NULL);
+- gpio_request(GPIO_FN_SCIFA4_RTS_, NULL);
+- gpio_request(GPIO_FN_SCIFA4_CTS_, NULL);
+-
+- /* Ethernet/SMSC */
+- gpio_request(GPIO_PORT224, NULL);
+- gpio_direction_input(GPIO_PORT224);
+-
+- /* SMSC/USB */
+- gpio_request(GPIO_FN_CS4_, NULL);
+-
+- /* MMCIF */
+- gpio_request(GPIO_FN_MMCCLK0, NULL);
+- gpio_request(GPIO_FN_MMCCMD0_PU, NULL);
+- gpio_request(GPIO_FN_MMCD0_0_PU, NULL);
+- gpio_request(GPIO_FN_MMCD0_1_PU, NULL);
+- gpio_request(GPIO_FN_MMCD0_2_PU, NULL);
+- gpio_request(GPIO_FN_MMCD0_3_PU, NULL);
+- gpio_request(GPIO_FN_MMCD0_4_PU, NULL);
+- gpio_request(GPIO_FN_MMCD0_5_PU, NULL);
+- gpio_request(GPIO_FN_MMCD0_6_PU, NULL);
+- gpio_request(GPIO_FN_MMCD0_7_PU, NULL);
+-
+- /* SDHI */
+- gpio_request(GPIO_FN_SDHIWP0, NULL);
+- gpio_request(GPIO_FN_SDHICD0, NULL);
+- gpio_request(GPIO_FN_SDHICMD0, NULL);
+- gpio_request(GPIO_FN_SDHICLK0, NULL);
+- gpio_request(GPIO_FN_SDHID0_3, NULL);
+- gpio_request(GPIO_FN_SDHID0_2, NULL);
+- gpio_request(GPIO_FN_SDHID0_1, NULL);
+- gpio_request(GPIO_FN_SDHID0_0, NULL);
+- gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL);
+- gpio_request(GPIO_PORT15, NULL);
+- gpio_direction_output(GPIO_PORT15, 1);
+-
+- /* I2C */
+- gpio_request(GPIO_FN_PORT27_I2C_SCL3, NULL);
+- gpio_request(GPIO_FN_PORT28_I2C_SDA3, NULL);
+-
+- gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
+-
+- return 0;
+-}
+-
+-const struct rmobile_sysinfo sysinfo = {
+- CONFIG_RMOBILE_BOARD_STRING
+-};
+-
+-int dram_init(void)
+-{
+- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+- return 0;
+-}
+-
+-int board_eth_init(bd_t *bis)
+-{
+- int ret = 0;
+-#ifdef CONFIG_SMC911X
+- ret = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+-#endif
+- return ret;
+-}
+-
+-void reset_cpu(ulong addr)
+-{
+- /* Soft Power On Reset */
+- writel((1 << 31), RESCNT2);
+-}
+diff --git a/board/logicpd/imx31_litekit/lowlevel_init.S b/board/logicpd/imx31_litekit/lowlevel_init.S
+index 95b0c08..0ce8905 100644
+--- a/board/logicpd/imx31_litekit/lowlevel_init.S
++++ b/board/logicpd/imx31_litekit/lowlevel_init.S
+@@ -54,7 +54,7 @@ lowlevel_init:
+ REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE
+ REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
+
+- REG CCM_PDR0, PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0)
++ REG CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0)
+
+ REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0x33) | PLL_MFI(7) | PLL_MFN(0x23)
+ REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
+diff --git a/board/raidsonic/ib62x0/ib62x0.c b/board/raidsonic/ib62x0/ib62x0.c
+index b7e6e41..1164d6b 100644
+--- a/board/raidsonic/ib62x0/ib62x0.c
++++ b/board/raidsonic/ib62x0/ib62x0.c
+@@ -23,7 +23,6 @@
+
+ #include <common.h>
+ #include <miiphy.h>
+-#include <asm/io.h>
+ #include <asm/arch/cpu.h>
+ #include <asm/arch/kirkwood.h>
+ #include <asm/arch/mpp.h>
+@@ -42,8 +41,6 @@ int board_early_init_f(void)
+ IB62x0_OE_VAL_HIGH,
+ IB62x0_OE_LOW, IB62x0_OE_HIGH);
+
+- /* Set SATA activity LEDs to default off */
+- writel(MVSATAHC_LED_POLARITY_CTRL, MVSATAHC_LED_CONF_REG);
+ /* Multi-Purpose Pins Functionality configuration */
+ u32 kwmpp_config[] = {
+ MPP0_NF_IO2,
+diff --git a/board/raidsonic/ib62x0/ib62x0.h b/board/raidsonic/ib62x0/ib62x0.h
+index 0118c2b..0c30690 100644
+--- a/board/raidsonic/ib62x0/ib62x0.h
++++ b/board/raidsonic/ib62x0/ib62x0.h
+@@ -37,8 +37,4 @@
+ #define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
+ #define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
+
+-/* SATAHC related */
+-#define MVSATAHC_LED_CONF_REG (MV_SATA_BASE + 0x2C)
+-#define MVSATAHC_LED_POLARITY_CTRL (1 << 3)
+-
+ #endif /* __IB62x0_H */
+diff --git a/board/spear/x600/Makefile b/board/spear/x600/Makefile
+deleted file mode 100644
+index 8c4e7e2..0000000
+--- a/board/spear/x600/Makefile
++++ /dev/null
+@@ -1,47 +0,0 @@
+-#
+-# (C) Copyright 2000-2004
+-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+-#
+-# See file CREDITS for list of people who contributed to this
+-# project.
+-#
+-# This program is free software; you can redistribute it and/or
+-# modify it under the terms of the GNU General Public License as
+-# published by the Free Software Foundation; either version 2 of
+-# the License, or (at your option) any later version.
+-#
+-# This program is distributed in the hope that it will be useful,
+-# but WITHOUT ANY WARRANTY; without even the implied warranty of
+-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-# GNU General Public License for more details.
+-#
+-# You should have received a copy of the GNU General Public License
+-# along with this program; if not, write to the Free Software
+-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+-# MA 02111-1307 USA
+-#
+-
+-include $(TOPDIR)/config.mk
+-
+-LIB = $(obj)lib$(BOARD).o
+-
+-ifndef CONFIG_SPL_BUILD
+-COBJS := fpga.o $(BOARD).o
+-endif
+-SOBJS :=
+-
+-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+-OBJS := $(addprefix $(obj),$(COBJS))
+-SOBJS := $(addprefix $(obj),$(SOBJS))
+-
+-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+- $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+-
+-#########################################################################
+-
+-# defines $(obj).depend target
+-include $(SRCTREE)/rules.mk
+-
+-sinclude $(obj).depend
+-
+-#########################################################################
+diff --git a/board/spear/x600/fpga.c b/board/spear/x600/fpga.c
+deleted file mode 100644
+index 85eb31b..0000000
+--- a/board/spear/x600/fpga.c
++++ /dev/null
+@@ -1,280 +0,0 @@
+-/*
+- * Copyright (C) 2012 Stefan Roese <sr at denx.de>
+- *
+- * See file CREDITS for list of people who contributed to this
+- * project.
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of
+- * the License, or (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+- * MA 02111-1307 USA
+- */
+-
+-#include <common.h>
+-#include <spartan3.h>
+-#include <command.h>
+-#include <asm/gpio.h>
+-#include <asm/io.h>
+-#include <asm/arch/hardware.h>
+-#include <asm/arch/spr_misc.h>
+-#include <asm/arch/spr_ssp.h>
+-
+-/*
+- * FPGA program pin configuration on X600:
+- *
+- * Only PROG and DONE are connected to GPIOs. INIT is not connected to the
+- * SoC at all. And CLOCK and DATA are connected to the SSP2 port. We use
+- * 16bit serial writes via this SSP port to write the data bits into the
+- * FPGA.
+- */
+-#define CONFIG_SYS_FPGA_PROG 2
+-#define CONFIG_SYS_FPGA_DONE 3
+-
+-/*
+- * Set the active-low FPGA reset signal.
+- */
+-static void fpga_reset(int assert)
+-{
+- /*
+- * On x600 we have no means to toggle the FPGA reset signal
+- */
+- debug("%s:%d: RESET (%d)\n", __func__, __LINE__, assert);
+-}
+-
+-/*
+- * Set the FPGA's active-low SelectMap program line to the specified level
+- */
+-static int fpga_pgm_fn(int assert, int flush, int cookie)
+-{
+- debug("%s:%d: FPGA PROG (%d)\n", __func__, __LINE__, assert);
+-
+- gpio_set_value(CONFIG_SYS_FPGA_PROG, assert);
+-
+- return assert;
+-}
+-
+-/*
+- * Test the state of the active-low FPGA INIT line. Return 1 on INIT
+- * asserted (low).
+- */
+-static int fpga_init_fn(int cookie)
+-{
+- static int state;
+-
+- debug("%s:%d: init (state=%d)\n", __func__, __LINE__, state);
+-
+- /*
+- * On x600, the FPGA INIT signal is not connected to the SoC.
+- * We can't read the INIT status. Let's return the "correct"
+- * INIT signal state generated via a local state-machine.
+- */
+- if (++state == 1) {
+- return 1;
+- } else {
+- state = 0;
+- return 0;
+- }
+-}
+-
+-/*
+- * Test the state of the active-high FPGA DONE pin
+- */
+-static int fpga_done_fn(int cookie)
+-{
+- struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE;
+-
+- /*
+- * Wait for Tx-FIFO to become empty before looking for DONE
+- */
+- while (!(readl(&ssp->sspsr) & SSPSR_TFE))
+- ;
+-
+- if (gpio_get_value(CONFIG_SYS_FPGA_DONE))
+- return 1;
+- else
+- return 0;
+-}
+-
+-/*
+- * FPGA pre-configuration function. Just make sure that
+- * FPGA reset is asserted to keep the FPGA from starting up after
+- * configuration.
+- */
+-static int fpga_pre_config_fn(int cookie)
+-{
+- debug("%s:%d: FPGA pre-configuration\n", __func__, __LINE__);
+- fpga_reset(TRUE);
+-
+- return 0;
+-}
+-
+-/*
+- * FPGA post configuration function. Blip the FPGA reset line and then see if
+- * the FPGA appears to be running.
+- */
+-static int fpga_post_config_fn(int cookie)
+-{
+- int rc = 0;
+-
+- debug("%s:%d: FPGA post configuration\n", __func__, __LINE__);
+-
+- fpga_reset(TRUE);
+- udelay(100);
+- fpga_reset(FALSE);
+- udelay(100);
+-
+- return rc;
+-}
+-
+-static int fpga_clk_fn(int assert_clk, int flush, int cookie)
+-{
+- /*
+- * No dedicated clock signal on x600 (data & clock generated)
+- * in SSP interface. So we don't have to do anything here.
+- */
+- return assert_clk;
+-}
+-
+-static int fpga_wr_fn(int assert_write, int flush, int cookie)
+-{
+- struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE;
+- static int count;
+- static u16 data;
+-
+- /*
+- * First collect 16 bits of data
+- */
+- data = data << 1;
+- if (assert_write)
+- data |= 1;
+-
+- /*
+- * If 16 bits are not available, return for more bits
+- */
+- count++;
+- if (count != 16)
+- return assert_write;
+-
+- count = 0;
+-
+- /*
+- * Wait for Tx-FIFO to become ready
+- */
+- while (!(readl(&ssp->sspsr) & SSPSR_TNF))
+- ;
+-
+- /* Send 16 bits to FPGA via SSP bus */
+- writel(data, &ssp->sspdr);
+-
+- return assert_write;
+-}
+-
+-static Xilinx_Spartan3_Slave_Serial_fns x600_fpga_fns = {
+- fpga_pre_config_fn,
+- fpga_pgm_fn,
+- fpga_clk_fn,
+- fpga_init_fn,
+- fpga_done_fn,
+- fpga_wr_fn,
+- fpga_post_config_fn,
+-};
+-
+-static Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
+- XILINX_XC3S1200E_DESC(slave_serial, &x600_fpga_fns, 0)
+-};
+-
+-/*
+- * Initialize the SelectMap interface. We assume that the mode and the
+- * initial state of all of the port pins have already been set!
+- */
+-static void fpga_serialslave_init(void)
+-{
+- debug("%s:%d: Initialize serial slave interface\n", __func__, __LINE__);
+- fpga_pgm_fn(FALSE, FALSE, 0); /* make sure program pin is inactive */
+-}
+-
+-static int expi_setup(int freq)
+-{
+- struct misc_regs *misc = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+- int pll2_m, pll2_n, pll2_p, expi_x, expi_y;
+-
+- pll2_m = (freq * 2) / 1000;
+- pll2_n = 15;
+- pll2_p = 1;
+- expi_x = 1;
+- expi_y = 2;
+-
+- /*
+- * Disable reset, Low compression, Disable retiming, Enable Expi,
+- * Enable soft reset, DMA, PLL2, Internal
+- */
+- writel(EXPI_CLK_CFG_LOW_COMPR | EXPI_CLK_CFG_CLK_EN | EXPI_CLK_CFG_RST |
+- EXPI_CLK_SYNT_EN | EXPI_CLK_CFG_SEL_PLL2 |
+- EXPI_CLK_CFG_INT_CLK_EN | (expi_y << 16) | (expi_x << 24),
+- &misc->expi_clk_cfg);
+-
+- /*
+- * 6 uA, Internal feedback, 1st order, Non-dithered, Sample Parameters,
+- * Enable PLL2, Disable reset
+- */
+- writel((pll2_m << 24) | (pll2_p << 8) | (pll2_n), &misc->pll2_frq);
+- writel(PLL2_CNTL_6UA | PLL2_CNTL_SAMPLE | PLL2_CNTL_ENABLE |
+- PLL2_CNTL_RESETN | PLL2_CNTL_LOCK, &misc->pll2_cntl);
+-
+- /*
+- * Disable soft reset
+- */
+- clrbits_le32(&misc->expi_clk_cfg, EXPI_CLK_CFG_RST);
+-
+- return 0;
+-}
+-
+-/*
+- * Initialize the fpga
+- */
+-int x600_init_fpga(void)
+-{
+- struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE;
+- struct misc_regs *misc = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+-
+- /* Enable SSP2 clock */
+- writel(readl(&misc->periph1_clken) | MISC_SSP2ENB | MISC_GPIO4ENB,
+- &misc->periph1_clken);
+-
+- /* Set EXPI clock to 45 MHz */
+- expi_setup(45000);
+-
+- /* Configure GPIO directions */
+- gpio_direction_output(CONFIG_SYS_FPGA_PROG, 0);
+- gpio_direction_input(CONFIG_SYS_FPGA_DONE);
+-
+- writel(SSPCR0_DSS_16BITS, &ssp->sspcr0);
+- writel(SSPCR1_SSE, &ssp->sspcr1);
+-
+- /*
+- * Set lowest prescale divisor value (CPSDVSR) of 2 for max download
+- * speed.
+- *
+- * Actual data clock rate is: 80MHz / (CPSDVSR * (SCR + 1))
+- * With CPSDVSR at 2 and SCR at 0, the maximume clock rate is 40MHz.
+- */
+- writel(2, &ssp->sspcpsr);
+-
+- fpga_init();
+- fpga_serialslave_init();
+-
+- debug("%s:%d: Adding fpga 0\n", __func__, __LINE__);
+- fpga_add(fpga_xilinx, &fpga[0]);
+-
+- return 0;
+-}
+diff --git a/board/spear/x600/fpga.h b/board/spear/x600/fpga.h
+deleted file mode 100644
+index 2b18557..0000000
+--- a/board/spear/x600/fpga.h
++++ /dev/null
+@@ -1,23 +0,0 @@
+-/*
+- * Copyright (C) 2012 Stefan Roese <sr at denx.de>
+- *
+- * See file CREDITS for list of people who contributed to this
+- * project.
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of
+- * the License, or (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+- * MA 02111-1307 USA
+- */
+-
+-int x600_init_fpga(void);
+diff --git a/board/spear/x600/x600.c b/board/spear/x600/x600.c
+deleted file mode 100644
+index 96ec0ad..0000000
+--- a/board/spear/x600/x600.c
++++ /dev/null
+@@ -1,124 +0,0 @@
+-/*
+- * (C) Copyright 2009
+- * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com.
+- *
+- * Copyright (C) 2012 Stefan Roese <sr at denx.de>
+- *
+- * See file CREDITS for list of people who contributed to this
+- * project.
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of
+- * the License, or (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+- * MA 02111-1307 USA
+- */
+-
+-#include <common.h>
+-#include <nand.h>
+-#include <netdev.h>
+-#include <phy.h>
+-#include <rtc.h>
+-#include <asm/io.h>
+-#include <asm/arch/hardware.h>
+-#include <asm/arch/spr_defs.h>
+-#include <asm/arch/spr_misc.h>
+-#include <linux/mtd/fsmc_nand.h>
+-#include "fpga.h"
+-
+-static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
+-
+-int board_init(void)
+-{
+- /*
+- * X600 is equipped with an M41T82 RTC. This RTC has the
+- * HT bit (Halt Update), which needs to be cleared upon
+- * power-up. Otherwise the RTC is halted.
+- */
+- rtc_reset();
+-
+- return spear_board_init(MACH_TYPE_SPEAR600);
+-}
+-
+-int board_late_init(void)
+-{
+- /*
+- * Monitor and env protection on by default
+- */
+- flash_protect(FLAG_PROTECT_SET,
+- CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE +
+- CONFIG_SYS_SPL_LEN + CONFIG_SYS_MONITOR_LEN +
+- 2 * CONFIG_ENV_SECT_SIZE - 1,
+- &flash_info[0]);
+-
+- /* Init FPGA subsystem */
+- x600_init_fpga();
+-
+- return 0;
+-}
+-
+-/*
+- * board_nand_init - Board specific NAND initialization
+- * @nand: mtd private chip structure
+- *
+- * Called by nand_init_chip to initialize the board specific functions
+- */
+-
+-void board_nand_init(void)
+-{
+- struct misc_regs *const misc_regs_p =
+- (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+- struct nand_chip *nand = &nand_chip[0];
+-
+- if (!(readl(&misc_regs_p->auto_cfg_reg) & MISC_NANDDIS))
+- fsmc_nand_init(nand);
+-}
+-
+-int designware_board_phy_init(struct eth_device *dev, int phy_addr,
+- int (*mii_write)(struct eth_device *, u8, u8, u16),
+- int dw_reset_phy(struct eth_device *))
+-{
+- /* Extended PHY control 1, select GMII */
+- mii_write(dev, phy_addr, 23, 0x0020);
+-
+- /* Software reset necessary after GMII mode selction */
+- dw_reset_phy(dev);
+-
+- /* Enable extended page register access */
+- mii_write(dev, phy_addr, 31, 0x0001);
+-
+- /* 17e: Enhanced LED behavior, needs to be written twice */
+- mii_write(dev, phy_addr, 17, 0x09ff);
+- mii_write(dev, phy_addr, 17, 0x09ff);
+-
+- /* 16e: Enhanced LED method select */
+- mii_write(dev, phy_addr, 16, 0xe0ea);
+-
+- /* Disable extended page register access */
+- mii_write(dev, phy_addr, 31, 0x0000);
+-
+- /* Enable clock output pin */
+- mii_write(dev, phy_addr, 18, 0x0049);
+-
+- return 0;
+-}
+-
+-int board_eth_init(bd_t *bis)
+-{
+- int ret = 0;
+-
+- if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_PHY_ADDR,
+- PHY_INTERFACE_MODE_GMII) >= 0)
+- ret++;
+-
+- return ret;
+-}
+diff --git a/board/st-ericsson/snowball/snowball.c b/board/st-ericsson/snowball/snowball.c
+index e750df1..8c743c0 100644
+--- a/board/st-ericsson/snowball/snowball.c
++++ b/board/st-ericsson/snowball/snowball.c
+@@ -253,10 +253,6 @@ int board_late_init(void)
+ if ((raise_ab8500_gpio16() < 0))
+ printf("error: cant' raise GPIO16\n");
+
+- /* empty UART RX FIFO */
+- while (tstc())
+- (void) getc();
+-
+ return 0;
+ }
+
+diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c
+index 4954475..99f833f 100644
+--- a/board/ti/beagle/beagle.c
++++ b/board/ti/beagle/beagle.c
+@@ -488,7 +488,7 @@ int board_mmc_init(bd_t *bis)
+ }
+ #endif
+
+-#if defined(CONFIG_USB_EHCI) && !defined(CONFIG_SPL_BUILD)
++#ifdef CONFIG_USB_EHCI
+ /* Call usb_stop() before starting the kernel */
+ void show_boot_progress(int val)
+ {
+diff --git a/board/tqc/tqm85xx/Makefile b/board/tqc/tqm85xx/Makefile
+new file mode 100644
+index 0000000..0a5501f
+--- /dev/null
++++ b/board/tqc/tqm85xx/Makefile
+@@ -0,0 +1,50 @@
++#
++# (C) Copyright 2001-2006
++# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
++#
++# See file CREDITS for list of people who contributed to this
++# project.
++#
++# This program is free software; you can redistribute it and/or
++# modify it under the terms of the GNU General Public License as
++# published by the Free Software Foundation; either version 2 of
++# the License, or (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++# MA 02111-1307 USA
++#
++
++include $(TOPDIR)/config.mk
++
++LIB = $(obj)lib$(BOARD).o
++
++COBJS-y += $(BOARD).o
++COBJS-y += sdram.o
++COBJS-y += law.o
++COBJS-y += tlb.o
++
++COBJS-$(CONFIG_NAND) += nand.o
++
++COBJS := $(COBJS-y)
++SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
++OBJS := $(addprefix $(obj),$(COBJS))
++SOBJS := $(addprefix $(obj),$(SOBJS))
++
++$(LIB): $(obj).depend $(OBJS) $(SOBJS)
++ $(call cmd_link_o_target, $(OBJS))
++
++#########################################################################
++
++# defines $(obj).depend target
++include $(SRCTREE)/rules.mk
++
++sinclude $(obj).depend
++
++#########################################################################
+diff --git a/board/tqc/tqm85xx/law.c b/board/tqc/tqm85xx/law.c
+new file mode 100644
+index 0000000..c596303
+--- /dev/null
++++ b/board/tqc/tqm85xx/law.c
+@@ -0,0 +1,79 @@
++/*
++ * Copyright 2008 Freescale Semiconductor, Inc.
++ *
++ * (C) Copyright 2000
++ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <common.h>
++#include <asm/fsl_law.h>
++#include <asm/mmu.h>
++
++/*
++ * LAW(Local Access Window) configuration:
++ *
++ * Standard mapping:
++ *
++ * 0x0000_0000 0x7fff_ffff DDR 2G
++ * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
++ * 0xc000_0000 0xdfff_ffff RapidIO or PCI express 512M
++ * 0xe000_0000 0xe000_ffff CCSR 1M
++ * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
++ * 0xe300_0000 0xe3ff_ffff CAN and NAND Flash 16M
++ * 0xef00_0000 0xefff_ffff PCI express IO 16M
++ * 0xfc00_0000 0xffff_ffff FLASH (boot bank) 128M
++ *
++ * Big FLASH mapping:
++ *
++ * 0x0000_0000 0x7fff_ffff DDR 2G
++ * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
++ * 0xa000_0000 0xa000_ffff CCSR 1M
++ * 0xa200_0000 0xa2ff_ffff PCI1 IO 16M
++ * 0xa300_0000 0xa3ff_ffff CAN and NAND Flash 16M
++ * 0xaf00_0000 0xafff_ffff PCI express IO 16M
++ * 0xb000_0000 0xbfff_ffff RapidIO or PCI express 256M
++ * 0xc000_0000 0xffff_ffff FLASH (boot bank) 1G
++ *
++ * Notes:
++ * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
++ * If flash is 8M at default position (last 8M), no LAW needed.
++ */
++
++#ifdef CONFIG_TQM_BIGFLASH
++#define LAW_3_SIZE LAW_SIZE_1G
++#define LAW_5_SIZE LAW_SIZE_256M
++#else
++#define LAW_3_SIZE LAW_SIZE_128M
++#define LAW_5_SIZE LAW_SIZE_512M
++#endif
++
++struct law_entry law_table[] = {
++ SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_2G, LAW_TRGT_IF_DDR),
++ SET_LAW(CONFIG_SYS_LBC_FLASH_BASE, LAW_3_SIZE, LAW_TRGT_IF_LBC),
++#ifndef CONFIG_PCIE1
++ SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_RIO),
++#endif /* CONFIG_PCIE1 */
++#if defined(CONFIG_CAN_DRIVER) || defined(CONFIG_NAND)
++ SET_LAW(CONFIG_SYS_CAN_BASE, LAW_SIZE_16M, LAW_TRGT_IF_LBC),
++#endif /* CONFIG_CAN_DRIVER || CONFIG_NAND */
++};
++
++int num_law_entries = ARRAY_SIZE (law_table);
+diff --git a/board/tqc/tqm85xx/nand.c b/board/tqc/tqm85xx/nand.c
+new file mode 100644
+index 0000000..4b16c31
+--- /dev/null
++++ b/board/tqc/tqm85xx/nand.c
+@@ -0,0 +1,472 @@
++/*
++ * (C) Copyright 2008 Wolfgang Grandegger <wg at denx.de>
++ *
++ * (C) Copyright 2006
++ * Thomas Waehner, TQ-System GmbH, thomas.waehner at tqs.de.
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <common.h>
++#include <asm/processor.h>
++#include <asm/immap_85xx.h>
++#include <asm/processor.h>
++#include <asm/mmu.h>
++#include <asm/io.h>
++#include <asm/errno.h>
++#include <linux/mtd/mtd.h>
++#include <linux/mtd/fsl_upm.h>
++#include <ioports.h>
++
++#include <nand.h>
++
++DECLARE_GLOBAL_DATA_PTR;
++
++extern uint get_lbc_clock (void);
++
++/* index of UPM RAM array run pattern for NAND command cycle */
++#define CONFIG_SYS_NAN_UPM_WRITE_CMD_OFS 0x08
++
++/* index of UPM RAM array run pattern for NAND address cycle */
++#define CONFIG_SYS_NAND_UPM_WRITE_ADDR_OFS 0x10
++
++/* Structure for table with supported UPM timings */
++struct upm_freq {
++ ulong freq;
++ const u32 *upm_patt;
++ uchar gpl4_disable;
++ uchar ehtr;
++ uchar ead;
++};
++
++/* NAND-FLASH UPM tables for TQM85XX according to TQM8548.pq.timing.101.doc */
++
++/* UPM pattern for bus clock = 25 MHz */
++static const u32 upm_patt_25[] = {
++ /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
++ /* 0x00 */ 0x0ff32000, 0x0fa32000, 0x3fb32005, 0xfffffc00,
++ /* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++
++ /* UPM Read Burst RAM array entry -> NAND Write CMD */
++ /* 0x08 */ 0x00ff2c30, 0x00ff2c30, 0x0fff2c35, 0xfffffc00,
++ /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++
++ /* UPM Read Burst RAM array entry -> NAND Write ADDR */
++ /* 0x10 */ 0x00f3ec30, 0x00f3ec30, 0x0ff3ec35, 0xfffffc00,
++ /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++
++ /* UPM Write Single RAM array entry -> NAND Write Data */
++ /* 0x18 */ 0x00f32c00, 0x00f32c00, 0x0ff32c05, 0xfffffc00,
++ /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++
++ /* UPM Write Burst RAM array entry -> unused */
++ /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++ /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++ /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++ /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
++
++ /* UPM Refresh Timer RAM array entry -> unused */
++ /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++ /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++ /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
++
++ /* UPM Exception RAM array entry -> unsused */
++ /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
++};
++
++/* UPM pattern for bus clock = 33.3 MHz */
++static const u32 upm_patt_33[] = {
++ /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
++ /* 0x00 */ 0x0ff32000, 0x0fa32100, 0x3fb32005, 0xfffffc00,
++ /* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++
++ /* UPM Read Burst RAM array entry -> NAND Write CMD */
++ /* 0x08 */ 0x00ff2c30, 0x00ff2c30, 0x0fff2c35, 0xfffffc00,
++ /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++
++ /* UPM Read Burst RAM array entry -> NAND Write ADDR */
++ /* 0x10 */ 0x00f3ec30, 0x00f3ec30, 0x0ff3ec35, 0xfffffc00,
++ /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++
++ /* UPM Write Single RAM array entry -> NAND Write Data */
++ /* 0x18 */ 0x00f32c00, 0x00f32c00, 0x0ff32c05, 0xfffffc00,
++ /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++
++ /* UPM Write Burst RAM array entry -> unused */
++ /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++ /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++ /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++ /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
++
++ /* UPM Refresh Timer RAM array entry -> unused */
++ /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++ /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++ /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
++
++ /* UPM Exception RAM array entry -> unsused */
++ /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
++};
++
++/* UPM pattern for bus clock = 41.7 MHz */
++static const u32 upm_patt_42[] = {
++ /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
++ /* 0x00 */ 0x0ff32000, 0x0fa32100, 0x3fb32005, 0xfffffc00,
++ /* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++
++ /* UPM Read Burst RAM array entry -> NAND Write CMD */
++ /* 0x08 */ 0x00ff2c30, 0x00ff2c30, 0x0fff2c35, 0xfffffc00,
++ /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++
++ /* UPM Read Burst RAM array entry -> NAND Write ADDR */
++ /* 0x10 */ 0x00f3ec30, 0x00f3ec30, 0x0ff3ec35, 0xfffffc00,
++ /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++
++ /* UPM Write Single RAM array entry -> NAND Write Data */
++ /* 0x18 */ 0x00f32c00, 0x00f32c00, 0x0ff32c05, 0xfffffc00,
++ /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++
++ /* UPM Write Burst RAM array entry -> unused */
++ /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++ /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++ /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++ /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
++
++ /* UPM Refresh Timer RAM array entry -> unused */
++ /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++ /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++ /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
++
++ /* UPM Exception RAM array entry -> unsused */
++ /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
++};
++
++/* UPM pattern for bus clock = 50 MHz */
++static const u32 upm_patt_50[] = {
++ /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
++ /* 0x00 */ 0x0ff33000, 0x0fa33100, 0x0fa33005, 0xfffffc00,
++ /* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++
++ /* UPM Read Burst RAM array entry -> NAND Write CMD */
++ /* 0x08 */ 0x00ff3d30, 0x00ff3c30, 0x0fff3c35, 0xfffffc00,
++ /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++
++ /* UPM Read Burst RAM array entry -> NAND Write ADDR */
++ /* 0x10 */ 0x00f3fd30, 0x00f3fc30, 0x0ff3fc35, 0xfffffc00,
++ /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++
++ /* UPM Write Single RAM array entry -> NAND Write Data */
++ /* 0x18 */ 0x00f33d00, 0x00f33c00, 0x0ff33c05, 0xfffffc00,
++ /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++
++ /* UPM Write Burst RAM array entry -> unused */
++ /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++ /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++ /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++ /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
++
++ /* UPM Refresh Timer RAM array entry -> unused */
++ /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++ /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++ /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
++
++ /* UPM Exception RAM array entry -> unsused */
++ /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
++};
++
++/* UPM pattern for bus clock = 66.7 MHz */
++static const u32 upm_patt_67[] = {
++ /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
++ /* 0x00 */ 0x0ff33000, 0x0fe33000, 0x0fa33100, 0x0fa33000,
++ /* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++
++ /* UPM Read Burst RAM array entry -> NAND Write CMD */
++ /* 0x08 */ 0x00ff3d30, 0x00ff3c30, 0x0fff3c30, 0x0fff3c35,
++ /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++
++ /* UPM Read Burst RAM array entry -> NAND Write ADDR */
++ /* 0x10 */ 0x00f3fd30, 0x00f3fc30, 0x0ff3fc30, 0x0ff3fc35,
++ /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++
++ /* UPM Write Single RAM array entry -> NAND Write Data */
++ /* 0x18 */ 0x00f33d00, 0x00f33c00, 0x0ff33c00, 0x0ff33c05,
++ /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++
++ /* UPM Write Burst RAM array entry -> unused */
++ /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++ /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++ /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++ /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
++
++ /* UPM Refresh Timer RAM array entry -> unused */
++ /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++ /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++ /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
++
++ /* UPM Exception RAM array entry -> unsused */
++ /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
++};
++
++/* UPM pattern for bus clock = 83.3 MHz */
++static const u32 upm_patt_83[] = {
++ /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
++ /* 0x00 */ 0x0ff33000, 0x0fe33000, 0x0fa33100, 0x0fa33000,
++ /* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++
++ /* UPM Read Burst RAM array entry -> NAND Write CMD */
++ /* 0x08 */ 0x00ff3e30, 0x00ff3c30, 0x0fff3c30, 0x0fff3c35,
++ /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++
++ /* UPM Read Burst RAM array entry -> NAND Write ADDR */
++ /* 0x10 */ 0x00f3fe30, 0x00f3fc30, 0x0ff3fc30, 0x0ff3fc35,
++ /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++
++ /* UPM Write Single RAM array entry -> NAND Write Data */
++ /* 0x18 */ 0x00f33e00, 0x00f33c00, 0x0ff33c00, 0x0ff33c05,
++ /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++
++ /* UPM Write Burst RAM array entry -> unused */
++ /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++ /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++ /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++ /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
++
++ /* UPM Refresh Timer RAM array entry -> unused */
++ /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++ /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++ /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
++
++ /* UPM Exception RAM array entry -> unsused */
++ /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
++};
++
++/* UPM pattern for bus clock = 100 MHz */
++static const u32 upm_patt_100[] = {
++ /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
++ /* 0x00 */ 0x0ff33100, 0x0fe33000, 0x0fa33200, 0x0fa33000,
++ /* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++
++ /* UPM Read Burst RAM array entry -> NAND Write CMD */
++ /* 0x08 */ 0x00ff3f30, 0x00ff3c30, 0x0fff3c30, 0x0fff3c35,
++ /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++
++ /* UPM Read Burst RAM array entry -> NAND Write ADDR */
++ /* 0x10 */ 0x00f3ff30, 0x00f3fc30, 0x0ff3fc30, 0x0ff3fc35,
++ /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++
++ /* UPM Write Single RAM array entry -> NAND Write Data */
++ /* 0x18 */ 0x00f33f00, 0x00f33c00, 0x0ff33c00, 0x0ff33c05,
++ /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++
++ /* UPM Write Burst RAM array entry -> unused */
++ /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++ /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++ /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++ /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
++
++ /* UPM Refresh Timer RAM array entry -> unused */
++ /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++ /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++ /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
++
++ /* UPM Exception RAM array entry -> unsused */
++ /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
++};
++
++/* UPM pattern for bus clock = 133.3 MHz */
++static const u32 upm_patt_133[] = {
++ /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
++ /* 0x00 */ 0x0ff33100, 0x0fe33000, 0x0fa33300, 0x0fa33000,
++ /* 0x04 */ 0x0fa33000, 0x0fa33005, 0xfffffc00, 0xfffffc00,
++
++ /* UPM Read Burst RAM array entry -> NAND Write CMD */
++ /* 0x08 */ 0x00ff3f30, 0x00ff3d30, 0x0fff3d30, 0x0fff3c35,
++ /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++
++ /* UPM Read Burst RAM array entry -> NAND Write ADDR */
++ /* 0x10 */ 0x00f3ff30, 0x00f3fd30, 0x0ff3fd30, 0x0ff3fc35,
++ /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++
++ /* UPM Write Single RAM array entry -> NAND Write Data */
++ /* 0x18 */ 0x00f33f00, 0x00f33d00, 0x0ff33d00, 0x0ff33c05,
++ /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++
++ /* UPM Write Burst RAM array entry -> unused */
++ /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++ /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++ /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++ /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
++
++ /* UPM Refresh Timer RAM array entry -> unused */
++ /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++ /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++ /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
++
++ /* UPM Exception RAM array entry -> unsused */
++ /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
++};
++
++/* UPM pattern for bus clock = 166.7 MHz */
++static const u32 upm_patt_167[] = {
++ /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
++ /* 0x00 */ 0x0ff33200, 0x0fe33000, 0x0fa33300, 0x0fa33300,
++ /* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++
++ /* UPM Read Burst RAM array entry -> NAND Write CMD */
++ /* 0x08 */ 0x00ff3f30, 0x00ff3f30, 0x0fff3e30, 0xffff3c35,
++ /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++
++ /* UPM Read Burst RAM array entry -> NAND Write ADDR */
++ /* 0x10 */ 0x00f3ff30, 0x00f3ff30, 0x0ff3fe30, 0x0ff3fc35,
++ /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++
++ /* UPM Write Single RAM array entry -> NAND Write Data */
++ /* 0x18 */ 0x00f33f00, 0x00f33f00, 0x0ff33e00, 0x0ff33c05,
++ /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++
++ /* UPM Write Burst RAM array entry -> unused */
++ /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++ /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++ /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++ /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
++
++ /* UPM Refresh Timer RAM array entry -> unused */
++ /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++ /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
++ /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
++
++ /* UPM Exception RAM array entry -> unsused */
++ /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
++};
++
++/* Supported UPM timings */
++struct upm_freq upm_freq_table[] = {
++ /* nominal freq. | ptr to table | GPL4 dis. | EHTR | EAD */
++ {25000000, upm_patt_25, 1, 0, 0},
++ {33333333, upm_patt_33, 1, 0, 0},
++ {41666666, upm_patt_42, 1, 0, 0},
++ {50000000, upm_patt_50, 0, 0, 0},
++ {66666666, upm_patt_67, 0, 0, 0},
++ {83333333, upm_patt_83, 0, 0, 0},
++ {100000000, upm_patt_100, 0, 1, 1},
++ {133333333, upm_patt_133, 0, 1, 1},
++ {166666666, upm_patt_167, 0, 1, 1},
++};
++
++#define UPM_FREQS (sizeof(upm_freq_table) / sizeof(struct upm_freq))
++
++volatile const u32 *nand_upm_patt;
++
++/*
++ * write into UPMB ram
++ */
++static void upmb_write (u_char addr, ulong val)
++{
++ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
++
++ out_be32 (&lbc->mdr, val);
++
++ clrsetbits_be32(&lbc->mbmr, MxMR_MAD_MSK,
++ MxMR_OP_WARR | (addr & MxMR_MAD_MSK));
++
++ /* dummy access to perform write */
++ out_8 ((void __iomem *)CONFIG_SYS_NAND_BASE, 0);
++
++ clrbits_be32(&lbc->mbmr, MxMR_OP_WARR);
++}
++
++/*
++ * Initialize UPM for NAND flash access.
++ */
++static void nand_upm_setup (volatile fsl_lbc_t *lbc)
++{
++ uint i, j;
++ uint or3 = CONFIG_SYS_OR3_PRELIM;
++ uint clock = get_lbc_clock ();
++
++ set_lbc_br(3, 0); /* disable bank and reset all bits */
++ set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
++
++ /*
++ * Search appropriate UPM table for bus clock.
++ * If the bus clock exceeds a tolerated value, take the UPM timing for
++ * the next higher supported frequency to ensure that access works
++ * (even the access may be slower then).
++ */
++ for (i = 0; (i < UPM_FREQS) && (clock > upm_freq_table[i].freq); i++)
++ ;
++
++ if (i >= UPM_FREQS)
++ /* no valid entry found */
++ /* take last entry with configuration for max. bus clock */
++ i--;
++
++ if (upm_freq_table[i].ehtr) {
++ /* EHTR must be set due to TQM8548 timing specification */
++ or3 |= OR_UPM_EHTR;
++ }
++ if (upm_freq_table[i].ead)
++ /* EAD must be set due to TQM8548 timing specification */
++ or3 |= OR_UPM_EAD;
++
++ set_lbc_or(3, or3);
++
++ /* Assign address of table */
++ nand_upm_patt = upm_freq_table[i].upm_patt;
++
++ for (j = 0; j < 64; j++) {
++ upmb_write (j, *nand_upm_patt);
++ nand_upm_patt++;
++ }
++
++ /* Put UPM back to normal operation mode */
++ if (upm_freq_table[i].gpl4_disable)
++ /* GPL4 must be disabled according to timing specification */
++ out_be32 (&lbc->mbmr, MxMR_OP_NORM | MxMR_GPL_x4DIS);
++
++ return;
++}
++
++static struct fsl_upm_nand fun = {
++ .width = 8,
++ .upm_cmd_offset = 0x08,
++ .upm_addr_offset = 0x10,
++ .upm_mar_chip_offset = CONFIG_SYS_NAND_CS_DIST,
++ .chip_offset = CONFIG_SYS_NAND_CS_DIST,
++ .chip_delay = NAND_BIG_DELAY_US,
++ .wait_flags = FSL_UPM_WAIT_RUN_PATTERN | FSL_UPM_WAIT_WRITE_BUFFER,
++};
++
++void board_nand_select_device (struct nand_chip *nand, int chip)
++{
++}
++
++int board_nand_init (struct nand_chip *nand)
++{
++ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
++
++ if (!nand_upm_patt)
++ nand_upm_setup (lbc);
++
++ fun.upm.io_addr = nand->IO_ADDR_R;
++ fun.upm.mxmr = (void __iomem *)&lbc->mbmr;
++ fun.upm.mdr = (void __iomem *)&lbc->mdr;
++ fun.upm.mar = (void __iomem *)&lbc->mar;
++
++ return fsl_upm_nand_init (nand, &fun);
++}
+diff --git a/board/tqc/tqm85xx/sdram.c b/board/tqc/tqm85xx/sdram.c
+new file mode 100644
+index 0000000..baf073e
+--- /dev/null
++++ b/board/tqc/tqm85xx/sdram.c
+@@ -0,0 +1,436 @@
++
++/*
++ * (C) Copyright 2005
++ * Stefan Roese, DENX Software Engineering, sr at denx.de.
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <common.h>
++#include <asm/processor.h>
++#include <asm/immap_85xx.h>
++#include <asm/processor.h>
++#include <asm/mmu.h>
++
++struct sdram_conf_s {
++ unsigned long size;
++ unsigned long reg;
++#ifdef CONFIG_TQM8548
++ unsigned long refresh;
++#endif /* CONFIG_TQM8548 */
++};
++
++typedef struct sdram_conf_s sdram_conf_t;
++
++#ifdef CONFIG_TQM8548
++#ifdef CONFIG_TQM8548_AG
++sdram_conf_t ddr_cs_conf[] = {
++ {(1024 << 20), 0x80044202, 0x0002D000}, /* 1024MB, 14x10(4) */
++ { (512 << 20), 0x80044102, 0x0001A000}, /* 512MB, 13x10(4) */
++ { (256 << 20), 0x80040102, 0x00014000}, /* 256MB, 13x10(4) */
++ { (128 << 20), 0x80040101, 0x0000C000}, /* 128MB, 13x9(4) */
++};
++#else /* !CONFIG_TQM8548_AG */
++sdram_conf_t ddr_cs_conf[] = {
++ {(512 << 20), 0x80044102, 0x0001A000}, /* 512MB, 13x10(4) */
++ {(256 << 20), 0x80040102, 0x00014000}, /* 256MB, 13x10(4) */
++ {(128 << 20), 0x80040101, 0x0000C000}, /* 128MB, 13x9(4) */
++};
++#endif /* CONFIG_TQM8548_AG */
++#else /* !CONFIG_TQM8548 */
++sdram_conf_t ddr_cs_conf[] = {
++ {(512 << 20), 0x80000202}, /* 512MB, 14x10(4) */
++ {(256 << 20), 0x80000102}, /* 256MB, 13x10(4) */
++ {(128 << 20), 0x80000101}, /* 128MB, 13x9(4) */
++ {( 64 << 20), 0x80000001}, /* 64MB, 12x9(4) */
++};
++#endif /* CONFIG_TQM8548 */
++
++#define N_DDR_CS_CONF (sizeof(ddr_cs_conf) / sizeof(ddr_cs_conf[0]))
++
++int cas_latency (void);
++static phys_size_t sdram_setup(int);
++
++/*
++ * Autodetect onboard DDR SDRAM on 85xx platforms
++ *
++ * NOTE: Some of the hardcoded values are hardware dependant,
++ * so this should be extended for other future boards
++ * using this routine!
++ */
++phys_size_t fixed_sdram(void)
++{
++ int casl = 0;
++ phys_size_t dram_size = 0;
++
++ casl = cas_latency();
++ dram_size = sdram_setup(casl);
++ if ((dram_size == 0) && (casl != CONFIG_DDR_DEFAULT_CL)) {
++ /*
++ * Try again with default CAS latency
++ */
++ printf("Problem with CAS lantency, using default CL %d/10!\n",
++ CONFIG_DDR_DEFAULT_CL);
++ dram_size = sdram_setup(CONFIG_DDR_DEFAULT_CL);
++ puts(" ");
++ }
++ return dram_size;
++}
++
++static phys_size_t sdram_setup(int casl)
++{
++ int i;
++ volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
++#ifdef CONFIG_TQM8548
++ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
++#if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE)
++ volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
++#endif
++#else /* !CONFIG_TQM8548 */
++ unsigned long cfg_ddr_timing1;
++ unsigned long cfg_ddr_mode;
++#endif /* CONFIG_TQM8548 */
++
++ /*
++ * Disable memory controller.
++ */
++ ddr->cs0_config = 0;
++ ddr->sdram_cfg = 0;
++
++#ifdef CONFIG_TQM8548
++ /* Timing and refresh settings for DDR2-533 and below */
++
++ ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24;
++ ddr->cs0_config = ddr_cs_conf[0].reg;
++ ddr->timing_cfg_3 = 0x00020000;
++
++ /* TIMING CFG 1, 533MHz
++ * PRETOACT: 4 Clocks
++ * ACTTOPRE: 12 Clocks
++ * ACTTORW: 4 Clocks
++ * CASLAT: 4 Clocks
++ * REFREC: EXT_REFREC:REFREC 53 Clocks
++ * WRREC: 4 Clocks
++ * ACTTOACT: 3 Clocks
++ * WRTORD: 2 Clocks
++ */
++ ddr->timing_cfg_1 = 0x4C47D432;
++
++ /* TIMING CFG 2, 533MHz
++ * ADD_LAT: 3 Clocks
++ * CPO: READLAT + 1
++ * WR_LAT: 3 Clocks
++ * RD_TO_PRE: 2 Clocks
++ * WR_DATA_DELAY: 1/2 Clock
++ * CKE_PLS: 3 Clock
++ * FOUR_ACT: 14 Clocks
++ */
++ ddr->timing_cfg_2 = 0x331848CE;
++
++ /* DDR SDRAM Mode, 533MHz
++ * MRS: Extended Mode Register
++ * OUT: Outputs enabled
++ * RDQS: no
++ * DQS: enabled
++ * OCD: default state
++ * RTT: 75 Ohms
++ * Posted CAS: 3 Clocks
++ * ODS: reduced strength
++ * DLL: enabled
++ * MR: Mode Register
++ * PD: fast exit
++ * WR: 4 Clocks
++ * DLL: no DLL reset
++ * TM: normal
++ * CAS latency: 4 Clocks
++ * BT: sequential
++ * Burst length: 4
++ */
++ ddr->sdram_mode = 0x439E0642;
++
++ /* DDR SDRAM Interval, 533MHz
++ * REFINT: 1040 Clocks
++ * BSTOPRE: 256
++ */
++ ddr->sdram_interval = (1040 << 16) | 0x100;
++
++ /*
++ * Workaround for erratum DDR19 according to MPC8548 Device Errata
++ * document, Rev. 1: DDR IO receiver must be set to an acceptable
++ * bias point by modifying a hidden register.
++ */
++ if (SVR_REV (get_svr ()) < 0x21)
++ gur->ddrioovcr = 0x90000000; /* enable, VSEL 1.8V */
++
++ /* DDR SDRAM CFG 2
++ * FRC_SR: normal mode
++ * SR_IE: no self-refresh interrupt
++ * DLL_RST_DIS: don't care, leave at reset value
++ * DQS_CFG: differential DQS signals
++ * ODT_CFG: assert ODT to internal IOs only during reads to DRAM
++ * LVWx_CFG: don't care, leave at reset value
++ * NUM_PR: 1 refresh will be issued at a time
++ * DM_CFG: don't care, leave at reset value
++ * D_INIT: no data initialization
++ */
++ ddr->sdram_cfg_2 = 0x04401000;
++
++ /* DDR SDRAM MODE 2
++ * MRS: Extended Mode Register 2
++ */
++ ddr->sdram_mode_2 = 0x8000C000;
++
++ /* DDR SDRAM CLK CNTL
++ * CLK_ADJUST: 1/2 Clock 0x02000000
++ * CLK_ADJUST: 5/8 Clock 0x02800000
++ */
++ ddr->sdram_clk_cntl = 0x02800000;
++
++ /* wait for clock stabilization */
++ asm ("sync;isync;msync");
++ udelay (1000);
++
++#if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE)
++ /*
++ * Workaround for erratum DDR20 according to MPC8548 Device Errata
++ * document, Rev. 1: "CKE signal may not function correctly after
++ * assertion of HRESET"
++ */
++
++ /* 1. Configure DDR register as is done in normal DDR configuration.
++ * Do not set DDR_SDRAM_CFG[MEM_EN].
++ *
++ * 2. Set reserved bit EEBACR[3] at offset 0x1000
++ */
++ ecm->eebacr |= 0x10000000;
++
++ /*
++ * 3. Before DDR_SDRAM_CFG[MEM_EN] is set, write DDR_SDRAM_CFG_2[D_INIT]
++ *
++ * DDR_SDRAM_CFG_2:
++ * FRC_SR: normal mode
++ * SR_IE: no self-refresh interrupt
++ * DLL_RST_DIS: don't care, leave at reset value
++ * DQS_CFG: differential DQS signals
++ * ODT_CFG: assert ODT to internal IOs only during reads to DRAM
++ * LVWx_CFG: don't care, leave at reset value
++ * NUM_PR: 1 refresh will be issued at a time
++ * DM_CFG: don't care, leave at reset value
++ * D_INIT: enable data initialization
++ */
++ ddr->sdram_cfg_2 |= 0x00000010;
++
++ /*
++ * 4. Before DDR_SDRAM_CFG[MEM_EN] set, write D3[21] to disable data
++ * training
++ */
++ ddr->debug[2] |= 0x00000400;
++
++ /*
++ * 5. Wait 200 micro-seconds
++ */
++ udelay (200);
++
++ /*
++ * 6. Set DDR_SDRAM_CFG[MEM_EN]
++ *
++ * BTW, initialize DDR_SDRAM_CFG:
++ * MEM_EN: enabled
++ * SREN: don't care, leave at reset value
++ * ECC_EN: no error report
++ * RD_EN: no registered DIMMs
++ * SDRAM_TYPE: DDR2
++ * DYN_PWR: no power management
++ * 32_BE: don't care, leave at reset value
++ * 8_BE: 4 beat burst
++ * NCAP: don't care, leave at reset value
++ * 2T_EN: 1T Timing
++ * BA_INTLV_CTL: no interleaving
++ * x32_EN: x16 organization
++ * PCHB8: MA[10] for auto-precharge
++ * HSE: half strength for single and 2-layer stacks
++ * (full strength for 3- and 4-layer stacks not
++ * yet considered)
++ * MEM_HALT: no halt
++ * BI: automatic initialization
++ */
++ ddr->sdram_cfg = 0x83000008;
++
++ /*
++ * 7. Poll DDR_SDRAM_CFG_2[D_INIT] until it is cleared by hardware
++ */
++ asm ("sync;isync;msync");
++ while (ddr->sdram_cfg_2 & 0x00000010)
++ asm ("eieio");
++
++ /*
++ * 8. Clear D3[21] to re-enable data training
++ */
++ ddr->debug[2] &= ~0x00000400;
++
++ /*
++ * 9. Set D2(21) to force data training to run
++ */
++ ddr->debug[1] |= 0x00000400;
++
++ /*
++ * 10. Poll on D2[21] until it is cleared by hardware
++ */
++ asm ("sync;isync;msync");
++ while (ddr->debug[1] & 0x00000400)
++ asm ("eieio");
++
++ /*
++ * 11. Clear reserved bit EEBACR[3] at offset 0x1000
++ */
++ ecm->eebacr &= ~0x10000000;
++
++#else /* !(CONFIG_TQM8548_AG || CONFIG_TQM8548_BE) */
++
++ /* DDR SDRAM CLK CNTL
++ * MEM_EN: enabled
++ * SREN: don't care, leave at reset value
++ * ECC_EN: no error report
++ * RD_EN: no register DIMMs
++ * SDRAM_TYPE: DDR2
++ * DYN_PWR: no power management
++ * 32_BE: don't care, leave at reset value
++ * 8_BE: 4 beat burst
++ * NCAP: don't care, leave at reset value
++ * 2T_EN: 1T Timing
++ * BA_INTLV_CTL: no interleaving
++ * x32_EN: x16 organization
++ * PCHB8: MA[10] for auto-precharge
++ * HSE: half strength for single and 2-layer stacks
++ * (full strength for 3- and 4-layer stacks no yet considered)
++ * MEM_HALT: no halt
++ * BI: automatic initialization
++ */
++ ddr->sdram_cfg = 0x83000008;
++
++#endif /* CONFIG_TQM8548_AG || CONFIG_TQM8548_BE */
++
++ asm ("sync; isync; msync");
++ udelay (1000);
++#else /* !CONFIG_TQM8548 */
++ switch (casl) {
++ case 20:
++ cfg_ddr_timing1 = 0x47405331 | (3 << 16);
++ cfg_ddr_mode = 0x40020002 | (2 << 4);
++ break;
++
++ case 25:
++ cfg_ddr_timing1 = 0x47405331 | (4 << 16);
++ cfg_ddr_mode = 0x40020002 | (6 << 4);
++ break;
++
++ case 30:
++ default:
++ cfg_ddr_timing1 = 0x47405331 | (5 << 16);
++ cfg_ddr_mode = 0x40020002 | (3 << 4);
++ break;
++ }
++
++ ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24;
++ ddr->cs0_config = ddr_cs_conf[0].reg;
++ ddr->timing_cfg_1 = cfg_ddr_timing1;
++ ddr->timing_cfg_2 = 0x00000800; /* P9-45,may need tuning */
++ ddr->sdram_mode = cfg_ddr_mode;
++ ddr->sdram_interval = 0x05160100; /* autocharge,no open page */
++ ddr->err_disable = 0x0000000D;
++
++ asm ("sync; isync; msync");
++ udelay (1000);
++
++ ddr->sdram_cfg = 0xc2000000; /* unbuffered,no DYN_PWR */
++ asm ("sync; isync; msync");
++ udelay (1000);
++#endif /* CONFIG_TQM8548 */
++
++ /*
++ * get_ram_size() depends on having tlbs for the DDR, but they are
++ * not yet setup because we don't know the size. Set up a temp
++ * mapping and delete it when done.
++ */
++ setup_ddr_tlbs(CONFIG_SYS_DDR_EARLY_SIZE_MB);
++ for (i = 0; i < N_DDR_CS_CONF; i++) {
++ ddr->cs0_config = ddr_cs_conf[i].reg;
++
++ if (get_ram_size (0, ddr_cs_conf[i].size) ==
++ ddr_cs_conf[i].size) {
++ /*
++ * size detected -> set Chip Select Bounds Register
++ */
++ ddr->cs0_bnds = (ddr_cs_conf[i].size - 1) >> 24;
++
++ break;
++ }
++ }
++ clear_ddr_tlbs(CONFIG_SYS_DDR_EARLY_SIZE_MB);
++
++#ifdef CONFIG_TQM8548
++ if (i < N_DDR_CS_CONF) {
++ /* Adjust refresh rate for DDR2 */
++
++ ddr->timing_cfg_3 = ddr_cs_conf[i].refresh & 0x00070000;
++
++ ddr->timing_cfg_1 = (ddr->timing_cfg_1 & 0xFFFF0FFF) |
++ (ddr_cs_conf[i].refresh & 0x0000F000);
++
++ return ddr_cs_conf[i].size;
++ }
++#endif /* CONFIG_TQM8548 */
++
++ /* return size if detected, else return 0 */
++ return (i < N_DDR_CS_CONF) ? ddr_cs_conf[i].size : 0;
++}
++
++#if defined(CONFIG_SYS_DRAM_TEST)
++int testdram (void)
++{
++ uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
++ uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
++ uint *p;
++
++ printf ("SDRAM test phase 1:\n");
++ for (p = pstart; p < pend; p++)
++ *p = 0xaaaaaaaa;
++
++ for (p = pstart; p < pend; p++) {
++ if (*p != 0xaaaaaaaa) {
++ printf ("SDRAM test fails at: %08x\n", (uint) p);
++ return 1;
++ }
++ }
++
++ printf ("SDRAM test phase 2:\n");
++ for (p = pstart; p < pend; p++)
++ *p = 0x55555555;
++
++ for (p = pstart; p < pend; p++) {
++ if (*p != 0x55555555) {
++ printf ("SDRAM test fails at: %08x\n", (uint) p);
++ return 1;
++ }
++ }
++
++ printf ("SDRAM test passed.\n");
++ return 0;
++}
++#endif
+diff --git a/board/tqc/tqm85xx/tlb.c b/board/tqc/tqm85xx/tlb.c
+new file mode 100644
+index 0000000..f9f8cc9
+--- /dev/null
++++ b/board/tqc/tqm85xx/tlb.c
+@@ -0,0 +1,214 @@
++/*
++ * Copyright 2008 Freescale Semiconductor, Inc.
++ *
++ * (C) Copyright 2000
++ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <common.h>
++#include <asm/mmu.h>
++
++struct fsl_e_tlb_entry tlb_table[] = {
++ /* TLB 0 - for temp stack in cache */
++ SET_TLB_ENTRY (0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
++ MAS3_SX | MAS3_SW | MAS3_SR, 0,
++ 0, 0, BOOKE_PAGESZ_4K, 0),
++ SET_TLB_ENTRY (0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
++ CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
++ MAS3_SX | MAS3_SW | MAS3_SR, 0,
++ 0, 0, BOOKE_PAGESZ_4K, 0),
++ SET_TLB_ENTRY (0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
++ CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
++ MAS3_SX | MAS3_SW | MAS3_SR, 0,
++ 0, 0, BOOKE_PAGESZ_4K, 0),
++ SET_TLB_ENTRY (0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
++ CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
++ MAS3_SX | MAS3_SW | MAS3_SR, 0,
++ 0, 0, BOOKE_PAGESZ_4K, 0),
++
++#ifndef CONFIG_TQM_BIGFLASH
++ /*
++ * TLB 0, 1: 128M Non-cacheable, guarded
++ * 0xf8000000 128M FLASH
++ * Out of reset this entry is only 4K.
++ */
++ SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
++ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
++ 0, 1, BOOKE_PAGESZ_64M, 1),
++ SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE + 0x4000000,
++ CONFIG_SYS_FLASH_BASE + 0x4000000,
++ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
++ 0, 0, BOOKE_PAGESZ_64M, 1),
++
++ /*
++ * TLB 2: 256M Non-cacheable, guarded
++ * 0x80000000 256M PCI1 MEM First half
++ */
++ SET_TLB_ENTRY (1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
++ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
++ 0, 2, BOOKE_PAGESZ_256M, 1),
++
++ /*
++ * TLB 3: 256M Non-cacheable, guarded
++ * 0x90000000 256M PCI1 MEM Second half
++ */
++ SET_TLB_ENTRY (1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
++ CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
++ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
++ 0, 3, BOOKE_PAGESZ_256M, 1),
++
++#ifdef CONFIG_PCIE1
++ /*
++ * TLB 4: 256M Non-cacheable, guarded
++ * 0xc0000000 256M PCI express MEM First half
++ */
++ SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BUS, CONFIG_SYS_PCIE1_MEM_BUS,
++ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
++ 0, 4, BOOKE_PAGESZ_256M, 1),
++
++ /*
++ * TLB 5: 256M Non-cacheable, guarded
++ * 0xd0000000 256M PCI express MEM Second half
++ */
++ SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BUS + 0x10000000,
++ CONFIG_SYS_PCIE1_MEM_BUS + 0x10000000,
++ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
++ 0, 5, BOOKE_PAGESZ_256M, 1),
++#else /* !CONFIG_PCIE */
++ /*
++ * TLB 4: 256M Non-cacheable, guarded
++ * 0xc0000000 256M Rapid IO MEM First half
++ */
++ SET_TLB_ENTRY (1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE,
++ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
++ 0, 4, BOOKE_PAGESZ_256M, 1),
++
++ /*
++ * TLB 5: 256M Non-cacheable, guarded
++ * 0xd0000000 256M Rapid IO MEM Second half
++ */
++ SET_TLB_ENTRY (1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
++ CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
++ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
++ 0, 5, BOOKE_PAGESZ_256M, 1),
++#endif /* CONFIG_PCIE */
++
++ /*
++ * TLB 6: 64M Non-cacheable, guarded
++ * 0xe0000000 1M CCSRBAR
++ * 0xe2000000 16M PCI1 IO
++ * 0xe3000000 16M CAN and NAND Flash
++ */
++ SET_TLB_ENTRY (1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
++ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
++ 0, 6, BOOKE_PAGESZ_64M, 1),
++#ifdef CONFIG_PCIE1
++ /*
++ * TLB 9: 16M Non-cacheable, guarded
++ * 0xef000000 16M PCI express IO
++ */
++ SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_IO_BUS, CONFIG_SYS_PCIE1_IO_BUS,
++ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
++ 0, 9, BOOKE_PAGESZ_16M, 1),
++#endif /* CONFIG_PCIE */
++
++#else /* CONFIG_TQM_BIGFLASH */
++
++ /*
++ * TLB 0,1,2,3: 1G Non-cacheable, guarded
++ * 0xc0000000 1G FLASH
++ * Out of reset this entry is only 4K.
++ */
++ SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
++ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
++ 0, 3, BOOKE_PAGESZ_256M, 1),
++ SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE + 0x10000000,
++ CONFIG_SYS_FLASH_BASE + 0x10000000,
++ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
++ 0, 2, BOOKE_PAGESZ_256M, 1),
++ SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE + 0x20000000,
++ CONFIG_SYS_FLASH_BASE + 0x20000000,
++ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
++ 0, 1, BOOKE_PAGESZ_256M, 1),
++ SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE + 0x30000000,
++ CONFIG_SYS_FLASH_BASE + 0x30000000,
++ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
++ 0, 0, BOOKE_PAGESZ_256M, 1),
++
++ /*
++ * TLB 4: 256M Non-cacheable, guarded
++ * 0x80000000 256M PCI1 MEM First half
++ */
++ SET_TLB_ENTRY (1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
++ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
++ 0, 4, BOOKE_PAGESZ_256M, 1),
++
++ /*
++ * TLB 5: 256M Non-cacheable, guarded
++ * 0x90000000 256M PCI1 MEM Second half
++ */
++ SET_TLB_ENTRY (1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
++ CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
++ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
++ 0, 5, BOOKE_PAGESZ_256M, 1),
++
++#ifdef CONFIG_PCIE1
++ /*
++ * TLB 6: 256M Non-cacheable, guarded
++ * 0xc0000000 256M PCI express MEM First half
++ */
++ SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BUS, CONFIG_SYS_PCIE1_MEM_BUS,
++ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
++ 0, 6, BOOKE_PAGESZ_256M, 1),
++#else /* !CONFIG_PCIE */
++ /*
++ * TLB 6: 256M Non-cacheable, guarded
++ * 0xb0000000 256M Rapid IO MEM First half
++ */
++ SET_TLB_ENTRY (1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE,
++ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
++ 0, 6, BOOKE_PAGESZ_256M, 1),
++
++#endif /* CONFIG_PCIE */
++
++ /*
++ * TLB 7: 64M Non-cacheable, guarded
++ * 0xa0000000 1M CCSRBAR
++ * 0xa2000000 16M PCI1 IO
++ * 0xa3000000 16M CAN and NAND Flash
++ */
++ SET_TLB_ENTRY (1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
++ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
++ 0, 7, BOOKE_PAGESZ_64M, 1),
++#ifdef CONFIG_PCIE1
++ /*
++ * TLB 10: 16M Non-cacheable, guarded
++ * 0xaf000000 16M PCI express IO
++ */
++ SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_IO_BASE, CONFIG_SYS_PCIE1_IO_BASE,
++ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
++ 0, 10, BOOKE_PAGESZ_16M, 1),
++#endif /* CONFIG_PCIE */
++
++#endif /* CONFIG_TQM_BIGFLASH */
++};
++
++int num_tlb_entries = ARRAY_SIZE (tlb_table);
+diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c
+new file mode 100644
+index 0000000..8fb73ab
+--- /dev/null
++++ b/board/tqc/tqm85xx/tqm85xx.c
+@@ -0,0 +1,626 @@
++/*
++ * (C) Copyright 2008 Wolfgang Grandegger <wg at denx.de>
++ *
++ * (C) Copyright 2006
++ * Thomas Waehner, TQ-Systems GmbH, thomas.waehner at tqs.de.
++ *
++ * (C) Copyright 2005
++ * Stefan Roese, DENX Software Engineering, sr at denx.de.
++ *
++ * Copyright 2004 Freescale Semiconductor.
++ * (C) Copyright 2002,2003, Motorola Inc.
++ * Xianghua Xiao, (X.Xiao at motorola.com)
++ *
++ * (C) Copyright 2002 Scott McNutt <smcnutt at artesyncp.com>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <common.h>
++#include <pci.h>
++#include <asm/processor.h>
++#include <asm/immap_85xx.h>
++#include <asm/fsl_pci.h>
++#include <asm/io.h>
++#include <asm/fsl_serdes.h>
++#include <linux/compiler.h>
++#include <ioports.h>
++#include <flash.h>
++#include <libfdt.h>
++#include <fdt_support.h>
++#include <netdev.h>
++
++DECLARE_GLOBAL_DATA_PTR;
++
++extern flash_info_t flash_info[]; /* FLASH chips info */
++
++void local_bus_init (void);
++ulong flash_get_size (ulong base, int banknum);
++
++#ifdef CONFIG_PS2MULT
++void ps2mult_early_init (void);
++#endif
++
++#ifdef CONFIG_CPM2
++/*
++ * I/O Port configuration table
++ *
++ * if conf is 1, then that port pin will be configured at boot time
++ * according to the five values podr/pdir/ppar/psor/pdat for that entry
++ */
++
++const iop_conf_t iop_conf_tab[4][32] = {
++
++ /* Port A: conf, ppar, psor, pdir, podr, pdat */
++ {
++ {1, 1, 1, 0, 0, 0}, /* PA31: FCC1 MII COL */
++ {1, 1, 1, 0, 0, 0}, /* PA30: FCC1 MII CRS */
++ {1, 1, 1, 1, 0, 0}, /* PA29: FCC1 MII TX_ER */
++ {1, 1, 1, 1, 0, 0}, /* PA28: FCC1 MII TX_EN */
++ {1, 1, 1, 0, 0, 0}, /* PA27: FCC1 MII RX_DV */
++ {1, 1, 1, 0, 0, 0}, /* PA26: FCC1 MII RX_ER */
++ {0, 1, 0, 1, 0, 0}, /* PA25: FCC1 ATMTXD[0] */
++ {0, 1, 0, 1, 0, 0}, /* PA24: FCC1 ATMTXD[1] */
++ {0, 1, 0, 1, 0, 0}, /* PA23: FCC1 ATMTXD[2] */
++ {0, 1, 0, 1, 0, 0}, /* PA22: FCC1 ATMTXD[3] */
++ {1, 1, 0, 1, 0, 0}, /* PA21: FCC1 MII TxD[3] */
++ {1, 1, 0, 1, 0, 0}, /* PA20: FCC1 MII TxD[2] */
++ {1, 1, 0, 1, 0, 0}, /* PA19: FCC1 MII TxD[1] */
++ {1, 1, 0, 1, 0, 0}, /* PA18: FCC1 MII TxD[0] */
++ {1, 1, 0, 0, 0, 0}, /* PA17: FCC1 MII RxD[0] */
++ {1, 1, 0, 0, 0, 0}, /* PA16: FCC1 MII RxD[1] */
++ {1, 1, 0, 0, 0, 0}, /* PA15: FCC1 MII RxD[2] */
++ {1, 1, 0, 0, 0, 0}, /* PA14: FCC1 MII RxD[3] */
++ {0, 1, 0, 0, 0, 0}, /* PA13: FCC1 ATMRXD[3] */
++ {0, 1, 0, 0, 0, 0}, /* PA12: FCC1 ATMRXD[2] */
++ {0, 1, 0, 0, 0, 0}, /* PA11: FCC1 ATMRXD[1] */
++ {0, 1, 0, 0, 0, 0}, /* PA10: FCC1 ATMRXD[0] */
++ {0, 1, 1, 1, 0, 0}, /* PA9 : FCC1 L1TXD */
++ {0, 1, 1, 0, 0, 0}, /* PA8 : FCC1 L1RXD */
++ {0, 0, 0, 1, 0, 0}, /* PA7 : PA7 */
++ {0, 1, 1, 1, 0, 0}, /* PA6 : TDM A1 L1RSYNC */
++ {0, 0, 0, 1, 0, 0}, /* PA5 : PA5 */
++ {0, 0, 0, 1, 0, 0}, /* PA4 : PA4 */
++ {0, 0, 0, 1, 0, 0}, /* PA3 : PA3 */
++ {0, 0, 0, 1, 0, 0}, /* PA2 : PA2 */
++ {0, 0, 0, 0, 0, 0}, /* PA1 : FREERUN */
++ {0, 0, 0, 1, 0, 0} /* PA0 : PA0 */
++ },
++
++ /* Port B: conf, ppar, psor, pdir, podr, pdat */
++ {
++ {1, 1, 0, 1, 0, 0}, /* PB31: FCC2 MII TX_ER */
++ {1, 1, 0, 0, 0, 0}, /* PB30: FCC2 MII RX_DV */
++ {1, 1, 1, 1, 0, 0}, /* PB29: FCC2 MII TX_EN */
++ {1, 1, 0, 0, 0, 0}, /* PB28: FCC2 MII RX_ER */
++ {1, 1, 0, 0, 0, 0}, /* PB27: FCC2 MII COL */
++ {1, 1, 0, 0, 0, 0}, /* PB26: FCC2 MII CRS */
++ {1, 1, 0, 1, 0, 0}, /* PB25: FCC2 MII TxD[3] */
++ {1, 1, 0, 1, 0, 0}, /* PB24: FCC2 MII TxD[2] */
++ {1, 1, 0, 1, 0, 0}, /* PB23: FCC2 MII TxD[1] */
++ {1, 1, 0, 1, 0, 0}, /* PB22: FCC2 MII TxD[0] */
++ {1, 1, 0, 0, 0, 0}, /* PB21: FCC2 MII RxD[0] */
++ {1, 1, 0, 0, 0, 0}, /* PB20: FCC2 MII RxD[1] */
++ {1, 1, 0, 0, 0, 0}, /* PB19: FCC2 MII RxD[2] */
++ {1, 1, 0, 0, 0, 0}, /* PB18: FCC2 MII RxD[3] */
++ {1, 1, 0, 0, 0, 0}, /* PB17: FCC3:RX_DIV */
++ {1, 1, 0, 0, 0, 0}, /* PB16: FCC3:RX_ERR */
++ {1, 1, 0, 1, 0, 0}, /* PB15: FCC3:TX_ERR */
++ {1, 1, 0, 1, 0, 0}, /* PB14: FCC3:TX_EN */
++ {1, 1, 0, 0, 0, 0}, /* PB13: FCC3:COL */
++ {1, 1, 0, 0, 0, 0}, /* PB12: FCC3:CRS */
++ {1, 1, 0, 0, 0, 0}, /* PB11: FCC3:RXD */
++ {1, 1, 0, 0, 0, 0}, /* PB10: FCC3:RXD */
++ {1, 1, 0, 0, 0, 0}, /* PB9 : FCC3:RXD */
++ {1, 1, 0, 0, 0, 0}, /* PB8 : FCC3:RXD */
++ {1, 1, 0, 1, 0, 0}, /* PB7 : FCC3:TXD */
++ {1, 1, 0, 1, 0, 0}, /* PB6 : FCC3:TXD */
++ {1, 1, 0, 1, 0, 0}, /* PB5 : FCC3:TXD */
++ {1, 1, 0, 1, 0, 0}, /* PB4 : FCC3:TXD */
++ {0, 0, 0, 0, 0, 0}, /* PB3 : pin doesn't exist */
++ {0, 0, 0, 0, 0, 0}, /* PB2 : pin doesn't exist */
++ {0, 0, 0, 0, 0, 0}, /* PB1 : pin doesn't exist */
++ {0, 0, 0, 0, 0, 0} /* PB0 : pin doesn't exist */
++ },
++
++ /* Port C: conf, ppar, psor, pdir, podr, pdat */
++ {
++ {0, 0, 0, 1, 0, 0}, /* PC31: PC31 */
++ {0, 0, 0, 1, 0, 0}, /* PC30: PC30 */
++ {0, 1, 1, 0, 0, 0}, /* PC29: SCC1 EN *CLSN */
++ {0, 0, 0, 1, 0, 0}, /* PC28: PC28 */
++ {0, 0, 0, 1, 0, 0}, /* PC27: UART Clock in */
++ {0, 0, 0, 1, 0, 0}, /* PC26: PC26 */
++ {0, 0, 0, 1, 0, 0}, /* PC25: PC25 */
++ {0, 0, 0, 1, 0, 0}, /* PC24: PC24 */
++ {0, 1, 0, 1, 0, 0}, /* PC23: ATMTFCLK */
++ {0, 1, 0, 0, 0, 0}, /* PC22: ATMRFCLK */
++ {1, 1, 0, 0, 0, 0}, /* PC21: SCC1 EN RXCLK */
++ {1, 1, 0, 0, 0, 0}, /* PC20: SCC1 EN TXCLK */
++ {1, 1, 0, 0, 0, 0}, /* PC19: FCC2 MII RX_CLK CLK13 */
++ {1, 1, 0, 0, 0, 0}, /* PC18: FCC Tx Clock (CLK14) */
++ {1, 1, 0, 0, 0, 0}, /* PC17: PC17 */
++ {1, 1, 0, 0, 0, 0}, /* PC16: FCC Tx Clock (CLK16) */
++ {0, 1, 0, 0, 0, 0}, /* PC15: PC15 */
++ {0, 1, 0, 0, 0, 0}, /* PC14: SCC1 EN *CD */
++ {0, 1, 0, 0, 0, 0}, /* PC13: PC13 */
++ {0, 1, 0, 1, 0, 0}, /* PC12: PC12 */
++ {0, 0, 0, 1, 0, 0}, /* PC11: LXT971 transmit control */
++ {0, 0, 0, 1, 0, 0}, /* PC10: FETHMDC */
++ {0, 0, 0, 0, 0, 0}, /* PC9 : FETHMDIO */
++ {0, 0, 0, 1, 0, 0}, /* PC8 : PC8 */
++ {0, 0, 0, 1, 0, 0}, /* PC7 : PC7 */
++ {0, 0, 0, 1, 0, 0}, /* PC6 : PC6 */
++ {0, 0, 0, 1, 0, 0}, /* PC5 : PC5 */
++ {0, 0, 0, 1, 0, 0}, /* PC4 : PC4 */
++ {0, 0, 0, 1, 0, 0}, /* PC3 : PC3 */
++ {0, 0, 0, 1, 0, 1}, /* PC2 : ENET FDE */
++ {0, 0, 0, 1, 0, 0}, /* PC1 : ENET DSQE */
++ {0, 0, 0, 1, 0, 0}, /* PC0 : ENET LBK */
++ },
++
++ /* Port D: conf, ppar, psor, pdir, podr, pdat */
++ {
++#ifdef CONFIG_TQM8560
++ {1, 1, 0, 0, 0, 0}, /* PD31: SCC1 EN RxD */
++ {1, 1, 1, 1, 0, 0}, /* PD30: SCC1 EN TxD */
++ {1, 1, 0, 1, 0, 0}, /* PD29: SCC1 EN TENA */
++#else /* !CONFIG_TQM8560 */
++ {0, 0, 0, 0, 0, 0}, /* PD31: PD31 */
++ {0, 0, 0, 0, 0, 0}, /* PD30: PD30 */
++ {0, 0, 0, 0, 0, 0}, /* PD29: PD29 */
++#endif /* CONFIG_TQM8560 */
++ {1, 1, 0, 0, 0, 0}, /* PD28: PD28 */
++ {1, 1, 0, 1, 0, 0}, /* PD27: PD27 */
++ {1, 1, 0, 1, 0, 0}, /* PD26: PD26 */
++ {0, 0, 0, 1, 0, 0}, /* PD25: PD25 */
++ {0, 0, 0, 1, 0, 0}, /* PD24: PD24 */
++ {0, 0, 0, 1, 0, 0}, /* PD23: PD23 */
++ {0, 0, 0, 1, 0, 0}, /* PD22: PD22 */
++ {0, 0, 0, 1, 0, 0}, /* PD21: PD21 */
++ {0, 0, 0, 1, 0, 0}, /* PD20: PD20 */
++ {0, 0, 0, 1, 0, 0}, /* PD19: PD19 */
++ {0, 0, 0, 1, 0, 0}, /* PD18: PD18 */
++ {0, 1, 0, 0, 0, 0}, /* PD17: FCC1 ATMRXPRTY */
++ {0, 1, 0, 1, 0, 0}, /* PD16: FCC1 ATMTXPRTY */
++ {0, 1, 1, 0, 1, 0}, /* PD15: I2C SDA */
++ {0, 0, 0, 1, 0, 0}, /* PD14: LED */
++ {0, 0, 0, 0, 0, 0}, /* PD13: PD13 */
++ {0, 0, 0, 0, 0, 0}, /* PD12: PD12 */
++ {0, 0, 0, 0, 0, 0}, /* PD11: PD11 */
++ {0, 0, 0, 0, 0, 0}, /* PD10: PD10 */
++ {0, 1, 0, 1, 0, 0}, /* PD9 : SMC1 TXD */
++ {0, 1, 0, 0, 0, 0}, /* PD8 : SMC1 RXD */
++ {0, 0, 0, 1, 0, 1}, /* PD7 : PD7 */
++ {0, 0, 0, 1, 0, 1}, /* PD6 : PD6 */
++ {0, 0, 0, 1, 0, 1}, /* PD5 : PD5 */
++ {0, 0, 0, 1, 0, 1}, /* PD4 : PD4 */
++ {0, 0, 0, 0, 0, 0}, /* PD3 : pin doesn't exist */
++ {0, 0, 0, 0, 0, 0}, /* PD2 : pin doesn't exist */
++ {0, 0, 0, 0, 0, 0}, /* PD1 : pin doesn't exist */
++ {0, 0, 0, 0, 0, 0} /* PD0 : pin doesn't exist */
++ }
++};
++#endif /* CONFIG_CPM2 */
++
++#define CASL_STRING1 "casl=xx"
++#define CASL_STRING2 "casl="
++
++static const int casl_table[] = { 20, 25, 30 };
++#define N_CASL (sizeof(casl_table) / sizeof(casl_table[0]))
++
++int cas_latency (void)
++{
++ char buf[128];
++ int casl;
++ int val;
++ int i;
++
++ casl = CONFIG_DDR_DEFAULT_CL;
++
++ i = getenv_f("serial#", buf, sizeof(buf));
++
++ if (i >0) {
++ if (strncmp(buf + strlen (buf) - strlen (CASL_STRING1),
++ CASL_STRING2, strlen (CASL_STRING2)) == 0) {
++ val = simple_strtoul (buf + strlen (buf) - 2, NULL, 10);
++
++ for (i = 0; i < N_CASL; ++i) {
++ if (val == casl_table[i]) {
++ return val;
++ }
++ }
++ }
++ }
++
++ return casl;
++}
++
++int checkboard (void)
++{
++ char buf[64];
++ int i = getenv_f("serial#", buf, sizeof(buf));
++
++ printf ("Board: %s", CONFIG_BOARDNAME);
++ if (i > 0) {
++ puts(", serial# ");
++ puts(buf);
++ }
++ putc ('\n');
++
++ /*
++ * Initialize local bus.
++ */
++ local_bus_init ();
++
++ return 0;
++}
++
++int misc_init_r (void)
++{
++ /*
++ * Adjust flash start and offset to detected values
++ */
++ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
++ gd->bd->bi_flashoffset = 0;
++
++ /*
++ * Recalculate CS configuration if second FLASH bank is available
++ */
++ if (flash_info[0].size > 0) {
++ set_lbc_or(1, ((-flash_info[0].size) & 0xffff8000) |
++ (CONFIG_SYS_OR1_PRELIM & 0x00007fff));
++ set_lbc_br(1, gd->bd->bi_flashstart |
++ (CONFIG_SYS_BR1_PRELIM & 0x00007fff));
++ /*
++ * Re-check to get correct base address for bank 1
++ */
++ flash_get_size (gd->bd->bi_flashstart, 0);
++ } else {
++ set_lbc_or(1, 0);
++ set_lbc_br(1, 0);
++ }
++
++ /*
++ * If bank 1 is equipped, bank 0 is mapped after bank 1
++ */
++ set_lbc_or(0, ((-flash_info[1].size) & 0xffff8000) |
++ (CONFIG_SYS_OR0_PRELIM & 0x00007fff));
++ set_lbc_br(0, (gd->bd->bi_flashstart + flash_info[0].size) |
++ (CONFIG_SYS_BR0_PRELIM & 0x00007fff));
++
++ /*
++ * Re-check to get correct base address for bank 0
++ */
++ flash_get_size (gd->bd->bi_flashstart + flash_info[0].size, 1);
++
++ /*
++ * Re-do flash protection upon new addresses
++ */
++ flash_protect (FLAG_PROTECT_CLEAR,
++ gd->bd->bi_flashstart, 0xffffffff,
++ &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
++
++ /* Monitor protection ON by default */
++ flash_protect (FLAG_PROTECT_SET,
++ CONFIG_SYS_MONITOR_BASE, 0xffffffff,
++ &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
++
++ /* Environment protection ON by default */
++ flash_protect (FLAG_PROTECT_SET,
++ CONFIG_ENV_ADDR,
++ CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
++ &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
++
++#ifdef CONFIG_ENV_ADDR_REDUND
++ /* Redundant environment protection ON by default */
++ flash_protect (FLAG_PROTECT_SET,
++ CONFIG_ENV_ADDR_REDUND,
++ CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
++ &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
++#endif
++
++ return 0;
++}
++
++#ifdef CONFIG_CAN_DRIVER
++/*
++ * Initialize UPMC RAM
++ */
++static void upmc_write (u_char addr, uint val)
++{
++ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
++
++ out_be32 (&lbc->mdr, val);
++
++ clrsetbits_be32(&lbc->mcmr, MxMR_MAD_MSK,
++ MxMR_OP_WARR | (addr & MxMR_MAD_MSK));
++
++ /* dummy access to perform write */
++ out_8 ((void __iomem *)CONFIG_SYS_CAN_BASE, 0);
++
++ /* normal operation */
++ clrbits_be32(&lbc->mcmr, MxMR_OP_WARR);
++}
++#endif /* CONFIG_CAN_DRIVER */
++
++uint get_lbc_clock (void)
++{
++ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
++ sys_info_t sys_info;
++ ulong clkdiv = lbc->lcrr & LCRR_CLKDIV;
++
++ get_sys_info (&sys_info);
++
++ if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
++#ifdef CONFIG_MPC8548
++ /*
++ * Yes, the entire PQ38 family use the same
++ * bit-representation for twice the clock divider value.
++ */
++ clkdiv *= 2;
++#endif
++ return sys_info.freqSystemBus / clkdiv;
++ }
++
++ puts("Invalid clock divider value in CONFIG_SYS_LBC_LCRR\n");
++
++ return 0;
++}
++
++/*
++ * Initialize Local Bus
++ */
++void local_bus_init (void)
++{
++ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
++ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
++ uint lbc_mhz = get_lbc_clock () / 1000000;
++
++#ifdef CONFIG_MPC8548
++ uint svr = get_svr ();
++ uint lcrr;
++
++ /*
++ * MPC revision < 2.0
++ * According to MPC8548E_Device_Errata Rev. L, Erratum LBIU1:
++ * Modify engineering use only register at address 0xE_0F20.
++ * "1. Read register at offset 0xE_0F20
++ * 2. And value with 0x0000_FFFF
++ * 3. OR result with 0x0000_0004
++ * 4. Write result back to offset 0xE_0F20."
++ *
++ * According to MPC8548E_Device_Errata Rev. L, Erratum LBIU2:
++ * Modify engineering use only register at address 0xE_0F20.
++ * "1. Read register at offset 0xE_0F20
++ * 2. And value with 0xFFFF_FFDF
++ * 3. Write result back to offset 0xE_0F20."
++ *
++ * Since it is the same register, we do the modification in one step.
++ */
++ if (SVR_MAJ (svr) < 2) {
++ uint dummy = gur->lbiuiplldcr1;
++ dummy &= 0x0000FFDF;
++ dummy |= 0x00000004;
++ gur->lbiuiplldcr1 = dummy;
++ }
++
++ lcrr = CONFIG_SYS_LBC_LCRR;
++
++ /*
++ * Local Bus Clock > 83.3 MHz. According to timing
++ * specifications set LCRR[EADC] to 2 delay cycles.
++ */
++ if (lbc_mhz > 83) {
++ lcrr &= ~LCRR_EADC;
++ lcrr |= LCRR_EADC_2;
++ }
++
++ /*
++ * According to MPC8548ERMAD Rev. 1.3, 13.3.1.16, 13-30
++ * disable PLL bypass for Local Bus Clock > 83 MHz.
++ */
++ if (lbc_mhz >= 66)
++ lcrr &= (~LCRR_DBYP); /* DLL Enabled */
++
++ else
++ lcrr |= LCRR_DBYP; /* DLL Bypass */
++
++ lbc->lcrr = lcrr;
++ asm ("sync;isync;msync");
++
++ /*
++ * According to MPC8548ERMAD Rev.1.3 read back LCRR
++ * and terminate with isync
++ */
++ lcrr = lbc->lcrr;
++ asm ("isync;");
++
++ /* let DLL stabilize */
++ udelay (500);
++
++#else /* !CONFIG_MPC8548 */
++
++ /*
++ * Errata LBC11.
++ * Fix Local Bus clock glitch when DLL is enabled.
++ *
++ * If localbus freq is < 66MHz, DLL bypass mode must be used.
++ * If localbus freq is > 133MHz, DLL can be safely enabled.
++ * Between 66 and 133, the DLL is enabled with an override workaround.
++ */
++
++ if (lbc_mhz < 66) {
++ lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP; /* DLL Bypass */
++ lbc->ltedr = LTEDR_BMD | LTEDR_PARD | LTEDR_WPD | LTEDR_WARA |
++ LTEDR_RAWA | LTEDR_CSD; /* Disable all error checking */
++
++ } else if (lbc_mhz >= 133) {
++ lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */
++
++ } else {
++ /*
++ * On REV1 boards, need to change CLKDIV before enable DLL.
++ * Default CLKDIV is 8, change it to 4 temporarily.
++ */
++ uint pvr = get_pvr ();
++ uint temp_lbcdll = 0;
++
++ if (pvr == PVR_85xx_REV1) {
++ /* FIXME: Justify the high bit here. */
++ lbc->lcrr = 0x10000004;
++ }
++
++ lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */
++ udelay (200);
++
++ /*
++ * Sample LBC DLL ctrl reg, upshift it to set the
++ * override bits.
++ */
++ temp_lbcdll = gur->lbcdllcr;
++ gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
++ asm ("sync;isync;msync");
++ }
++#endif /* !CONFIG_MPC8548 */
++
++#ifdef CONFIG_CAN_DRIVER
++ /*
++ * According to timing specifications EAD must be
++ * set if Local Bus Clock is > 83 MHz.
++ */
++ if (lbc_mhz > 83)
++ set_lbc_or(2, CONFIG_SYS_OR2_CAN | OR_UPM_EAD);
++ else
++ set_lbc_or(2, CONFIG_SYS_OR2_CAN);
++ set_lbc_br(2, CONFIG_SYS_BR2_CAN);
++
++ /* LGPL4 is UPWAIT */
++ out_be32(&lbc->mcmr, MxMR_DSx_3_CYCL | MxMR_GPL_x4DIS | MxMR_WLFx_3X);
++
++ /* Initialize UPMC for CAN: single read */
++ upmc_write (0x00, 0xFFFFED00);
++ upmc_write (0x01, 0xCCFFCC00);
++ upmc_write (0x02, 0x00FFCF00);
++ upmc_write (0x03, 0x00FFCF00);
++ upmc_write (0x04, 0x00FFDC00);
++ upmc_write (0x05, 0x00FFCF00);
++ upmc_write (0x06, 0x00FFED00);
++ upmc_write (0x07, 0x3FFFCC07);
++
++ /* Initialize UPMC for CAN: single write */
++ upmc_write (0x18, 0xFFFFED00);
++ upmc_write (0x19, 0xCCFFEC00);
++ upmc_write (0x1A, 0x00FFED80);
++ upmc_write (0x1B, 0x00FFED80);
++ upmc_write (0x1C, 0x00FFFC00);
++ upmc_write (0x1D, 0x0FFFEC00);
++ upmc_write (0x1E, 0x0FFFEF00);
++ upmc_write (0x1F, 0x3FFFEC05);
++#endif /* CONFIG_CAN_DRIVER */
++}
++
++/*
++ * Initialize PCI Devices, report devices found.
++ */
++
++#ifdef CONFIG_PCI1
++static struct pci_controller pci1_hose;
++#endif /* CONFIG_PCI1 */
++
++void pci_init_board (void)
++{
++ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
++ int first_free_busno = 0;
++#ifdef CONFIG_PCI1
++ struct fsl_pci_info pci_info;
++ int pcie_ep;
++
++ u32 devdisr = in_be32(&gur->devdisr);
++
++ uint pci_32 = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_PCI32;
++ uint pci_arb = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_ARB;
++ uint pci_speed = CONFIG_SYS_CLK_FREQ; /* PCI PSPEED in [4:5] */
++ uint pci_clk_sel = in_be32(&gur->porpllsr) & MPC85xx_PORDEVSR_PCI1_SPD;
++
++ if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
++ SET_STD_PCI_INFO(pci_info, 1);
++ set_next_law(pci_info.mem_phys,
++ law_size_bits(pci_info.mem_size), pci_info.law);
++ set_next_law(pci_info.io_phys,
++ law_size_bits(pci_info.io_size), pci_info.law);
++
++ pcie_ep = fsl_setup_hose(&pci1_hose, pci_info.regs);
++ printf("PCI1: %d bit, %s MHz, %s, %s, %s\n",
++ (pci_32) ? 32 : 64,
++ (pci_speed == 33333333) ? "33" :
++ (pci_speed == 66666666) ? "66" : "unknown",
++ pci_clk_sel ? "sync" : "async",
++ pcie_ep ? "agent" : "host",
++ pci_arb ? "arbiter" : "external-arbiter");
++ first_free_busno = fsl_pci_init_port(&pci_info,
++ &pci1_hose, first_free_busno);
++#ifdef CONFIG_PCIX_CHECK
++ if (!(in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1)) {
++ ushort reg16 =
++ PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ |
++ PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
++ uint dev = PCI_BDF(0, 0, 0);
++
++ /* PCI-X init */
++ if (CONFIG_SYS_CLK_FREQ < 66000000)
++ puts ("PCI-X will only work at 66 MHz\n");
++
++ pci_write_config_word(dev, PCIX_COMMAND, reg16);
++ }
++#endif
++ } else {
++ printf("PCI1: disabled\n");
++ }
++#else
++ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1);
++#endif
++
++ fsl_pcie_init_board(first_free_busno);
++}
++
++#ifdef CONFIG_OF_BOARD_SETUP
++void ft_board_setup (void *blob, bd_t *bd)
++{
++ ft_cpu_setup (blob, bd);
++
++ FT_FSL_PCI_SETUP;
++}
++#endif /* CONFIG_OF_BOARD_SETUP */
++
++#ifdef CONFIG_BOARD_EARLY_INIT_R
++int board_early_init_r (void)
++{
++#ifdef CONFIG_PS2MULT
++ ps2mult_early_init ();
++#endif /* CONFIG_PS2MULT */
++ return (0);
++}
++#endif /* CONFIG_BOARD_EARLY_INIT_R */
++
++int board_eth_init(bd_t *bis)
++{
++ cpu_eth_init(bis); /* Intialize TSECs first */
++ return pci_eth_init(bis);
++}
+diff --git a/board/tqc/tqm8xx/u-boot.lds b/board/tqc/tqm8xx/u-boot.lds
+index e905c26..4f08be6 100644
+--- a/board/tqc/tqm8xx/u-boot.lds
++++ b/board/tqc/tqm8xx/u-boot.lds
+@@ -43,6 +43,8 @@ SECTIONS
+ drivers/pcmcia/libpcmcia.o (.text.pcmcia_hardware_enable)
+ drivers/rtc/librtc.o (.text*)
+ drivers/misc/libmisc.o (.text*)
++ *(.text.print_buffer)
++ *(.text.print_size)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/env_embedded.o (.ppcenv*)
+diff --git a/board/ttcontrol/vision2/vision2.c b/board/ttcontrol/vision2/vision2.c
+index f28eab0..82aa4da 100644
+--- a/board/ttcontrol/vision2/vision2.c
++++ b/board/ttcontrol/vision2/vision2.c
+@@ -43,7 +43,7 @@
+
+ DECLARE_GLOBAL_DATA_PTR;
+
+-static struct fb_videomode nec_nl6448bc26_09c = {
++static struct fb_videomode const nec_nl6448bc26_09c = {
+ "NEC_NL6448BC26-09C",
+ 60, /* Refresh */
+ 640, /* xres */
+diff --git a/board/xilinx/zynq/Makefile b/board/xilinx/zynq/Makefile
+deleted file mode 100644
+index ef4faa1..0000000
+--- a/board/xilinx/zynq/Makefile
++++ /dev/null
+@@ -1,54 +0,0 @@
+-#
+-# (C) Copyright 2000-2006
+-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+-#
+-# See file CREDITS for list of people who contributed to this
+-# project.
+-#
+-# This program is free software; you can redistribute it and/or
+-# modify it under the terms of the GNU General Public License as
+-# published by the Free Software Foundation; either version 2 of
+-# the License, or (at your option) any later version.
+-#
+-# This program is distributed in the hope that it will be useful,
+-# but WITHOUT ANY WARRANTY; without even the implied warranty of
+-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-# GNU General Public License for more details.
+-#
+-# You should have received a copy of the GNU General Public License
+-# along with this program; if not, write to the Free Software
+-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+-# MA 02111-1307 USA
+-#
+-
+-include $(TOPDIR)/config.mk
+-ifneq ($(OBJTREE),$(SRCTREE))
+-$(shell mkdir -p $(obj)../common)
+-endif
+-
+-LIB = $(obj)lib$(BOARD).o
+-
+-COBJS-y := board.o
+-
+-COBJS := $(sort $(COBJS-y))
+-
+-SRCS := $(COBJS:.o=.c)
+-OBJS := $(addprefix $(obj),$(COBJS))
+-
+-$(LIB): $(obj).depend $(OBJS)
+- $(call cmd_link_o_target, $(OBJS))
+-
+-clean:
+- rm -f $(OBJS)
+-
+-distclean: clean
+- rm -f $(LIB) core *.bak $(obj).depend
+-
+-#########################################################################
+-
+-# defines $(obj).depend target
+-include $(SRCTREE)/rules.mk
+-
+-sinclude $(obj).depend
+-
+-#########################################################################
+diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
+deleted file mode 100644
+index 8ed75c3..0000000
+--- a/board/xilinx/zynq/board.c
++++ /dev/null
+@@ -1,54 +0,0 @@
+-/*
+- * (C) Copyright 2012 Michal Simek <monstr at monstr.eu>
+- *
+- * See file CREDITS for list of people who contributed to this
+- * project.
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of
+- * the License, or (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+- * MA 02111-1307 USA
+- */
+-
+-#include <common.h>
+-#include <netdev.h>
+-
+-DECLARE_GLOBAL_DATA_PTR;
+-
+-int board_init(void)
+-{
+- icache_enable();
+-
+- return 0;
+-}
+-
+-
+-#ifdef CONFIG_CMD_NET
+-int board_eth_init(bd_t *bis)
+-{
+- u32 ret = 0;
+-
+-#if defined(CONFIG_ZYNQ_GEM) && defined(CONFIG_ZYNQ_GEM_BASEADDR0)
+- ret = zynq_gem_initialize(bis, CONFIG_ZYNQ_GEM_BASEADDR0);
+-#endif
+-
+- return ret;
+-}
+-#endif
+-
+-int dram_init(void)
+-{
+- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+-
+- return 0;
+-}
+diff --git a/boards.cfg b/boards.cfg
+index 2381231..ac8e39d 100644
+--- a/boards.cfg
++++ b/boards.cfg
+@@ -67,7 +67,6 @@ mx1ads arm arm920t - -
+ scb9328 arm arm920t - - imx
+ cm4008 arm arm920t - - ks8695
+ cm41xx arm arm920t - - ks8695
+-mini2440 arm arm920t mini2440 friendlyarm s3c24x0
+ VCMA9 arm arm920t vcma9 mpl s3c24x0
+ smdk2410 arm arm920t - samsung s3c24x0
+ omap1510inn arm arm925t - ti
+@@ -152,7 +151,6 @@ enbw_cmc arm arm926ejs enbw_cmc enbw
+ calimain arm arm926ejs calimain omicron davinci
+ pogo_e02 arm arm926ejs - cloudengines kirkwood
+ dns325 arm arm926ejs - d-link kirkwood
+-iconnect arm arm926ejs - iomega kirkwood
+ lschlv2 arm arm926ejs lsxl buffalo kirkwood lsxl:LSCHLV2
+ lsxhl arm arm926ejs lsxl buffalo kirkwood lsxl:LSXHL
+ km_kirkwood arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD
+@@ -161,12 +159,9 @@ kmnusa arm arm926ejs km_arm keymile
+ mgcoge3un arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_MGCOGE3UN
+ kmcoge5un arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_COGE5UN
+ portl2 arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_PORTL2
+-d2net_v2 arm arm926ejs net2big_v2 LaCie kirkwood lacie_kw:D2NET_V2
+ inetspace_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:INETSPACE_V2
+ net2big_v2 arm arm926ejs net2big_v2 LaCie kirkwood lacie_kw:NET2BIG_V2
+-netspace_lite_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:NETSPACE_LITE_V2
+ netspace_max_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:NETSPACE_MAX_V2
+-netspace_mini_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:NETSPACE_MINI_V2
+ netspace_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:NETSPACE_V2
+ dreamplug arm arm926ejs - Marvell kirkwood
+ guruplug arm arm926ejs - Marvell kirkwood
+@@ -218,7 +213,6 @@ spear600 arm arm926ejs spear600 spear
+ spear600_nand arm arm926ejs spear600 spear spear spear6xx_evb:spear600,nand
+ spear600_usbtty arm arm926ejs spear600 spear spear spear6xx_evb:spear600,usbtty
+ spear600_usbtty_nand arm arm926ejs spear600 spear spear spear6xx_evb:spear600,usbtty,nand
+-x600 arm arm926ejs - spear spear x600
+ versatileab arm arm926ejs versatile armltd versatile versatile:ARCH_VERSATILE_AB
+ versatilepb arm arm926ejs versatile armltd versatile versatile:ARCH_VERSATILE_PB
+ versatileqemu arm arm926ejs versatile armltd versatile versatile:ARCH_VERSATILE_QEMU,ARCH_VERSATILE_PB
+@@ -240,6 +234,7 @@ mx6qarm2 arm armv7 mx6qarm2 freesca
+ mx6qsabreauto arm armv7 mx6qsabreauto freescale mx6 mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg
+ mx6qsabrelite arm armv7 mx6qsabrelite freescale mx6 mx6qsabrelite:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
+ mx6qsabresd arm armv7 mx6qsabresd freescale mx6 mx6qsabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
++nitrogen6x arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
+ cm_t35 arm armv7 cm_t35 - omap3
+ omap3_overo arm armv7 overo - omap3
+ omap3_pandora arm armv7 pandora - omap3
+@@ -280,10 +275,6 @@ ventana arm armv7:arm720t ventana nvidia
+ whistler arm armv7:arm720t whistler nvidia tegra20
+ u8500_href arm armv7 u8500 st-ericsson u8500
+ snowball arm armv7 snowball st-ericsson u8500
+-kzm9g arm armv7 kzm9g kmc rmobile
+-armadillo-800eva arm armv7 armadillo-800eva atmark-techno rmobile
+-zynq arm armv7 zynq xilinx zynq
+-socfpga_cyclone5 arm armv7 socfpga_cyclone5 altera socfpga
+ actux1_4_16 arm ixp actux1 - - actux1:FLASH2X2
+ actux1_4_32 arm ixp actux1 - - actux1:FLASH2X2,RAM_32MB
+ actux1_8_16 arm ixp actux1 - - actux1:FLASH1X8
+@@ -843,6 +834,13 @@ BSC9131RDB_SPIFLASH powerpc mpc85xx bsc9131rdb freesca
+ stxgp3 powerpc mpc85xx stxgp3 stx
+ stxssa powerpc mpc85xx stxssa stx - stxssa
+ stxssa_4M powerpc mpc85xx stxssa stx - stxssa:STXSSA_4M
++TQM8540 powerpc mpc85xx tqm85xx tqc - TQM85xx:MPC8540,TQM8540=y,HOSTNAME=tqm8540,BOARDNAME="TQM8540"
++TQM8541 powerpc mpc85xx tqm85xx tqc - TQM85xx:MPC8541,TQM8541=y,HOSTNAME=tqm8541,BOARDNAME="TQM8541"
++TQM8548 powerpc mpc85xx tqm85xx tqc - TQM85xx:MPC8548,TQM8548=y,HOSTNAME=tqm8548,BOARDNAME="TQM8548"
++TQM8548_AG powerpc mpc85xx tqm85xx tqc - TQM85xx:MPC8548,TQM8548_AG=y,HOSTNAME=tqm8485,BOARDNAME="TQM8548_AG"
++TQM8548_BE powerpc mpc85xx tqm85xx tqc - TQM85xx:MPC8548,TQM8548_BE=y,HOSTNAME=tqm8548,BOARDNAME="TQM8548_BE"
++TQM8555 powerpc mpc85xx tqm85xx tqc - TQM85xx:MPC8555,TQM8555=y,HOSTNAME=tqm8555,BOARDNAME="TQM8555"
++TQM8560 powerpc mpc85xx tqm85xx tqc - TQM85xx:MPC8560,TQM8560=y,HOSTNAME=tqm8560,BOARDNAME="TQM8560"
+ xpedite520x powerpc mpc85xx - xes
+ xpedite537x powerpc mpc85xx - xes
+ xpedite550x powerpc mpc85xx - xes
+diff --git a/common/Makefile b/common/Makefile
+index 973f05a..125b2be 100644
+--- a/common/Makefile
++++ b/common/Makefile
+@@ -107,7 +107,6 @@ COBJS-$(CONFIG_CMD_GPIO) += cmd_gpio.o
+ COBJS-$(CONFIG_CMD_I2C) += cmd_i2c.o
+ COBJS-$(CONFIG_CMD_IDE) += cmd_ide.o
+ COBJS-$(CONFIG_CMD_IMMAP) += cmd_immap.o
+-COBJS-$(CONFIG_CMD_INI) += cmd_ini.o
+ COBJS-$(CONFIG_CMD_IRQ) += cmd_irq.o
+ COBJS-$(CONFIG_CMD_ITEST) += cmd_itest.o
+ COBJS-$(CONFIG_CMD_JFFS2) += cmd_jffs2.o
+@@ -199,10 +198,6 @@ endif
+
+ ifdef CONFIG_SPL_BUILD
+ COBJS-$(CONFIG_SPL_YMODEM_SUPPORT) += xyzModem.o
+-COBJS-$(CONFIG_SPL_NET_SUPPORT) += cmd_nvedit.o
+-COBJS-$(CONFIG_SPL_NET_SUPPORT) += env_common.o
+-COBJS-$(CONFIG_SPL_NET_SUPPORT) += env_nowhere.o
+-COBJS-$(CONFIG_SPL_NET_SUPPORT) += miiphyutil.o
+ endif
+ COBJS-y += console.o
+ COBJS-y += dlmalloc.o
+diff --git a/common/cmd_cache.c b/common/cmd_cache.c
+index 5512f92..9c228e2 100644
+--- a/common/cmd_cache.c
++++ b/common/cmd_cache.c
+@@ -36,24 +36,21 @@ void __weak invalidate_icache_all(void)
+ puts("No arch specific invalidate_icache_all available!\n");
+ }
+
+-int do_icache(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
++int do_icache ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+ {
+ switch (argc) {
+ case 2: /* on / off */
+ switch (parse_argv(argv[1])) {
+- case 0:
+- icache_disable();
++ case 0: icache_disable();
+ break;
+- case 1:
+- icache_enable();
++ case 1: icache_enable ();
+ break;
+- case 2:
+- invalidate_icache_all();
++ case 2: invalidate_icache_all();
+ break;
+ }
+- break;
++ /* FALL TROUGH */
+ case 1: /* get status */
+- printf("Instruction Cache is %s\n",
++ printf ("Instruction Cache is %s\n",
+ icache_status() ? "ON" : "OFF");
+ return 0;
+ default:
+@@ -68,42 +65,40 @@ void __weak flush_dcache_all(void)
+ /* please define arch specific flush_dcache_all */
+ }
+
+-int do_dcache(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
++int do_dcache ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+ {
+ switch (argc) {
+- case 2: /* on / off */
++ case 2: /* on / off */
+ switch (parse_argv(argv[1])) {
+- case 0:
+- dcache_disable();
++ case 0: dcache_disable();
+ break;
+- case 1:
+- dcache_enable();
++ case 1: dcache_enable ();
+ break;
+- case 2:
+- flush_dcache_all();
++ case 2: flush_dcache_all();
+ break;
+ }
+- break;
++ /* FALL TROUGH */
+ case 1: /* get status */
+- printf("Data (writethrough) Cache is %s\n",
++ printf ("Data (writethrough) Cache is %s\n",
+ dcache_status() ? "ON" : "OFF");
+ return 0;
+ default:
+ return CMD_RET_USAGE;
+ }
+ return 0;
++
+ }
+
+ static int parse_argv(const char *s)
+ {
+- if (strcmp(s, "flush") == 0)
+- return 2;
+- else if (strcmp(s, "on") == 0)
+- return 1;
+- else if (strcmp(s, "off") == 0)
+- return 0;
+-
+- return -1;
++ if (strcmp(s, "flush") == 0) {
++ return (2);
++ } else if (strcmp(s, "on") == 0) {
++ return (1);
++ } else if (strcmp(s, "off") == 0) {
++ return (0);
++ }
++ return (-1);
+ }
+
+
+diff --git a/common/cmd_echo.c b/common/cmd_echo.c
+index 1e499fb..43a6da5 100644
+--- a/common/cmd_echo.c
++++ b/common/cmd_echo.c
+@@ -30,31 +30,17 @@ int do_echo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+ int putnl = 1;
+
+ for (i = 1; i < argc; i++) {
+- char *p = argv[i];
+- char *nls; /* new-line suppression */
++ char *p = argv[i], c;
+
+ if (i > 1)
+ putc(' ');
+-
+- nls = strstr(p, "\\c");
+- if (nls) {
+- char *prenls = p;
+-
+- putnl = 0;
+- /*
+- * be paranoid and guess that someone might
+- * say \c more than once
+- */
+- while (nls) {
+- *nls = '\0';
+- puts(prenls);
+- *nls = '\\';
+- prenls = nls + 2;
+- nls = strstr(prenls, "\\c");
++ while ((c = *p++) != '\0') {
++ if (c == '\\' && *p == 'c') {
++ putnl = 0;
++ p++;
++ } else {
++ putc(c);
+ }
+- puts(prenls);
+- } else {
+- puts(p);
+ }
+ }
+
+diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c
+index 795814d..b64b975 100644
+--- a/common/cmd_i2c.c
++++ b/common/cmd_i2c.c
+@@ -557,18 +557,28 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char * const arg
+
+ /*
+ * Syntax:
+- * i2c probe {addr}{.0, .1, .2}
++ * i2c probe {addr}
++ *
++ * Returns zero (success) if one or more I2C devices was found
+ */
+ static int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+ {
+ int j;
++ int addr = -1;
++ int found = 0;
+ #if defined(CONFIG_SYS_I2C_NOPROBES)
+ int k, skip;
+ uchar bus = GET_BUS_NUM;
+ #endif /* NOPROBES */
+
++ if (argc == 2)
++ addr = simple_strtol(argv[1], 0, 16);
++
+ puts ("Valid chip addresses:");
+ for (j = 0; j < 128; j++) {
++ if ((0 <= addr) && (j != addr))
++ continue;
++
+ #if defined(CONFIG_SYS_I2C_NOPROBES)
+ skip = 0;
+ for (k=0; k < NUM_ELEMENTS_NOPROBE; k++) {
+@@ -580,8 +590,10 @@ static int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv
+ if (skip)
+ continue;
+ #endif
+- if (i2c_probe(j) == 0)
++ if (i2c_probe(j) == 0) {
+ printf(" %02X", j);
++ found++;
++ }
+ }
+ putc ('\n');
+
+@@ -594,7 +606,7 @@ static int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv
+ putc ('\n');
+ #endif
+
+- return 0;
++ return (0 == found);
+ }
+
+ /*
+@@ -1331,7 +1343,7 @@ U_BOOT_CMD(
+ "i2c mm chip address[.0, .1, .2] - write to I2C device (auto-incrementing)\n"
+ "i2c mw chip address[.0, .1, .2] value [count] - write to I2C device (fill)\n"
+ "i2c nm chip address[.0, .1, .2] - write to I2C device (constant address)\n"
+- "i2c probe - show devices on the I2C bus\n"
++ "i2c probe [address] - test for and show device(s) on the I2C bus\n"
+ "i2c read chip address[.0, .1, .2] length memaddress - read to memory \n"
+ "i2c reset - re-init the I2C Controller\n"
+ #if defined(CONFIG_CMD_SDRAM)
+diff --git a/common/cmd_ini.c b/common/cmd_ini.c
+deleted file mode 100644
+index 74481cb..0000000
+--- a/common/cmd_ini.c
++++ /dev/null
+@@ -1,275 +0,0 @@
+-/*
+- * inih -- simple .INI file parser
+- *
+- * Copyright (c) 2009, Brush Technology
+- * Copyright (c) 2012:
+- * Joe Hershberger, National Instruments, joe.hershberger at ni.com
+- * All rights reserved.
+- *
+- * The "inih" library is distributed under the following license, which is
+- * derived from and very similar to the 3-clause BSD license:
+- *
+- * Redistribution and use in source and binary forms, with or without
+- * modification, are permitted provided that the following conditions are met:
+- * * Redistributions of source code must retain the above copyright
+- * notice, this list of conditions and the following disclaimer.
+- * * Redistributions in binary form must reproduce the above copyright
+- * notice, this list of conditions and the following disclaimer in the
+- * documentation and/or other materials provided with the distribution.
+- * * Neither the name of Brush Technology nor the names of its contributors
+- * may be used to endorse or promote products derived from this software
+- * without specific prior written permission.
+- *
+- * THIS SOFTWARE IS PROVIDED BY BRUSH TECHNOLOGY ''AS IS'' AND ANY
+- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+- * DISCLAIMED. IN NO EVENT SHALL BRUSH TECHNOLOGY BE LIABLE FOR ANY
+- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+- *
+- * Go to the project home page for more info:
+- * http://code.google.com/p/inih/
+- */
+-
+-#include <common.h>
+-#include <command.h>
+-#include <environment.h>
+-#include <linux/ctype.h>
+-#include <linux/string.h>
+-
+-#ifdef CONFIG_INI_MAX_LINE
+-#define MAX_LINE CONFIG_INI_MAX_LINE
+-#else
+-#define MAX_LINE 200
+-#endif
+-
+-#ifdef CONFIG_INI_MAX_SECTION
+-#define MAX_SECTION CONFIG_INI_MAX_SECTION
+-#else
+-#define MAX_SECTION 50
+-#endif
+-
+-#ifdef CONFIG_INI_MAX_NAME
+-#define MAX_NAME CONFIG_INI_MAX_NAME
+-#else
+-#define MAX_NAME 50
+-#endif
+-
+-/* Strip whitespace chars off end of given string, in place. Return s. */
+-static char *rstrip(char *s)
+-{
+- char *p = s + strlen(s);
+-
+- while (p > s && isspace(*--p))
+- *p = '\0';
+- return s;
+-}
+-
+-/* Return pointer to first non-whitespace char in given string. */
+-static char *lskip(const char *s)
+-{
+- while (*s && isspace(*s))
+- s++;
+- return (char *)s;
+-}
+-
+-/* Return pointer to first char c or ';' comment in given string, or pointer to
+- null at end of string if neither found. ';' must be prefixed by a whitespace
+- character to register as a comment. */
+-static char *find_char_or_comment(const char *s, char c)
+-{
+- int was_whitespace = 0;
+-
+- while (*s && *s != c && !(was_whitespace && *s == ';')) {
+- was_whitespace = isspace(*s);
+- s++;
+- }
+- return (char *)s;
+-}
+-
+-/* Version of strncpy that ensures dest (size bytes) is null-terminated. */
+-static char *strncpy0(char *dest, const char *src, size_t size)
+-{
+- strncpy(dest, src, size);
+- dest[size - 1] = '\0';
+- return dest;
+-}
+-
+-/* Emulate the behavior of fgets but on memory */
+-static char *memgets(char *str, int num, char **mem, size_t *memsize)
+-{
+- char *end;
+- int len;
+- int newline = 1;
+-
+- end = memchr(*mem, '\n', *memsize);
+- if (end == NULL) {
+- if (*memsize == 0)
+- return NULL;
+- end = *mem + *memsize;
+- newline = 0;
+- }
+- len = min((end - *mem) + newline, num);
+- memcpy(str, *mem, len);
+- if (len < num)
+- str[len] = '\0';
+-
+- /* prepare the mem vars for the next call */
+- *memsize -= (end - *mem) + newline;
+- *mem += (end - *mem) + newline;
+-
+- return str;
+-}
+-
+-/* Parse given INI-style file. May have [section]s, name=value pairs
+- (whitespace stripped), and comments starting with ';' (semicolon). Section
+- is "" if name=value pair parsed before any section heading. name:value
+- pairs are also supported as a concession to Python's ConfigParser.
+-
+- For each name=value pair parsed, call handler function with given user
+- pointer as well as section, name, and value (data only valid for duration
+- of handler call). Handler should return nonzero on success, zero on error.
+-
+- Returns 0 on success, line number of first error on parse error (doesn't
+- stop on first error).
+-*/
+-static int ini_parse(char *filestart, size_t filelen,
+- int (*handler)(void *, char *, char *, char *), void *user)
+-{
+- /* Uses a fair bit of stack (use heap instead if you need to) */
+- char line[MAX_LINE];
+- char section[MAX_SECTION] = "";
+- char prev_name[MAX_NAME] = "";
+-
+- char *curmem = filestart;
+- char *start;
+- char *end;
+- char *name;
+- char *value;
+- size_t memleft = filelen;
+- int lineno = 0;
+- int error = 0;
+-
+- /* Scan through file line by line */
+- while (memgets(line, sizeof(line), &curmem, &memleft) != NULL) {
+- lineno++;
+- start = lskip(rstrip(line));
+-
+- if (*start == ';' || *start == '#') {
+- /*
+- * Per Python ConfigParser, allow '#' comments at start
+- * of line
+- */
+- }
+-#if CONFIG_INI_ALLOW_MULTILINE
+- else if (*prev_name && *start && start > line) {
+- /*
+- * Non-blank line with leading whitespace, treat as
+- * continuation of previous name's value (as per Python
+- * ConfigParser).
+- */
+- if (!handler(user, section, prev_name, start) && !error)
+- error = lineno;
+- }
+-#endif
+- else if (*start == '[') {
+- /* A "[section]" line */
+- end = find_char_or_comment(start + 1, ']');
+- if (*end == ']') {
+- *end = '\0';
+- strncpy0(section, start + 1, sizeof(section));
+- *prev_name = '\0';
+- } else if (!error) {
+- /* No ']' found on section line */
+- error = lineno;
+- }
+- } else if (*start && *start != ';') {
+- /* Not a comment, must be a name[=:]value pair */
+- end = find_char_or_comment(start, '=');
+- if (*end != '=')
+- end = find_char_or_comment(start, ':');
+- if (*end == '=' || *end == ':') {
+- *end = '\0';
+- name = rstrip(start);
+- value = lskip(end + 1);
+- end = find_char_or_comment(value, '\0');
+- if (*end == ';')
+- *end = '\0';
+- rstrip(value);
+- /* Strip double-quotes */
+- if (value[0] == '"' &&
+- value[strlen(value)-1] == '"') {
+- value[strlen(value)-1] = '\0';
+- value += 1;
+- }
+-
+- /*
+- * Valid name[=:]value pair found, call handler
+- */
+- strncpy0(prev_name, name, sizeof(prev_name));
+- if (!handler(user, section, name, value) &&
+- !error)
+- error = lineno;
+- } else if (!error)
+- /* No '=' or ':' found on name[=:]value line */
+- error = lineno;
+- }
+- }
+-
+- return error;
+-}
+-
+-static int ini_handler(void *user, char *section, char *name, char *value)
+-{
+- char *requested_section = (char *)user;
+-#ifdef CONFIG_INI_CASE_INSENSITIVE
+- int i;
+-
+- for (i = 0; i < strlen(requested_section); i++)
+- requested_section[i] = tolower(requested_section[i]);
+- for (i = 0; i < strlen(section); i++)
+- section[i] = tolower(section[i]);
+-#endif
+-
+- if (!strcmp(section, requested_section)) {
+-#ifdef CONFIG_INI_CASE_INSENSITIVE
+- for (i = 0; i < strlen(name); i++)
+- name[i] = tolower(name[i]);
+- for (i = 0; i < strlen(value); i++)
+- value[i] = tolower(value[i]);
+-#endif
+- setenv(name, value);
+- printf("ini: Imported %s as %s\n", name, value);
+- }
+-
+- /* success */
+- return 1;
+-}
+-
+-static int do_ini(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+-{
+- const char *section;
+- char *file_address;
+- size_t file_size;
+-
+- if (argc == 1)
+- return CMD_RET_USAGE;
+-
+- section = argv[1];
+- file_address = (char *)simple_strtoul(
+- argc < 3 ? getenv("loadaddr") : argv[2], NULL, 16);
+- file_size = (size_t)simple_strtoul(
+- argc < 4 ? getenv("filesize") : argv[3], NULL, 16);
+-
+- return ini_parse(file_address, file_size, ini_handler, (void *)section);
+-}
+-
+-U_BOOT_CMD(
+- ini, 4, 0, do_ini,
+- "parse an ini file in memory and merge the specified section into the env",
+- "section [[file-address] file-size]"
+-);
+diff --git a/common/cmd_md5sum.c b/common/cmd_md5sum.c
+index 3f81fdf..b93dd9b 100644
+--- a/common/cmd_md5sum.c
++++ b/common/cmd_md5sum.c
+@@ -1,7 +1,4 @@
+ /*
+- * (C) Copyright 2011
+- * Joe Hershberger, National Instruments, joe.hershberger at ni.com
+- *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+@@ -28,125 +25,6 @@
+ #include <command.h>
+ #include <u-boot/md5.h>
+
+-/*
+- * Store the resulting sum to an address or variable
+- */
+-static void store_result(const u8 *sum, const char *dest)
+-{
+- unsigned int i;
+-
+- if (*dest == '*') {
+- u8 *ptr;
+-
+- ptr = (u8 *)simple_strtoul(dest + 1, NULL, 16);
+- for (i = 0; i < 16; i++)
+- *ptr++ = sum[i];
+- } else {
+- char str_output[33];
+- char *str_ptr = str_output;
+-
+- for (i = 0; i < 16; i++) {
+- sprintf(str_ptr, "%02x", sum[i]);
+- str_ptr += 2;
+- }
+- str_ptr = '\0';
+- setenv(dest, str_output);
+- }
+-}
+-
+-#ifdef CONFIG_MD5SUM_VERIFY
+-static int parse_verify_sum(char *verify_str, u8 *vsum)
+-{
+- if (*verify_str == '*') {
+- u8 *ptr;
+-
+- ptr = (u8 *)simple_strtoul(verify_str + 1, NULL, 16);
+- memcpy(vsum, ptr, 16);
+- } else {
+- unsigned int i;
+- char *vsum_str;
+-
+- if (strlen(verify_str) == 32)
+- vsum_str = verify_str;
+- else {
+- vsum_str = getenv(verify_str);
+- if (vsum_str == NULL || strlen(vsum_str) != 32)
+- return 1;
+- }
+-
+- for (i = 0; i < 16; i++) {
+- char *nullp = vsum_str + (i + 1) * 2;
+- char end = *nullp;
+-
+- *nullp = '\0';
+- *(u8 *)(vsum + i) =
+- simple_strtoul(vsum_str + (i * 2), NULL, 16);
+- *nullp = end;
+- }
+- }
+- return 0;
+-}
+-
+-int do_md5sum(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+-{
+- ulong addr, len;
+- unsigned int i;
+- u8 output[16];
+- u8 vsum[16];
+- int verify = 0;
+- int ac;
+- char * const *av;
+-
+- if (argc < 3)
+- return CMD_RET_USAGE;
+-
+- av = argv + 1;
+- ac = argc - 1;
+- if (strcmp(*av, "-v") == 0) {
+- verify = 1;
+- av++;
+- ac--;
+- if (ac < 3)
+- return CMD_RET_USAGE;
+- }
+-
+- addr = simple_strtoul(*av++, NULL, 16);
+- len = simple_strtoul(*av++, NULL, 16);
+-
+- md5_wd((unsigned char *) addr, len, output, CHUNKSZ_MD5);
+-
+- if (!verify) {
+- printf("md5 for %08lx ... %08lx ==> ", addr, addr + len - 1);
+- for (i = 0; i < 16; i++)
+- printf("%02x", output[i]);
+- printf("\n");
+-
+- if (ac > 2)
+- store_result(output, *av);
+- } else {
+- char *verify_str = *av++;
+-
+- if (parse_verify_sum(verify_str, vsum)) {
+- printf("ERROR: %s does not contain a valid md5 sum\n",
+- verify_str);
+- return 1;
+- }
+- if (memcmp(output, vsum, 16) != 0) {
+- printf("md5 for %08lx ... %08lx ==> ", addr,
+- addr + len - 1);
+- for (i = 0; i < 16; i++)
+- printf("%02x", output[i]);
+- printf(" != ");
+- for (i = 0; i < 16; i++)
+- printf("%02x", vsum[i]);
+- printf(" ** ERROR **\n");
+- return 1;
+- }
+- }
+-
+- return 0;
+-}
+-#else
+ static int do_md5sum(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+ {
+ unsigned long addr, len;
+@@ -165,27 +43,11 @@ static int do_md5sum(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+ printf("%02x", output[i]);
+ printf("\n");
+
+- if (argc > 3)
+- store_result(output, argv[3]);
+-
+ return 0;
+ }
+-#endif
+
+-#ifdef CONFIG_MD5SUM_VERIFY
+-U_BOOT_CMD(
+- md5sum, 5, 1, do_md5sum,
+- "compute MD5 message digest",
+- "address count [[*]sum]\n"
+- " - compute MD5 message digest [save to sum]\n"
+- "md5sum -v address count [*]sum\n"
+- " - verify md5sum of memory area"
+-);
+-#else
+ U_BOOT_CMD(
+- md5sum, 4, 1, do_md5sum,
++ md5sum, 3, 1, do_md5sum,
+ "compute MD5 message digest",
+- "address count [[*]sum]\n"
+- " - compute MD5 message digest [save to sum]"
++ "address count"
+ );
+-#endif
+diff --git a/common/cmd_misc.c b/common/cmd_misc.c
+index 3b47a0c..973b1c2 100644
+--- a/common/cmd_misc.c
++++ b/common/cmd_misc.c
+@@ -53,30 +53,3 @@ U_BOOT_CMD(
+ "N\n"
+ " - delay execution for N seconds (N is _decimal_ !!!)"
+ );
+-
+-#ifdef CONFIG_CMD_TIMER
+-static int do_timer(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+-{
+- static ulong start;
+-
+- if (argc != 2)
+- return CMD_RET_USAGE;
+-
+- if (!strcmp(argv[1], "start"))
+- start = get_timer(0);
+-
+- if (!strcmp(argv[1], "get")) {
+- ulong msecs = get_timer(start) * 1000 / CONFIG_SYS_HZ;
+- printf("%ld.%03d\n", msecs / 1000, (int)(msecs % 1000));
+- }
+-
+- return 0;
+-}
+-
+-U_BOOT_CMD(
+- timer, 2, 1, do_timer,
+- "access the system timer",
+- "start - Reset the timer reference.\n"
+- "timer get - Print the time since 'start'."
+-);
+-#endif
+diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c
+index bb1d4ec..3474bc6 100644
+--- a/common/cmd_nvedit.c
++++ b/common/cmd_nvedit.c
+@@ -103,7 +103,6 @@ int get_env_id(void)
+ return env_id;
+ }
+
+-#ifndef CONFIG_SPL_BUILD
+ /*
+ * Command interface: print one or all environment variables
+ *
+@@ -197,7 +196,6 @@ static int do_env_grep(cmd_tbl_t *cmdtp, int flag,
+ return rcode;
+ }
+ #endif
+-#endif /* CONFIG_SPL_BUILD */
+
+ /*
+ * Perform consistency checking before setting, replacing, or deleting an
+@@ -215,9 +213,6 @@ int env_check_apply(const char *name, const char *oldval,
+ {
+ int console = -1;
+
+- /* Default value for NULL to protect string-manipulating functions */
+- newval = newval ? : "";
+-
+ /* Check for console redirection */
+ if (strcmp(name, "stdin") == 0)
+ console = stdin;
+@@ -442,7 +437,6 @@ int setenv_addr(const char *varname, const void *addr)
+ return setenv(varname, str);
+ }
+
+-#ifndef CONFIG_SPL_BUILD
+ int do_env_set(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+ {
+ if (argc < 2)
+@@ -542,7 +536,6 @@ int do_env_edit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+ return setenv(argv[1], buffer);
+ }
+ #endif /* CONFIG_CMD_EDITENV */
+-#endif /* CONFIG_SPL_BUILD */
+
+ /*
+ * Look up variable from environment,
+@@ -628,7 +621,6 @@ ulong getenv_ulong(const char *name, int base, ulong default_val)
+ return str ? simple_strtoul(str, NULL, base) : default_val;
+ }
+
+-#ifndef CONFIG_SPL_BUILD
+ #if defined(CONFIG_CMD_SAVEENV) && !defined(CONFIG_ENV_IS_NOWHERE)
+ int do_env_save(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+ {
+@@ -643,7 +635,6 @@ U_BOOT_CMD(
+ ""
+ );
+ #endif
+-#endif /* CONFIG_SPL_BUILD */
+
+
+ /*
+@@ -665,7 +656,6 @@ int envmatch(uchar *s1, int i2)
+ return -1;
+ }
+
+-#ifndef CONFIG_SPL_BUILD
+ static int do_env_default(cmd_tbl_t *cmdtp, int __flag,
+ int argc, char * const argv[])
+ {
+@@ -1124,4 +1114,3 @@ U_BOOT_CMD_COMPLETE(
+ var_complete
+ );
+ #endif
+-#endif /* CONFIG_SPL_BUILD */
+diff --git a/common/cmd_sha1sum.c b/common/cmd_sha1sum.c
+index 8db5456..2713a14 100644
+--- a/common/cmd_sha1sum.c
++++ b/common/cmd_sha1sum.c
+@@ -1,7 +1,4 @@
+ /*
+- * (C) Copyright 2011
+- * Joe Hershberger, National Instruments, joe.hershberger at ni.com
+- *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+@@ -28,125 +25,6 @@
+ #include <command.h>
+ #include <sha1.h>
+
+-/*
+- * Store the resulting sum to an address or variable
+- */
+-static void store_result(const u8 *sum, const char *dest)
+-{
+- unsigned int i;
+-
+- if (*dest == '*') {
+- u8 *ptr;
+-
+- ptr = (u8 *)simple_strtoul(dest + 1, NULL, 16);
+- for (i = 0; i < 20; i++)
+- *ptr++ = sum[i];
+- } else {
+- char str_output[41];
+- char *str_ptr = str_output;
+-
+- for (i = 0; i < 20; i++) {
+- sprintf(str_ptr, "%02x", sum[i]);
+- str_ptr += 2;
+- }
+- str_ptr = '\0';
+- setenv(dest, str_output);
+- }
+-}
+-
+-#ifdef CONFIG_SHA1SUM_VERIFY
+-static int parse_verify_sum(char *verify_str, u8 *vsum)
+-{
+- if (*verify_str == '*') {
+- u8 *ptr;
+-
+- ptr = (u8 *)simple_strtoul(verify_str + 1, NULL, 16);
+- memcpy(vsum, ptr, 20);
+- } else {
+- unsigned int i;
+- char *vsum_str;
+-
+- if (strlen(verify_str) == 40)
+- vsum_str = verify_str;
+- else {
+- vsum_str = getenv(verify_str);
+- if (vsum_str == NULL || strlen(vsum_str) != 40)
+- return 1;
+- }
+-
+- for (i = 0; i < 20; i++) {
+- char *nullp = vsum_str + (i + 1) * 2;
+- char end = *nullp;
+-
+- *nullp = '\0';
+- *(u8 *)(vsum + i) =
+- simple_strtoul(vsum_str + (i * 2), NULL, 16);
+- *nullp = end;
+- }
+- }
+- return 0;
+-}
+-
+-int do_sha1sum(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+-{
+- ulong addr, len;
+- unsigned int i;
+- u8 output[20];
+- u8 vsum[20];
+- int verify = 0;
+- int ac;
+- char * const *av;
+-
+- if (argc < 3)
+- return CMD_RET_USAGE;
+-
+- av = argv + 1;
+- ac = argc - 1;
+- if (strcmp(*av, "-v") == 0) {
+- verify = 1;
+- av++;
+- ac--;
+- if (ac < 3)
+- return CMD_RET_USAGE;
+- }
+-
+- addr = simple_strtoul(*av++, NULL, 16);
+- len = simple_strtoul(*av++, NULL, 16);
+-
+- sha1_csum_wd((unsigned char *) addr, len, output, CHUNKSZ_SHA1);
+-
+- if (!verify) {
+- printf("SHA1 for %08lx ... %08lx ==> ", addr, addr + len - 1);
+- for (i = 0; i < 20; i++)
+- printf("%02x", output[i]);
+- printf("\n");
+-
+- if (ac > 2)
+- store_result(output, *av);
+- } else {
+- char *verify_str = *av++;
+-
+- if (parse_verify_sum(verify_str, vsum)) {
+- printf("ERROR: %s does not contain a valid SHA1 sum\n",
+- verify_str);
+- return 1;
+- }
+- if (memcmp(output, vsum, 20) != 0) {
+- printf("SHA1 for %08lx ... %08lx ==> ", addr,
+- addr + len - 1);
+- for (i = 0; i < 20; i++)
+- printf("%02x", output[i]);
+- printf(" != ");
+- for (i = 0; i < 20; i++)
+- printf("%02x", vsum[i]);
+- printf(" ** ERROR **\n");
+- return 1;
+- }
+- }
+-
+- return 0;
+-}
+-#else
+ static int do_sha1sum(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+ {
+ unsigned long addr, len;
+@@ -165,27 +43,11 @@ static int do_sha1sum(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+ printf("%02x", output[i]);
+ printf("\n");
+
+- if (argc > 3)
+- store_result(output, argv[3]);
+-
+ return 0;
+ }
+-#endif
+
+-#ifdef CONFIG_SHA1SUM_VERIFY
+-U_BOOT_CMD(
+- sha1sum, 5, 1, do_sha1sum,
+- "compute SHA1 message digest",
+- "address count [[*]sum]\n"
+- " - compute SHA1 message digest [save to sum]\n"
+- "sha1sum -v address count [*]sum\n"
+- " - verify sha1sum of memory area"
+-);
+-#else
+ U_BOOT_CMD(
+- sha1sum, 4, 1, do_sha1sum,
++ sha1sum, 3, 1, do_sha1sum,
+ "compute SHA1 message digest",
+- "address count [[*]sum]\n"
+- " - compute SHA1 message digest [save to sum]"
++ "address count"
+ );
+-#endif
+diff --git a/common/cmd_test.c b/common/cmd_test.c
+index 6da06b9..fcb5ef2 100644
+--- a/common/cmd_test.c
++++ b/common/cmd_test.c
+@@ -33,12 +33,12 @@ int do_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+ if (argc < 3)
+ return 1;
+
+-#ifdef DEBUG
++#if 0
+ {
+- debug("test(%d):", argc);
++ printf("test:");
+ left = 1;
+ while (argv[left])
+- debug(" '%s'", argv[left++]);
++ printf(" %s", argv[left++]);
+ }
+ #endif
+
+diff --git a/common/env_common.c b/common/env_common.c
+index 57221ef..3e46c26 100644
+--- a/common/env_common.c
++++ b/common/env_common.c
+@@ -231,7 +231,6 @@ int set_default_vars(int nvars, char * const vars[])
+ nvars, vars, 1 /* do_apply */);
+ }
+
+-#ifndef CONFIG_SPL_BUILD
+ /*
+ * Check if CRC is valid and (if yes) import the environment.
+ * Note that "buf" may or may not be aligned.
+@@ -263,7 +262,6 @@ int env_import(const char *buf, int check)
+
+ return 0;
+ }
+-#endif
+
+ void env_relocate(void)
+ {
+@@ -271,8 +269,7 @@ void env_relocate(void)
+ env_reloc();
+ #endif
+ if (gd->env_valid == 0) {
+-#if defined(CONFIG_ENV_IS_NOWHERE) || defined(CONFIG_SPL_BUILD)
+- /* Environment not changable */
++#if defined(CONFIG_ENV_IS_NOWHERE) /* Environment not changable */
+ set_default_env(NULL);
+ #else
+ bootstage_error(BOOTSTAGE_ID_NET_CHECKSUM);
+@@ -283,7 +280,7 @@ void env_relocate(void)
+ }
+ }
+
+-#if defined(CONFIG_AUTO_COMPLETE) && !defined(CONFIG_SPL_BUILD)
++#ifdef CONFIG_AUTO_COMPLETE
+ int env_complete(char *var, int maxv, char *cmdv[], int bufsz, char *buf)
+ {
+ ENTRY *match;
+diff --git a/common/main.c b/common/main.c
+index 9507cec..81984ac 100644
+--- a/common/main.c
++++ b/common/main.c
+@@ -222,8 +222,7 @@ int abortboot(int bootdelay)
+ #ifdef CONFIG_MENUPROMPT
+ printf(CONFIG_MENUPROMPT);
+ #else
+- if (bootdelay >= 0)
+- printf("Hit any key to stop autoboot: %2d ", bootdelay);
++ printf("Hit any key to stop autoboot: %2d ", bootdelay);
+ #endif
+
+ #if defined CONFIG_ZERO_BOOTDELAY_CHECK
+@@ -383,7 +382,7 @@ void main_loop (void)
+
+ debug ("### main_loop: bootcmd=\"%s\"\n", s ? s : "<UNDEFINED>");
+
+- if (bootdelay != -1 && s && !abortboot(bootdelay)) {
++ if (bootdelay >= 0 && s && !abortboot (bootdelay)) {
+ # ifdef CONFIG_AUTOBOOT_KEYED
+ int prev = disable_ctrlc(1); /* disable Control C checking */
+ # endif
+diff --git a/common/serial.c b/common/serial.c
+index 4f2bc7f..75cc1bb 100644
+--- a/common/serial.c
++++ b/common/serial.c
+@@ -122,14 +122,6 @@ void serial_initialize(void)
+ serial_register(&uartlite_serial3_device);
+ # endif /* XILINX_UARTLITE_BASEADDR3 */
+ #endif /* CONFIG_XILINX_UARTLITE */
+-#if defined(CONFIG_ZYNQ_SERIAL)
+-# ifdef CONFIG_ZYNQ_SERIAL_BASEADDR0
+- serial_register(&uart_zynq_serial0_device);
+-# endif
+-# ifdef CONFIG_ZYNQ_SERIAL_BASEADDR1
+- serial_register(&uart_zynq_serial1_device);
+-# endif
+-#endif
+ serial_assign(default_serial_console()->name);
+ }
+
+diff --git a/common/spl/Makefile b/common/spl/Makefile
+index 5698a23..7cf01ad 100644
+--- a/common/spl/Makefile
++++ b/common/spl/Makefile
+@@ -18,7 +18,6 @@ COBJS-$(CONFIG_SPL_FRAMEWORK) += spl.o
+ COBJS-$(CONFIG_SPL_NOR_SUPPORT) += spl_nor.o
+ COBJS-$(CONFIG_SPL_YMODEM_SUPPORT) += spl_ymodem.o
+ COBJS-$(CONFIG_SPL_NAND_SUPPORT) += spl_nand.o
+-COBJS-$(CONFIG_SPL_NET_SUPPORT) += spl_net.o
+ endif
+
+ COBJS := $(sort $(COBJS-y))
+diff --git a/common/spl/spl.c b/common/spl/spl.c
+index 40a7aca..c640f87 100644
+--- a/common/spl/spl.c
++++ b/common/spl/spl.c
+@@ -155,8 +155,6 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
+ CONFIG_SYS_SPL_MALLOC_SIZE);
+ #endif
+
+- timer_init();
+-
+ #ifdef CONFIG_SPL_BOARD_INIT
+ spl_board_init();
+ #endif
+@@ -196,15 +194,6 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
+ spl_spi_load_image();
+ break;
+ #endif
+-#ifdef CONFIG_SPL_ETH_SUPPORT
+- case BOOT_DEVICE_CPGMAC:
+-#ifdef CONFIG_SPL_ETH_DEVICE
+- spl_net_load_image(CONFIG_SPL_ETH_DEVICE);
+-#else
+- spl_net_load_image(NULL);
+-#endif
+- break;
+-#endif
+ default:
+ debug("SPL: Un-supported Boot Device\n");
+ hang();
+diff --git a/common/spl/spl_net.c b/common/spl/spl_net.c
+deleted file mode 100644
+index e1596fe..0000000
+--- a/common/spl/spl_net.c
++++ /dev/null
+@@ -1,52 +0,0 @@
+-/*
+- * (C) Copyright 2000-2004
+- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+- *
+- * (C) Copyright 2012
+- * Ilya Yanok <ilya.yanok at gmail.com>
+- *
+- * See file CREDITS for list of people who contributed to this
+- * project.
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of
+- * the License, or (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc.
+- */
+-#include <common.h>
+-#include <spl.h>
+-#include <net.h>
+-
+-DECLARE_GLOBAL_DATA_PTR;
+-
+-void spl_net_load_image(const char *device)
+-{
+- int rv;
+-
+- env_init();
+- env_relocate();
+- setenv("autoload", "yes");
+- load_addr = CONFIG_SYS_TEXT_BASE - sizeof(struct image_header);
+- rv = eth_initialize(gd->bd);
+- if (rv == 0) {
+- printf("No Ethernet devices found\n");
+- hang();
+- }
+- if (device)
+- setenv("ethact", device);
+- rv = NetLoop(BOOTP);
+- if (rv < 0) {
+- printf("Problem booting with BOOTP\n");
+- hang();
+- }
+- spl_parse_image_header((struct image_header *)load_addr);
+-}
+diff --git a/config.mk b/config.mk
+index 51b4783..c3822a2 100644
+--- a/config.mk
++++ b/config.mk
+@@ -128,7 +128,6 @@ endif
+ # cc-version
+ # Usage gcc-ver := $(call cc-version)
+ cc-version = $(shell $(SHELL) $(SRCTREE)/tools/gcc-version.sh $(CC))
+-binutils-version = $(shell $(SHELL) $(SRCTREE)/tools/binutils-version.sh $(AS))
+
+ #
+ # Include the make variables (CC, etc...)
+diff --git a/disk/part_dos.c b/disk/part_dos.c
+index 5c454e6..c9a3e2b 100644
+--- a/disk/part_dos.c
++++ b/disk/part_dos.c
+@@ -94,13 +94,12 @@ int test_part_dos (block_dev_desc_t *dev_desc)
+ {
+ ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, dev_desc->blksz);
+
+- if (dev_desc->block_read(dev_desc->dev, 0, 1, (ulong *) buffer) != 1)
+- return -1;
+-
+- if (test_block_type(buffer) != DOS_MBR)
+- return -1;
+-
+- return 0;
++ if ((dev_desc->block_read(dev_desc->dev, 0, 1, (ulong *) buffer) != 1) ||
++ (buffer[DOS_PART_MAGIC_OFFSET + 0] != 0x55) ||
++ (buffer[DOS_PART_MAGIC_OFFSET + 1] != 0xaa) ) {
++ return (-1);
++ }
++ return (0);
+ }
+
+ /* Print a partition that is relative to its Extended partition table
+@@ -118,13 +117,17 @@ static void print_partition_extended (block_dev_desc_t *dev_desc, int ext_part_s
+ return;
+ }
+ i=test_block_type(buffer);
+- if (i != DOS_MBR) {
++ if(i==-1) {
+ printf ("bad MBR sector signature 0x%02x%02x\n",
+ buffer[DOS_PART_MAGIC_OFFSET],
+ buffer[DOS_PART_MAGIC_OFFSET + 1]);
+ return;
+ }
+-
++ if(i==DOS_PBR) {
++ printf (" 1\t\t 0\t%10ld\t%2x\n",
++ dev_desc->lba, buffer[DOS_PBR_MEDIA_TYPE_OFFSET]);
++ return;
++ }
+ /* Print all primary/logical partitions */
+ pt = (dos_partition_t *) (buffer + DOS_PART_TBL_OFFSET);
+ for (i = 0; i < 4; i++, pt++) {
+diff --git a/doc/README.mini2440 b/doc/README.mini2440
+deleted file mode 100644
+index 311ca52..0000000
+--- a/doc/README.mini2440
++++ /dev/null
+@@ -1,28 +0,0 @@
+-U-Boot for FriendlyARM Mini2440 (s3c2440)
+-
+-This file contains information for the port of U-Boot to FriendlyARM
+-mini2440
+-
+-All information about the board can be found on :
+-http://www.friendlyarm.net/products/mini2440
+-
+-To build u-boot : ./MAKEALL mini2440
+-
+-Overview :
+---------
+-FriendlyARM Mini 2440 SBC (Single-Board Computer) with 400 MHz Samsung S3C2440
+-ARM9 processor. The board measures 100 x 100 mm, ideal for learning about ARM9
+-systems. It's a low cost board.
+-
+-Boot Methods :
+-------------
+-Mini2440 can boot from NOR or NAND.
+-
+-Build :
+------
+-./MAKEALL mini2440
+-
+-or
+-
+-make mini2440_config
+-make
+diff --git a/doc/README.rmobile b/doc/README.rmobile
+deleted file mode 100644
+index 7ec63f1..0000000
+--- a/doc/README.rmobile
++++ /dev/null
+@@ -1,65 +0,0 @@
+-Summary
+-=======
+-
+-This README is about U-Boot support for Renesas's ARM Cortex-A9 based RMOBILE[1]
+-family of SoCs. Renesas's RMOBILE SoC family contains an ARM Cortex-A9.
+-
+-Currently the following boards are supported:
+-
+-* KMC KZM-A9-GT [2]
+-
+-* Atmark-Techno Armadillo-800-EVA [3]
+-
+-Toolchain
+-=========
+-
+-ARM Cortex-A9 support ARM v7 instruction set (-march=armv7a).
+-But currently we compile with -march=armv5 to allow more compilers to work.
+-(For U-Boot code this has no performance impact.)
+-Because there was no compiler which is supporting armv7a not much before.
+-Currently, ELDK[4], Linaro[5], CodeSourcey[6] and Emdebian[7] supports -march=armv7a
+-and you can get.
+-
+-Build
+-=====
+-
+-* KZM-A9-GT
+-
+-make kzm9g_config
+-make
+-
+-* Armadillo-800-EVA
+-
+-make armadillo-800eva_config
+-make
+-
+-Links
+-=====
+-
+-[1] Renesas RMOBILE:
+-
+-http://am.renesas.com/products/soc/assp/mobile/r_mobile/index.jsp
+-
+-[2] KZM-A9-GT
+-
+-http://www.kmckk.co.jp/kzma9-gt/index.html
+-
+-[3] Armadillo-800-EVA
+-
+-http://armadillo.atmark-techno.com/armadillo-800-EVA
+-
+-[4] ELDK
+-
+-http://www.denx.de/wiki/view/ELDK-5/WebHome#Section_1.6.
+-
+-[5] Linaro
+-
+-http://www.linaro.org/downloads/
+-
+-[6] CodeSourcey
+-
+-http://www.mentor.com/embedded-software/codesourcery
+-
+-[7] Emdebian
+-
+-http://www.emdebian.org/crosstools.html
+diff --git a/doc/README.scrapyard b/doc/README.scrapyard
+index d0f4716..5929a8e 100644
+--- a/doc/README.scrapyard
++++ b/doc/README.scrapyard
+@@ -11,9 +11,8 @@ easily if here is something they might want to dig for...
+
+ Board Arch CPU removed Commit last known maintainer/contact
+ =============================================================================
+-TQM85xx powerpc MPC85xx - - Stefan Roese <sr at denx.de>
+-apollon arm omap24xx 535c74f 2012-09-18 Kyungmin Park <kyungmin.park at samsung.com>
+-tb0229 mips mips32 3f3110d 2011-12-12
++apollon arm omap24xx - 2012-09-06 Kyungmin Park <kyungmin.park at samsung.com>
++tb0229 mips mips32 - 2011-12-12
+ rmu powerpc MPC850 fb82fd7 2011-12-07 Wolfgang Denk <wd at denx.de>
+ OXC powerpc MPC8240 309a292 2011-12-07
+ BAB7xx powerpc MPC740/MPC750 c53043b 2011-12-07 Frank Gottschling <fgottschling at eltec.de>
+diff --git a/doc/git-mailrc b/doc/git-mailrc
+index e7276d9..d7fc3c8 100644
+--- a/doc/git-mailrc
++++ b/doc/git-mailrc
+@@ -46,7 +46,6 @@ alias imx uboot, sbabic
+ alias kirkwood uboot, prafulla
+ alias omap ti
+ alias pxa uboot, marex
+-alias rmobile uboot, iwamatsu
+ alias s3c samsung
+ alias s5pc samsung
+ alias samsung uboot, prom
+diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
+index d50ac3b..17f4b73 100644
+--- a/drivers/gpio/Makefile
++++ b/drivers/gpio/Makefile
+@@ -44,7 +44,6 @@ COBJS-$(CONFIG_SH_GPIO_PFC) += sh_pfc.o
+ COBJS-$(CONFIG_OMAP_GPIO) += omap_gpio.o
+ COBJS-$(CONFIG_DB8500_GPIO) += db8500_gpio.o
+ COBJS-$(CONFIG_BCM2835_GPIO) += bcm2835_gpio.o
+-COBJS-$(CONFIG_S3C2440_GPIO) += s3c2440_gpio.o
+
+ COBJS := $(COBJS-y)
+ SRCS := $(COBJS:.o=.c)
+diff --git a/drivers/gpio/pca953x.c b/drivers/gpio/pca953x.c
+index be13745..359fdee 100644
+--- a/drivers/gpio/pca953x.c
++++ b/drivers/gpio/pca953x.c
+@@ -221,7 +221,7 @@ cmd_tbl_t cmd_pca953x[] = {
+ int do_pca953x(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+ {
+ static uint8_t chip = CONFIG_SYS_I2C_PCA953X_ADDR;
+- int ret = CMD_RET_USAGE, val;
++ int val;
+ ulong ul_arg2 = 0;
+ ulong ul_arg3 = 0;
+ cmd_tbl_t *c;
+@@ -232,7 +232,7 @@ int do_pca953x(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+ if (!c || !((argc == (c->maxargs)) ||
+ (((int)c->cmd == PCA953X_CMD_DEVICE) &&
+ (argc == (c->maxargs - 1))))) {
+- return CMD_RET_USAGE;
++ return cmd_usage(cmdtp);
+ }
+
+ /* arg2 used as chip number or pin number */
+@@ -246,53 +246,32 @@ int do_pca953x(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+ switch ((int)c->cmd) {
+ #ifdef CONFIG_CMD_PCA953X_INFO
+ case PCA953X_CMD_INFO:
+- ret = pca953x_info(chip);
+- if (ret)
+- ret = CMD_RET_FAILURE;
+- break;
++ return pca953x_info(chip);
+ #endif
+-
+ case PCA953X_CMD_DEVICE:
+ if (argc == 3)
+ chip = (uint8_t)ul_arg2;
+ printf("Current device address: 0x%x\n", chip);
+- ret = CMD_RET_SUCCESS;
+- break;
+-
++ return 0;
+ case PCA953X_CMD_INPUT:
+- ret = pca953x_set_dir(chip, (1 << ul_arg2),
++ pca953x_set_dir(chip, (1 << ul_arg2),
+ PCA953X_DIR_IN << ul_arg2);
+ val = (pca953x_get_val(chip) & (1 << ul_arg2)) != 0;
+
+- if (ret)
+- ret = CMD_RET_FAILURE;
+- else
+- printf("chip 0x%02x, pin 0x%lx = %d\n", chip, ul_arg2,
+- val);
+- break;
+-
++ printf("chip 0x%02x, pin 0x%lx = %d\n", chip, ul_arg2, val);
++ return val;
+ case PCA953X_CMD_OUTPUT:
+- ret = pca953x_set_dir(chip, (1 << ul_arg2),
++ pca953x_set_dir(chip, (1 << ul_arg2),
+ (PCA953X_DIR_OUT << ul_arg2));
+- if (!ret)
+- ret = pca953x_set_val(chip, (1 << ul_arg2),
+- (ul_arg3 << ul_arg2));
+- if (ret)
+- ret = CMD_RET_FAILURE;
+- break;
+-
++ return pca953x_set_val(chip, (1 << ul_arg2),
++ (ul_arg3 << ul_arg2));
+ case PCA953X_CMD_INVERT:
+- ret = pca953x_set_pol(chip, (1 << ul_arg2),
++ return pca953x_set_pol(chip, (1 << ul_arg2),
+ (ul_arg3 << ul_arg2));
+- if (ret)
+- ret = CMD_RET_FAILURE;
+- break;
++ default:
++ /* We should never get here */
++ return 1;
+ }
+-
+- if (ret == CMD_RET_FAILURE)
+- eprintf("Error talking to chip at 0x%x\n", chip);
+-
+- return ret;
+ }
+
+ U_BOOT_CMD(
+@@ -308,7 +287,7 @@ U_BOOT_CMD(
+ " - set pin as output and drive low or high\n"
+ "pca953x invert pin 0|1\n"
+ " - disable/enable polarity inversion for reads\n"
+- "pca953x input pin\n"
++ "pca953x intput pin\n"
+ " - set pin as input and read value"
+ );
+
+diff --git a/drivers/gpio/s3c2440_gpio.c b/drivers/gpio/s3c2440_gpio.c
+deleted file mode 100644
+index 43bbf11..0000000
+--- a/drivers/gpio/s3c2440_gpio.c
++++ /dev/null
+@@ -1,95 +0,0 @@
+-/*
+- * Copyright (C) 2012
+- * Gabriel Huau <contact at huau-gabriel.fr>
+- *
+- * See file CREDITS for list of people who contributed to this
+- * project.
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of
+- * the License, or (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+- * MA 02111-1307 USA
+- */
+-#include <common.h>
+-#include <asm/arch/s3c2440.h>
+-#include <asm/gpio.h>
+-#include <asm/io.h>
+-
+-#define GPIO_INPUT 0x0
+-#define GPIO_OUTPUT 0x1
+-
+-/* 0x4 means that we want DAT and not CON register */
+-#define GPIO_PORT(x) ((((x) >> 5) & 0x3) + 0x4)
+-#define GPIO_BIT(x) ((x) & 0x3f)
+-
+-/*
+- * It's how we calculate the full port address
+- * We have to get the number of the port + 1 (Port A is at 0x56000001 ...)
+- * We move it at the second digit, and finally we add 0x4 because we want
+- * to modify GPIO DAT and not CON
+- */
+-#define GPIO_FULLPORT(x) (S3C24X0_GPIO_BASE | ((GPIO_PORT(gpio) + 1) << 1))
+-
+-int gpio_set_value(unsigned gpio, int value)
+-{
+- unsigned l = readl(GPIO_FULLPORT(gpio));
+- unsigned bit;
+- unsigned port = GPIO_FULLPORT(gpio);
+-
+- /*
+- * All GPIO Port have a configuration on
+- * 2 bits excepted the first GPIO (A) which
+- * have only 1 bit of configuration.
+- */
+- if (!GPIO_PORT(gpio))
+- bit = (0x1 << GPIO_BIT(gpio));
+- else
+- bit = (0x3 << GPIO_BIT(gpio));
+-
+- if (value)
+- l |= bit;
+- else
+- l &= ~bit;
+-
+- return writel(port, l);
+-}
+-
+-int gpio_get_value(unsigned gpio)
+-{
+- unsigned l = readl(GPIO_FULLPORT(gpio));
+-
+- if (GPIO_PORT(gpio) == 0) /* PORT A */
+- return (l >> GPIO_BIT(gpio)) & 0x1;
+- return (l >> GPIO_BIT(gpio)) & 0x3;
+-}
+-
+-int gpio_request(unsigned gpio, const char *label)
+-{
+- return 0;
+-}
+-
+-int gpio_free(unsigned gpio)
+-{
+- return 0;
+-}
+-
+-int gpio_direction_input(unsigned gpio)
+-{
+- return writel(GPIO_FULLPORT(gpio), GPIO_INPUT << GPIO_BIT(gpio));
+-}
+-
+-int gpio_direction_output(unsigned gpio, int value)
+-{
+- writel(GPIO_FULLPORT(gpio), GPIO_OUTPUT << GPIO_BIT(gpio));
+- return gpio_set_value(gpio, value);
+-}
+diff --git a/drivers/i2c/sh_i2c.c b/drivers/i2c/sh_i2c.c
+index 3147123..fd8cb92 100644
+--- a/drivers/i2c/sh_i2c.c
++++ b/drivers/i2c/sh_i2c.c
+@@ -52,6 +52,22 @@ static u8 iccl, icch;
+
+ #define IRQ_WAIT 1000
+
++static void irq_wait(struct sh_i2c *base)
++{
++ int i;
++ u8 status;
++
++ for (i = 0 ; i < IRQ_WAIT ; i++) {
++ status = readb(&base->icsr);
++ if (SH_IC_WAIT & status)
++ break;
++
++ udelay(10);
++ }
++
++ writeb(status & ~SH_IC_WAIT, &base->icsr);
++}
++
+ static void irq_dte(struct sh_i2c *base)
+ {
+ int i;
+diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
+index 994dd9f..c6aa5db 100644
+--- a/drivers/mtd/nand/atmel_nand.c
++++ b/drivers/mtd/nand/atmel_nand.c
+@@ -652,9 +652,8 @@ static int atmel_pmecc_nand_init_params(struct nand_chip *nand,
+ sector_size = host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
+ host->pmecc_index_table_offset = CONFIG_PMECC_INDEX_TABLE_OFFSET;
+
+- MTDDEBUG(MTD_DEBUG_LEVEL1,
+- "Initialize PMECC params, cap: %d, sector: %d\n",
+- cap, sector_size);
++ printk(KERN_INFO "Initialize PMECC params, cap: %d, sector: %d\n",
++ cap, sector_size);
+
+ host->pmecc = (struct pmecc_regs __iomem *) ATMEL_BASE_PMECC;
+ host->pmerrloc = (struct pmecc_errloc_regs __iomem *)
+diff --git a/drivers/mtd/nand/fsl_upm.c b/drivers/mtd/nand/fsl_upm.c
+index 11eb167..31c174b 100644
+--- a/drivers/mtd/nand/fsl_upm.c
++++ b/drivers/mtd/nand/fsl_upm.c
+@@ -57,7 +57,7 @@ static void fun_wait(struct fsl_upm_nand *fun)
+ debug("unexpected busy state\n");
+ } else {
+ /*
+- * If the R/B pin is not connected,
++ * If the R/B pin is not connected, like on the TQM8548,
+ * a short delay is necessary.
+ */
+ udelay(1);
+@@ -115,10 +115,10 @@ static void fun_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+ fsl_upm_run_pattern(&fun->upm, fun->width, io_addr, mar);
+
+ /*
+- * Some boards/chips needs this. At least the MPC8360E-RDK
+- * needs it. Probably weird chip, because I don't see any
+- * need for this on MPC8555E + Samsung K9F1G08U0A. Usually
+- * here are 0-2 unexpected busy states per block read.
++ * Some boards/chips needs this. At least the MPC8360E-RDK and
++ * TQM8548 need it. Probably weird chip, because I don't see
++ * any need for this on MPC8555E + Samsung K9F1G08U0A. Usually
++ * here are 0-2 unexpected busy states per block read.
+ */
+ if (fun->wait_flags & FSL_UPM_WAIT_RUN_PATTERN)
+ fun_wait(fun);
+diff --git a/drivers/mtd/spi/atmel.c b/drivers/mtd/spi/atmel.c
+index 006f6d5..1ecece0 100644
+--- a/drivers/mtd/spi/atmel.c
++++ b/drivers/mtd/spi/atmel.c
+@@ -109,14 +109,6 @@ static const struct atmel_spi_flash_params atmel_spi_flash_table[] = {
+ .nr_sectors = 32,
+ .name = "AT45DB642D",
+ },
+- {
+- .idcode1 = 0x47,
+- .l2_page_size = 8,
+- .pages_per_block = 16,
+- .blocks_per_sector = 16,
+- .nr_sectors = 64,
+- .name = "AT25DF321",
+- },
+ };
+
+ static int at45_wait_ready(struct spi_flash *flash, unsigned long timeout)
+@@ -518,19 +510,11 @@ struct spi_flash *spi_flash_probe_atmel(struct spi_slave *spi, u8 *idcode)
+ asf->flash.erase = dataflash_erase_p2;
+ }
+
+- asf->flash.page_size = page_size;
+- asf->flash.sector_size = page_size;
+ break;
+
+ case DF_FAMILY_AT26F:
+ case DF_FAMILY_AT26DF:
+ asf->flash.read = spi_flash_cmd_read_fast;
+- asf->flash.write = spi_flash_cmd_write_multi;
+- asf->flash.erase = spi_flash_cmd_erase;
+- asf->flash.page_size = page_size;
+- asf->flash.sector_size = 4096;
+- /* clear SPRL# bit for locked flash */
+- spi_flash_cmd_write_status(&asf->flash, 0);
+ break;
+
+ default:
+@@ -538,6 +522,7 @@ struct spi_flash *spi_flash_probe_atmel(struct spi_slave *spi, u8 *idcode)
+ goto err;
+ }
+
++ asf->flash.sector_size = page_size;
+ asf->flash.size = page_size * params->pages_per_block
+ * params->blocks_per_sector
+ * params->nr_sectors;
+diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c
+index 1db586d..b2516d1 100644
+--- a/drivers/net/davinci_emac.c
++++ b/drivers/net/davinci_emac.c
+@@ -897,8 +897,7 @@ int davinci_emac_initialize(void)
+ }
+
+ #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
+- defined(CONFIG_MACH_DAVINCI_DA850_EVM) && \
+- !defined(CONFIG_DRIVER_TI_EMAC_RMII_NO_NEGOTIATE)
++ defined(CONFIG_MACH_DAVINCI_DA850_EVM)
+ for (i = 0; i < num_phy; i++) {
+ if (phy[i].is_phy_connected(i))
+ phy[i].auto_negotiate(i);
+diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
+index dfc22a4..65d0f23 100644
+--- a/drivers/serial/Makefile
++++ b/drivers/serial/Makefile
+@@ -56,7 +56,6 @@ COBJS-$(CONFIG_S3C44B0_SERIAL) += serial_s3c44b0.o
+ COBJS-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o
+ COBJS-$(CONFIG_SANDBOX_SERIAL) += sandbox.o
+ COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o
+-COBJS-$(CONFIG_ZYNQ_SERIAL) += serial_zynq.o
+
+ ifndef CONFIG_SPL_BUILD
+ COBJS-$(CONFIG_USB_TTY) += usbtty.o
+diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c
+deleted file mode 100644
+index 3832236..0000000
+--- a/drivers/serial/serial_zynq.c
++++ /dev/null
+@@ -1,247 +0,0 @@
+-/*
+- * Copyright (C) 2012 Michal Simek <monstr at monstr.eu>
+- * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved.
+- *
+- * See file CREDITS for list of people who contributed to this
+- * project.
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of
+- * the License, or (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+- * MA 02111-1307 USA
+- */
+-
+-#include <common.h>
+-#include <watchdog.h>
+-#include <asm/io.h>
+-#include <linux/compiler.h>
+-#include <serial.h>
+-
+-#define ZYNQ_UART_SR_TXFULL 0x00000010 /* TX FIFO full */
+-#define ZYNQ_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
+-
+-#define ZYNQ_UART_CR_TX_EN 0x00000010 /* TX enabled */
+-#define ZYNQ_UART_CR_RX_EN 0x00000004 /* RX enabled */
+-#define ZYNQ_UART_CR_TXRST 0x00000002 /* TX logic reset */
+-#define ZYNQ_UART_CR_RXRST 0x00000001 /* RX logic reset */
+-
+-#define ZYNQ_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */
+-
+-/* Some clock/baud constants */
+-#define ZYNQ_UART_BDIV 15 /* Default/reset BDIV value */
+-#define ZYNQ_UART_BASECLK 3125000L /* master / (bdiv + 1) */
+-
+-struct uart_zynq {
+- u32 control; /* Control Register [8:0] */
+- u32 mode; /* Mode Register [10:0] */
+- u32 reserved1[4];
+- u32 baud_rate_gen; /* Baud Rate Generator [15:0] */
+- u32 reserved2[4];
+- u32 channel_sts; /* Channel Status [11:0] */
+- u32 tx_rx_fifo; /* FIFO [15:0] or [7:0] */
+- u32 baud_rate_divider; /* Baud Rate Divider [7:0] */
+-};
+-
+-static struct uart_zynq *uart_zynq_ports[2] = {
+-#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR0
+- [0] = (struct uart_zynq *)CONFIG_ZYNQ_SERIAL_BASEADDR0,
+-#endif
+-#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR1
+- [1] = (struct uart_zynq *)CONFIG_ZYNQ_SERIAL_BASEADDR1,
+-#endif
+-};
+-
+-struct uart_zynq_params {
+- u32 baudrate;
+- u32 clock;
+-};
+-
+-static struct uart_zynq_params uart_zynq_ports_param[2] = {
+-#if defined(CONFIG_ZYNQ_SERIAL_BAUDRATE0) && defined(CONFIG_ZYNQ_SERIAL_CLOCK0)
+- [0].baudrate = CONFIG_ZYNQ_SERIAL_BAUDRATE0,
+- [0].clock = CONFIG_ZYNQ_SERIAL_CLOCK0,
+-#endif
+-#if defined(CONFIG_ZYNQ_SERIAL_BAUDRATE1) && defined(CONFIG_ZYNQ_SERIAL_CLOCK1)
+- [1].baudrate = CONFIG_ZYNQ_SERIAL_BAUDRATE1,
+- [1].clock = CONFIG_ZYNQ_SERIAL_CLOCK1,
+-#endif
+-};
+-
+-/* Set up the baud rate in gd struct */
+-static void uart_zynq_serial_setbrg(const int port)
+-{
+- /* Calculation results. */
+- unsigned int calc_bauderror, bdiv, bgen;
+- unsigned long calc_baud = 0;
+- unsigned long baud = uart_zynq_ports_param[port].baudrate;
+- unsigned long clock = uart_zynq_ports_param[port].clock;
+- struct uart_zynq *regs = uart_zynq_ports[port];
+-
+- /* master clock
+- * Baud rate = ------------------
+- * bgen * (bdiv + 1)
+- *
+- * Find acceptable values for baud generation.
+- */
+- for (bdiv = 4; bdiv < 255; bdiv++) {
+- bgen = clock / (baud * (bdiv + 1));
+- if (bgen < 2 || bgen > 65535)
+- continue;
+-
+- calc_baud = clock / (bgen * (bdiv + 1));
+-
+- /*
+- * Use first calculated baudrate with
+- * an acceptable (<3%) error
+- */
+- if (baud > calc_baud)
+- calc_bauderror = baud - calc_baud;
+- else
+- calc_bauderror = calc_baud - baud;
+- if (((calc_bauderror * 100) / baud) < 3)
+- break;
+- }
+-
+- writel(bdiv, ®s->baud_rate_divider);
+- writel(bgen, ®s->baud_rate_gen);
+-}
+-
+-/* Initialize the UART, with...some settings. */
+-static int uart_zynq_serial_init(const int port)
+-{
+- struct uart_zynq *regs = uart_zynq_ports[port];
+-
+- if (!regs)
+- return -1;
+-
+- /* RX/TX enabled & reset */
+- writel(ZYNQ_UART_CR_TX_EN | ZYNQ_UART_CR_RX_EN | ZYNQ_UART_CR_TXRST | \
+- ZYNQ_UART_CR_RXRST, ®s->control);
+- writel(ZYNQ_UART_MR_PARITY_NONE, ®s->mode); /* 8 bit, no parity */
+- uart_zynq_serial_setbrg(port);
+-
+- return 0;
+-}
+-
+-static void uart_zynq_serial_putc(const char c, const int port)
+-{
+- struct uart_zynq *regs = uart_zynq_ports[port];
+-
+- while ((readl(®s->channel_sts) & ZYNQ_UART_SR_TXFULL) != 0)
+- WATCHDOG_RESET();
+-
+- if (c == '\n') {
+- writel('\r', ®s->tx_rx_fifo);
+- while ((readl(®s->channel_sts) & ZYNQ_UART_SR_TXFULL) != 0)
+- WATCHDOG_RESET();
+- }
+- writel(c, ®s->tx_rx_fifo);
+-}
+-
+-static void uart_zynq_serial_puts(const char *s, const int port)
+-{
+- while (*s)
+- uart_zynq_serial_putc(*s++, port);
+-}
+-
+-static int uart_zynq_serial_tstc(const int port)
+-{
+- struct uart_zynq *regs = uart_zynq_ports[port];
+-
+- return (readl(®s->channel_sts) & ZYNQ_UART_SR_RXEMPTY) == 0;
+-}
+-
+-static int uart_zynq_serial_getc(const int port)
+-{
+- struct uart_zynq *regs = uart_zynq_ports[port];
+-
+- while (!uart_zynq_serial_tstc(port))
+- WATCHDOG_RESET();
+- return readl(®s->tx_rx_fifo);
+-}
+-
+-#if !defined(CONFIG_SERIAL_MULTI)
+-int serial_init(void)
+-{
+- return uart_zynq_serial_init(0);
+-}
+-
+-void serial_setbrg(void)
+-{
+- uart_zynq_serial_setbrg(0);
+-}
+-
+-void serial_putc(const char c)
+-{
+- uart_zynq_serial_putc(c, 0);
+-}
+-
+-void serial_puts(const char *s)
+-{
+- uart_zynq_serial_puts(s, 0);
+-}
+-
+-int serial_getc(void)
+-{
+- return uart_zynq_serial_getc(0);
+-}
+-
+-int serial_tstc(void)
+-{
+- return uart_zynq_serial_tstc(0);
+-}
+-#else
+-/* Multi serial device functions */
+-#define DECLARE_PSSERIAL_FUNCTIONS(port) \
+- int uart_zynq##port##_init(void) \
+- { return uart_zynq_serial_init(port); } \
+- void uart_zynq##port##_setbrg(void) \
+- { return uart_zynq_serial_setbrg(port); } \
+- int uart_zynq##port##_getc(void) \
+- { return uart_zynq_serial_getc(port); } \
+- int uart_zynq##port##_tstc(void) \
+- { return uart_zynq_serial_tstc(port); } \
+- void uart_zynq##port##_putc(const char c) \
+- { uart_zynq_serial_putc(c, port); } \
+- void uart_zynq##port##_puts(const char *s) \
+- { uart_zynq_serial_puts(s, port); }
+-
+-/* Serial device descriptor */
+-#define INIT_PSSERIAL_STRUCTURE(port, __name) { \
+- .name = __name, \
+- .init = uart_zynq##port##_init, \
+- .uninit = NULL, \
+- .setbrg = uart_zynq##port##_setbrg, \
+- .getc = uart_zynq##port##_getc, \
+- .tstc = uart_zynq##port##_tstc, \
+- .putc = uart_zynq##port##_putc, \
+- .puts = uart_zynq##port##_puts, \
+-}
+-
+-DECLARE_PSSERIAL_FUNCTIONS(0);
+-struct serial_device uart_zynq_serial0_device =
+- INIT_PSSERIAL_STRUCTURE(0, "ttyPS0");
+-DECLARE_PSSERIAL_FUNCTIONS(1);
+-struct serial_device uart_zynq_serial1_device =
+- INIT_PSSERIAL_STRUCTURE(1, "ttyPS1");
+-
+-__weak struct serial_device *default_serial_console(void)
+-{
+- if (uart_zynq_ports[0])
+- return &uart_zynq_serial0_device;
+- if (uart_zynq_ports[1])
+- return &uart_zynq_serial1_device;
+-
+- return NULL;
+-}
+-#endif
+diff --git a/drivers/usb/host/ehci-mx5.c b/drivers/usb/host/ehci-mx5.c
+index 58cdcbe..fbfd310 100644
+--- a/drivers/usb/host/ehci-mx5.c
++++ b/drivers/usb/host/ehci-mx5.c
+@@ -221,7 +221,8 @@ int ehci_hcd_init(void)
+
+ set_usboh3_clk();
+ enable_usboh3_clk(1);
+- set_usb_phy2_clk();
++ set_usb_phy_clk();
++ enable_usb_phy1_clk(1);
+ enable_usb_phy2_clk(1);
+ mdelay(1);
+
+diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c
+index 9f7794f..19d061f 100644
+--- a/drivers/video/cfb_console.c
++++ b/drivers/video/cfb_console.c
+@@ -66,11 +66,7 @@
+ * CONFIG_CONSOLE_TIME - display time/date in upper right
+ * corner, needs CONFIG_CMD_DATE and
+ * CONFIG_CONSOLE_CURSOR
+- * CONFIG_VIDEO_LOGO - display Linux Logo in upper left corner.
+- * Use CONFIG_SPLASH_SCREEN_ALIGN with
+- * environment variable "splashpos" to place
+- * the logo on other position. In this case
+- * no CONSOLE_EXTRA_INFO is possible.
++ * CONFIG_VIDEO_LOGO - display Linux Logo in upper left corner
+ * CONFIG_VIDEO_BMP_LOGO - use bmp_logo instead of linux_logo
+ * CONFIG_CONSOLE_EXTRA_INFO - display additional board information
+ * strings that normaly goes to serial
+@@ -1484,42 +1480,7 @@ int video_display_bitmap(ulong bmp_image, int x, int y)
+
+
+ #ifdef CONFIG_VIDEO_LOGO
+-static int video_logo_xpos;
+-static int video_logo_ypos;
+-
+-static void plot_logo_or_black(void *screen, int width, int x, int y, \
+- int black);
+-
+-static void logo_plot(void *screen, int width, int x, int y)
+-{
+- plot_logo_or_black(screen, width, x, y, 0);
+-}
+-
+-static void logo_black(void)
+-{
+- plot_logo_or_black(video_fb_address, \
+- VIDEO_COLS, \
+- video_logo_xpos, \
+- video_logo_ypos, \
+- 1);
+-}
+-
+-static int do_clrlogo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+-{
+- if (argc != 1)
+- return cmd_usage(cmdtp);
+-
+- logo_black();
+- return 0;
+-}
+-
+-U_BOOT_CMD(
+- clrlogo, 1, 0, do_clrlogo,
+- "fill the boot logo area with black",
+- " "
+- );
+-
+-static void plot_logo_or_black(void *screen, int width, int x, int y, int black)
++void logo_plot(void *screen, int width, int x, int y)
+ {
+
+ int xcount, i;
+@@ -1527,21 +1488,8 @@ static void plot_logo_or_black(void *screen, int width, int x, int y, int black)
+ int ycount = video_logo_height;
+ unsigned char r, g, b, *logo_red, *logo_blue, *logo_green;
+ unsigned char *source;
+- unsigned char *dest;
+-
+-#ifdef CONFIG_SPLASH_SCREEN_ALIGN
+- if (x == BMP_ALIGN_CENTER)
+- x = max(0, (VIDEO_VISIBLE_COLS - VIDEO_LOGO_WIDTH) / 2);
+- else if (x < 0)
+- x = max(0, VIDEO_VISIBLE_COLS - VIDEO_LOGO_WIDTH + x + 1);
+-
+- if (y == BMP_ALIGN_CENTER)
+- y = max(0, (VIDEO_VISIBLE_ROWS - VIDEO_LOGO_HEIGHT) / 2);
+- else if (y < 0)
+- y = max(0, VIDEO_VISIBLE_ROWS - VIDEO_LOGO_HEIGHT + y + 1);
+-#endif /* CONFIG_SPLASH_SCREEN_ALIGN */
+-
+- dest = (unsigned char *)screen + (y * width + x) * VIDEO_PIXEL_SIZE;
++ unsigned char *dest = (unsigned char *) screen +
++ ((y * width * VIDEO_PIXEL_SIZE) + x * VIDEO_PIXEL_SIZE);
+
+ #ifdef CONFIG_VIDEO_BMP_LOGO
+ source = bmp_logo_bitmap;
+@@ -1577,15 +1525,9 @@ static void plot_logo_or_black(void *screen, int width, int x, int y, int black)
+ #endif
+ xcount = VIDEO_LOGO_WIDTH;
+ while (xcount--) {
+- if (black) {
+- r = 0x00;
+- g = 0x00;
+- b = 0x00;
+- } else {
+- r = logo_red[*source - VIDEO_LOGO_LUT_OFFSET];
+- g = logo_green[*source - VIDEO_LOGO_LUT_OFFSET];
+- b = logo_blue[*source - VIDEO_LOGO_LUT_OFFSET];
+- }
++ r = logo_red[*source - VIDEO_LOGO_LUT_OFFSET];
++ g = logo_green[*source - VIDEO_LOGO_LUT_OFFSET];
++ b = logo_blue[*source - VIDEO_LOGO_LUT_OFFSET];
+
+ switch (VIDEO_DATA_FORMAT) {
+ case GDF__8BIT_INDEX:
+@@ -1650,66 +1592,42 @@ static void *video_logo(void)
+ char info[128];
+ int space, len;
+ __maybe_unused int y_off = 0;
+- __maybe_unused ulong addr;
+- __maybe_unused char *s;
+
+-#ifdef CONFIG_SPLASH_SCREEN_ALIGN
+- s = getenv("splashpos");
++#ifdef CONFIG_SPLASH_SCREEN
++ char *s;
++ ulong addr;
++
++ s = getenv("splashimage");
+ if (s != NULL) {
+- if (s[0] == 'm')
+- video_logo_xpos = BMP_ALIGN_CENTER;
+- else
+- video_logo_xpos = simple_strtol(s, NULL, 0);
++ int x = 0, y = 0;
+
+- s = strchr(s + 1, ',');
++ addr = simple_strtoul(s, NULL, 16);
++#ifdef CONFIG_SPLASH_SCREEN_ALIGN
++ s = getenv("splashpos");
+ if (s != NULL) {
+- if (s[1] == 'm')
+- video_logo_ypos = BMP_ALIGN_CENTER;
++ if (s[0] == 'm')
++ x = BMP_ALIGN_CENTER;
+ else
+- video_logo_ypos = simple_strtol(s + 1, NULL, 0);
++ x = simple_strtol(s, NULL, 0);
++
++ s = strchr(s + 1, ',');
++ if (s != NULL) {
++ if (s[1] == 'm')
++ y = BMP_ALIGN_CENTER;
++ else
++ y = simple_strtol(s + 1, NULL, 0);
++ }
+ }
+- }
+ #endif /* CONFIG_SPLASH_SCREEN_ALIGN */
+
+-#ifdef CONFIG_SPLASH_SCREEN
+- s = getenv("splashimage");
+- if (s != NULL) {
+-
+- addr = simple_strtoul(s, NULL, 16);
+-
+-
+- if (video_display_bitmap(addr,
+- video_logo_xpos,
+- video_logo_ypos) == 0) {
++ if (video_display_bitmap(addr, x, y) == 0) {
+ video_logo_height = 0;
+ return ((void *) (video_fb_address));
+ }
+ }
+ #endif /* CONFIG_SPLASH_SCREEN */
+
+- logo_plot(video_fb_address, VIDEO_COLS,
+- video_logo_xpos, video_logo_ypos);
+-
+-#ifdef CONFIG_SPLASH_SCREEN_ALIGN
+- /*
+- * when using splashpos for video_logo, skip any info
+- * output on video console if the logo is not at 0,0
+- */
+- if (video_logo_xpos || video_logo_ypos) {
+- /*
+- * video_logo_height is used in text and cursor offset
+- * calculations. Since the console is below the logo,
+- * we need to adjust the logo height
+- */
+- if (video_logo_ypos == BMP_ALIGN_CENTER)
+- video_logo_height += max(0, (VIDEO_VISIBLE_ROWS - \
+- VIDEO_LOGO_HEIGHT) / 2);
+- else if (video_logo_ypos > 0)
+- video_logo_height += video_logo_ypos;
+-
+- return video_fb_address + video_logo_height * VIDEO_LINE_LEN;
+- }
+-#endif
++ logo_plot(video_fb_address, VIDEO_COLS, 0, 0);
+
+ sprintf(info, " %s", version_string);
+
+diff --git a/drivers/video/ipu_common.c b/drivers/video/ipu_common.c
+index 2020da9..ad4af52 100644
+--- a/drivers/video/ipu_common.c
++++ b/drivers/video/ipu_common.c
+@@ -94,6 +94,7 @@ struct ipu_ch_param {
+ temp1; \
+ })
+
++#define IPU_SW_RST_TOUT_USEC (10000)
+
+ void clk_enable(struct clk *clk)
+ {
+@@ -163,13 +164,13 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
+
+ static int clk_ipu_enable(struct clk *clk)
+ {
+-#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
+ u32 reg;
+
+ reg = __raw_readl(clk->enable_reg);
+ reg |= MXC_CCM_CCGR_CG_MASK << clk->enable_shift;
+ __raw_writel(reg, clk->enable_reg);
+
++#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
+ /* Handshake with IPU when certain clock rates are changed. */
+ reg = __raw_readl(&mxc_ccm->ccdr);
+ reg &= ~MXC_CCM_CCDR_IPU_HS_MASK;
+@@ -185,13 +186,13 @@ static int clk_ipu_enable(struct clk *clk)
+
+ static void clk_ipu_disable(struct clk *clk)
+ {
+-#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
+ u32 reg;
+
+ reg = __raw_readl(clk->enable_reg);
+ reg &= ~(MXC_CCM_CCGR_CG_MASK << clk->enable_shift);
+ __raw_writel(reg, clk->enable_reg);
+
++#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
+ /*
+ * No handshake with IPU whe dividers are changed
+ * as its not enabled.
+@@ -211,9 +212,15 @@ static void clk_ipu_disable(struct clk *clk)
+ static struct clk ipu_clk = {
+ .name = "ipu_clk",
+ .rate = CONFIG_IPUV3_CLK,
++#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
+ .enable_reg = (u32 *)(CCM_BASE_ADDR +
+ offsetof(struct mxc_ccm_reg, CCGR5)),
+- .enable_shift = MXC_CCM_CCGR5_CG5_OFFSET,
++ .enable_shift = MXC_CCM_CCGR5_IPU_OFFSET,
++#else
++ .enable_reg = (u32 *)(CCM_BASE_ADDR +
++ offsetof(struct mxc_ccm_reg, CCGR3)),
++ .enable_shift = MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET,
++#endif
+ .enable = clk_ipu_enable,
+ .disable = clk_ipu_disable,
+ .usecount = 0,
+@@ -392,11 +399,20 @@ void ipu_reset(void)
+ {
+ u32 *reg;
+ u32 value;
++ int timeout = IPU_SW_RST_TOUT_USEC;
+
+ reg = (u32 *)SRC_BASE_ADDR;
+ value = __raw_readl(reg);
+ value = value | SW_IPU_RST;
+ __raw_writel(value, reg);
++
++ while (__raw_readl(reg) & SW_IPU_RST) {
++ udelay(1);
++ if (!(timeout--)) {
++ printf("ipu software reset timeout\n");
++ break;
++ }
++ };
+ }
+
+ /*
+diff --git a/drivers/video/mxc_ipuv3_fb.c b/drivers/video/mxc_ipuv3_fb.c
+index 47b336e..ace226c 100644
+--- a/drivers/video/mxc_ipuv3_fb.c
++++ b/drivers/video/mxc_ipuv3_fb.c
+@@ -45,7 +45,7 @@ static int mxcfb_unmap_video_memory(struct fb_info *fbi);
+
+ /* graphics setup */
+ static GraphicDevice panel;
+-static struct fb_videomode *gmode;
++static struct fb_videomode const *gmode;
+ static uint8_t gdisp;
+ static uint32_t gpixfmt;
+
+@@ -503,7 +503,7 @@ static struct fb_info *mxcfb_init_fbinfo(void)
+ * @return Appropriate error code to the kernel common code
+ */
+ static int mxcfb_probe(u32 interface_pix_fmt, uint8_t disp,
+- struct fb_videomode *mode)
++ struct fb_videomode const *mode)
+ {
+ struct fb_info *fbi;
+ struct mxcfb_info *mxcfbi;
+@@ -619,7 +619,9 @@ void video_set_lut(unsigned int index, /* color number */
+ return;
+ }
+
+-int ipuv3_fb_init(struct fb_videomode *mode, uint8_t disp, uint32_t pixfmt)
++int ipuv3_fb_init(struct fb_videomode const *mode,
++ uint8_t disp,
++ uint32_t pixfmt)
+ {
+ gmode = mode;
+ gdisp = disp;
+diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c
+index d6d55b9..3deffd5 100644
+--- a/fs/ext4/ext4_common.c
++++ b/fs/ext4/ext4_common.c
+@@ -314,7 +314,7 @@ int ext4fs_checksum_update(unsigned int i)
+ struct ext_filesystem *fs = get_fs();
+ __u16 crc = 0;
+
+- desc = (struct ext2_block_group *)&fs->bgd[i];
++ desc = (struct ext2_block_group *)&fs->gd[i];
+ if (fs->sb->feature_ro_compat & EXT4_FEATURE_RO_COMPAT_GDT_CSUM) {
+ int offset = offsetof(struct ext2_block_group, bg_checksum);
+
+@@ -874,17 +874,17 @@ long int ext4fs_get_new_blk_no(void)
+ char *zero_buffer = zalloc(fs->blksz);
+ if (!journal_buffer || !zero_buffer)
+ goto fail;
+- struct ext2_block_group *bgd = (struct ext2_block_group *)fs->gdtable;
++ struct ext2_block_group *gd = (struct ext2_block_group *)fs->gdtable;
+
+ if (fs->first_pass_bbmap == 0) {
+ for (i = 0; i < fs->no_blkgrp; i++) {
+- if (bgd[i].free_blocks) {
+- if (bgd[i].bg_flags & EXT4_BG_BLOCK_UNINIT) {
+- put_ext4(((uint64_t) (bgd[i].block_id *
++ if (gd[i].free_blocks) {
++ if (gd[i].bg_flags & EXT4_BG_BLOCK_UNINIT) {
++ put_ext4(((uint64_t) (gd[i].block_id *
+ fs->blksz)),
+ zero_buffer, fs->blksz);
+- bgd[i].bg_flags =
+- bgd[i].
++ gd[i].bg_flags =
++ gd[i].
+ bg_flags & ~EXT4_BG_BLOCK_UNINIT;
+ memcpy(fs->blk_bmaps[i], zero_buffer,
+ fs->blksz);
+@@ -897,16 +897,16 @@ long int ext4fs_get_new_blk_no(void)
+ fs->curr_blkno = fs->curr_blkno +
+ (i * fs->blksz * 8);
+ fs->first_pass_bbmap++;
+- bgd[i].free_blocks--;
++ gd[i].free_blocks--;
+ fs->sb->free_blocks--;
+- status = ext4fs_devread(bgd[i].block_id *
++ status = ext4fs_devread(gd[i].block_id *
+ fs->sect_perblk, 0,
+ fs->blksz,
+ journal_buffer);
+ if (status == 0)
+ goto fail;
+ if (ext4fs_log_journal(journal_buffer,
+- bgd[i].block_id))
++ gd[i].block_id))
+ goto fail;
+ goto success;
+ } else {
+@@ -935,19 +935,19 @@ restart:
+ if (bg_idx >= fs->no_blkgrp)
+ goto fail;
+
+- if (bgd[bg_idx].free_blocks == 0) {
++ if (gd[bg_idx].free_blocks == 0) {
+ debug("block group %u is full. Skipping\n", bg_idx);
+ fs->curr_blkno = fs->curr_blkno + blk_per_grp;
+ fs->curr_blkno--;
+ goto restart;
+ }
+
+- if (bgd[bg_idx].bg_flags & EXT4_BG_BLOCK_UNINIT) {
++ if (gd[bg_idx].bg_flags & EXT4_BG_BLOCK_UNINIT) {
+ memset(zero_buffer, '\0', fs->blksz);
+- put_ext4(((uint64_t) (bgd[bg_idx].block_id *
+- fs->blksz)), zero_buffer, fs->blksz);
++ put_ext4(((uint64_t) (gd[bg_idx].block_id * fs->blksz)),
++ zero_buffer, fs->blksz);
+ memcpy(fs->blk_bmaps[bg_idx], zero_buffer, fs->blksz);
+- bgd[bg_idx].bg_flags = bgd[bg_idx].bg_flags &
++ gd[bg_idx].bg_flags = gd[bg_idx].bg_flags &
+ ~EXT4_BG_BLOCK_UNINIT;
+ }
+
+@@ -961,18 +961,18 @@ restart:
+ /* journal backup */
+ if (prev_bg_bitmap_index != bg_idx) {
+ memset(journal_buffer, '\0', fs->blksz);
+- status = ext4fs_devread(bgd[bg_idx].block_id
++ status = ext4fs_devread(gd[bg_idx].block_id
+ * fs->sect_perblk,
+ 0, fs->blksz, journal_buffer);
+ if (status == 0)
+ goto fail;
+ if (ext4fs_log_journal(journal_buffer,
+- bgd[bg_idx].block_id))
++ gd[bg_idx].block_id))
+ goto fail;
+
+ prev_bg_bitmap_index = bg_idx;
+ }
+- bgd[bg_idx].free_blocks--;
++ gd[bg_idx].free_blocks--;
+ fs->sb->free_blocks--;
+ goto success;
+ }
+@@ -1000,21 +1000,19 @@ int ext4fs_get_new_inode_no(void)
+ char *zero_buffer = zalloc(fs->blksz);
+ if (!journal_buffer || !zero_buffer)
+ goto fail;
+- struct ext2_block_group *bgd = (struct ext2_block_group *)fs->gdtable;
++ struct ext2_block_group *gd = (struct ext2_block_group *)fs->gdtable;
+
+ if (fs->first_pass_ibmap == 0) {
+ for (i = 0; i < fs->no_blkgrp; i++) {
+- if (bgd[i].free_inodes) {
+- if (bgd[i].bg_itable_unused !=
+- bgd[i].free_inodes)
+- bgd[i].bg_itable_unused =
+- bgd[i].free_inodes;
+- if (bgd[i].bg_flags & EXT4_BG_INODE_UNINIT) {
++ if (gd[i].free_inodes) {
++ if (gd[i].bg_itable_unused != gd[i].free_inodes)
++ gd[i].bg_itable_unused =
++ gd[i].free_inodes;
++ if (gd[i].bg_flags & EXT4_BG_INODE_UNINIT) {
+ put_ext4(((uint64_t)
+- (bgd[i].inode_id *
+- fs->blksz)),
++ (gd[i].inode_id * fs->blksz)),
+ zero_buffer, fs->blksz);
+- bgd[i].bg_flags = bgd[i].bg_flags &
++ gd[i].bg_flags = gd[i].bg_flags &
+ ~EXT4_BG_INODE_UNINIT;
+ memcpy(fs->inode_bmaps[i],
+ zero_buffer, fs->blksz);
+@@ -1027,17 +1025,17 @@ int ext4fs_get_new_inode_no(void)
+ fs->curr_inode_no = fs->curr_inode_no +
+ (i * inodes_per_grp);
+ fs->first_pass_ibmap++;
+- bgd[i].free_inodes--;
+- bgd[i].bg_itable_unused--;
++ gd[i].free_inodes--;
++ gd[i].bg_itable_unused--;
+ fs->sb->free_inodes--;
+- status = ext4fs_devread(bgd[i].inode_id *
++ status = ext4fs_devread(gd[i].inode_id *
+ fs->sect_perblk, 0,
+ fs->blksz,
+ journal_buffer);
+ if (status == 0)
+ goto fail;
+ if (ext4fs_log_journal(journal_buffer,
+- bgd[i].inode_id))
++ gd[i].inode_id))
+ goto fail;
+ goto success;
+ } else
+@@ -1049,13 +1047,13 @@ restart:
+ fs->curr_inode_no++;
+ /* get the blockbitmap index respective to blockno */
+ ibmap_idx = fs->curr_inode_no / inodes_per_grp;
+- if (bgd[ibmap_idx].bg_flags & EXT4_BG_INODE_UNINIT) {
++ if (gd[ibmap_idx].bg_flags & EXT4_BG_INODE_UNINIT) {
+ memset(zero_buffer, '\0', fs->blksz);
+- put_ext4(((uint64_t) (bgd[ibmap_idx].inode_id *
++ put_ext4(((uint64_t) (gd[ibmap_idx].inode_id *
+ fs->blksz)), zero_buffer,
+ fs->blksz);
+- bgd[ibmap_idx].bg_flags =
+- bgd[ibmap_idx].bg_flags & ~EXT4_BG_INODE_UNINIT;
++ gd[ibmap_idx].bg_flags =
++ gd[ibmap_idx].bg_flags & ~EXT4_BG_INODE_UNINIT;
+ memcpy(fs->inode_bmaps[ibmap_idx], zero_buffer,
+ fs->blksz);
+ }
+@@ -1071,22 +1069,21 @@ restart:
+ /* journal backup */
+ if (prev_inode_bitmap_index != ibmap_idx) {
+ memset(journal_buffer, '\0', fs->blksz);
+- status = ext4fs_devread(bgd[ibmap_idx].inode_id
++ status = ext4fs_devread(gd[ibmap_idx].inode_id
+ * fs->sect_perblk,
+ 0, fs->blksz, journal_buffer);
+ if (status == 0)
+ goto fail;
+ if (ext4fs_log_journal(journal_buffer,
+- bgd[ibmap_idx].inode_id))
++ gd[ibmap_idx].inode_id))
+ goto fail;
+ prev_inode_bitmap_index = ibmap_idx;
+ }
+- if (bgd[ibmap_idx].bg_itable_unused !=
+- bgd[ibmap_idx].free_inodes)
+- bgd[ibmap_idx].bg_itable_unused =
+- bgd[ibmap_idx].free_inodes;
+- bgd[ibmap_idx].free_inodes--;
+- bgd[ibmap_idx].bg_itable_unused--;
++ if (gd[ibmap_idx].bg_itable_unused != gd[ibmap_idx].free_inodes)
++ gd[ibmap_idx].bg_itable_unused =
++ gd[ibmap_idx].free_inodes;
++ gd[ibmap_idx].free_inodes--;
++ gd[ibmap_idx].bg_itable_unused--;
+ fs->sb->free_inodes--;
+ goto success;
+ }
+diff --git a/fs/ext4/ext4fs.c b/fs/ext4/ext4fs.c
+index 3a5ef20..93dcb7e 100644
+--- a/fs/ext4/ext4fs.c
++++ b/fs/ext4/ext4fs.c
+@@ -209,14 +209,14 @@ static void ext4fs_update(void)
+
+ /* update block groups */
+ for (i = 0; i < fs->no_blkgrp; i++) {
+- fs->bgd[i].bg_checksum = ext4fs_checksum_update(i);
+- put_ext4((uint64_t)(fs->bgd[i].block_id * fs->blksz),
++ fs->gd[i].bg_checksum = ext4fs_checksum_update(i);
++ put_ext4((uint64_t)(fs->gd[i].block_id * fs->blksz),
+ fs->blk_bmaps[i], fs->blksz);
+ }
+
+ /* update inode table groups */
+ for (i = 0; i < fs->no_blkgrp; i++) {
+- put_ext4((uint64_t) (fs->bgd[i].inode_id * fs->blksz),
++ put_ext4((uint64_t) (fs->gd[i].inode_id * fs->blksz),
+ fs->inode_bmaps[i], fs->blksz);
+ }
+
+@@ -266,7 +266,7 @@ fail:
+
+ static void delete_single_indirect_block(struct ext2_inode *inode)
+ {
+- struct ext2_block_group *bgd = NULL;
++ struct ext2_block_group *gd = NULL;
+ static int prev_bg_bmap_idx = -1;
+ long int blknr;
+ int remainder;
+@@ -280,7 +280,7 @@ static void delete_single_indirect_block(struct ext2_inode *inode)
+ return;
+ }
+ /* get block group descriptor table */
+- bgd = (struct ext2_block_group *)fs->gdtable;
++ gd = (struct ext2_block_group *)fs->gdtable;
+
+ /* deleting the single indirect block associated with inode */
+ if (inode->b.blocks.indir_block != 0) {
+@@ -295,18 +295,18 @@ static void delete_single_indirect_block(struct ext2_inode *inode)
+ bg_idx--;
+ }
+ ext4fs_reset_block_bmap(blknr, fs->blk_bmaps[bg_idx], bg_idx);
+- bgd[bg_idx].free_blocks++;
++ gd[bg_idx].free_blocks++;
+ fs->sb->free_blocks++;
+ /* journal backup */
+ if (prev_bg_bmap_idx != bg_idx) {
+ status =
+- ext4fs_devread(bgd[bg_idx].block_id *
++ ext4fs_devread(gd[bg_idx].block_id *
+ fs->sect_perblk, 0, fs->blksz,
+ journal_buffer);
+ if (status == 0)
+ goto fail;
+ if (ext4fs_log_journal
+- (journal_buffer, bgd[bg_idx].block_id))
++ (journal_buffer, gd[bg_idx].block_id))
+ goto fail;
+ prev_bg_bmap_idx = bg_idx;
+ }
+@@ -326,7 +326,7 @@ static void delete_double_indirect_block(struct ext2_inode *inode)
+ unsigned int blk_per_grp = ext4fs_root->sblock.blocks_per_group;
+ unsigned int *di_buffer = NULL;
+ unsigned int *DIB_start_addr = NULL;
+- struct ext2_block_group *bgd = NULL;
++ struct ext2_block_group *gd = NULL;
+ struct ext_filesystem *fs = get_fs();
+ char *journal_buffer = zalloc(fs->blksz);
+ if (!journal_buffer) {
+@@ -334,7 +334,7 @@ static void delete_double_indirect_block(struct ext2_inode *inode)
+ return;
+ }
+ /* get the block group descriptor table */
+- bgd = (struct ext2_block_group *)fs->gdtable;
++ gd = (struct ext2_block_group *)fs->gdtable;
+
+ if (inode->b.blocks.double_indir_block != 0) {
+ di_buffer = zalloc(fs->blksz);
+@@ -362,11 +362,11 @@ static void delete_double_indirect_block(struct ext2_inode *inode)
+ ext4fs_reset_block_bmap(*di_buffer,
+ fs->blk_bmaps[bg_idx], bg_idx);
+ di_buffer++;
+- bgd[bg_idx].free_blocks++;
++ gd[bg_idx].free_blocks++;
+ fs->sb->free_blocks++;
+ /* journal backup */
+ if (prev_bg_bmap_idx != bg_idx) {
+- status = ext4fs_devread(bgd[bg_idx].block_id
++ status = ext4fs_devread(gd[bg_idx].block_id
+ * fs->sect_perblk, 0,
+ fs->blksz,
+ journal_buffer);
+@@ -374,7 +374,7 @@ static void delete_double_indirect_block(struct ext2_inode *inode)
+ goto fail;
+
+ if (ext4fs_log_journal(journal_buffer,
+- bgd[bg_idx].block_id))
++ gd[bg_idx].block_id))
+ goto fail;
+ prev_bg_bmap_idx = bg_idx;
+ }
+@@ -391,19 +391,19 @@ static void delete_double_indirect_block(struct ext2_inode *inode)
+ bg_idx--;
+ }
+ ext4fs_reset_block_bmap(blknr, fs->blk_bmaps[bg_idx], bg_idx);
+- bgd[bg_idx].free_blocks++;
++ gd[bg_idx].free_blocks++;
+ fs->sb->free_blocks++;
+ /* journal backup */
+ if (prev_bg_bmap_idx != bg_idx) {
+ memset(journal_buffer, '\0', fs->blksz);
+- status = ext4fs_devread(bgd[bg_idx].block_id *
++ status = ext4fs_devread(gd[bg_idx].block_id *
+ fs->sect_perblk, 0, fs->blksz,
+ journal_buffer);
+ if (status == 0)
+ goto fail;
+
+ if (ext4fs_log_journal(journal_buffer,
+- bgd[bg_idx].block_id))
++ gd[bg_idx].block_id))
+ goto fail;
+ prev_bg_bmap_idx = bg_idx;
+ }
+@@ -427,7 +427,7 @@ static void delete_triple_indirect_block(struct ext2_inode *inode)
+ unsigned int *tib_start_addr = NULL;
+ unsigned int *tip_buffer = NULL;
+ unsigned int *tipb_start_addr = NULL;
+- struct ext2_block_group *bgd = NULL;
++ struct ext2_block_group *gd = NULL;
+ struct ext_filesystem *fs = get_fs();
+ char *journal_buffer = zalloc(fs->blksz);
+ if (!journal_buffer) {
+@@ -435,7 +435,7 @@ static void delete_triple_indirect_block(struct ext2_inode *inode)
+ return;
+ }
+ /* get block group descriptor table */
+- bgd = (struct ext2_block_group *)fs->gdtable;
++ gd = (struct ext2_block_group *)fs->gdtable;
+
+ if (inode->b.blocks.triple_indir_block != 0) {
+ tigp_buffer = zalloc(fs->blksz);
+@@ -477,21 +477,20 @@ static void delete_triple_indirect_block(struct ext2_inode *inode)
+ bg_idx);
+
+ tip_buffer++;
+- bgd[bg_idx].free_blocks++;
++ gd[bg_idx].free_blocks++;
+ fs->sb->free_blocks++;
+ /* journal backup */
+ if (prev_bg_bmap_idx != bg_idx) {
+ status =
+- ext4fs_devread(
+- bgd[bg_idx].block_id *
+- fs->sect_perblk, 0,
+- fs->blksz,
+- journal_buffer);
++ ext4fs_devread(gd[bg_idx].block_id *
++ fs->sect_perblk, 0,
++ fs->blksz,
++ journal_buffer);
+ if (status == 0)
+ goto fail;
+
+ if (ext4fs_log_journal(journal_buffer,
+- bgd[bg_idx].
++ gd[bg_idx].
+ block_id))
+ goto fail;
+ prev_bg_bmap_idx = bg_idx;
+@@ -517,20 +516,20 @@ static void delete_triple_indirect_block(struct ext2_inode *inode)
+ fs->blk_bmaps[bg_idx], bg_idx);
+
+ tigp_buffer++;
+- bgd[bg_idx].free_blocks++;
++ gd[bg_idx].free_blocks++;
+ fs->sb->free_blocks++;
+ /* journal backup */
+ if (prev_bg_bmap_idx != bg_idx) {
+ memset(journal_buffer, '\0', fs->blksz);
+ status =
+- ext4fs_devread(bgd[bg_idx].block_id *
++ ext4fs_devread(gd[bg_idx].block_id *
+ fs->sect_perblk, 0,
+ fs->blksz, journal_buffer);
+ if (status == 0)
+ goto fail;
+
+ if (ext4fs_log_journal(journal_buffer,
+- bgd[bg_idx].block_id))
++ gd[bg_idx].block_id))
+ goto fail;
+ prev_bg_bmap_idx = bg_idx;
+ }
+@@ -547,19 +546,19 @@ static void delete_triple_indirect_block(struct ext2_inode *inode)
+ bg_idx--;
+ }
+ ext4fs_reset_block_bmap(blknr, fs->blk_bmaps[bg_idx], bg_idx);
+- bgd[bg_idx].free_blocks++;
++ gd[bg_idx].free_blocks++;
+ fs->sb->free_blocks++;
+ /* journal backup */
+ if (prev_bg_bmap_idx != bg_idx) {
+ memset(journal_buffer, '\0', fs->blksz);
+- status = ext4fs_devread(bgd[bg_idx].block_id *
++ status = ext4fs_devread(gd[bg_idx].block_id *
+ fs->sect_perblk, 0, fs->blksz,
+ journal_buffer);
+ if (status == 0)
+ goto fail;
+
+ if (ext4fs_log_journal(journal_buffer,
+- bgd[bg_idx].block_id))
++ gd[bg_idx].block_id))
+ goto fail;
+ prev_bg_bmap_idx = bg_idx;
+ }
+@@ -591,13 +590,13 @@ static int ext4fs_delete_file(int inodeno)
+ unsigned int blk_per_grp = ext4fs_root->sblock.blocks_per_group;
+ unsigned int inode_per_grp = ext4fs_root->sblock.inodes_per_group;
+ struct ext2_inode *inode_buffer = NULL;
+- struct ext2_block_group *bgd = NULL;
++ struct ext2_block_group *gd = NULL;
+ struct ext_filesystem *fs = get_fs();
+ char *journal_buffer = zalloc(fs->blksz);
+ if (!journal_buffer)
+ return -ENOMEM;
+ /* get the block group descriptor table */
+- bgd = (struct ext2_block_group *)fs->gdtable;
++ gd = (struct ext2_block_group *)fs->gdtable;
+ status = ext4fs_read_inode(ext4fs_root, inodeno, &inode);
+ if (status == 0)
+ goto fail;
+@@ -632,19 +631,19 @@ static int ext4fs_delete_file(int inodeno)
+ debug("EXT4_EXTENTS Block releasing %ld: %d\n",
+ blknr, bg_idx);
+
+- bgd[bg_idx].free_blocks++;
++ gd[bg_idx].free_blocks++;
+ fs->sb->free_blocks++;
+
+ /* journal backup */
+ if (prev_bg_bmap_idx != bg_idx) {
+ status =
+- ext4fs_devread(bgd[bg_idx].block_id *
++ ext4fs_devread(gd[bg_idx].block_id *
+ fs->sect_perblk, 0,
+ fs->blksz, journal_buffer);
+ if (status == 0)
+ goto fail;
+ if (ext4fs_log_journal(journal_buffer,
+- bgd[bg_idx].block_id))
++ gd[bg_idx].block_id))
+ goto fail;
+ prev_bg_bmap_idx = bg_idx;
+ }
+@@ -677,19 +676,19 @@ static int ext4fs_delete_file(int inodeno)
+ bg_idx);
+ debug("ActualB releasing %ld: %d\n", blknr, bg_idx);
+
+- bgd[bg_idx].free_blocks++;
++ gd[bg_idx].free_blocks++;
+ fs->sb->free_blocks++;
+ /* journal backup */
+ if (prev_bg_bmap_idx != bg_idx) {
+ memset(journal_buffer, '\0', fs->blksz);
+- status = ext4fs_devread(bgd[bg_idx].block_id
++ status = ext4fs_devread(gd[bg_idx].block_id
+ * fs->sect_perblk,
+ 0, fs->blksz,
+ journal_buffer);
+ if (status == 0)
+ goto fail;
+ if (ext4fs_log_journal(journal_buffer,
+- bgd[bg_idx].block_id))
++ gd[bg_idx].block_id))
+ goto fail;
+ prev_bg_bmap_idx = bg_idx;
+ }
+@@ -702,7 +701,7 @@ static int ext4fs_delete_file(int inodeno)
+
+ /* get the block no */
+ inodeno--;
+- blkno = __le32_to_cpu(bgd[ibmap_idx].inode_table_id) +
++ blkno = __le32_to_cpu(gd[ibmap_idx].inode_table_id) +
+ (inodeno % __le32_to_cpu(inode_per_grp)) / inodes_per_block;
+
+ /* get the offset of the inode */
+@@ -732,15 +731,15 @@ static int ext4fs_delete_file(int inodeno)
+ /* update the respective inode bitmaps */
+ inodeno++;
+ ext4fs_reset_inode_bmap(inodeno, fs->inode_bmaps[ibmap_idx], ibmap_idx);
+- bgd[ibmap_idx].free_inodes++;
++ gd[ibmap_idx].free_inodes++;
+ fs->sb->free_inodes++;
+ /* journal backup */
+ memset(journal_buffer, '\0', fs->blksz);
+- status = ext4fs_devread(bgd[ibmap_idx].inode_id *
++ status = ext4fs_devread(gd[ibmap_idx].inode_id *
+ fs->sect_perblk, 0, fs->blksz, journal_buffer);
+ if (status == 0)
+ goto fail;
+- if (ext4fs_log_journal(journal_buffer, bgd[ibmap_idx].inode_id))
++ if (ext4fs_log_journal(journal_buffer, gd[ibmap_idx].inode_id))
+ goto fail;
+
+ ext4fs_update();
+@@ -798,7 +797,7 @@ int ext4fs_init(void)
+ printf("Error in getting the block group descriptor table\n");
+ goto fail;
+ }
+- fs->bgd = (struct ext2_block_group *)fs->gdtable;
++ fs->gd = (struct ext2_block_group *)fs->gdtable;
+
+ /* load all the available bitmap block of the partition */
+ fs->blk_bmaps = zalloc(fs->no_blkgrp * sizeof(char *));
+@@ -812,7 +811,7 @@ int ext4fs_init(void)
+
+ for (i = 0; i < fs->no_blkgrp; i++) {
+ status =
+- ext4fs_devread(fs->bgd[i].block_id * fs->sect_perblk, 0,
++ ext4fs_devread(fs->gd[i].block_id * fs->sect_perblk, 0,
+ fs->blksz, (char *)fs->blk_bmaps[i]);
+ if (status == 0)
+ goto fail;
+@@ -829,7 +828,7 @@ int ext4fs_init(void)
+ }
+
+ for (i = 0; i < fs->no_blkgrp; i++) {
+- status = ext4fs_devread(fs->bgd[i].inode_id * fs->sect_perblk,
++ status = ext4fs_devread(fs->gd[i].inode_id * fs->sect_perblk,
+ 0, fs->blksz,
+ (char *)fs->inode_bmaps[i]);
+ if (status == 0)
+@@ -843,7 +842,7 @@ int ext4fs_init(void)
+ * reboot of a linux kernel
+ */
+ for (i = 0; i < fs->no_blkgrp; i++)
+- real_free_blocks = real_free_blocks + fs->bgd[i].free_blocks;
++ real_free_blocks = real_free_blocks + fs->gd[i].free_blocks;
+ if (real_free_blocks != fs->sb->free_blocks)
+ fs->sb->free_blocks = real_free_blocks;
+
+@@ -908,7 +907,7 @@ void ext4fs_deinit(void)
+
+ free(fs->gdtable);
+ fs->gdtable = NULL;
+- fs->bgd = NULL;
++ fs->gd = NULL;
+ /*
+ * reinitiliazed the global inode and
+ * block bitmap first execution check variables
+@@ -1088,7 +1087,7 @@ int ext4fs_write(const char *fname, unsigned char *buffer,
+ goto fail;
+ ibmap_idx = inodeno / ext4fs_root->sblock.inodes_per_group;
+ inodeno--;
+- itable_blkno = __le32_to_cpu(fs->bgd[ibmap_idx].inode_table_id) +
++ itable_blkno = __le32_to_cpu(fs->gd[ibmap_idx].inode_table_id) +
+ (inodeno % __le32_to_cpu(sblock->inodes_per_group)) /
+ inodes_per_block;
+ blkoff = (inodeno % inodes_per_block) * fs->inodesz;
+@@ -1106,7 +1105,7 @@ int ext4fs_write(const char *fname, unsigned char *buffer,
+ }
+ ibmap_idx = parent_inodeno / ext4fs_root->sblock.inodes_per_group;
+ parent_inodeno--;
+- parent_itable_blkno = __le32_to_cpu(fs->bgd[ibmap_idx].inode_table_id) +
++ parent_itable_blkno = __le32_to_cpu(fs->gd[ibmap_idx].inode_table_id) +
+ (parent_inodeno %
+ __le32_to_cpu(sblock->inodes_per_group)) / inodes_per_block;
+ blkoff = (parent_inodeno % inodes_per_block) * fs->inodesz;
+diff --git a/fs/fat/fat.c b/fs/fat/fat.c
+index 80156c8..41ae15e 100644
+--- a/fs/fat/fat.c
++++ b/fs/fat/fat.c
+@@ -85,7 +85,7 @@ int fat_register_device(block_dev_desc_t * dev_desc, int part_no)
+
+ /* Otherwise it might be a superfloppy (whole-disk FAT filesystem) */
+ if (!cur_dev) {
+- if (part_no != 0) {
++ if (part_no != 1) {
+ printf("** Partition %d not valid on device %d **\n",
+ part_no, dev_desc->dev);
+ return -1;
+diff --git a/fs/yaffs2/yaffs_guts.c b/fs/yaffs2/yaffs_guts.c
+index 21441fd..00d1c5a 100644
+--- a/fs/yaffs2/yaffs_guts.c
++++ b/fs/yaffs2/yaffs_guts.c
+@@ -321,8 +321,9 @@ static int yaffs_check_chunk_erased(struct yaffs_dev *dev, int nand_chunk)
+ int retval = YAFFS_OK;
+ u8 *data = yaffs_get_temp_buffer(dev);
+ struct yaffs_ext_tags tags;
++ int result;
+
+- yaffs_rd_chunk_tags_nand(dev, nand_chunk, data, &tags);
++ result = yaffs_rd_chunk_tags_nand(dev, nand_chunk, data, &tags);
+
+ if (tags.ecc_result > YAFFS_ECC_RESULT_NO_ERROR)
+ retval = YAFFS_FAIL;
+@@ -348,8 +349,9 @@ static int yaffs_verify_chunk_written(struct yaffs_dev *dev,
+ int retval = YAFFS_OK;
+ struct yaffs_ext_tags temp_tags;
+ u8 *buffer = yaffs_get_temp_buffer(dev);
++ int result;
+
+- yaffs_rd_chunk_tags_nand(dev, nand_chunk, buffer, &temp_tags);
++ result = yaffs_rd_chunk_tags_nand(dev, nand_chunk, buffer, &temp_tags);
+ if (memcmp(buffer, data, dev->data_bytes_per_chunk) ||
+ temp_tags.obj_id != tags->obj_id ||
+ temp_tags.chunk_id != tags->chunk_id ||
+@@ -1483,6 +1485,7 @@ static struct yaffs_cache *yaffs_grab_chunk_cache(struct yaffs_dev *dev)
+ struct yaffs_obj *the_obj;
+ int usage;
+ int i;
++ int pushout;
+
+ if (dev->param.n_caches < 1)
+ return NULL;
+@@ -1503,6 +1506,7 @@ static struct yaffs_cache *yaffs_grab_chunk_cache(struct yaffs_dev *dev)
+ the_obj = dev->cache[0].object;
+ usage = -1;
+ cache = NULL;
++ pushout = -1;
+
+ for (i = 0; i < dev->param.n_caches; i++) {
+ if (dev->cache[i].object &&
+@@ -1512,6 +1516,7 @@ static struct yaffs_cache *yaffs_grab_chunk_cache(struct yaffs_dev *dev)
+ usage = dev->cache[i].last_use;
+ the_obj = dev->cache[i].object;
+ cache = &dev->cache[i];
++ pushout = i;
+ }
+ }
+
+@@ -3171,6 +3176,8 @@ static void yaffs_check_obj_details_loaded(struct yaffs_obj *in)
+ struct yaffs_obj_hdr *oh;
+ struct yaffs_dev *dev;
+ struct yaffs_ext_tags tags;
++ int result;
++ int alloc_failed = 0;
+
+ if (!in || !in->lazy_loaded || in->hdr_chunk < 1)
+ return;
+@@ -3179,7 +3186,7 @@ static void yaffs_check_obj_details_loaded(struct yaffs_obj *in)
+ in->lazy_loaded = 0;
+ buf = yaffs_get_temp_buffer(dev);
+
+- yaffs_rd_chunk_tags_nand(dev, in->hdr_chunk, buf, &tags);
++ result = yaffs_rd_chunk_tags_nand(dev, in->hdr_chunk, buf, &tags);
+ oh = (struct yaffs_obj_hdr *)buf;
+
+ in->yst_mode = oh->yst_mode;
+@@ -3189,6 +3196,8 @@ static void yaffs_check_obj_details_loaded(struct yaffs_obj *in)
+ if (in->variant_type == YAFFS_OBJECT_TYPE_SYMLINK) {
+ in->variant.symlink_variant.alias =
+ yaffs_clone_str(oh->alias);
++ if (!in->variant.symlink_variant.alias)
++ alloc_failed = 1; /* Not returned */
+ }
+ yaffs_release_temp_buffer(dev, buf);
+ }
+@@ -3276,6 +3285,7 @@ int yaffs_update_oh(struct yaffs_obj *in, const YCHAR *name, int force,
+ struct yaffs_dev *dev = in->my_dev;
+ int prev_chunk_id;
+ int ret_val = 0;
++ int result = 0;
+ int new_chunk_id;
+ struct yaffs_ext_tags new_tags;
+ struct yaffs_ext_tags old_tags;
+@@ -3299,8 +3309,8 @@ int yaffs_update_oh(struct yaffs_obj *in, const YCHAR *name, int force,
+ prev_chunk_id = in->hdr_chunk;
+
+ if (prev_chunk_id > 0) {
+- yaffs_rd_chunk_tags_nand(dev, prev_chunk_id,
+- buffer, &old_tags);
++ result = yaffs_rd_chunk_tags_nand(dev, prev_chunk_id,
++ buffer, &old_tags);
+
+ yaffs_verify_oh(in, oh, &old_tags, 0);
+ memcpy(old_name, oh->name, sizeof(oh->name));
+@@ -4434,6 +4444,7 @@ int yaffs_get_obj_name(struct yaffs_obj *obj, YCHAR *name, int buffer_size)
+ } else if (obj->short_name[0]) {
+ yaffs_strcpy(name, obj->short_name);
+ } else if (obj->hdr_chunk > 0) {
++ int result;
+ u8 *buffer = yaffs_get_temp_buffer(obj->my_dev);
+
+ struct yaffs_obj_hdr *oh = (struct yaffs_obj_hdr *)buffer;
+@@ -4441,9 +4452,9 @@ int yaffs_get_obj_name(struct yaffs_obj *obj, YCHAR *name, int buffer_size)
+ memset(buffer, 0, obj->my_dev->data_bytes_per_chunk);
+
+ if (obj->hdr_chunk > 0) {
+- yaffs_rd_chunk_tags_nand(obj->my_dev,
+- obj->hdr_chunk,
+- buffer, NULL);
++ result = yaffs_rd_chunk_tags_nand(obj->my_dev,
++ obj->hdr_chunk,
++ buffer, NULL);
+ }
+ yaffs_load_name_from_oh(obj->my_dev, name, oh->name,
+ buffer_size);
+diff --git a/fs/yaffs2/yaffs_summary.c b/fs/yaffs2/yaffs_summary.c
+index 46e42f6..6f3c783 100644
+--- a/fs/yaffs2/yaffs_summary.c
++++ b/fs/yaffs2/yaffs_summary.c
+@@ -191,7 +191,10 @@ int yaffs_summary_read(struct yaffs_dev *dev,
+ struct yaffs_summary_header hdr;
+ struct yaffs_block_info *bi = yaffs_get_block_info(dev, blk);
+ int sum_bytes_per_chunk = dev->data_bytes_per_chunk - sizeof(hdr);
++ int sum_tags_bytes;
+
++ sum_tags_bytes = sizeof(struct yaffs_summary_tags) *
++ dev->chunks_per_summary;
+ buffer = yaffs_get_temp_buffer(dev);
+ n_bytes = sizeof(struct yaffs_summary_tags) * dev->chunks_per_summary;
+ chunk_in_block = dev->chunks_per_summary;
+diff --git a/fs/yaffs2/yaffs_verify.c b/fs/yaffs2/yaffs_verify.c
+index 97734a9..db48e56 100644
+--- a/fs/yaffs2/yaffs_verify.c
++++ b/fs/yaffs2/yaffs_verify.c
+@@ -224,6 +224,7 @@ void yaffs_verify_file(struct yaffs_obj *obj)
+ {
+ u32 x;
+ int required_depth;
++ int actual_depth;
+ int last_chunk;
+ u32 offset_in_chunk;
+ u32 the_chunk;
+@@ -255,6 +256,8 @@ void yaffs_verify_file(struct yaffs_obj *obj)
+ required_depth++;
+ }
+
++ actual_depth = obj->variant.file_variant.top_level;
++
+ /* Check that the chunks in the tnode tree are all correct.
+ * We do this by scanning through the tnode tree and
+ * checking the tags for every chunk match.
+diff --git a/fs/yaffs2/yaffs_yaffs1.c b/fs/yaffs2/yaffs_yaffs1.c
+index 357d8f7..d277e20 100644
+--- a/fs/yaffs2/yaffs_yaffs1.c
++++ b/fs/yaffs2/yaffs_yaffs1.c
+@@ -23,6 +23,7 @@ int yaffs1_scan(struct yaffs_dev *dev)
+ {
+ struct yaffs_ext_tags tags;
+ int blk;
++ int result;
+ int chunk;
+ int c;
+ int deleted;
+@@ -94,7 +95,8 @@ int yaffs1_scan(struct yaffs_dev *dev)
+ /* Read the tags and decide what to do */
+ chunk = blk * dev->param.chunks_per_block + c;
+
+- yaffs_rd_chunk_tags_nand(dev, chunk, NULL, &tags);
++ result = yaffs_rd_chunk_tags_nand(dev, chunk, NULL,
++ &tags);
+
+ /* Let's have a good look at this chunk... */
+
+@@ -179,8 +181,9 @@ int yaffs1_scan(struct yaffs_dev *dev)
+ yaffs_set_chunk_bit(dev, blk, c);
+ bi->pages_in_use++;
+
+- yaffs_rd_chunk_tags_nand(dev, chunk,
+- chunk_data, NULL);
++ result = yaffs_rd_chunk_tags_nand(dev, chunk,
++ chunk_data,
++ NULL);
+
+ oh = (struct yaffs_obj_hdr *)chunk_data;
+
+diff --git a/fs/yaffs2/yaffs_yaffs2.c b/fs/yaffs2/yaffs_yaffs2.c
+index f76dcae..f1dc972 100644
+--- a/fs/yaffs2/yaffs_yaffs2.c
++++ b/fs/yaffs2/yaffs_yaffs2.c
+@@ -946,6 +946,7 @@ static inline int yaffs2_scan_chunk(struct yaffs_dev *dev,
+ int is_shrink;
+ int is_unlinked;
+ struct yaffs_ext_tags tags;
++ int result;
+ int alloc_failed = 0;
+ int chunk = blk * dev->param.chunks_per_block + chunk_in_block;
+ struct yaffs_file_var *file_var;
+@@ -953,12 +954,12 @@ static inline int yaffs2_scan_chunk(struct yaffs_dev *dev,
+ struct yaffs_symlink_var *sl_var;
+
+ if (summary_available) {
+- yaffs_summary_fetch(dev, &tags, chunk_in_block);
++ result = yaffs_summary_fetch(dev, &tags, chunk_in_block);
+ tags.seq_number = bi->seq_number;
+ }
+
+ if (!summary_available || tags.obj_id == 0) {
+- yaffs_rd_chunk_tags_nand(dev, chunk, NULL, &tags);
++ result = yaffs_rd_chunk_tags_nand(dev, chunk, NULL, &tags);
+ dev->tags_used++;
+ } else {
+ dev->summary_used++;
+@@ -1113,7 +1114,10 @@ static inline int yaffs2_scan_chunk(struct yaffs_dev *dev,
+ * invalid data until needed.
+ */
+
+- yaffs_rd_chunk_tags_nand(dev, chunk, chunk_data, NULL);
++ result = yaffs_rd_chunk_tags_nand(dev,
++ chunk,
++ chunk_data,
++ NULL);
+
+ oh = (struct yaffs_obj_hdr *)chunk_data;
+
+@@ -1345,6 +1349,7 @@ int yaffs2_scan_backwards(struct yaffs_dev *dev)
+ int n_to_scan = 0;
+ enum yaffs_block_state state;
+ int c;
++ int deleted;
+ LIST_HEAD(hard_list);
+ struct yaffs_block_info *bi;
+ u32 seq_number;
+@@ -1462,6 +1467,7 @@ int yaffs2_scan_backwards(struct yaffs_dev *dev)
+ /* get the block to scan in the correct order */
+ blk = block_index[block_iter].block;
+ bi = yaffs_get_block_info(dev, blk);
++ deleted = 0;
+
+ summary_available = yaffs_summary_read(dev, dev->sum_tags, blk);
+
+diff --git a/include/bootstage.h b/include/bootstage.h
+index db94a95..a000538 100644
+--- a/include/bootstage.h
++++ b/include/bootstage.h
+@@ -210,7 +210,6 @@ enum bootstage_id {
+ */
+ ulong timer_get_boot_us(void);
+
+-#ifndef CONFIG_SPL_BUILD
+ /*
+ * Board code can implement show_boot_progress() if needed.
+ *
+@@ -218,11 +217,8 @@ ulong timer_get_boot_us(void);
+ * has occurred.
+ */
+ void show_boot_progress(int val);
+-#else
+-#define show_boot_progress(val) do {} while (0)
+-#endif
+
+-#if defined(CONFIG_BOOTSTAGE) && !defined(CONFIG_SPL_BUILD)
++#ifdef CONFIG_BOOTSTAGE
+ /* This is the full bootstage implementation */
+
+ /*
+diff --git a/include/config_uncmd_spl.h b/include/config_uncmd_spl.h
+deleted file mode 100644
+index bab3ddf..0000000
+--- a/include/config_uncmd_spl.h
++++ /dev/null
+@@ -1,44 +0,0 @@
+-/*
+- * (C) Copyright 2012
+- * Ilya Yanok, ilya.yanok at gmail.com
+- *
+- * See file CREDITS for list of people who contributed to this
+- * project.
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of
+- * the License, or (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc.
+- *
+- * We don't use any commands in SPL, but generic networking code
+- * has some features enabled/disabled based on CONFIG_CMD_*
+- * options. As we want a minimal set of features included
+- * into network SPL image, we undefine some config options here.
+- */
+-
+-#ifndef __CONFIG_UNCMD_SPL_H__
+-#define __CONFIG_UNCMD_SPL_H__
+-
+-#ifdef CONFIG_SPL_BUILD
+-/* SPL needs only BOOTP + TFTP so undefine other stuff to save space */
+-#undef CONFIG_CMD_CDP
+-#undef CONFIG_CMD_DHCP
+-#undef CONFIG_CMD_DNS
+-#undef CONFIG_CMD_LINK_LOCAL
+-#undef CONFIG_CMD_NFS
+-#undef CONFIG_CMD_PING
+-#undef CONFIG_CMD_RARP
+-#undef CONFIG_CMD_SNTP
+-#undef CONFIG_CMD_TFTPPUT
+-#undef CONFIG_CMD_TFTPSRV
+-#endif /* CONFIG_SPL_BUILD */
+-#endif /* __CONFIG_UNCMD_SPL_H__ */
+diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h
+new file mode 100644
+index 0000000..95455c4
+--- /dev/null
++++ b/include/configs/TQM85xx.h
+@@ -0,0 +1,697 @@
++/*
++ * (C) Copyright 2007
++ * Thomas Waehner, TQ-System GmbH, thomas.waehner at tqs.de.
++ *
++ * (C) Copyright 2005
++ * Stefan Roese, DENX Software Engineering, sr at denx.de.
++ *
++ * Wolfgang Denk <wd at denx.de>
++ * Copyright 2004 Freescale Semiconductor.
++ * (C) Copyright 2002,2003 Motorola,Inc.
++ * Xianghua Xiao <X.Xiao at motorola.com>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++/*
++ * TQM85xx (8560/40/55/41/48) board configuration file
++ */
++
++#ifndef __CONFIG_H
++#define __CONFIG_H
++
++/* High Level Configuration Options */
++#define CONFIG_BOOKE 1 /* BOOKE */
++#define CONFIG_E500 1 /* BOOKE e500 family */
++#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */
++
++#if defined(CONFIG_TQM8548_BE)
++#define CONFIG_SYS_TEXT_BASE 0xfff80000
++#else
++#define CONFIG_SYS_TEXT_BASE 0xfffc0000
++#endif
++
++#if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE)
++#define CONFIG_TQM8548
++#endif
++
++#define CONFIG_PCI
++#ifndef CONFIG_TQM8548_AG
++#define CONFIG_PCI1 /* PCI/PCI-X controller */
++#endif
++#ifdef CONFIG_TQM8548
++#define CONFIG_PCIE1 /* PCI Express interface */
++#endif
++
++#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
++#define CONFIG_PCIX_CHECK /* PCIX olny works at 66 MHz */
++#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
++
++#define CONFIG_TSEC_ENET /* tsec ethernet support */
++
++#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
++
++ /*
++ * Configuration for big NOR Flashes
++ *
++ * Define CONFIG_TQM_BIGFLASH for boards with more than 128 MiB NOR Flash.
++ * Please be aware, that this changes the whole memory map (new CCSRBAR
++ * address, etc). You have to use an adapted Linux kernel or FDT blob
++ * if this option is set.
++ */
++#undef CONFIG_TQM_BIGFLASH
++
++/*
++ * NAND flash support (disabled by default)
++ *
++ * Warning: NAND support will likely increase the U-Boot image size
++ * to more than 256 KB. Please adjust CONFIG_SYS_TEXT_BASE if necessary.
++ */
++#ifdef CONFIG_TQM8548_BE
++#define CONFIG_NAND
++#endif
++
++/*
++ * MPC8540 and MPC8548 don't have CPM module
++ */
++#if !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8548)
++#define CONFIG_CPM2 1 /* has CPM2 */
++#endif
++
++#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
++
++#if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE)
++#define CONFIG_CAN_DRIVER /* CAN Driver support */
++#endif
++
++/*
++ * sysclk for MPC85xx
++ *
++ * Two valid values are:
++ * 33333333
++ * 66666666
++ *
++ * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
++ * is likely the desired value here, so that is now the default.
++ * The board, however, can run at 66MHz. In any event, this value
++ * must match the settings of some switches. Details can be found
++ * in the README.mpc85xxads.
++ */
++
++#ifndef CONFIG_SYS_CLK_FREQ
++#define CONFIG_SYS_CLK_FREQ 33333333
++#endif
++
++/*
++ * These can be toggled for performance analysis, otherwise use default.
++ */
++#define CONFIG_L2_CACHE /* toggle L2 cache */
++#define CONFIG_BTB /* toggle branch predition */
++
++#define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
++
++#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
++#define CONFIG_SYS_MEMTEST_START 0x00000000
++#define CONFIG_SYS_MEMTEST_END 0x10000000
++
++#ifdef CONFIG_TQM_BIGFLASH
++#define CONFIG_SYS_CCSRBAR 0xA0000000
++#else
++#define CONFIG_SYS_CCSRBAR 0xE0000000
++#endif
++#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
++
++/*
++ * DDR Setup
++ */
++#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
++
++#if defined(CONFIG_TQM_BIGFLASH) || \
++ (!defined(CONFIG_TQM8548_AG) && !defined(CONFIG_TQM8548_BE))
++#define CONFIG_SYS_PPC_DDR_WIMGE (MAS2_I | MAS2_G)
++#define CONFIG_SYS_DDR_EARLY_SIZE_MB (512)
++#else
++#define CONFIG_SYS_PPC_DDR_WIMGE (0)
++#define CONFIG_SYS_DDR_EARLY_SIZE_MB (2 * 1024)
++#endif
++
++#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
++#ifdef CONFIG_TQM8548_AG
++#define CONFIG_VERY_BIG_RAM
++#endif
++
++#define CONFIG_NUM_DDR_CONTROLLERS 1
++#define CONFIG_DIMM_SLOTS_PER_CTLR 1
++#define CONFIG_CHIP_SELECTS_PER_CTRL 2
++
++#if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560)
++/* TQM8540 & 8560 need DLL-override */
++#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */
++#define CONFIG_DDR_DEFAULT_CL 25 /* CAS latency 2,5 */
++#endif /* CONFIG_TQM8540 || CONFIG_TQM8560 */
++
++#if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) || \
++ defined(CONFIG_TQM8548)
++#define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */
++#endif /* CONFIG_TQM8541 || CONFIG_TQM8555 || CONFIG_TQM8548 */
++
++/*
++ * Flash on the Local Bus
++ */
++#ifdef CONFIG_TQM_BIGFLASH
++#define CONFIG_SYS_FLASH0 0xE0000000
++#define CONFIG_SYS_FLASH1 0xC0000000
++#else /* !CONFIG_TQM_BIGFLASH */
++#define CONFIG_SYS_FLASH0 0xFC000000
++#define CONFIG_SYS_FLASH1 0xF8000000
++#endif /* CONFIG_TQM_BIGFLASH */
++#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
++
++#define CONFIG_SYS_LBC_FLASH_BASE CONFIG_SYS_FLASH1 /* Localbus flash start */
++#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH */
++
++/* Default ORx timings are for <= 41.7 MHz Local Bus Clock.
++ *
++ * Note: According to timing specifications external addr latch delay
++ * (EAD, bit #0) must be set if Local Bus Clock is > 83 MHz.
++ *
++ * For other Local Bus Clocks see following table:
++ *
++ * Clock/MHz CONFIG_SYS_ORx_PRELIM
++ * 166 0x.....CA5
++ * 133 0x.....C85
++ * 100 0x.....C65
++ * 83 0x.....FA2
++ * 66 0x.....C82
++ * 50 0x.....C60
++ * 42 0x.....040
++ * 33 0x.....030
++ * 25 0x.....020
++ *
++ */
++#ifdef CONFIG_TQM_BIGFLASH
++#define CONFIG_SYS_BR0_PRELIM 0xE0001801 /* port size 32bit */
++#define CONFIG_SYS_OR0_PRELIM 0xE0000040 /* 512MB Flash */
++#define CONFIG_SYS_BR1_PRELIM 0xC0001801 /* port size 32bit */
++#define CONFIG_SYS_OR1_PRELIM 0xE0000040 /* 512MB Flash */
++#else /* !CONFIG_TQM_BIGFLASH */
++#define CONFIG_SYS_BR0_PRELIM 0xfc001801 /* port size 32bit */
++#define CONFIG_SYS_OR0_PRELIM 0xfc000040 /* 64MB Flash */
++#define CONFIG_SYS_BR1_PRELIM 0xf8001801 /* port size 32bit */
++#define CONFIG_SYS_OR1_PRELIM 0xfc000040 /* 64MB Flash */
++#endif /* CONFIG_TQM_BIGFLASH */
++
++#define CONFIG_SYS_FLASH_CFI /* flash is CFI compat. */
++#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
++#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector */
++#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/
++#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* speed up output to Flash */
++
++#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
++#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
++#undef CONFIG_SYS_FLASH_CHECKSUM
++#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
++#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
++
++#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
++
++/*
++ * Note: when changing the Local Bus clock divider you have to
++ * change the timing values in CONFIG_SYS_ORx_PRELIM.
++ *
++ * LCRR[00:03] CLKDIV: System (CCB) clock divider. Valid values are 2, 4, 8.
++ * LCRR[16:17] EADC : External address delay cycles. It should be set to 2
++ * for Local Bus Clock > 83.3 MHz.
++ */
++#define CONFIG_SYS_LBC_LCRR 0x00030008 /* LB clock ratio reg */
++#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
++#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
++#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/
++
++#define CONFIG_SYS_INIT_RAM_LOCK 1
++#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_CCSRBAR \
++ + 0x04010000) /* Initial RAM address */
++#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size used area in RAM */
++
++#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
++#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
++
++#define CONFIG_SYS_MONITOR_LEN (~CONFIG_SYS_TEXT_BASE + 1)/* Reserved for Monitor */
++#define CONFIG_SYS_MALLOC_LEN (384 * 1024) /* Reserved for malloc */
++
++/* Serial Port */
++#if defined(CONFIG_TQM8560)
++
++#define CONFIG_CONS_ON_SCC /* define if console on SCC */
++#undef CONFIG_CONS_NONE /* define if console on something else */
++#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
++
++#else /* !CONFIG_TQM8560 */
++
++#define CONFIG_CONS_INDEX 1
++#define CONFIG_SYS_NS16550
++#define CONFIG_SYS_NS16550_SERIAL
++#define CONFIG_SYS_NS16550_REG_SIZE 1
++#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
++
++#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
++#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
++
++/* PS/2 Keyboard */
++#define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
++#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
++#define CONFIG_PS2SERIAL 2 /* .. on DUART2 */
++#define CONFIG_PS2MULT_DELAY (CONFIG_SYS_HZ/2) /* Initial delay */
++#define CONFIG_BOARD_EARLY_INIT_R 1
++
++#endif /* CONFIG_TQM8560 */
++
++#define CONFIG_BAUDRATE 115200
++
++#define CONFIG_SYS_BAUDRATE_TABLE \
++ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
++
++#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
++#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
++#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
++
++/* pass open firmware flat tree */
++#define CONFIG_OF_LIBFDT 1
++#define CONFIG_OF_BOARD_SETUP 1
++#define CONFIG_OF_STDOUT_VIA_ALIAS 1
++
++/* CAN */
++#define CONFIG_SYS_CAN_BASE (CONFIG_SYS_CCSRBAR \
++ + 0x03000000) /* CAN base address */
++#ifdef CONFIG_CAN_DRIVER
++#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 KiB address mask */
++#define CONFIG_SYS_OR2_CAN (CONFIG_SYS_CAN_OR_AM | OR_UPM_BI)
++#define CONFIG_SYS_BR2_CAN ((CONFIG_SYS_CAN_BASE & BR_BA) | \
++ BR_PS_8 | BR_MS_UPMC | BR_V)
++#endif /* CONFIG_CAN_DRIVER */
++
++/*
++ * I2C
++ */
++#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
++#define CONFIG_HARD_I2C /* I2C with hardware support */
++#undef CONFIG_SOFT_I2C /* I2C bit-banged */
++#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
++#define CONFIG_SYS_I2C_SLAVE 0x7F
++#define CONFIG_SYS_I2C_NOPROBES {0x48} /* Don't probe these addrs */
++#define CONFIG_SYS_I2C_OFFSET 0x3000
++
++/* I2C RTC */
++#define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */
++#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
++
++/* I2C EEPROM */
++/*
++ * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work also).
++ */
++#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
++#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
++#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
++#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
++#define CONFIG_SYS_I2C_MULTI_EEPROMS 1 /* more than one eeprom */
++
++/* I2C SYSMON (LM75) */
++#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
++#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
++#define CONFIG_SYS_DTT_MAX_TEMP 70
++#define CONFIG_SYS_DTT_LOW_TEMP -30
++#define CONFIG_SYS_DTT_HYSTERESIS 3
++
++#ifndef CONFIG_PCIE1
++/* RapidIO MMU */
++#ifdef CONFIG_TQM_BIGFLASH
++#define CONFIG_SYS_RIO_MEM_BASE 0xb0000000 /* base address */
++#define CONFIG_SYS_RIO_MEM_SIZE 0x10000000 /* 256M */
++#else /* !CONFIG_TQM_BIGFLASH */
++#define CONFIG_SYS_RIO_MEM_BASE 0xc0000000 /* base address */
++#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */
++#endif /* CONFIG_TQM_BIGFLASH */
++#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE
++#endif /* CONFIG_PCIE1 */
++
++/* NAND FLASH */
++#ifdef CONFIG_NAND
++
++#define CONFIG_NAND_FSL_UPM 1
++
++#define CONFIG_MTD_NAND_ECC_JFFS2 1 /* use JFFS2 ECC */
++
++/* address distance between chip selects */
++#define CONFIG_SYS_NAND_SELECT_DEVICE 1
++#define CONFIG_SYS_NAND_CS_DIST 0x200
++
++#define CONFIG_SYS_NAND_SIZE 0x8000
++#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_CCSRBAR + 0x03010000)
++
++#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
++#define CONFIG_SYS_NAND_MAX_CHIPS 2 /* Number of chips per device */
++
++/* CS3 for NAND Flash */
++#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_NAND_BASE & BR_BA) | \
++ BR_PS_8 | BR_MS_UPMB | BR_V)
++#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_NAND_SIZE) | OR_UPM_BI)
++
++#define NAND_BIG_DELAY_US 25 /* max tR for Samsung devices */
++
++#endif /* CONFIG_NAND */
++
++/*
++ * General PCI
++ * Addresses are mapped 1-1.
++ */
++#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
++#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS
++#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
++#define CONFIG_SYS_PCI1_IO_BUS (CONFIG_SYS_CCSRBAR + 0x02000000)
++#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BUS
++#define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */
++
++#ifdef CONFIG_PCIE1
++/*
++ * General PCI express
++ * Addresses are mapped 1-1.
++ */
++#ifdef CONFIG_TQM_BIGFLASH
++#define CONFIG_SYS_PCIE1_MEM_BUS 0xb0000000
++#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 512M */
++#define CONFIG_SYS_PCIE1_IO_BUS 0xaf000000
++#else /* !CONFIG_TQM_BIGFLASH */
++#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
++#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
++#define CONFIG_SYS_PCIE1_IO_BUS 0xef000000
++#endif /* CONFIG_TQM_BIGFLASH */
++#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
++#define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_BUS
++#define CONFIG_SYS_PCIE1_IO_SIZE 0x1000000 /* 16M */
++#endif /* CONFIG_PCIE1 */
++
++#if defined(CONFIG_PCI)
++
++#define CONFIG_PCI_PNP /* do pci plug-and-play */
++
++#define CONFIG_EEPRO100
++#undef CONFIG_TULIP
++
++#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
++#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
++
++#endif /* CONFIG_PCI */
++
++
++#define CONFIG_MII 1 /* MII PHY management */
++#define CONFIG_TSEC1 1
++#define CONFIG_TSEC1_NAME "TSEC0"
++#define CONFIG_TSEC2 1
++#define CONFIG_TSEC2_NAME "TSEC1"
++#define TSEC1_PHY_ADDR 2
++#define TSEC2_PHY_ADDR 1
++#define TSEC1_PHYIDX 0
++#define TSEC2_PHYIDX 0
++#define TSEC1_FLAGS TSEC_GIGABIT
++#define TSEC2_FLAGS TSEC_GIGABIT
++#define FEC_PHY_ADDR 3
++#define FEC_PHYIDX 0
++#define FEC_FLAGS 0
++#define CONFIG_HAS_ETH0
++#define CONFIG_HAS_ETH1
++#define CONFIG_HAS_ETH2
++
++#ifdef CONFIG_TQM8548
++/*
++ * TQM8548 has 4 ethernet ports. 4 ETSEC's.
++ *
++ * On the STK85xx Starterkit the ETSEC3/4 ports are on an
++ * additional adapter (AIO) between module and Starterkit.
++ */
++#define CONFIG_TSEC3 1
++#define CONFIG_TSEC3_NAME "TSEC2"
++#define CONFIG_TSEC4 1
++#define CONFIG_TSEC4_NAME "TSEC3"
++#define TSEC3_PHY_ADDR 4
++#define TSEC4_PHY_ADDR 5
++#define TSEC3_PHYIDX 0
++#define TSEC4_PHYIDX 0
++#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
++#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
++#define CONFIG_HAS_ETH3
++#define CONFIG_HAS_ETH4
++#endif /* CONFIG_TQM8548 */
++
++/* Options are TSEC[0-1], FEC */
++#define CONFIG_ETHPRIME "TSEC0"
++
++#if defined(CONFIG_TQM8540)
++/*
++ * TQM8540 has 3 ethernet ports. 2 TSEC's and one FEC.
++ * The FEC port is connected on the same signals as the FCC3 port
++ * of the TQM8560 to the baseboard (STK85xx Starterkit).
++ *
++ * On the STK85xx Starterkit the X47/X50 jumper has to be set to
++ * a - d (X50.2 - 3) to enable the FEC port.
++ */
++#define CONFIG_MPC85XX_FEC 1
++#define CONFIG_MPC85XX_FEC_NAME "FEC"
++#endif
++
++#if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555)
++/*
++ * TQM8541/55 have 4 ethernet ports. 2 TSEC's and 2 FCC's. Only one FCC port
++ * can be used at once, since only one FCC port is available on the STK85xx
++ * Starterkit.
++ *
++ * To use this port you have to configure U-Boot to use the FCC port 1...2
++ * and set the X47/X50 jumper to:
++ * FCC1: a - b (X47.2 - X50.2)
++ * FCC2: a - c (X50.2 - 1)
++ */
++#define CONFIG_ETHER_ON_FCC
++#define CONFIG_ETHER_INDEX 1 /* FCC channel for ethernet */
++#endif
++
++#if defined(CONFIG_TQM8560)
++/*
++ * TQM8560 has 5 ethernet ports. 2 TSEC's and 3 FCC's. Only one FCC port
++ * can be used at once, since only one FCC port is available on the STK85xx
++ * Starterkit.
++ *
++ * To use this port you have to configure U-Boot to use the FCC port 1...3
++ * and set the X47/X50 jumper to:
++ * FCC1: a - b (X47.2 - X50.2)
++ * FCC2: a - c (X50.2 - 1)
++ * FCC3: a - d (X50.2 - 3)
++ */
++#define CONFIG_ETHER_ON_FCC
++#define CONFIG_ETHER_INDEX 3 /* FCC channel for ethernet */
++#endif
++
++#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
++#define CONFIG_ETHER_ON_FCC1
++#define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | \
++ CMXFCR_TF1CS_MSK)
++#define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12)
++#define CONFIG_SYS_CPMFCR_RAMTYPE 0
++#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
++#endif
++
++#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
++#define CONFIG_ETHER_ON_FCC2
++#define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | \
++ CMXFCR_TF2CS_MSK)
++#define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK16 | CMXFCR_TF2CS_CLK13)
++#define CONFIG_SYS_CPMFCR_RAMTYPE 0
++#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
++#endif
++
++#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
++#define CONFIG_ETHER_ON_FCC3
++#define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | \
++ CMXFCR_TF3CS_MSK)
++#define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14)
++#define CONFIG_SYS_CPMFCR_RAMTYPE 0
++#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
++#endif
++
++/*
++ * Environment
++ */
++#define CONFIG_ENV_IS_IN_FLASH 1
++
++#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K (one sector) for env */
++#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
++#define CONFIG_ENV_SIZE 0x2000
++#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
++#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
++
++#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
++#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
++
++#define CONFIG_TIMESTAMP /* Print image info with ts */
++
++/*
++ * BOOTP options
++ */
++#define CONFIG_BOOTP_BOOTFILESIZE
++#define CONFIG_BOOTP_BOOTPATH
++#define CONFIG_BOOTP_GATEWAY
++#define CONFIG_BOOTP_HOSTNAME
++
++#ifdef CONFIG_NAND
++/*
++ * Use NAND-FLash as JFFS2 device
++ */
++#define CONFIG_CMD_NAND
++#define CONFIG_CMD_JFFS2
++
++#define CONFIG_JFFS2_NAND 1
++
++#ifdef CONFIG_CMD_MTDPARTS
++#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
++#define CONFIG_FLASH_CFI_MTD
++#define MTDIDS_DEFAULT "nand0=TQM85xx-nand"
++#define MTDPARTS_DEFAULT "mtdparts=TQM85xx-nand:-"
++#else
++#define CONFIG_JFFS2_DEV "nand0" /* NAND device jffs2 lives on */
++#define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */
++#define CONFIG_JFFS2_PART_SIZE 0x200000 /* size of jffs2 partition */
++#endif /* CONFIG_CMD_MTDPARTS */
++
++#endif /* CONFIG_NAND */
++
++/*
++ * Command line configuration.
++ */
++#include <config_cmd_default.h>
++
++#define CONFIG_CMD_PING
++#define CONFIG_CMD_I2C
++#define CONFIG_CMD_DHCP
++#define CONFIG_CMD_NFS
++#define CONFIG_CMD_SNTP
++#ifndef CONFIG_TQM8548_AG
++#define CONFIG_CMD_DATE
++#endif
++#define CONFIG_CMD_EEPROM
++#define CONFIG_CMD_DTT
++#define CONFIG_CMD_MII
++#define CONFIG_CMD_REGINFO
++
++#if defined(CONFIG_PCI)
++#define CONFIG_CMD_PCI
++#endif
++
++#undef CONFIG_WATCHDOG /* watchdog disabled */
++
++/*
++ * Miscellaneous configurable options
++ */
++#define CONFIG_SYS_LONGHELP /* undef to save memory */
++#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
++#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
++
++#if defined(CONFIG_CMD_KGDB)
++#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
++#else
++#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
++#endif
++
++#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
++ sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buf Size */
++#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
++#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
++#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
++
++/*
++ * For booting Linux, the board info and command line data
++ * have to be in the first 8 MB of memory, since this is
++ * the maximum mapped by the Linux kernel during initialization.
++ */
++#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
++
++#if defined(CONFIG_CMD_KGDB)
++#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/
++#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
++#endif
++
++#define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/
++
++#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
++
++#define CONFIG_PREBOOT "echo;" \
++ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
++ "echo"
++
++#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
++
++
++/*
++ * Setup some board specific values for the default environment variables
++ */
++#ifdef CONFIG_CPM2
++#define CONFIG_ENV_CONSDEV "consdev=ttyCPM0\0"
++#else
++#define CONFIG_ENV_CONSDEV "consdev=ttyS0\0"
++#endif
++#define CONFIG_ENV_FDT_FILE "fdt_file="MK_STR(CONFIG_HOSTNAME)"/" \
++ MK_STR(CONFIG_HOSTNAME)".dtb\0"
++#define CONFIG_ENV_BOOTFILE "bootfile="MK_STR(CONFIG_HOSTNAME)"/uImage\0"
++#define CONFIG_ENV_UBOOT "uboot="MK_STR(CONFIG_HOSTNAME)"/u-boot.bin\0" \
++ "uboot_addr="MK_STR(CONFIG_SYS_TEXT_BASE)"\0"
++
++#define CONFIG_EXTRA_ENV_SETTINGS \
++ CONFIG_ENV_BOOTFILE \
++ CONFIG_ENV_FDT_FILE \
++ CONFIG_ENV_CONSDEV \
++ "netdev=eth0\0" \
++ "nfsargs=setenv bootargs root=/dev/nfs rw " \
++ "nfsroot=$serverip:$rootpath\0" \
++ "ramargs=setenv bootargs root=/dev/ram rw\0" \
++ "addip=setenv bootargs $bootargs " \
++ "ip=$ipaddr:$serverip:$gatewayip:$netmask" \
++ ":$hostname:$netdev:off panic=1\0" \
++ "addcons=setenv bootargs $bootargs " \
++ "console=$consdev,$baudrate\0" \
++ "flash_nfs=run nfsargs addip addcons;" \
++ "bootm $kernel_addr - $fdt_addr\0" \
++ "flash_self=run ramargs addip addcons;" \
++ "bootm $kernel_addr $ramdisk_addr $fdt_addr\0" \
++ "net_nfs=tftp $kernel_addr_r $bootfile;" \
++ "tftp $fdt_addr_r $fdt_file;" \
++ "run nfsargs addip addcons;" \
++ "bootm $kernel_addr_r - $fdt_addr_r\0" \
++ "rootpath=/opt/eldk/ppc_85xx\0" \
++ "fdt_addr_r=900000\0" \
++ "kernel_addr_r=1000000\0" \
++ "fdt_addr=ffec0000\0" \
++ "kernel_addr=ffd00000\0" \
++ "ramdisk_addr=ff800000\0" \
++ CONFIG_ENV_UBOOT \
++ "load=tftp 100000 $uboot\0" \
++ "update=protect off $uboot_addr +$filesize;" \
++ "erase $uboot_addr +$filesize;" \
++ "cp.b 100000 $uboot_addr $filesize" \
++ "upd=run load update\0" \
++ ""
++#define CONFIG_BOOTCOMMAND "run flash_self"
++
++#endif /* __CONFIG_H */
+diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
+index 339d4bd..263a5ad 100644
+--- a/include/configs/am335x_evm.h
++++ b/include/configs/am335x_evm.h
+@@ -45,7 +45,7 @@
+ #define CONFIG_VERSION_VARIABLE
+
+ /* set to negative value for no autoboot */
+-#define CONFIG_BOOTDELAY 1
++#define CONFIG_BOOTDELAY 3
+ #define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr=0x80200000\0" \
+ "fdtaddr=0x80F80000\0" \
+@@ -54,7 +54,7 @@
+ "console=ttyO0,115200n8\0" \
+ "optargs=\0" \
+ "mmcdev=0\0" \
+- "mmcroot=/dev/mmcblk0p2 ro\0" \
++ "mmcroot=/dev/mmcblk0p2 rw\0" \
+ "mmcrootfstype=ext4 rootwait\0" \
+ "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \
+ "ramrootfstype=ext2\0" \
+@@ -195,7 +195,7 @@
+ #define CONFIG_SPL
+ #define CONFIG_SPL_FRAMEWORK
+ #define CONFIG_SPL_TEXT_BASE 0x402F0400
+-#define CONFIG_SPL_MAX_SIZE (101 * 1024)
++#define CONFIG_SPL_MAX_SIZE (46 * 1024)
+ #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
+
+ #define CONFIG_SPL_BSS_START_ADDR 0x80000000
+@@ -215,9 +215,6 @@
+ #define CONFIG_SPL_SERIAL_SUPPORT
+ #define CONFIG_SPL_GPIO_SUPPORT
+ #define CONFIG_SPL_YMODEM_SUPPORT
+-#define CONFIG_SPL_NET_SUPPORT
+-#define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL"
+-#define CONFIG_SPL_ETH_SUPPORT
+ #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
+
+ /*
+diff --git a/include/configs/armadillo-800eva.h b/include/configs/armadillo-800eva.h
+deleted file mode 100644
+index b4402dd..0000000
+--- a/include/configs/armadillo-800eva.h
++++ /dev/null
+@@ -1,160 +0,0 @@
+-/*
+- * Configuation settings for the bonito board
+- *
+- * Copyright (C) 2012 Renesas Solutions Corp.
+- *
+- * See file CREDITS for list of people who contributed to this
+- * project.
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of
+- * the License, or (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+- * MA 02111-1307 USA
+- */
+-
+-#ifndef __ARMADILLO_800EVA_H
+-#define __ARMADILLO_800EVA_H
+-
+-#undef DEBUG
+-#define CONFIG_ARMV7
+-#define CONFIG_R8A7740
+-#define CONFIG_RMOBILE
+-#define CONFIG_RMOBILE_BOARD_STRING "Armadillo-800EVA Board\n"
+-#define CONFIG_SH_GPIO_PFC
+-
+-#include <asm/arch/rmobile.h>
+-
+-#define CONFIG_CMD_MEMORY
+-#define CONFIG_CMD_DFL
+-#define CONFIG_CMD_SDRAM
+-#define CONFIG_CMD_RUN
+-#define CONFIG_CMD_LOADS
+-#define CONFIG_CMD_NET
+-#define CONFIG_CMD_MII
+-#define CONFIG_CMD_PING
+-#define CONFIG_CMD_DHCP
+-#define CONFIG_CMD_NFS
+-#define CONFIG_CMD_BOOTZ
+-
+-#define CONFIG_OF_LIBFDT
+-#define BOARD_LATE_INIT
+-
+-#define CONFIG_BAUDRATE 115200
+-#define CONFIG_BOOTDELAY 3
+-#define CONFIG_BOOTARGS ""
+-
+-#define CONFIG_VERSION_VARIABLE
+-#undef CONFIG_SHOW_BOOT_PROGRESS
+-
+-#define CONFIG_ARCH_CPU_INIT
+-#define CONFIG_DISPLAY_CPUINFO
+-#define CONFIG_DISPLAY_BOARDINFO
+-#define CONFIG_BOARD_EARLY_INIT_F
+-#define CONFIG_USE_ARCH_MEMSET
+-#define CONFIG_USE_ARCH_MEMCPY
+-#define CONFIG_TMU_TIMER
+-#define CONFIG_SYS_DCACHE_OFF
+-
+-/* STACK */
+-#define CONFIG_SYS_INIT_SP_ADDR 0xE8083000
+-#define STACK_AREA_SIZE 0xC000
+-#define LOW_LEVEL_MERAM_STACK \
+- (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
+-
+-/* MEMORY */
+-#define ARMADILLO_800EVA_SDRAM_BASE 0x40000000
+-#define ARMADILLO_800EVA_SDRAM_SIZE (512 * 1024 * 1024)
+-
+-#define CONFIG_SYS_LONGHELP
+-#define CONFIG_SYS_PROMPT "=> "
+-#define CONFIG_SYS_CBSIZE 256
+-#define CONFIG_SYS_PBSIZE 256
+-#define CONFIG_SYS_MAXARGS 16
+-#define CONFIG_SYS_BARGSIZE 512
+-#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
+-
+-/* SCIF */
+-#define CONFIG_SCIF_CONSOLE
+-#define CONFIG_CONS_SCIF1
+-#define SCIF0_BASE 0xe6c40000
+-#define SCIF1_BASE 0xe6c50000
+-#define SCIF2_BASE 0xe6c60000
+-#define SCIF4_BASE 0xe6c80000
+-#define CONFIG_SCIF_A
+-#undef CONFIG_SYS_CONSOLE_INFO_QUIET
+-#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+-#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+-
+-#define CONFIG_SYS_MEMTEST_START (ARMADILLO_800EVA_SDRAM_BASE)
+-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
+- 504 * 1024 * 1024)
+-#undef CONFIG_SYS_ALT_MEMTEST
+-#undef CONFIG_SYS_MEMTEST_SCRATCH
+-#undef CONFIG_SYS_LOADS_BAUD_CHANGE
+-
+-#define CONFIG_SYS_SDRAM_BASE (ARMADILLO_800EVA_SDRAM_BASE)
+-#define CONFIG_SYS_SDRAM_SIZE (ARMADILLO_800EVA_SDRAM_SIZE)
+-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \
+- 64 * 1024 * 1024)
+-#define CONFIG_NR_DRAM_BANKS 1
+-
+-#define CONFIG_SYS_MONITOR_BASE 0x00000000
+-#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
+-#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
+-#define CONFIG_SYS_GBL_DATA_SIZE (256)
+-#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
+-#define CONFIG_SYS_TEXT_BASE 0xE80C0000
+-
+-/* FLASH */
+-#define CONFIG_SYS_NO_FLASH
+-#define CONFIG_SYS_FLASH_CFI
+-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+-#define CONFIG_SYS_FLASH_BASE 0x00000000
+-#define CONFIG_SYS_MAX_FLASH_SECT 512
+-#define CONFIG_SYS_MAX_FLASH_BANKS 1
+-#define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) }
+-
+-#define CONFIG_SYS_FLASH_ERASE_TOUT 3000
+-#define CONFIG_SYS_FLASH_WRITE_TOUT 3000
+-#define CONFIG_SYS_FLASH_LOCK_TOUT 3000
+-#define CONFIG_SYS_FLASH_UNLOCK_TOUT 3000
+-
+-/* ENV setting */
+-#define CONFIG_ENV_IS_IN_FLASH
+-#define CONFIG_ENV_OVERWRITE 1
+-#define CONFIG_ENV_SECT_SIZE (128 * 1024)
+-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
+- CONFIG_SYS_MONITOR_LEN)
+-#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR)
+-#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
+-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
+-
+-/* SH Ether */
+-#define CONFIG_NET_MULTI
+-#define CONFIG_SH_ETHER
+-#define CONFIG_SH_ETHER_USE_PORT 0
+-#define CONFIG_SH_ETHER_PHY_ADDR 0x0
+-#define CONFIG_SH_ETHER_BASE_ADDR 0xe9a00000
+-#define CONFIG_SH_ETHER_SH7734_MII (0x01)
+-#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
+-#define CONFIG_PHYLIB
+-#define CONFIG_PHY_SMSC
+-#define CONFIG_BITBANGMII
+-#define CONFIG_BITBANGMII_MULTI
+-
+-/* Board Clock */
+-#define CONFIG_SYS_CLK_FREQ 50000000
+-#define CONFIG_SYS_TMU_CLK_DIV 4
+-#define CONFIG_SYS_HZ 1000
+-
+-#endif /* __ARMADILLO_800EVA_H */
+diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h
+index 611e3e2..1e1fbe5 100644
+--- a/include/configs/at91sam9261ek.h
++++ b/include/configs/at91sam9261ek.h
+@@ -48,8 +48,6 @@
+
+ #define CONFIG_DISPLAY_CPUINFO
+
+-#define CONFIG_OF_LIBFDT
+-
+ #define CONFIG_ATMEL_LEGACY
+ #define CONFIG_SYS_TEXT_BASE 0x21f00000
+
+diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h
+index e988d81..4ca280a 100644
+--- a/include/configs/at91sam9m10g45ek.h
++++ b/include/configs/at91sam9m10g45ek.h
+@@ -47,8 +47,6 @@
+ #define CONFIG_BOARD_EARLY_INIT_F
+ #define CONFIG_DISPLAY_CPUINFO
+
+-#define CONFIG_OF_LIBFDT
+-
+ /* general purpose I/O */
+ #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
+ #define CONFIG_AT91_GPIO
+diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h
+index cbdc3e9..1ceb31a 100644
+--- a/include/configs/at91sam9x5ek.h
++++ b/include/configs/at91sam9x5ek.h
+@@ -42,8 +42,6 @@
+ #define CONFIG_BOARD_EARLY_INIT_F
+ #define CONFIG_DISPLAY_CPUINFO
+
+-#define CONFIG_OF_LIBFDT
+-
+ /* general purpose I/O */
+ #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
+ #define CONFIG_AT91_GPIO
+diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h
+index 1e65806..2d2ee5f 100644
+--- a/include/configs/devkit8000.h
++++ b/include/configs/devkit8000.h
+@@ -198,7 +198,6 @@
+ "run commonargs; " \
+ "setenv bootargs ${bootargs} " \
+ "root=/dev/mmcblk0p2 " \
+- "rootwait " \
+ "${kernelopts}\0" \
+ "nandargs=" \
+ "run commonargs; " \
+diff --git a/include/configs/ea20.h b/include/configs/ea20.h
+index c82b5b6..337d504 100644
+--- a/include/configs/ea20.h
++++ b/include/configs/ea20.h
+@@ -30,7 +30,6 @@
+ #define CONFIG_USE_SPIFLASH
+ #define CONFIG_SYS_USE_NAND
+ #define CONFIG_DRIVER_TI_EMAC_USE_RMII
+-#define CONFIG_DRIVER_TI_EMAC_RMII_NO_NEGOTIATE
+ #define CONFIG_BOARD_EARLY_INIT_F
+ #define CONFIG_BOARD_LATE_INIT
+ #define CONFIG_VIDEO
+@@ -98,7 +97,6 @@
+ * Network & Ethernet Configuration
+ */
+ #ifdef CONFIG_DRIVER_TI_EMAC
+-#define CONFIG_EMAC_MDIO_PHY_NUM 0
+ #define CONFIG_MII
+ #define CONFIG_BOOTP_DEFAULT
+ #define CONFIG_BOOTP_DNS
+@@ -122,14 +120,10 @@
+ #define CONFIG_VIDEO_DA8XX
+ #define CONFIG_CFB_CONSOLE
+ #define CONFIG_VGA_AS_SINGLE_DEVICE
+-#define CONFIG_SPLASH_SCREEN_ALIGN
++#define CONFIG_SPLASH_SCREEN
+ #define CONFIG_VIDEO_LOGO
+-#define CONFIG_SYS_CONSOLE_INFO_QUIET
+ #define CONFIG_VIDEO_BMP_RLE8
+-#define CONFIG_VIDEO_BMP_LOGO
+ #define CONFIG_CMD_BMP
+-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+-#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+ #endif
+
+ /*
+@@ -200,7 +194,6 @@
+
+ #define CONFIG_NAND_DAVINCI
+ #define CONFIG_SYS_NAND_PAGE_2K
+-#define CONFIG_SYS_NAND_NO_SUBPAGE
+ #define CONFIG_SYS_NAND_CS 2
+ #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
+ #undef CONFIG_SYS_NAND_HW_ECC
+@@ -239,39 +232,31 @@
+ #define xstr(s) str(s)
+ #define str(s) #s
+
++
+ #define CONFIG_HOSTNAME ea20
+-#define CONFIG_EXTRA_ENV_SETTINGS \
++#define CONFIG_EXTRA_ENV_SETTINGS \
+ "as=3\0" \
+- "netdev=eth0\0" \
++ "netdev=eth0\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "rfsbargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rfsbpath}\0" \
+- "testrfsargs=setenv bootargs root=/dev/nfs rw " \
+- "nfsroot=${serverip}:${testrfspath}\0" \
+- "ramargs=setenv bootargs root=/dev/ram rw initrd=" \
+- "0x${ramdisk_addr_r},4M\0" \
+- "mtdids=nand0=davinci_nand.0\0" \
+- "serverip=192.168.5.249\0" \
+- "ipaddr=192.168.5.248\0" \
+- "rootpath=/opt/eldk/arm\0" \
+- "splashpos=230,180\0" \
+- "testrfspath=/opt/eldk/test_arm\0" \
+- "tempmac=setenv ethaddr 02:ea:20:ff:ff:ff\0" \
++ "ramargs=setenv bootargs root=/dev/ram rw\0" \
++ "mtdids=nand0=davinci_nand.0\0" \
++ "mtdparts=mtdparts=davinci_nand.0:8m(Settings),8m(aKernel)," \
++ "8m(bKernel),76m(aRootfs),76m(bRootfs),-(MassSD)\0" \
+ "nandargs=setenv bootargs rootfstype=ubifs ro chk_data_crc " \
+ "ubi.mtd=${as} root=ubi0:rootfs\0" \
+- "nandrwargs=setenv bootargs rootfstype=ubifs rw chk_data_crc " \
+- "ubi.mtd=${as} root=ubi0:rootfs\0" \
+ "addip_sta=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
+- "addip=if test -n ${ipdyn};then run addip_dyn;" \
++ "addip=if test -n ${ipdyn};then run addip_dyn;" \
+ "else run addip_sta;fi\0" \
+ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+ "addtty=setenv bootargs ${bootargs}" \
+ " console=${consoledev},${baudrate}n8\0" \
+- "addmisc=setenv bootargs ${bootargs} ${misc}\0" \
++ "addmisc=setenv bootargs ${bootargs} ${misc}\0" \
+ "addmem=setenv bootargs ${bootargs} mem=${memory}\0" \
+ "consoledev=ttyS0\0" \
+ "loadaddr=c0000014\0" \
+@@ -279,57 +264,44 @@
+ "kernel_addr_r=c0700000\0" \
+ "hostname=" xstr(CONFIG_HOSTNAME) "\0" \
+ "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
+- "ramdisk_file=" xstr(CONFIG_HOSTNAME) "/image.ext2\0" \
++ "ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0" \
+ "flash_self=run ramargs addip addtty addmtd addmisc addmem;" \
+- "bootm ${kernel_addr_r}\0" \
++ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "flash_nfs=run nfsargs addip addtty addmtd addmisc addmem;" \
+ "bootm ${kernel_addr}\0" \
+- "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
++ "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
+ "run nfsargs addip addtty addmtd addmisc addmem;" \
+- "bootm ${kernel_addr_r}\0" \
+- "net_rfsb=tftp ${kernel_addr_r} ${bootfile}; " \
+- "run rfsbargs addip addtty addmtd addmisc addmem; " \
+- "bootm ${kernel_addr_r}\0" \
+- "net_testrfs=tftp ${kernel_addr_r} ${bootfile}; " \
+- "run testrfsargs addip addtty addmtd addmisc addmem; " \
+- "bootm ${kernel_addr_r}\0" \
++ "bootm ${kernel_addr_r}\0" \
++ "net_rfsb=tftp ${kernel_addr_r} ${bootfile}; " \
++ "run rfsbargs addip addtty addmtd addmisc addmem; " \
++ "bootm ${kernel_addr_r}\0" \
+ "net_self_load=tftp ${kernel_addr_r} ${bootfile};" \
+ "tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \
+- "nand_nand=ubi part nand0,${as};ubifsmount rootfs;" \
+- "ubifsload ${kernel_addr_r} /boot/uImage;" \
+- "ubifsumount; run nandargs addip addtty " \
+- "addmtd addmisc addmem;clrlogo;" \
+- "bootm ${kernel_addr_r}\0" \
+- "nand_nandrw=ubi part nand0,${as};ubifsmount rootfs;" \
+- "ubifsload ${kernel_addr_r} /boot/uImage;" \
+- "ubifsumount; run nandrwargs addip addtty " \
+- "addmtd addmisc addmem;clrlogo;" \
+- "bootm ${kernel_addr_r}\0" \
+- "net_nandrw=tftp ${kernel_addr_r} ${bootfile}; run nandrwargs" \
+- " addip addtty addmtd addmisc addmem;" \
+- "clrlogo;bootm ${kernel_addr_r}\0" \
+- "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \
+- "load_magic=if sf probe 0;then sf " \
+- "read c0000000 0x10000 0x60000;fi\0" \
+- "load_nand=ubi part nand0,${as};ubifsmount rootfs;" \
+- "if ubifsload c0000014 /boot/u-boot.bin;" \
+- "then mw c0000008 ${filesize};else echo Error reading" \
+- " u-boot from nand!;fi\0" \
+- "load_net=if sf probe 0;then sf read c0000000 0x10000 " \
+- "0x60000;tftp c0000014 ${u-boot};" \
+- "mw c0000008 ${filesize};fi\0" \
+- "upd=if sf probe 0;then sf erase 10000 60000;" \
+- "sf write c0000000 10000 60000;fi\0" \
+- "ublupdate=if tftp C0700000 ${ublname};then sf probe 0; " \
+- "sf erase 0 10000;" \
+- "sf write 0xc0700000 0 ${filesize};fi\0" \
+- "ubootupd_net=if run load_net;then echo Updating u-boot;" \
+- "if run upd; then echo U-Boot updated;" \
++ "nand_nand=ubi part nand0,${as};ubifsmount rootfs;" \
++ "ubifsload ${kernel_addr_r} /boot/uImage;" \
++ "ubifsumount; run nandargs addip addtty " \
++ "addmtd addmisc addmem;bootm ${kernel_addr_r}\0" \
++ "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \
++ "load_magic=if sf probe 0;then sf " \
++ "read c0000000 0x10000 0x60000;fi\0" \
++ "load_nand=ubi part nand0,${as};ubifsmount rootfs;" \
++ "if ubifsload c0000014 /boot/u-boot.bin;" \
++ "then mw c0000008 ${filesize};else echo Error reading " \
++ "u-boot from nand!;fi\0" \
++ "load_net=if sf probe 0;then sf read c0000000 0x10000 0x60000;" \
++ "tftp c0000014 ${u-boot};" \
++ "mw c0000008 ${filesize};" \
++ "fi\0" \
++ "upd=if sf probe 0;then sf erase 10000 60000;" \
++ "sf write c0000000 10000 60000;" \
++ "fi\0" \
++ "ubootupd_net=if run load_net;then echo Updating u-boot;" \
++ "if run upd; then echo U-Boot updated;" \
+ "else echo Error updating u-boot !;" \
+ "echo Board without bootloader !!;" \
+ "fi;" \
+- "else echo U-Boot not downloaded..exiting;fi\0" \
+- "ubootupd_nand=echo run load_magic,run load_nand,run upd;\0" \
+- "bootcmd=run tempmac;run net_testrfs\0"
++ "else echo U-Boot not downloaded..exiting;fi\0" \
++ "ubootupd_nand=echo run load_magic,run load_nand,run upd;\0" \
++ "bootcmd=run net_nfs\0"
+
+ #endif /* __CONFIG_H */
+diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h
+index adb505e..f2cfaf8 100644
+--- a/include/configs/edminiv2.h
++++ b/include/configs/edminiv2.h
+@@ -222,7 +222,7 @@
+ /*
+ * Size of malloc() pool
+ */
+-#define CONFIG_SYS_MALLOC_LEN (1024 * 256) /* 256kB for malloc() */
++#define CONFIG_SYS_MALLOC_LEN (1024 * 128) /* 128kB for malloc() */
+
+ /*
+ * Other required minimal configurations
+diff --git a/include/configs/iconnect.h b/include/configs/iconnect.h
+deleted file mode 100644
+index 2b523c9..0000000
+--- a/include/configs/iconnect.h
++++ /dev/null
+@@ -1,129 +0,0 @@
+-/*
+- * (C) Copyright 2009-2012
+- * Wojciech Dubowik <wojciech.dubowik at neratec.com>
+- * Luka Perkov <uboot at lukaperkov.net>
+- *
+- * See file CREDITS for list of people who contributed to this
+- * project.
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of
+- * the License, or (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+- */
+-
+-#ifndef _CONFIG_ICONNECT_H
+-#define _CONFIG_ICONNECT_H
+-
+-/*
+- * Version number information
+- */
+-#define CONFIG_IDENT_STRING " Iomega iConnect"
+-
+-/*
+- * High level configuration options
+- */
+-#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
+-#define CONFIG_KIRKWOOD /* SOC Family Name */
+-#define CONFIG_KW88F6281 /* SOC Name */
+-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
+-
+-/*
+- * Machine type
+- */
+-#define CONFIG_MACH_TYPE MACH_TYPE_ICONNECT
+-
+-/*
+- * Compression configuration
+- */
+-#define CONFIG_BZIP2
+-#define CONFIG_LZMA
+-#define CONFIG_LZO
+-
+-/*
+- * Commands configuration
+- */
+-#define CONFIG_SYS_NO_FLASH /* declare no flash (NOR/SPI) */
+-#define CONFIG_SYS_MVFS
+-#include <config_cmd_default.h>
+-#define CONFIG_CMD_ENV
+-#define CONFIG_CMD_MII
+-#define CONFIG_CMD_NAND
+-#define CONFIG_CMD_PING
+-#define CONFIG_CMD_USB
+-
+-/*
+- * mv-common.h should be defined after CMD configs since it used them
+- * to enable certain macros
+- */
+-#include "mv-common.h"
+-
+-#undef CONFIG_SYS_PROMPT
+-#define CONFIG_SYS_PROMPT "iconnect => "
+-
+-/*
+- * Environment variables configuration
+- */
+-#ifdef CONFIG_CMD_NAND
+-#define CONFIG_ENV_IS_IN_NAND
+-#define CONFIG_ENV_SECT_SIZE 0x20000
+-#else
+-#define CONFIG_ENV_IS_NOWHERE
+-#endif
+-#define CONFIG_ENV_SIZE 0x20000
+-#define CONFIG_ENV_OFFSET 0x80000
+-
+-/*
+- * Default environment variables
+- */
+-#define CONFIG_BOOTCOMMAND \
+- "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \
+- "ubi part rootfs; " \
+- "ubifsmount rootfs; " \
+- "ubifsload 0x800000 ${kernel}; " \
+- "bootm 0x800000"
+-
+-#define CONFIG_MTDPARTS \
+- "mtdparts=orion_nand:" \
+- "0x80000 at 0x0(uboot)," \
+- "0x20000 at 0x80000(uboot_env)," \
+- "- at 0xa0000(rootfs)\0"
+-
+-#define CONFIG_EXTRA_ENV_SETTINGS \
+- "console=console=ttyS0,115200\0" \
+- "mtdids=nand0=orion_nand\0" \
+- "mtdparts="CONFIG_MTDPARTS \
+- "kernel=/boot/uImage\0" \
+- "bootargs_root=noinitrd ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs\0"
+-
+-/*
+- * Ethernet driver configuration
+- */
+-#ifdef CONFIG_CMD_NET
+-#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
+-#define CONFIG_PHY_BASE_ADR 11
+-#undef CONFIG_RESET_PHY_R
+-#endif /* CONFIG_CMD_NET */
+-
+-/*
+- * File system
+- */
+-#define CONFIG_CMD_EXT2
+-#define CONFIG_CMD_FAT
+-#define CONFIG_CMD_JFFS2
+-#define CONFIG_CMD_UBI
+-#define CONFIG_CMD_UBIFS
+-#define CONFIG_RBTREE
+-#define CONFIG_MTD_DEVICE
+-#define CONFIG_MTD_PARTITIONS
+-#define CONFIG_CMD_MTDPARTS
+-
+-#endif /* _CONFIG_ICONNECT_H */
+diff --git a/include/configs/ima3-mx53.h b/include/configs/ima3-mx53.h
+index dbc59b9..499fb37 100644
+--- a/include/configs/ima3-mx53.h
++++ b/include/configs/ima3-mx53.h
+@@ -28,9 +28,6 @@
+ #include <asm/arch/imx-regs.h>
+ #include <asm/arch/mx5x_pins.h>
+
+-#define CONFIG_SYS_MX5_HCLK 24000000
+-#define CONFIG_SYS_MX5_CLK32 32768
+-
+ #define CONFIG_DISPLAY_CPUINFO
+ #define CONFIG_DISPLAY_BOARDINFO
+
+diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h
+index 762cc10..fba181f 100644
+--- a/include/configs/km_kirkwood.h
++++ b/include/configs/km_kirkwood.h
+@@ -62,8 +62,6 @@
+ #define CONFIG_KM_ENV_IS_IN_SPI_NOR
+ #define CONFIG_KM_FPGA_CONFIG
+ #define CONFIG_KM_PIGGY4_88E6352
+-#define CONFIG_MV88E6352_SWITCH
+-#define CONFIG_KM_MVEXTSW_ADDR 0x10
+
+ /* KM_MGCOGE3UN */
+ #elif defined(CONFIG_KM_MGCOGE3UN)
+diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h
+deleted file mode 100644
+index 3a882e3..0000000
+--- a/include/configs/kzm9g.h
++++ /dev/null
+@@ -1,169 +0,0 @@
+-/*
+- * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj at renesas.com>
+- * Copyright (C) 2012 Renesas Solutions Corp.
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of
+- * the License, or (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+- * MA 02111-1307 USA
+- */
+-
+-#ifndef __KZM9G_H
+-#define __KZM9G_H
+-
+-#undef DEBUG
+-
+-#define CONFIG_RMOBILE
+-#define CONFIG_SH73A0
+-#define CONFIG_KZM_A9_GT
+-#define CONFIG_RMOBILE_BOARD_STRING "KMC KZM-A9-GT"
+-#define CONFIG_MACH_TYPE MACH_TYPE_KZM9G
+-
+-#include <asm/arch/rmobile.h>
+-
+-#define CONFIG_ARCH_CPU_INIT
+-#define CONFIG_DISPLAY_CPUINFO
+-#define CONFIG_DISPLAY_BOARDINFO
+-#define CONFIG_BOARD_EARLY_INIT_F
+-#define CONFIG_L2_OFF
+-#define CONFIG_OF_LIBFDT
+-
+-#include <config_cmd_default.h>
+-#define CONFIG_CMDLINE_TAG
+-#define CONFIG_SETUP_MEMORY_TAGS
+-#define CONFIG_INITRD_TAG
+-#define CONFIG_DOS_PARTITION
+-#define CONFIG_CMD_FAT
+-#define CONFIG_CMD_BOOTZ
+-
+-#define CONFIG_BAUDRATE 115200
+-#define CONFIG_BOOTARGS "root=/dev/null console=ttySC4,115200"
+-#define CONFIG_BOOTDELAY 3
+-
+-#define CONFIG_VERSION_VARIABLE
+-#undef CONFIG_SHOW_BOOT_PROGRESS
+-
+-/* MEMORY */
+-#define KZM_SDRAM_BASE (0x40000000)
+-#define PHYS_SDRAM KZM_SDRAM_BASE
+-#define PHYS_SDRAM_SIZE (512 * 1024 * 1024)
+-#define CONFIG_NR_DRAM_BANKS (1)
+-
+-/* NOR Flash */
+-#define KZM_FLASH_BASE (0x00000000)
+-#define CONFIG_SYS_FLASH_BASE (KZM_FLASH_BASE)
+-#define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT)
+-#define CONFIG_SYS_MAX_FLASH_BANKS (1)
+-#define CONFIG_SYS_MAX_FLASH_SECT (512)
+-
+-/* prompt */
+-#define CONFIG_SYS_LONGHELP
+-#define CONFIG_SYS_PROMPT "KZM-A9-GT# "
+-#define CONFIG_SYS_CBSIZE 256
+-#define CONFIG_SYS_PBSIZE 256
+-#define CONFIG_SYS_MAXARGS 16
+-#define CONFIG_SYS_BARGSIZE 512
+-#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
+-
+-/* SCIF */
+-#define CONFIG_SCIF_CONSOLE
+-#define CONFIG_CONS_SCIF4
+-#undef CONFIG_SYS_CONSOLE_INFO_QUIET
+-#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+-#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+-
+-#define CONFIG_SYS_MEMTEST_START (KZM_SDRAM_BASE)
+-#define CONFIG_SYS_MEMTEST_END \
+- (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
+-#undef CONFIG_SYS_ALT_MEMTEST
+-#undef CONFIG_SYS_MEMTEST_SCRATCH
+-#undef CONFIG_SYS_LOADS_BAUD_CHANGE
+-
+-#define CONFIG_SYS_INIT_RAM_ADDR (0xE5600000) /* on MERAM */
+-#define CONFIG_SYS_INIT_RAM_SIZE (0x10000)
+-#define LOW_LEVEL_MERAM_STACK (CONFIG_SYS_INIT_RAM_ADDR - 4)
+-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+- CONFIG_SYS_INIT_RAM_SIZE - \
+- GENERATED_GBL_DATA_SIZE)
+-#define CONFIG_SDRAM_OFFSET_FOR_RT (16 * 1024 * 1024)
+-#define CONFIG_SYS_SDRAM_BASE (KZM_SDRAM_BASE + CONFIG_SDRAM_OFFSET_FOR_RT)
+-#define CONFIG_SYS_SDRAM_SIZE (PHYS_SDRAM_SIZE - CONFIG_SDRAM_OFFSET_FOR_RT)
+-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
+-
+-#define CONFIG_SYS_MONITOR_BASE (KZM_FLASH_BASE)
+-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
+-#define CONFIG_SYS_GBL_DATA_SIZE (256)
+-#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
+-
+-#define CONFIG_SYS_TEXT_BASE 0x00000000
+-#define CONFIG_STANDALONE_LOAD_ADDR 0x41000000
+-
+-/* FLASH */
+-#define CONFIG_FLASH_CFI_DRIVER
+-#define CONFIG_SYS_FLASH_CFI
+-#undef CONFIG_SYS_FLASH_QUIET_TEST
+-#define CONFIG_SYS_FLASH_EMPTY_INFO
+-#define FLASH_SECTOR_SIZE (256 * 1024) /* 256 KB sectors */
+-#define CONFIG_ENV_SIZE FLASH_SECTOR_SIZE
+-#define CONFIG_ENV_OFFSET FLASH_SECTOR_SIZE
+-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+-
+-/* Timeout for Flash erase operations (in ms) */
+-#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
+-/* Timeout for Flash write operations (in ms) */
+-#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
+-/* Timeout for Flash set sector lock bit operations (in ms) */
+-#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
+-/* Timeout for Flash clear lock bit operations (in ms) */
+-#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
+-
+-#undef CONFIG_SYS_FLASH_PROTECTION
+-#undef CONFIG_SYS_DIRECT_FLASH_TFTP
+-#define CONFIG_ENV_IS_IN_FLASH
+-
+-/* GPIO / PFC */
+-#define CONFIG_SH_GPIO_PFC
+-
+-/* Clock */
+-#define CONFIG_GLOBAL_TIMER
+-#define CONFIG_SYS_CLK_FREQ (48000000)
+-#define CONFIG_SYS_CPU_CLK (1196000000)
+-#define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */
+-#define CFG_HZ (1000)
+-#define CONFIG_SYS_HZ CFG_HZ
+-
+-/* Ether */
+-#define CONFIG_NET_MULTI
+-#define CONFIG_CMD_PING
+-#define CONFIG_CMD_DHCP
+-#define CONFIG_SMC911X
+-#define CONFIG_SMC911X_BASE (0x10000000)
+-#define CONFIG_SMC911X_32_BIT
+-#define CONFIG_NFS_TIMEOUT 10000UL
+-
+-/* I2C */
+-#define CONFIG_CMD_I2C
+-#define CONFIG_SH_I2C 1
+-#define CONFIG_HARD_I2C
+-#define CONFIG_I2C_MULTI_BUS
+-#define CONFIG_SYS_MAX_I2C_BUS (2)
+-#define CONFIG_SYS_I2C_MODULE
+-#define CONFIG_SYS_I2C_SPEED (100000) /* 100 kHz */
+-#define CONFIG_SYS_I2C_SLAVE (0x7F)
+-#define CONFIG_SH_I2C_DATA_HIGH (4)
+-#define CONFIG_SH_I2C_DATA_LOW (5)
+-#define CONFIG_SH_I2C_CLOCK (41666666)
+-#define CONFIG_SH_I2C_BASE0 (0xE6820000)
+-#define CONFIG_SH_I2C_BASE1 (0xE6822000)
+-
+-#endif /* __KZM9G_H */
+diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h
+index 09b5798..c35c2db 100644
+--- a/include/configs/lacie_kw.h
++++ b/include/configs/lacie_kw.h
+@@ -27,20 +27,9 @@
+ #elif defined(CONFIG_NETSPACE_V2)
+ #define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_V2
+ #define CONFIG_IDENT_STRING " NS v2"
+-#elif defined(CONFIG_NETSPACE_LITE_V2)
+-#define MACH_TYPE_NETSPACE_LITE_V2 2983 /* missing in mach-types.h */
+-#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_LITE_V2
+-#define CONFIG_IDENT_STRING " NS v2 Lite"
+-#elif defined(CONFIG_NETSPACE_MINI_V2)
+-#define MACH_TYPE_NETSPACE_MINI_V2 2831 /* missing in mach-types.h */
+-#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_MINI_V2
+-#define CONFIG_IDENT_STRING " NS v2 Mini"
+ #elif defined(CONFIG_NETSPACE_MAX_V2)
+ #define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_MAX_V2
+ #define CONFIG_IDENT_STRING " NS Max v2"
+-#elif defined(CONFIG_D2NET_V2)
+-#define CONFIG_MACH_TYPE MACH_TYPE_D2NET_V2
+-#define CONFIG_IDENT_STRING " D2 v2"
+ #elif defined(CONFIG_NET2BIG_V2)
+ #define CONFIG_MACH_TYPE MACH_TYPE_NET2BIG_V2
+ #define CONFIG_IDENT_STRING " 2Big v2"
+@@ -52,13 +41,8 @@
+ * High Level Configuration Options (easy to change)
+ */
+ #define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
+-#define CONFIG_KIRKWOOD /* SoC Family Name */
+-/* SoC name */
+-#if defined(CONFIG_NETSPACE_LITE_V2) || defined(CONFIG_NETSPACE_MINI_V2)
+-#define CONFIG_KW88F6192
+-#else
+-#define CONFIG_KW88F6281
+-#endif
++#define CONFIG_KIRKWOOD /* SOC Family Name */
++#define CONFIG_KW88F6281 /* SOC Name */
+ #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
+
+ /*
+@@ -72,9 +56,7 @@
+ #define CONFIG_CMD_SF
+ #define CONFIG_CMD_I2C
+ #define CONFIG_CMD_IDE
+-#ifndef CONFIG_NETSPACE_MINI_V2 /* No USB ports on Network Space v2 Mini */
+ #define CONFIG_CMD_USB
+-#endif
+
+ /*
+ * Core clock definition
+@@ -86,14 +68,9 @@
+ */
+ #define CONFIG_NR_DRAM_BANKS 1
+
+-/*
+- * Different SDRAM configuration and size for some of the boards derived
+- * from the Network Space v2
+- */
+-#if defined(CONFIG_INETSPACE_V2)
++#ifdef CONFIG_INETSPACE_V2
++/* Different SDRAM configuration and size for Internet Space v2 */
+ #define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-is2.cfg
+-#elif defined(CONFIG_NETSPACE_LITE_V2) || defined(CONFIG_NETSPACE_MINI_V2)
+-#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-ns2l.cfg
+ #endif
+
+ /*
+@@ -111,9 +88,7 @@
+ #define CONFIG_ENV_SPI_MAX_HZ 20000000 /* 20Mhz */
+ #define CONFIG_SYS_IDE_MAXBUS 1
+ #define CONFIG_SYS_IDE_MAXDEVICE 1
+-#if defined(CONFIG_D2NET_V2)
+-#define CONFIG_SYS_PROMPT "d2v2> "
+-#elif defined(CONFIG_NET2BIG_V2)
++#if defined(CONFIG_NET2BIG_V2)
+ #define CONFIG_SYS_PROMPT "2big2> "
+ #else
+ #define CONFIG_SYS_PROMPT "ns2> "
+@@ -133,8 +108,7 @@
+ */
+ #ifdef CONFIG_MVSATA_IDE
+ #define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
+-#if defined(CONFIG_NETSPACE_MAX_V2) || defined(CONFIG_D2NET_V2) || \
+- defined(CONFIG_NET2BIG_V2)
++#if defined(CONFIG_NETSPACE_MAX_V2) || defined(CONFIG_NET2BIG_V2)
+ #define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET
+ #endif
+ #endif /* CONFIG_MVSATA_IDE */
+@@ -156,12 +130,6 @@
+ #endif /* CONFIG_CMD_I2C */
+
+ /*
+- * Partition support
+- */
+-#define CONFIG_DOS_PARTITION
+-#define CONFIG_EFI_PARTITION
+-
+-/*
+ * File systems support
+ */
+ #define CONFIG_CMD_EXT2
+diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h
+index bdbb820..9eb2a54 100644
+--- a/include/configs/m28evk.h
++++ b/include/configs/m28evk.h
+@@ -246,20 +246,18 @@
+ #define CONFIG_MXS_SPI_DMA_ENABLE
+ #define CONFIG_SPI_HALF_DUPLEX
+ #define CONFIG_DEFAULT_SPI_BUS 2
+-#define CONFIG_DEFAULT_SPI_CS 0
+ #define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0
+
+ /* SPI FLASH */
+ #ifdef CONFIG_CMD_SF
+ #define CONFIG_SPI_FLASH
+ #define CONFIG_SPI_FLASH_STMICRO
+-#define CONFIG_SF_DEFAULT_BUS 2
+-#define CONFIG_SF_DEFAULT_CS 0
+-#define CONFIG_SF_DEFAULT_SPEED 40000000
++#define CONFIG_SF_DEFAULT_CS 2
+ #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
++#define CONFIG_SF_DEFAULT_SPEED 40000000
+
+-#define CONFIG_ENV_SPI_BUS 2
+ #define CONFIG_ENV_SPI_CS 0
++#define CONFIG_ENV_SPI_BUS 2
+ #define CONFIG_ENV_SPI_MAX_HZ 40000000
+ #define CONFIG_ENV_SPI_MODE SPI_MODE_0
+ #endif
+diff --git a/include/configs/mini2440.h b/include/configs/mini2440.h
+deleted file mode 100644
+index 980b4a5..0000000
+--- a/include/configs/mini2440.h
++++ /dev/null
+@@ -1,186 +0,0 @@
+-/*
+- * (C) Copyright 2002
+- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+- * Marius Groeger <mgroeger at sysgo.de>
+- * Gary Jennejohn <gj at denx.de>
+- * David Mueller <d.mueller at elsoft.ch>
+- *
+- * (C) Copyright 2009-2010
+- * Michel Pollet <buserror at gmail.com>
+- *
+- * (C) Copyright 2012
+- * Gabriel Huau <contact at huau-gabriel.fr>
+- *
+- * Configuation settings for the MINI2440 board.
+- *
+- * See file CREDITS for list of people who contributed to this
+- * project.
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of
+- * the License, or (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+- * MA 02111-1307 USA
+- */
+-
+-#ifndef __CONFIG_H
+-#define __CONFIG_H
+-
+-#define CONFIG_SYS_TEXT_BASE 0x0
+-#define CONFIG_S3C2440_GPIO
+-
+-/*
+- * High Level Configuration Options
+- */
+-#define CONFIG_ARM920T /* This is an ARM920T Core */
+-#define CONFIG_S3C24X0 /* in a SAMSUNG S3C24X0 SoC */
+-#define CONFIG_S3C2440 /* in a SAMSUNG S3C2440 SoC */
+-#define CONFIG_MINI2440 /* on a MIN2440 Board */
+-
+-#define MACH_TYPE_MINI2440 1999
+-#define CONFIG_MACH_TYPE MACH_TYPE_MINI2440
+-
+-/*
+- * We don't use lowlevel_init
+- */
+-#define CONFIG_SKIP_LOWLEVEL_INIT
+-#define CONFIG_BOARD_EARLY_INIT_F
+-
+-/*
+- * input clock of PLL
+- */
+-/* MINI2440 has 12.0000MHz input clock */
+-#define CONFIG_SYS_CLK_FREQ 12000000
+-
+-/*
+- * Size of malloc() pool
+- */
+-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048*1024)
+-
+-/*
+- * Hardware drivers
+- */
+-#define CONFIG_DRIVER_DM9000
+-#define CONFIG_DRIVER_DM9000_NO_EEPROM
+-#define CONFIG_DM9000_BASE 0x20000300
+-#define DM9000_IO CONFIG_DM9000_BASE
+-#define DM9000_DATA (CONFIG_DM9000_BASE+4)
+-
+-/*
+- * select serial console configuration
+- */
+-#define CONFIG_S3C24X0_SERIAL
+-#define CONFIG_SERIAL1
+-
+-/*
+- * allow to overwrite serial and ethaddr
+- */
+-#define CONFIG_ENV_OVERWRITE
+-
+-/*
+- * Command definition
+- */
+-#include <config_cmd_default.h>
+-
+-#define CONFIG_CMD_DHCP
+-#define CONFIG_CMD_PORTIO
+-#define CONFIG_CMD_REGINFO
+-#define CONFIG_CMD_SAVES
+-
+-/*
+- * Miscellaneous configurable options
+- */
+-#define CONFIG_LONGHELP
+-#define CONFIG_SYS_PROMPT "MINI2440 => "
+-#define CONFIG_SYS_CBSIZE 256
+-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+-#define CONFIG_SYS_MAXARGS 32
+-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+-
+-#define CONFIG_SYS_MEMTEST_START 0x30000000
+-#define CONFIG_SYS_MEMTEST_END 0x34000000 /* 64MB in DRAM */
+-
+-/* default load address */
+-#define CONFIG_SYS_LOAD_ADDR 0x32000000
+-
+-/* boot parameters address */
+-#define CONFIG_BOOT_PARAM_ADDR 0x30000100
+-
+-/*
+- * the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need
+- * it to wrap 100 times (total 1562500) to get 1 sec.
+- */
+-#define CONFIG_SYS_HZ 1562500
+-
+-/*
+- * valid baudrates
+- */
+-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+-#define CONFIG_BAUDRATE 115200
+-
+-/*
+- * Stack sizes
+- * The stack sizes are set up in start.S using the settings below
+- */
+-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+-#ifdef CONFIG_USE_IRQ
+-#define CONFIG_STACKSIZE_IRQ (8*1024) /* IRQ stack */
+-#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
+-#endif
+-
+-/*
+- * Physical Memory Map
+- */
+-#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+-#define PHYS_SDRAM_SIZE (64*1024*1024) /* 64MB of DRAM */
+-#define CONFIG_SYS_SDRAM_BASE 0x30000000
+-#define CONFIG_SYS_FLASH_BASE 0x0
+-
+-/*
+- * Stack should be on the SRAM because
+- * DRAM is not init
+- */
+-#define CONFIG_SYS_INIT_SP_ADDR (0x40001000 - GENERATED_GBL_DATA_SIZE)
+-
+-/*
+- * NOR FLASH organization
+- * Now uses the standard CFI interface
+- * FLASH and environment organization
+- */
+-#define CONFIG_SYS_FLASH_CFI
+-#define CONFIG_FLASH_CFI_DRIVER
+-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+-#define CONFIG_SYS_MONITOR_BASE 0x0
+-/* max number of memory banks */
+-#define CONFIG_SYS_MAX_FLASH_BANKS 1
+-/* 512 * 4096 sectors, or 32 * 64k blocks */
+-#define CONFIG_SYS_MAX_FLASH_SECT 512
+-#define CONFIG_FLASH_SHOW_PROGRESS 1
+-
+-/*
+- * Config for NOR flash
+- */
+-#define CONFIG_ENV_IS_IN_FLASH
+-#define CONFIG_MY_ENV_OFFSET 0x40000
+-/* addr of environment */
+-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_MY_ENV_OFFSET)
+-/* 16k Total Size of Environment Sector */
+-#define CONFIG_ENV_SIZE 0x4000
+-
+-/* ATAG configuration */
+-#define CONFIG_INITRD_TAG
+-#define CONFIG_SETUP_MEMORY_TAGS
+-#define CONFIG_CMDLINE_TAG
+-#define CONFIG_CMDLINE_EDITING
+-#define CONFIG_AUTO_COMPLETE
+-
+-#endif /* __CONFIG_H */
+diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h
+index 1e19ffa..f6a4497 100644
+--- a/include/configs/motionpro.h
++++ b/include/configs/motionpro.h
+@@ -2,7 +2,7 @@
+ * (C) Copyright 2003-2007
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+- * Based on Motion-PRO board config file by Robert McCullough, rob at promessinc.com
++ * Based on PRO Motion board config file by Andy Joseph, andy at promessdev.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+@@ -100,7 +100,6 @@
+
+ #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+ #define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
+-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+ #define CONFIG_ETHADDR 00:50:C2:40:10:00
+ #define CONFIG_OVERWRITE_ETHADDR_ONCE 1
+@@ -112,21 +111,21 @@
+ #define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "hostname=motionpro\0" \
+- "netmask=255.255.255.0\0" \
+- "ipaddr=192.168.1.106\0" \
+- "serverip=192.168.1.100\0" \
+- "gatewayip=192.168.1.100\0" \
++ "netmask=255.255.0.0\0" \
++ "ipaddr=192.168.160.22\0" \
++ "serverip=192.168.1.1\0" \
++ "gatewayip=192.168.1.1\0" \
+ "console=ttyPSC0,115200\0" \
+ "u-boot_addr=400000\0" \
+ "kernel_addr=400000\0" \
+ "fdt_addr=700000\0" \
+ "ramdisk_addr=800000\0" \
+ "multi_image_addr=800000\0" \
+- "rootpath=/opt/eldk-4.2/ppc_6xx\0" \
+- "u-boot=/tftpboot/motionpro/u-boot.bin\0" \
+- "bootfile=/tftpboot/motionpro/uImage\0" \
+- "fdt_file=/tftpboot/motionpro/motionpro.dtb\0" \
+- "ramdisk_file=/tftpboot/motionpro/uRamdisk\0" \
++ "rootpath=/opt/eldk/ppc_6xx\0" \
++ "u-boot=motionpro/u-boot.bin\0" \
++ "bootfile=motionpro/uImage\0" \
++ "fdt_file=motionpro/motionpro.dtb\0" \
++ "ramdisk_file=motionpro/uRamdisk\0" \
+ "multi_image_file=kernel+initrd+dtb.img\0" \
+ "load=tftp ${u-boot_addr} ${u-boot}\0" \
+ "update=prot off fff00000 +${filesize};" \
+@@ -136,32 +135,25 @@
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+- "fat_args=setenv bootargs root=/dev/sda rw\0" \
+- "mtdids=nor0=ff000000.flash\0" \
+- "mtdparts=ff000000.flash:13m(fs),2m(kernel),384k(uboot)," \
+- "128k(env),128k(redund_env)," \
+- "128k(dtb),128k(user_data)\0" \
+- "addcons=setenv bootargs ${bootargs} console=${console}\0" \
+- "addmtd=setenv bootargs ${bootargs} mtdparts=${mtdparts}\0" \
++ "fat_args=setenv bootargs rw\0" \
++ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:" \
+ "${netmask}:${hostname}:${netdev}:off panic=1 " \
+ "console=${console}\0" \
+ "net_nfs=tftp ${kernel_addr} ${bootfile}; " \
+- "tftp ${fdt_addr} ${fdt_file}; " \
+- "run nfsargs addip addmtd; " \
++ "tftp ${fdt_addr} ${fdt_file}; run nfsargs addip; " \
+ "bootm ${kernel_addr} - ${fdt_addr}\0" \
+ "net_self=tftp ${kernel_addr} ${bootfile}; " \
+ "tftp ${fdt_addr} ${fdt_file}; " \
+ "tftp ${ramdisk_addr} ${ramdisk_file}; " \
+- "nfs ${ramdisk_addr} ${serverip}:${rootpath}/images/uRamdisk; " \
+- "run ramargs addip addcons addmtd; " \
++ "run ramargs addip; " \
+ "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
+- "fat_multi=run fat_args addip addmtd; fatload ide 0:1 " \
++ "fat_multi=run fat_args addip; fatload ide 0:1 " \
+ "${multi_image_addr} ${multi_image_file}; " \
+ "bootm ${multi_image_addr}\0" \
+ ""
+-#define CONFIG_BOOTCOMMAND "run fat_multi"
++#define CONFIG_BOOTCOMMAND "run net_nfs"
+
+ /*
+ * do board-specific init
+@@ -217,7 +209,7 @@
+ #define CONFIG_SYS_RAMBOOT 1
+ #endif
+
+-#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* 384 kB for Monitor */
++#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 kB for Monitor */
+ #define CONFIG_SYS_MALLOC_LEN (1024 << 10) /* 1 MiB for malloc() */
+ #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* initial mem map for Linux */
+
+@@ -282,7 +274,7 @@
+ #define CONFIG_FLASH_CFI_MTD
+ #define MTDIDS_DEFAULT "nor0=motionpro-0"
+ #define MTDPARTS_DEFAULT "mtdparts=motionpro-0:" \
+- "13m(fs),2m(kernel),384k(uboot)," \
++ "13m(fs),2m(kernel),256k(uboot)," \
+ "128k(env),128k(redund_env)," \
+ "128k(dtb),-(user_data)"
+
+diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h
+index b272674..223b5b0 100644
+--- a/include/configs/mx31pdk.h
++++ b/include/configs/mx31pdk.h
+@@ -203,11 +203,11 @@
+
+ /* Configuration of lowlevel_init.S (clocks and SDRAM) */
+ #define CCM_CCMR_SETUP 0x074B0BF5
+-#define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | \
+- PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | \
+- PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | \
+- PDR0_MCU_PODF(0))
+-#define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | \
++#define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | \
++ PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | \
++ PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | \
++ PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0))
++#define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | \
+ PLL_MFN(12))
+
+ #define ESDMISC_MDDR_SETUP 0x00000004
+diff --git a/include/configs/mx51_efikamx.h b/include/configs/mx51_efikamx.h
+index 439b5f3..ffe771f 100644
+--- a/include/configs/mx51_efikamx.h
++++ b/include/configs/mx51_efikamx.h
+@@ -37,8 +37,6 @@
+
+ #include <asm/arch/imx-regs.h>
+
+-#define CONFIG_SYS_MX5_HCLK 24000000
+-#define CONFIG_SYS_MX5_CLK32 32768
+ #define CONFIG_DISPLAY_CPUINFO
+ #define CONFIG_DISPLAY_BOARDINFO
+
+diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h
+index 46b5373..34b0783 100644
+--- a/include/configs/mx51evk.h
++++ b/include/configs/mx51evk.h
+@@ -28,8 +28,6 @@
+
+ #define CONFIG_MX51 /* in a mx51 */
+
+-#define CONFIG_SYS_MX5_HCLK 24000000
+-#define CONFIG_SYS_MX5_CLK32 32768
+ #define CONFIG_DISPLAY_CPUINFO
+ #define CONFIG_DISPLAY_BOARDINFO
+
+@@ -98,6 +96,7 @@
+ /*
+ * Eth Configs
+ */
++#define CONFIG_HAS_ETH1
+ #define CONFIG_MII
+
+ #define CONFIG_FEC_MXC
+diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h
+index 6ab4cde..fea93b4 100644
+--- a/include/configs/mx53ard.h
++++ b/include/configs/mx53ard.h
+@@ -24,8 +24,6 @@
+
+ #define CONFIG_MX53
+
+-#define CONFIG_SYS_MX5_HCLK 24000000
+-#define CONFIG_SYS_MX5_CLK32 32768
+ #define CONFIG_DISPLAY_CPUINFO
+ #define CONFIG_DISPLAY_BOARDINFO
+
+diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h
+index a6977fe..832050e 100644
+--- a/include/configs/mx53evk.h
++++ b/include/configs/mx53evk.h
+@@ -24,8 +24,6 @@
+
+ #define CONFIG_MX53
+
+-#define CONFIG_SYS_MX5_HCLK 24000000
+-#define CONFIG_SYS_MX5_CLK32 32768
+ #define CONFIG_DISPLAY_CPUINFO
+ #define CONFIG_DISPLAY_BOARDINFO
+
+@@ -75,6 +73,7 @@
+ #define CONFIG_DOS_PARTITION
+
+ /* Eth Configs */
++#define CONFIG_HAS_ETH1
+ #define CONFIG_MII
+
+ #define CONFIG_FEC_MXC
+diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h
+index 49cd021..6a6aaa1 100644
+--- a/include/configs/mx53loco.h
++++ b/include/configs/mx53loco.h
+@@ -25,8 +25,6 @@
+
+ #define CONFIG_MX53
+
+-#define CONFIG_SYS_MX5_HCLK 24000000
+-#define CONFIG_SYS_MX5_CLK32 32768
+ #define CONFIG_DISPLAY_BOARDINFO
+
+ #define CONFIG_MACH_TYPE MACH_TYPE_MX53_LOCO
+@@ -60,6 +58,7 @@
+ #define CONFIG_DOS_PARTITION
+
+ /* Eth Configs */
++#define CONFIG_HAS_ETH1
+ #define CONFIG_MII
+
+ #define CONFIG_FEC_MXC
+@@ -119,8 +118,8 @@
+ "script=boot.scr\0" \
+ "uimage=uImage\0" \
+ "mmcdev=0\0" \
+- "mmcpart=1\0" \
+- "mmcroot=/dev/mmcblk0p2 rw\0" \
++ "mmcpart=2\0" \
++ "mmcroot=/dev/mmcblk0p3 rw\0" \
+ "mmcrootfstype=ext3 rootwait\0" \
+ "mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \
+ "root=${mmcroot} " \
+@@ -223,6 +222,6 @@
+ #define CONFIG_SPLASH_SCREEN
+ #define CONFIG_BMP_16BPP
+ #define CONFIG_VIDEO_LOGO
+-#define CONFIG_IPUV3_CLK 200000000
++#define CONFIG_IPUV3_CLK 133000000
+
+ #endif /* __CONFIG_H */
+diff --git a/include/configs/mx53smd.h b/include/configs/mx53smd.h
+index f54d328..ff2a290 100644
+--- a/include/configs/mx53smd.h
++++ b/include/configs/mx53smd.h
+@@ -24,8 +24,6 @@
+
+ #define CONFIG_MX53
+
+-#define CONFIG_SYS_MX5_HCLK 24000000
+-#define CONFIG_SYS_MX5_CLK32 32768
+ #define CONFIG_DISPLAY_CPUINFO
+ #define CONFIG_DISPLAY_BOARDINFO
+
+diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h
+index 6c17895..965bea3 100644
+--- a/include/configs/mx6qarm2.h
++++ b/include/configs/mx6qarm2.h
+@@ -23,8 +23,6 @@
+ #define __CONFIG_H
+
+ #define CONFIG_MX6Q
+-#define CONFIG_SYS_MX6_HCLK 24000000
+-#define CONFIG_SYS_MX6_CLK32 32768
+ #define CONFIG_DISPLAY_CPUINFO
+ #define CONFIG_DISPLAY_BOARDINFO
+
+diff --git a/include/configs/mx6qsabre_common.h b/include/configs/mx6qsabre_common.h
+index 5542481..247e8d6 100644
+--- a/include/configs/mx6qsabre_common.h
++++ b/include/configs/mx6qsabre_common.h
+@@ -18,8 +18,6 @@
+ #define __MX6QSABRE_COMMON_CONFIG_H
+
+ #define CONFIG_MX6Q
+-#define CONFIG_SYS_MX6_HCLK 24000000
+-#define CONFIG_SYS_MX6_CLK32 32768
+ #define CONFIG_DISPLAY_CPUINFO
+ #define CONFIG_DISPLAY_BOARDINFO
+
+@@ -88,7 +86,7 @@
+ "initrd_high=0xffffffff\0" \
+ "mmcdev=0\0" \
+ "mmcpart=1\0" \
+- "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
++ "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
+ "mmcargs=setenv bootargs console=${console},${baudrate} " \
+ "root=${mmcroot}\0" \
+ "loadbootscript=" \
+diff --git a/include/configs/mx6qsabreauto.h b/include/configs/mx6qsabreauto.h
+index 760f3ce..a878dec 100644
+--- a/include/configs/mx6qsabreauto.h
++++ b/include/configs/mx6qsabreauto.h
+@@ -1,7 +1,7 @@
+ /*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+- * Configuration settings for the Freescale i.MX6Q SabreAuto board.
++ * Configuration settings for the Freescale i.MX6Q SabreSD board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+@@ -15,7 +15,6 @@
+ #define CONFIG_MACH_TYPE 3529
+ #define CONFIG_MXC_UART_BASE UART4_BASE
+ #define CONFIG_CONSOLE_DEV "ttymxc3"
+-#define CONFIG_MMCROOT "/dev/mmcblk0p2"
+ #define PHYS_SDRAM_SIZE (2u * 1024 * 1024 * 1024)
+
+ #include "mx6qsabre_common.h"
+diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
+index b6c5773..b69ba5b 100644
+--- a/include/configs/mx6qsabrelite.h
++++ b/include/configs/mx6qsabrelite.h
+@@ -23,8 +23,6 @@
+ #define __CONFIG_H
+
+ #define CONFIG_MX6Q
+-#define CONFIG_SYS_MX6_HCLK 24000000
+-#define CONFIG_SYS_MX6_CLK32 32768
+ #define CONFIG_DISPLAY_CPUINFO
+ #define CONFIG_DISPLAY_BOARDINFO
+
+@@ -39,7 +37,7 @@
+ #define CONFIG_REVISION_TAG
+
+ /* Size of malloc() pool */
+-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
++#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
+
+ #define CONFIG_BOARD_EARLY_INIT_F
+ #define CONFIG_MISC_INIT_R
+@@ -121,6 +119,20 @@
+ /* Miscellaneous commands */
+ #define CONFIG_CMD_BMODE
+
++/* Framebuffer and LCD */
++#define CONFIG_VIDEO
++#define CONFIG_VIDEO_IPUV3
++#define CONFIG_CFB_CONSOLE
++#define CONFIG_VGA_AS_SINGLE_DEVICE
++#define CONFIG_SYS_CONSOLE_IS_IN_ENV
++#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
++#define CONFIG_VIDEO_BMP_RLE8
++#define CONFIG_SPLASH_SCREEN
++#define CONFIG_BMP_16BPP
++#define CONFIG_VIDEO_LOGO
++#define CONFIG_IPUV3_CLK 260000000
++#define CONFIG_CMD_HDMIDETECT
++
+ /* allow to overwrite serial and ethaddr */
+ #define CONFIG_ENV_OVERWRITE
+ #define CONFIG_CONS_INDEX 1
+@@ -145,8 +157,8 @@
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0" \
+ "mmcdev=0\0" \
+- "mmcpart=1\0" \
+- "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
++ "mmcpart=2\0" \
++ "mmcroot=/dev/mmcblk0p3 rootwait rw\0" \
+ "mmcargs=setenv bootargs console=${console},${baudrate} " \
+ "root=${mmcroot}\0" \
+ "loadbootscript=" \
+diff --git a/include/configs/mx6qsabresd.h b/include/configs/mx6qsabresd.h
+index 771d129..f2ce79e 100644
+--- a/include/configs/mx6qsabresd.h
++++ b/include/configs/mx6qsabresd.h
+@@ -20,7 +20,6 @@
+ #define CONFIG_MACH_TYPE 3980
+ #define CONFIG_MXC_UART_BASE UART1_BASE
+ #define CONFIG_CONSOLE_DEV "ttymxc0"
+-#define CONFIG_MMCROOT "/dev/mmcblk1p2"
+ #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
+
+ #include "mx6qsabre_common.h"
+diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h
+new file mode 100644
+index 0000000..401a773
+--- /dev/null
++++ b/include/configs/nitrogen6x.h
+@@ -0,0 +1,248 @@
++/*
++ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
++ *
++ * Configuration settings for the Boundary Devices Nitrogen6X
++ * and Freescale i.MX6Q Sabre Lite boards.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#ifndef __CONFIG_H
++#define __CONFIG_H
++
++#define CONFIG_MX6Q
++#define CONFIG_DISPLAY_CPUINFO
++#define CONFIG_DISPLAY_BOARDINFO
++
++#define CONFIG_MACH_TYPE 3769
++
++#include <asm/arch/imx-regs.h>
++#include <asm/imx-common/gpio.h>
++
++#define CONFIG_CMDLINE_TAG
++#define CONFIG_SETUP_MEMORY_TAGS
++#define CONFIG_INITRD_TAG
++#define CONFIG_REVISION_TAG
++
++/* Size of malloc() pool */
++#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
++
++#define CONFIG_BOARD_EARLY_INIT_F
++#define CONFIG_MISC_INIT_R
++#define CONFIG_MXC_GPIO
++
++#define CONFIG_MXC_UART
++#define CONFIG_MXC_UART_BASE UART2_BASE
++
++#define CONFIG_CMD_SF
++#ifdef CONFIG_CMD_SF
++#define CONFIG_SPI_FLASH
++#define CONFIG_SPI_FLASH_SST
++#define CONFIG_MXC_SPI
++#define CONFIG_SF_DEFAULT_BUS 0
++#define CONFIG_SF_DEFAULT_CS (0|(IMX_GPIO_NR(3, 19)<<8))
++#define CONFIG_SF_DEFAULT_SPEED 25000000
++#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
++#endif
++
++/* I2C Configs */
++#define CONFIG_CMD_I2C
++#define CONFIG_I2C_MULTI_BUS
++#define CONFIG_I2C_MXC
++#define CONFIG_SYS_I2C_SPEED 100000
++
++/* MMC Configs */
++#define CONFIG_FSL_ESDHC
++#define CONFIG_FSL_USDHC
++#define CONFIG_SYS_FSL_ESDHC_ADDR 0
++#define CONFIG_SYS_FSL_USDHC_NUM 2
++
++#define CONFIG_MMC
++#define CONFIG_CMD_MMC
++#define CONFIG_GENERIC_MMC
++#define CONFIG_CMD_EXT2
++#define CONFIG_CMD_FAT
++#define CONFIG_DOS_PARTITION
++
++#define CONFIG_CMD_SATA
++/*
++ * SATA Configs
++ */
++#ifdef CONFIG_CMD_SATA
++#define CONFIG_DWC_AHSATA
++#define CONFIG_SYS_SATA_MAX_DEVICE 1
++#define CONFIG_DWC_AHSATA_PORT_ID 0
++#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
++#define CONFIG_LBA48
++#define CONFIG_LIBATA
++#endif
++
++#define CONFIG_CMD_PING
++#define CONFIG_CMD_DHCP
++#define CONFIG_CMD_MII
++#define CONFIG_CMD_NET
++#define CONFIG_FEC_MXC
++#define CONFIG_MII
++#define IMX_FEC_BASE ENET_BASE_ADDR
++#define CONFIG_FEC_XCV_TYPE RGMII
++#define CONFIG_ETHPRIME "FEC"
++#define CONFIG_FEC_MXC_PHYADDR 6
++#define CONFIG_PHYLIB
++#define CONFIG_PHY_MICREL
++#define CONFIG_PHY_MICREL_KSZ9021
++
++/* USB Configs */
++#define CONFIG_CMD_USB
++#define CONFIG_CMD_FAT
++#define CONFIG_USB_EHCI
++#define CONFIG_USB_EHCI_MX6
++#define CONFIG_USB_STORAGE
++#define CONFIG_USB_HOST_ETHER
++#define CONFIG_USB_ETHER_ASIX
++#define CONFIG_USB_ETHER_SMSC95XX
++#define CONFIG_MXC_USB_PORT 1
++#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
++#define CONFIG_MXC_USB_FLAGS 0
++
++/* Miscellaneous commands */
++#define CONFIG_CMD_BMODE
++#define CONFIG_CMD_SETEXPR
++
++/* Framebuffer and LCD */
++#define CONFIG_VIDEO
++#define CONFIG_VIDEO_IPUV3
++#define CONFIG_CFB_CONSOLE
++#define CONFIG_VGA_AS_SINGLE_DEVICE
++#define CONFIG_SYS_CONSOLE_IS_IN_ENV
++#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
++#define CONFIG_VIDEO_BMP_RLE8
++#define CONFIG_SPLASH_SCREEN
++#define CONFIG_BMP_16BPP
++#define CONFIG_VIDEO_LOGO
++#define CONFIG_IPUV3_CLK 260000000
++#define CONFIG_CMD_HDMIDETECT
++#define CONFIG_CONSOLE_MUX
++
++/* allow to overwrite serial and ethaddr */
++#define CONFIG_ENV_OVERWRITE
++#define CONFIG_CONS_INDEX 1
++#define CONFIG_BAUDRATE 115200
++
++/* Command definition */
++#include <config_cmd_default.h>
++
++#undef CONFIG_CMD_IMLS
++
++#define CONFIG_BOOTDELAY 3
++
++#define CONFIG_PREBOOT ""
++
++#define CONFIG_LOADADDR 0x10800000
++#define CONFIG_SYS_TEXT_BASE 0x17800000
++
++#define CONFIG_EXTRA_ENV_SETTINGS \
++ "console=ttymxc1\0" \
++ "clearenv=if sf probe || sf probe || sf probe 1 ; then sf erase 0xc0000 0x2000 && " \
++ "echo restored environment to factory default ; fi\0" \
++ "bootcmd=for dtype in sata mmc ; do " \
++ "for disk in 0 1 ; do ${dtype} dev ${disk} ;" \
++ "for fs in fat ext2 ; do " \
++ "${fs}load ${dtype} ${disk}:1 10008000 " \
++ "/6q_bootscript" \
++ "&& source 10008000 ; " \
++ "done ; " \
++ "done ; " \
++ "done; " \
++ "setenv stdout serial,vga ; " \
++ "echo ; echo 6q_bootscript not found ; " \
++ "echo ; echo serial console at 115200, 8N1 ; " \
++ "echo ; echo details at http://boundarydevices.com/6q_bootscript ; setenv stdout serial\0" \
++ "upgradeu=for dtype in sata mmc ; do " \
++ "for disk in 0 1 ; do ${dtype} dev ${disk} ;" \
++ "for fs in fat ext2 ; do " \
++ "${fs}load ${dtype} ${disk}:1 10008000 " \
++ "/6q_upgrade " \
++ "&& source 10008000 ; " \
++ "done ; " \
++ "done ; " \
++ "done\0" \
++
++#define CONFIG_ARP_TIMEOUT 200UL
++
++/* Miscellaneous configurable options */
++#define CONFIG_SYS_LONGHELP
++#define CONFIG_SYS_HUSH_PARSER
++#define CONFIG_SYS_PROMPT "U-Boot > "
++#define CONFIG_AUTO_COMPLETE
++#define CONFIG_SYS_CBSIZE 256
++
++/* Print Buffer Size */
++#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
++#define CONFIG_SYS_MAXARGS 16
++#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
++
++#define CONFIG_SYS_MEMTEST_START 0x10000000
++#define CONFIG_SYS_MEMTEST_END 0x10010000
++
++#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
++#define CONFIG_SYS_HZ 1000
++
++#define CONFIG_CMDLINE_EDITING
++
++/* Physical Memory Map */
++#define CONFIG_NR_DRAM_BANKS 1
++#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
++#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
++
++#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
++#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
++#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
++
++#define CONFIG_SYS_INIT_SP_OFFSET \
++ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
++#define CONFIG_SYS_INIT_SP_ADDR \
++ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
++
++/* FLASH and environment organization */
++#define CONFIG_SYS_NO_FLASH
++
++#define CONFIG_ENV_SIZE (8 * 1024)
++
++/* #define CONFIG_ENV_IS_IN_MMC */
++#define CONFIG_ENV_IS_IN_SPI_FLASH
++
++#if defined(CONFIG_ENV_IS_IN_MMC)
++#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
++#define CONFIG_SYS_MMC_ENV_DEV 0
++#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
++#define CONFIG_ENV_OFFSET (768 * 1024)
++#define CONFIG_ENV_SECT_SIZE (8 * 1024)
++#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
++#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
++#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
++#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
++#endif
++
++#define CONFIG_OF_LIBFDT
++#define CONFIG_CMD_BOOTZ
++
++#define CONFIG_SYS_DCACHE_OFF
++
++#ifndef CONFIG_SYS_DCACHE_OFF
++#define CONFIG_CMD_CACHE
++#endif
++
++#endif /* __CONFIG_H */
+diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h
+index eacb5f5..b4756be 100644
+--- a/include/configs/omap4_panda.h
++++ b/include/configs/omap4_panda.h
+@@ -31,6 +31,7 @@
+ /*
+ * High Level Configuration Options
+ */
++#define CONFIG_PANDA /* working with Panda */
+
+ /* USB UHH support options */
+ #define CONFIG_CMD_USB
+diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h
+deleted file mode 100644
+index d9eb5d9..0000000
+--- a/include/configs/socfpga_cyclone5.h
++++ /dev/null
+@@ -1,236 +0,0 @@
+-/*
+- * Copyright (C) 2012 Altera Corporation <www.altera.com>
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+- */
+-#ifndef __CONFIG_H
+-#define __CONFIG_H
+-
+-#include <asm/arch/socfpga_base_addrs.h>
+-
+-/*
+- * High level configuration
+- */
+-
+-#define CONFIG_ARMV7
+-#define CONFIG_L2_OFF
+-#define CONFIG_SYS_DCACHE_OFF
+-#undef CONFIG_USE_IRQ
+-
+-#define CONFIG_MISC_INIT_R
+-#define CONFIG_SINGLE_BOOTLOADER
+-#define CONFIG_SOCFPGA
+-
+-#define CONFIG_SYS_TEXT_BASE 0x08000040
+-#define V_NS16550_CLK 1000000
+-#define CONFIG_BAUDRATE 57600
+-#define CONFIG_SYS_HZ 1000
+-#define CONFIG_TIMER_CLOCK_KHZ 2400
+-#define CONFIG_SYS_LOAD_ADDR 0x7fc0
+-
+-/* Console I/O Buffer Size */
+-#define CONFIG_SYS_CBSIZE 256
+-/* Monitor Command Prompt */
+-#define CONFIG_SYS_PROMPT "SOCFPGA_CYCLONE5 # "
+-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+- sizeof(CONFIG_SYS_PROMPT) + 16)
+-
+-/*
+- * Display CPU and Board Info
+- */
+-#define CONFIG_DISPLAY_CPUINFO
+-#define CONFIG_DISPLAY_BOARDINFO
+-
+-/*
+- * Enable early stage initialization at C environment
+- */
+-#define CONFIG_BOARD_EARLY_INIT_F
+-
+-/* flat device tree */
+-#define CONFIG_OF_LIBFDT
+-/* skip updating the FDT blob */
+-#define CONFIG_FDT_BLOB_SKIP_UPDATE
+-/* Initial Memory map size for Linux, minus 4k alignment for DFT blob */
+-#define CONFIG_SYS_BOOTMAPSZ ((256*1024*1024) - (4*1024))
+-
+-#define CONFIG_SPL_RAM_DEVICE
+-#define CONFIG_SPL_STACK (&__stack_start)
+-#define CONFIG_SYS_SPL_MALLOC_START ((unsigned long) (&__malloc_start))
+-#define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start)
+-
+-/*
+- * Memory allocation (MALLOC)
+- */
+-/* Room required on the stack for the environment data */
+-#define CONFIG_ENV_SIZE 1024
+-/* Size of DRAM reserved for malloc() use */
+-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
+-
+-/* SP location before relocation, must use scratch RAM */
+-#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
+-/* Reserving 0x100 space at back of scratch RAM for debug info */
+-#define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100)
+-/* Stack pointer prior relocation, must situated at on-chip RAM */
+-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+- CONFIG_SYS_INIT_RAM_SIZE - \
+- GENERATED_GBL_DATA_SIZE)
+-
+-
+-/*
+- * Command line configuration.
+- */
+-#define CONFIG_SYS_NO_FLASH
+-#include <config_cmd_default.h>
+-/* FAT file system support */
+-#define CONFIG_CMD_FAT
+-
+-
+-/*
+- * Misc
+- */
+-#define CONFIG_DOS_PARTITION 1
+-
+-#ifdef CONFIG_SPL_BUILD
+-#undef CONFIG_PARTITIONS
+-#endif
+-
+-/*
+- * Environment setup
+- */
+-
+-/* Delay before automatically booting the default image */
+-#define CONFIG_BOOTDELAY 3
+-/* Enable auto completion of commands using TAB */
+-#define CONFIG_AUTO_COMPLETE
+-/* use "hush" command parser */
+-#define CONFIG_SYS_HUSH_PARSER
+-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+-#define CONFIG_CMD_RUN
+-
+-#define CONFIG_BOOTCOMMAND "run ramboot"
+-
+-/*
+- * arguments passed to the bootm command. The value of
+- * CONFIG_BOOTARGS goes into the environment value "bootargs".
+- * Do note the value will overide also the chosen node in FDT blob.
+- */
+-#define CONFIG_BOOTARGS "console=ttyS0,57600,mem=256M at 0x0"
+-
+-#define CONFIG_EXTRA_ENV_SETTINGS \
+- "verify=n\0" \
+- "loadaddr= " MK_STR(CONFIG_SYS_LOAD_ADDR) "\0" \
+- "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
+- "bootm ${loadaddr} - ${fdt_addr}\0" \
+- "bootimage=uImage\0" \
+- "fdt_addr=100\0" \
+- "fsloadcmd=ext2load\0" \
+- "bootm ${loadaddr} - ${fdt_addr}\0" \
+- "qspiroot=/dev/mtdblock0\0" \
+- "qspirootfstype=jffs2\0" \
+- "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
+- " root=${qspiroot} rw rootfstype=${qspirootfstype};"\
+- "bootm ${loadaddr} - ${fdt_addr}\0"
+-
+-/* using environment setting for stdin, stdout, stderr */
+-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+-/* Enable the call to overwrite_console() */
+-#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+-/* Enable overwrite of previous console environment settings */
+-#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+-
+-/* max number of command args */
+-#define CONFIG_SYS_MAXARGS 16
+-
+-
+-/*
+- * Hardware drivers
+- */
+-
+-/*
+- * SDRAM Memory Map
+- */
+-/* We have 1 bank of DRAM */
+-#define CONFIG_NR_DRAM_BANKS 1
+-/* SDRAM Bank #1 */
+-#define CONFIG_SYS_SDRAM_BASE 0x00000000
+-/* SDRAM memory size */
+-#define PHYS_SDRAM_1_SIZE 0x80000000
+-
+-#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
+-#define CONFIG_SYS_MEMTEST_START 0x00000000
+-#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE
+-
+-/*
+- * NS16550 Configuration
+- */
+-#define UART0_BASE SOCFPGA_UART0_ADDRESS
+-#define CONFIG_SYS_NS16550
+-#define CONFIG_SYS_NS16550_SERIAL
+-#define CONFIG_SYS_NS16550_REG_SIZE -4
+-#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+-#define CONFIG_CONS_INDEX 1
+-#define CONFIG_SYS_NS16550_COM1 UART0_BASE
+-
+-#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
+-
+-/*
+- * FLASH
+- */
+-#define CONFIG_SYS_NO_FLASH
+-
+-/*
+- * L4 OSC1 Timer 0
+- */
+-/* This timer use eosc1 where the clock frequency is fixed
+- * throughout any condition */
+-#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
+-
+-/* reload value when timer count to zero */
+-#define TIMER_LOAD_VAL 0xFFFFFFFF
+-
+-#define CONFIG_ENV_IS_NOWHERE
+-
+-/*
+- * SPL "Second Program Loader" aka Initial Software
+- */
+-
+-/* Enable building of SPL globally */
+-#define CONFIG_SPL
+-#define CONFIG_SPL_FRAMEWORK
+-
+-/* TEXT_BASE for linking the SPL binary */
+-#define CONFIG_SPL_TEXT_BASE 0xFFFF0000
+-
+-/* Stack size for SPL */
+-#define CONFIG_SPL_STACK_SIZE (4 * 1024)
+-
+-/* MALLOC size for SPL */
+-#define CONFIG_SPL_MALLOC_SIZE (5 * 1024)
+-
+-#define CONFIG_SPL_SERIAL_SUPPORT
+-#define CONFIG_SPL_BOARD_INIT
+-
+-#define CHUNKSZ_CRC32 (1 * 1024)
+-
+-#define CONFIG_CRC32_VERIFY
+-
+-/* Linker script for SPL */
+-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds"
+-
+-/* Support for common/libcommon.o in SPL binary */
+-#define CONFIG_SPL_LIBCOMMON_SUPPORT
+-/* Support for lib/libgeneric.o in SPL binary */
+-#define CONFIG_SPL_LIBGENERIC_SUPPORT
+-
+-#endif /* __CONFIG_H */
+diff --git a/include/configs/vision2.h b/include/configs/vision2.h
+index fba897c..848df88 100644
+--- a/include/configs/vision2.h
++++ b/include/configs/vision2.h
+@@ -30,8 +30,6 @@
+
+ #include <asm/arch/imx-regs.h>
+
+-#define CONFIG_SYS_MX5_HCLK 24000000
+-#define CONFIG_SYS_MX5_CLK32 32768
+ #define CONFIG_DISPLAY_CPUINFO
+ #define CONFIG_DISPLAY_BOARDINFO
+
+diff --git a/include/configs/x600.h b/include/configs/x600.h
+deleted file mode 100644
+index 3082aaa..0000000
+--- a/include/configs/x600.h
++++ /dev/null
+@@ -1,339 +0,0 @@
+-/*
+- * (C) Copyright 2009
+- * Vipin Kumar, STMicroelectronics, <vipin.kumar at st.com>
+- *
+- * Copyright (C) 2012 Stefan Roese <sr at denx.de>
+- *
+- * See file CREDITS for list of people who contributed to this
+- * project.
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of
+- * the License, or (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+- * MA 02111-1307 USA
+- */
+-
+-#ifndef __CONFIG_H
+-#define __CONFIG_H
+-
+-/*
+- * High Level Configuration Options
+- * (easy to change)
+- */
+-#define CONFIG_SPEAR600 /* SPEAr600 SoC */
+-#define CONFIG_X600 /* on X600 board */
+-
+-#include <asm/arch/hardware.h>
+-
+-/* Timer, HZ specific defines */
+-#define CONFIG_SYS_HZ 1000
+-#define CONFIG_SYS_HZ_CLOCK 8300000
+-
+-#define CONFIG_SYS_TEXT_BASE 0x00800040
+-#define CONFIG_SYS_FLASH_BASE 0xf8000000
+-/* Reserve 8KiB for SPL */
+-#define CONFIG_SPL_PAD_TO 8192 /* decimal for 'dd' */
+-#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO
+-#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \
+- CONFIG_SYS_SPL_LEN)
+-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+-#define CONFIG_SYS_MONITOR_LEN 0x60000
+-
+-#define CONFIG_ENV_IS_IN_FLASH
+-
+-/* Serial Configuration (PL011) */
+-#define CONFIG_SYS_SERIAL0 0xD0000000
+-#define CONFIG_SYS_SERIAL1 0xD0080000
+-#define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, \
+- (void *)CONFIG_SYS_SERIAL1 }
+-#define CONFIG_PL011_SERIAL
+-#define CONFIG_PL011_CLOCK (48 * 1000 * 1000)
+-#define CONFIG_CONS_INDEX 0
+-#define CONFIG_BAUDRATE 115200
+-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \
+- 57600, 115200 }
+-#define CONFIG_SYS_LOADS_BAUD_CHANGE
+-
+-/* NOR FLASH config options */
+-#define CONFIG_ST_SMI
+-#define CONFIG_SYS_MAX_FLASH_BANKS 1
+-#define CONFIG_SYS_FLASH_BANK_SIZE 0x01000000
+-#define CONFIG_SYS_FLASH_ADDR_BASE { CONFIG_SYS_FLASH_BASE }
+-#define CONFIG_SYS_MAX_FLASH_SECT 128
+-#define CONFIG_SYS_FLASH_EMPTY_INFO
+-#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ)
+-#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * CONFIG_SYS_HZ)
+-
+-/* NAND FLASH config options */
+-#define CONFIG_NAND_FSMC
+-#define CONFIG_SYS_NAND_SELF_INIT
+-#define CONFIG_SYS_MAX_NAND_DEVICE 1
+-#define CONFIG_SYS_NAND_BASE CONFIG_FSMC_NAND_BASE
+-#define CONFIG_MTD_ECC_SOFT
+-#define CONFIG_SYS_FSMC_NAND_8BIT
+-#define CONFIG_SYS_NAND_ONFI_DETECTION
+-
+-/* UBI/UBI config options */
+-#define CONFIG_MTD_DEVICE
+-#define CONFIG_MTD_PARTITIONS
+-#define CONFIG_RBTREE
+-
+-/* Ethernet config options */
+-#define CONFIG_MII
+-#define CONFIG_DESIGNWARE_ETH
+-#define CONFIG_DW_SEARCH_PHY
+-#define CONFIG_NET_MULTI
+-#define CONFIG_PHY_RESET_DELAY 10000 /* in usec */
+-#define CONFIG_DW_AUTONEG
+-#define CONFIG_PHY_ADDR 0 /* PHY address */
+-#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
+-
+-#define CONFIG_SPEAR_GPIO
+-
+-/* I2C config options */
+-#define CONFIG_HARD_I2C
+-#define CONFIG_DW_I2C
+-#define CONFIG_SYS_I2C_SPEED 400000
+-#define CONFIG_SYS_I2C_SLAVE 0x02
+-#define CONFIG_I2C_CHIPADDRESS 0x50
+-
+-#define CONFIG_RTC_M41T62 1
+-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+-
+-/* FPGA config options */
+-#define CONFIG_FPGA
+-#define CONFIG_FPGA_XILINX
+-#define CONFIG_FPGA_SPARTAN3
+-#define CONFIG_FPGA_COUNT 1
+-
+-/*
+- * Command support defines
+- */
+-#define CONFIG_CMD_CACHE
+-#define CONFIG_CMD_DATE
+-#define CONFIG_CMD_DHCP
+-#define CONFIG_CMD_ENV
+-#define CONFIG_CMD_FPGA
+-#define CONFIG_CMD_GPIO
+-#define CONFIG_CMD_I2C
+-#define CONFIG_CMD_MEMORY
+-#define CONFIG_CMD_MII
+-#define CONFIG_CMD_MTDPARTS
+-#define CONFIG_CMD_NAND
+-#define CONFIG_CMD_NET
+-#define CONFIG_CMD_PING
+-#define CONFIG_CMD_RUN
+-#define CONFIG_CMD_SAVES
+-#define CONFIG_CMD_UBI
+-#define CONFIG_CMD_UBIFS
+-#define CONFIG_LZO
+-
+-/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+-#include <config_cmd_default.h>
+-
+-#define CONFIG_BOOTDELAY 3
+-
+-#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
+-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+-
+-/*
+- * U-Boot Environment placing definitions.
+- */
+-#define CONFIG_ENV_SECT_SIZE 0x00010000
+-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
+- CONFIG_SYS_MONITOR_LEN)
+-#define CONFIG_ENV_SIZE 0x02000
+-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \
+- CONFIG_ENV_SECT_SIZE)
+-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
+-
+-/* Miscellaneous configurable options */
+-#define CONFIG_ARCH_CPU_INIT
+-#define CONFIG_DISPLAY_CPUINFO
+-#define CONFIG_BOOT_PARAMS_ADDR 0x00000100
+-#define CONFIG_CMDLINE_TAG
+-#define CONFIG_OF_LIBFDT /* enable passing of devicetree */
+-#define CONFIG_SETUP_MEMORY_TAGS
+-#define CONFIG_MISC_INIT_R
+-#define CONFIG_BOARD_LATE_INIT
+-#define CONFIG_LOOPW /* enable loopw command */
+-#define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */
+-#define CONFIG_ZERO_BOOTDELAY_CHECK
+-#define CONFIG_AUTOBOOT_KEYED
+-#define CONFIG_AUTOBOOT_STOP_STR " "
+-#define CONFIG_AUTOBOOT_PROMPT \
+- "Hit SPACE in %d seconds to stop autoboot.\n", bootdelay
+-
+-#define CONFIG_SYS_MEMTEST_START 0x00800000
+-#define CONFIG_SYS_MEMTEST_END 0x04000000
+-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
+-#define CONFIG_IDENT_STRING "-SPEAr"
+-#define CONFIG_SYS_LONGHELP
+-#define CONFIG_SYS_PROMPT "X600> "
+-#define CONFIG_CMDLINE_EDITING
+-#define CONFIG_SYS_CBSIZE 256
+-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+- sizeof(CONFIG_SYS_PROMPT) + 16)
+-#define CONFIG_SYS_MAXARGS 16
+-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+-#define CONFIG_SYS_LOAD_ADDR 0x00800000
+-#define CONFIG_SYS_CONSOLE_INFO_QUIET
+-#define CONFIG_SYS_64BIT_VSPRINTF
+-
+-/* Use last 2 lwords in internal SRAM for bootcounter */
+-#define CONFIG_BOOTCOUNT_LIMIT
+-#define CONFIG_SYS_BOOTCOUNT_ADDR 0xd2801ff8
+-
+-#define CONFIG_HOSTNAME x600
+-#define CONFIG_UBI_PART ubi0
+-#define CONFIG_UBIFS_VOLUME rootfs
+-
+-#define xstr(s) str(s)
+-#define str(s) #s
+-
+-#define MTDIDS_DEFAULT "nand0=nand"
+-#define MTDPARTS_DEFAULT "mtdparts=nand:64M(ubi0),64M(ubi1)"
+-
+-#define CONFIG_EXTRA_ENV_SETTINGS \
+- "u-boot_addr=1000000\0" \
+- "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.spr\0" \
+- "load=tftp ${u-boot_addr} ${u-boot}\0" \
+- "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) " +${filesize};"\
+- "erase " xstr(CONFIG_SYS_MONITOR_BASE) " +${filesize};" \
+- "cp.b ${u-boot_addr} " xstr(CONFIG_SYS_MONITOR_BASE) \
+- " ${filesize};" \
+- "protect on " xstr(CONFIG_SYS_MONITOR_BASE) \
+- " +${filesize}\0" \
+- "upd=run load update\0" \
+- "ubifs=" xstr(CONFIG_HOSTNAME) "/ubifs.img\0" \
+- "part=" xstr(CONFIG_UBI_PART) "\0" \
+- "vol=" xstr(CONFIG_UBIFS_VOLUME) "\0" \
+- "load_ubifs=tftp ${kernel_addr} ${ubifs}\0" \
+- "update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}" \
+- " ${filesize}\0" \
+- "upd_ubifs=run load_ubifs update_ubifs\0" \
+- "init_ubifs=nand erase.part ubi0;ubi part ${part};" \
+- "ubi create ${vol} 4000000\0" \
+- "netdev=eth0\0" \
+- "rootpath=/opt/eldk-4.2/arm\0" \
+- "nfsargs=setenv bootargs root=/dev/nfs rw " \
+- "nfsroot=${serverip}:${rootpath}\0" \
+- "ramargs=setenv bootargs root=/dev/ram rw\0" \
+- "boot_part=0\0" \
+- "altbootcmd=if test $boot_part -eq 0;then " \
+- "echo Switching to partition 1!;" \
+- "setenv boot_part 1;" \
+- "else; " \
+- "echo Switching to partition 0!;" \
+- "setenv boot_part 0;" \
+- "fi;" \
+- "saveenv;boot\0" \
+- "ubifsargs=set bootargs ubi.mtd=ubi${boot_part} " \
+- "root=ubi0:rootfs rootfstype=ubifs\0" \
+- "kernel=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
+- "kernel_fs=/boot/uImage \0" \
+- "kernel_addr=1000000\0" \
+- "dtb=" xstr(CONFIG_HOSTNAME) "/" xstr(CONFIG_HOSTNAME) ".dtb\0" \
+- "dtb_fs=/boot/" xstr(CONFIG_HOSTNAME) ".dtb\0" \
+- "dtb_addr=1800000\0" \
+- "load_kernel=tftp ${kernel_addr} ${kernel}\0" \
+- "load_dtb=tftp ${dtb_addr} ${dtb}\0" \
+- "addip=setenv bootargs ${bootargs} " \
+- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+- ":${hostname}:${netdev}:off panic=1\0" \
+- "addcon=setenv bootargs ${bootargs} console=ttyAMA0," \
+- "${baudrate}\0" \
+- "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+- "net_nfs=run load_dtb load_kernel; " \
+- "run nfsargs addip addcon addmtd addmisc;" \
+- "bootm ${kernel_addr} - ${dtb_addr}\0" \
+- "mtdids=" MTDIDS_DEFAULT "\0" \
+- "mtdparts=" MTDPARTS_DEFAULT "\0" \
+- "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip" \
+- " addcon addmisc addmtd;" \
+- "bootm ${kernel_addr} - ${dtb_addr}\0" \
+- "ubifs_mount=ubi part ubi${boot_part};ubifsmount rootfs\0" \
+- "ubifs_load=ubifsload ${kernel_addr} ${kernel_fs};" \
+- "ubifsload ${dtb_addr} ${dtb_fs};\0" \
+- "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip addcon " \
+- "addmtd addmisc;bootm ${kernel_addr} - ${dtb_addr}\0" \
+- "bootcmd=run nand_ubifs\0" \
+- "\0"
+-
+-/* Stack sizes */
+-#define CONFIG_STACKSIZE (512 * 1024)
+-
+-/* Physical Memory Map */
+-#define CONFIG_NR_DRAM_BANKS 1
+-#define PHYS_SDRAM_1 0x00000000
+-#define PHYS_SDRAM_1_MAXSIZE 0x40000000
+-
+-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+-#define CONFIG_SYS_INIT_RAM_ADDR 0xD2800000
+-#define CONFIG_SYS_INIT_RAM_SIZE 0x2000
+-
+-#define CONFIG_SYS_INIT_SP_OFFSET \
+- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+-
+-#define CONFIG_SYS_INIT_SP_ADDR \
+- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+-
+-/*
+- * SPL related defines
+- */
+-#define CONFIG_SPL
+-#define CONFIG_SPL_TEXT_BASE 0xd2800b00
+-#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/spear"
+-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds"
+-
+-#define CONFIG_SPL_SERIAL_SUPPORT
+-#define CONFIG_SPL_LIBCOMMON_SUPPORT /* image.c */
+-#define CONFIG_SPL_LIBGENERIC_SUPPORT /* string.c */
+-#define CONFIG_SPL_NO_PRINTF
+-
+-/*
+- * Please select/define only one of the following
+- * Each definition corresponds to a supported DDR chip.
+- * DDR configuration is based on the following selection
+- */
+-#define CONFIG_DDR_MT47H64M16 1
+-#define CONFIG_DDR_MT47H32M16 0
+-#define CONFIG_DDR_MT47H128M8 0
+-
+-/*
+- * Synchronous/Asynchronous operation of DDR
+- *
+- * Select CONFIG_DDR_2HCLK for DDR clk = 333MHz, synchronous operation
+- * Select CONFIG_DDR_HCLK for DDR clk = 166MHz, synchronous operation
+- * Select CONFIG_DDR_PLL2 for DDR clk = PLL2, asynchronous operation
+- */
+-#define CONFIG_DDR_2HCLK 1
+-#define CONFIG_DDR_HCLK 0
+-#define CONFIG_DDR_PLL2 0
+-
+-/*
+- * xxx_BOOT_SUPPORTED macro defines whether a booting type is supported
+- * or not. Modify/Add to only these macros to define new boot types
+- */
+-#define USB_BOOT_SUPPORTED 0
+-#define PCIE_BOOT_SUPPORTED 0
+-#define SNOR_BOOT_SUPPORTED 1
+-#define NAND_BOOT_SUPPORTED 1
+-#define PNOR_BOOT_SUPPORTED 0
+-#define TFTP_BOOT_SUPPORTED 0
+-#define UART_BOOT_SUPPORTED 0
+-#define SPI_BOOT_SUPPORTED 0
+-#define I2C_BOOT_SUPPORTED 0
+-#define MMC_BOOT_SUPPORTED 0
+-
+-#endif /* __CONFIG_H */
+diff --git a/include/configs/xilinx-ppc.h b/include/configs/xilinx-ppc.h
+index 2bdaa05..1235c37 100644
+--- a/include/configs/xilinx-ppc.h
++++ b/include/configs/xilinx-ppc.h
+@@ -118,7 +118,7 @@
+ /* serial communication */
+ #ifdef XPAR_UARTLITE_0_BASEADDR
+ #define CONFIG_XILINX_UARTLITE
+-#define XILINX_UARTLITE_BASEADDR XPAR_UARTLITE_0_BASEADDR
++#define CONFIG_SERIAL_BASE XPAR_UARTLITE_0_BASEADDR
+ #define CONFIG_BAUDRATE XPAR_UARTLITE_0_BAUDRATE
+ #define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE }
+ #else
+diff --git a/include/configs/zynq.h b/include/configs/zynq.h
+deleted file mode 100644
+index 34ac3ef..0000000
+--- a/include/configs/zynq.h
++++ /dev/null
+@@ -1,112 +0,0 @@
+-/*
+- * (C) Copyright 2012 Michal Simek <monstr at monstr.eu>
+- *
+- * See file CREDITS for list of people who contributed to this
+- * project.
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of
+- * the License, or (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+- * MA 02111-1307 USA
+- */
+-
+-#ifndef __CONFIG_ZYNQ_H
+-#define __CONFIG_ZYNQ_H
+-
+-#define CONFIG_ARMV7 /* This is an ARM V7 CPU core */
+-#define CONFIG_ZYNQ
+-
+-/* CPU clock */
+-#define CONFIG_CPU_FREQ_HZ 800000000
+-#define CONFIG_SYS_HZ 1000
+-
+-/* Ram */
+-#define CONFIG_NR_DRAM_BANKS 1
+-#define CONFIG_SYS_TEXT_BASE 0
+-#define CONFIG_SYS_SDRAM_BASE 0
+-#define CONFIG_SYS_SDRAM_SIZE 0x40000000
+-#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
+-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x1000)
+-
+-/* The following table includes the supported baudrates */
+-#define CONFIG_SYS_BAUDRATE_TABLE \
+- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
+-
+-#define CONFIG_BAUDRATE 115200
+-
+-/* XPSS Serial driver */
+-#define CONFIG_SERIAL_MULTI
+-#define CONFIG_ZYNQ_SERIAL
+-#define CONFIG_ZYNQ_SERIAL_BASEADDR0 0xE0001000
+-#define CONFIG_ZYNQ_SERIAL_BAUDRATE0 CONFIG_BAUDRATE
+-#define CONFIG_ZYNQ_SERIAL_CLOCK0 50000000
+-
+-/* SCU timer address is hardcoded */
+-#define CONFIG_SCUTIMER_BASEADDR 0xF8F00600
+-
+-/* Ethernet driver */
+-#define CONFIG_NET_MULTI
+-#define CONFIG_ZYNQ_GEM
+-#define CONFIG_ZYNQ_GEM_BASEADDR0 0xE000B000
+-
+-#define CONFIG_BOOTP_SERVERIP
+-#define CONFIG_BOOTP_BOOTPATH
+-#define CONFIG_BOOTP_GATEWAY
+-#define CONFIG_BOOTP_HOSTNAME
+-#define CONFIG_BOOTP_MAY_FAIL
+-
+-/* MII and Phylib */
+-#define CONFIG_MII
+-#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+-#define CONFIG_PHYLIB
+-#define CONFIG_PHY_MARVELL
+-
+-/* Environment */
+-#define CONFIG_ENV_IS_NOWHERE
+-#define CONFIG_ENV_SIZE 0x10000
+-
+-#define CONFIG_SYS_NO_FLASH
+-
+-#define CONFIG_SYS_MALLOC_LEN 0x400000
+-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE
+-#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN
+-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+- CONFIG_SYS_INIT_RAM_SIZE - \
+- GENERATED_GBL_DATA_SIZE)
+-
+-#define CONFIG_SYS_PROMPT "U-Boot> "
+-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+- sizeof(CONFIG_SYS_PROMPT) + 16)
+-
+-#define CONFIG_SYS_LOAD_ADDR 0
+-#define CONFIG_SYS_MAXARGS 15 /* max number of command args */
+-#define CONFIG_SYS_LONGHELP
+-#define CONFIG_AUTO_COMPLETE
+-#define CONFIG_CMDLINE_EDITING
+-
+-#define CONFIG_SYS_HUSH_PARSER
+-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+-
+-/* OF */
+-#define CONFIG_FIT
+-#define CONFIG_OF_LIBFDT
+-
+-/* Commands */
+-#include <config_cmd_default.h>
+-
+-#define CONFIG_CMD_PING
+-#define CONFIG_CMD_DHCP
+-#define CONFIG_CMD_MII
+-
+-#endif /* __CONFIG_ZYNQ_H */
+diff --git a/include/ext4fs.h b/include/ext4fs.h
+index 23298fc..b6eedde 100644
+--- a/include/ext4fs.h
++++ b/include/ext4fs.h
+@@ -94,7 +94,7 @@ struct ext_filesystem {
+ /* Superblock */
+ struct ext2_sblock *sb;
+ /* Block group descritpor table */
+- struct ext2_block_group *bgd;
++ struct ext2_block_group *gd;
+ char *gdtable;
+
+ /* Block Bitmap Related */
+diff --git a/include/ide.h b/include/ide.h
+index 385e909..8ecc9dd 100644
+--- a/include/ide.h
++++ b/include/ide.h
+@@ -24,7 +24,7 @@
+ #ifndef _IDE_H
+ #define _IDE_H
+
+-#define IDE_BUS(dev) (dev / (CONFIG_SYS_IDE_MAXDEVICE / CONFIG_SYS_IDE_MAXBUS))
++#define IDE_BUS(dev) (dev >> 1)
+
+ #define ATA_CURR_BASE(dev) (CONFIG_SYS_ATA_BASE_ADDR+ide_bus_offset[IDE_BUS(dev)])
+
+diff --git a/include/ipu_pixfmt.h b/include/ipu_pixfmt.h
+index 4baa711..1163bf4 100644
+--- a/include/ipu_pixfmt.h
++++ b/include/ipu_pixfmt.h
+@@ -76,7 +76,9 @@
+ #define IPU_PIX_FMT_YVU422P fourcc('Y', 'V', '1', '6') /*< 16 YVU 4:2:2 */
+ #define IPU_PIX_FMT_YUV422P fourcc('4', '2', '2', 'P') /*< 16 YUV 4:2:2 */
+
+-int ipuv3_fb_init(struct fb_videomode *mode, uint8_t disp, uint32_t pixfmt);
++int ipuv3_fb_init(struct fb_videomode const *mode,
++ uint8_t disp,
++ uint32_t pixfmt);
+ void ipuv3_fb_shutdown(void);
+
+ #endif
+diff --git a/include/serial.h b/include/serial.h
+index 826b488..d76d6df 100644
+--- a/include/serial.h
++++ b/include/serial.h
+@@ -90,11 +90,6 @@ extern struct serial_device bfin_serial2_device;
+ extern struct serial_device bfin_serial3_device;
+ #endif
+
+-#if defined(CONFIG_ZYNQ_SERIAL)
+-extern struct serial_device uart_zynq_serial0_device;
+-extern struct serial_device uart_zynq_serial1_device;
+-#endif
+-
+ extern void serial_register(struct serial_device *);
+ extern void serial_initialize(void);
+ extern void serial_stdio_init(void);
+diff --git a/include/sh_tmu.h b/include/sh_tmu.h
+index 96c589d..a55d141 100644
+--- a/include/sh_tmu.h
++++ b/include/sh_tmu.h
+@@ -47,7 +47,7 @@ struct tmu_regs {
+ };
+ #endif /* CONFIG_SH3 */
+
+-#if defined(CONFIG_SH4) || defined(CONFIG_SH4A) || defined(CONFIG_RMOBILE)
++#if defined(CONFIG_SH4) || defined(CONFIG_SH4A)
+ struct tmu_regs {
+ u32 reserved;
+ u8 tstr;
+diff --git a/include/spl.h b/include/spl.h
+index b02f36f..af94a82 100644
+--- a/include/spl.h
++++ b/include/spl.h
+@@ -71,9 +71,6 @@ void spl_ymodem_load_image(void);
+ /* SPI SPL functions */
+ void spl_spi_load_image(void);
+
+-/* Ethernet SPL functions */
+-void spl_net_load_image(const char *device);
+-
+ #ifdef CONFIG_SPL_BOARD_INIT
+ void spl_board_init(void);
+ #endif
+diff --git a/lib/Makefile b/lib/Makefile
+index a099885..45798de 100644
+--- a/lib/Makefile
++++ b/lib/Makefile
+@@ -53,17 +53,12 @@ COBJS-$(CONFIG_SHA1) += sha1.o
+ COBJS-$(CONFIG_SHA256) += sha256.o
+ COBJS-y += strmhz.o
+ COBJS-$(CONFIG_RBTREE) += rbtree.o
++else
++COBJS-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += display_options.o
+ endif
+
+ ifdef CONFIG_SPL_BUILD
+ COBJS-$(CONFIG_SPL_YMODEM_SUPPORT) += crc16.o
+-COBJS-$(CONFIG_SPL_NET_SUPPORT) += crc32.o
+-ifneq ($(CONFIG_SPL_SPI_FLASH_SUPPORT)$(CONFIG_SPL_NET_SUPPORT),)
+-COBJS-y += display_options.o
+-endif
+-COBJS-$(CONFIG_SPL_NET_SUPPORT) += errno.o
+-COBJS-$(CONFIG_SPL_NET_SUPPORT) += hashtable.o
+-COBJS-$(CONFIG_SPL_NET_SUPPORT) += net_utils.o
+ endif
+ COBJS-y += crc32.o
+ COBJS-y += ctype.o
+diff --git a/lib/hashtable.c b/lib/hashtable.c
+index 94a7b61..670a704 100644
+--- a/lib/hashtable.c
++++ b/lib/hashtable.c
+@@ -435,7 +435,6 @@ int hdelete_r(const char *key, struct hsearch_data *htab, int do_apply)
+ * hexport()
+ */
+
+-#ifndef CONFIG_SPL_BUILD
+ /*
+ * Export the data stored in the hash table in linearized form.
+ *
+@@ -602,7 +601,6 @@ ssize_t hexport_r(struct hsearch_data *htab, const char sep,
+
+ return size;
+ }
+-#endif
+
+
+ /*
+diff --git a/mkconfig b/mkconfig
+index 7c9aa74..d3363c6 100755
+--- a/mkconfig
++++ b/mkconfig
+@@ -185,7 +185,6 @@ cat << EOF >> config.h
+ #include <configs/${CONFIG_NAME}.h>
+ #include <asm/config.h>
+ #include <config_fallbacks.h>
+-#include <config_uncmd_spl.h>
+ EOF
+
+ exit 0
+diff --git a/net/bootp.c b/net/bootp.c
+index cd5c5dd..661e371 100644
+--- a/net/bootp.c
++++ b/net/bootp.c
+@@ -341,15 +341,6 @@ BootpTimeout(void)
+ }
+ }
+
+-#define put_vci(e, str) \
+- do { \
+- size_t vci_strlen = strlen(str); \
+- *e++ = 60; /* Vendor Class Identifier */ \
+- *e++ = vci_strlen; \
+- memcpy(e, str, vci_strlen); \
+- e += vci_strlen; \
+- } while (0)
+-
+ /*
+ * Initialize BOOTP extension fields in the request.
+ */
+@@ -361,6 +352,7 @@ static int DhcpExtended(u8 *e, int message_type, IPaddr_t ServerID,
+ u8 *cnt;
+ #if defined(CONFIG_BOOTP_PXE)
+ char *uuid;
++ size_t vci_strlen;
+ u16 clientarch;
+ #endif
+
+@@ -445,10 +437,12 @@ static int DhcpExtended(u8 *e, int message_type, IPaddr_t ServerID,
+ printf("Invalid pxeuuid: %s\n", uuid);
+ }
+ }
+-#endif
+
+-#ifdef CONFIG_BOOTP_VCI_STRING
+- put_vci(e, CONFIG_BOOTP_VCI_STRING);
++ *e++ = 60; /* Vendor Class Identifier */
++ vci_strlen = strlen(CONFIG_BOOTP_VCI_STRING);
++ *e++ = vci_strlen;
++ memcpy(e, CONFIG_BOOTP_VCI_STRING, vci_strlen);
++ e += vci_strlen;
+ #endif
+
+ #if defined(CONFIG_BOOTP_VENDOREX)
+@@ -535,15 +529,6 @@ static int BootpExtended(u8 *e)
+ *e++ = (576 - 312 + OPT_FIELD_SIZE) & 0xff;
+ #endif
+
+-#if defined(CONFIG_BOOTP_VCI_STRING) || \
+- (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_NET_VCI_STRING))
+-#ifdef CONFIG_SPL_BUILD
+- put_vci(e, CONFIG_SPL_NET_VCI_STRING);
+-#else
+- put_vci(e, CONFIG_BOOTP_VCI_STRING);
+-#endif
+-#endif
+-
+ #if defined(CONFIG_BOOTP_SUBNETMASK)
+ *e++ = 1; /* Subnet mask request */
+ *e++ = 4;
+diff --git a/net/net.c b/net/net.c
+index 569fec4..809fb14 100644
+--- a/net/net.c
++++ b/net/net.c
+@@ -1161,7 +1161,7 @@ NetReceive(uchar *inpkt, int len)
+
+ #ifdef CONFIG_NETCONSOLE
+ nc_input_packet((uchar *)ip + IP_UDP_HDR_SIZE,
+- src_ip,
++ ntohl(ip->ip_src),
+ ntohs(ip->udp_dst),
+ ntohs(ip->udp_src),
+ ntohs(ip->udp_len) - UDP_HDR_SIZE);
+diff --git a/spl/Makefile b/spl/Makefile
+index e9d0ec4..d9b1c2f 100644
+--- a/spl/Makefile
++++ b/spl/Makefile
+@@ -57,9 +57,6 @@ LIBS-$(CONFIG_SPL_NAND_SUPPORT) += drivers/mtd/nand/libnand.o
+ LIBS-$(CONFIG_SPL_ONENAND_SUPPORT) += drivers/mtd/onenand/libonenand.o
+ LIBS-$(CONFIG_SPL_DMA_SUPPORT) += drivers/dma/libdma.o
+ LIBS-$(CONFIG_SPL_POST_MEM_SUPPORT) += post/drivers/memory.o
+-LIBS-$(CONFIG_SPL_NET_SUPPORT) += net/libnet.o
+-LIBS-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/libnet.o
+-LIBS-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/phy/libphy.o
+
+ ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
+ LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
+diff --git a/tools/binutils-version.sh b/tools/binutils-version.sh
+deleted file mode 100755
+index d4d9eb4..0000000
+--- a/tools/binutils-version.sh
++++ /dev/null
+@@ -1,20 +0,0 @@
+-#!/bin/sh
+-#
+-# binutils-version [-p] gas-command
+-#
+-# Prints the binutils version of `gas-command' in a canonical 4-digit form
+-# such as `0222' for binutils 2.22
+-#
+-
+-gas="$*"
+-
+-if [ ${#gas} -eq 0 ]; then
+- echo "Error: No assembler specified."
+- printf "Usage:\n\t$0 <gas-command>\n"
+- exit 1
+-fi
+-
+-MAJOR=$($gas --version | head -1 | awk '{print $NF}' | cut -d . -f 1)
+-MINOR=$($gas --version | head -1 | awk '{print $NF}' | cut -d . -f 2)
+-
+-printf "%02d%02d\\n" $MAJOR $MINOR
diff --git a/recipes-bsp/u-boot/u-boot-fslc_2012.10.bb b/recipes-bsp/u-boot/u-boot-fslc_2012.10.bb
index 7db9339..04848a6 100644
--- a/recipes-bsp/u-boot/u-boot-fslc_2012.10.bb
+++ b/recipes-bsp/u-boot/u-boot-fslc_2012.10.bb
@@ -14,6 +14,8 @@ PR = "r2"
SRCREV = "8f78e9e9bd4c2471fdd03644058aed3038dcbf38"
SRC_URI = "git://github.com/Freescale/u-boot-imx.git"
+SRC_URI_append_imx6qnitrogen6w =" file://support_nitrogen6x_config.patch"
+
S = "${WORKDIR}/git"
PACKAGE_ARCH = "${MACHINE_ARCH}"
diff --git a/recipes-kernel/linux/linux-imx-3.0.35/imx6qnitrogen6w/defconfig b/recipes-kernel/linux/linux-imx-3.0.35/imx6qnitrogen6w/defconfig
new file mode 100644
index 0000000..35e4cc3
--- /dev/null
+++ b/recipes-kernel/linux/linux-imx-3.0.35/imx6qnitrogen6w/defconfig
@@ -0,0 +1,3020 @@
+#
+# Automatically generated make config: don't edit
+# Linux/arm 3.0.35 Kernel Configuration
+#
+CONFIG_ARM=y
+CONFIG_HAVE_PWM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_HAVE_SCHED_CLOCK=y
+CONFIG_GENERIC_GPIO=y
+# CONFIG_ARCH_USES_GETTIMEOFFSET is not set
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_KTIME_SCALAR=y
+CONFIG_HAVE_PROC_CPU=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_GENERIC_LOCKBREAK=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_ARCH_HAS_CPUFREQ=y
+CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ZONE_DMA=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_FIQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+# CONFIG_ARM_PATCH_PHYS_VIRT is not set
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_HAVE_IRQ_WORK=y
+CONFIG_IRQ_WORK=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_CROSS_COMPILE=""
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_HAVE_KERNEL_LZO=y
+CONFIG_KERNEL_GZIP=y
+# CONFIG_KERNEL_LZMA is not set
+# CONFIG_KERNEL_LZO is not set
+CONFIG_DEFAULT_HOSTNAME="(none)"
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_FHANDLE is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+CONFIG_HAVE_GENERIC_HARDIRQS=y
+
+#
+# IRQ subsystem
+#
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_HAVE_SPARSE_IRQ=y
+CONFIG_GENERIC_IRQ_SHOW=y
+# CONFIG_SPARSE_IRQ is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_PREEMPT_RCU=y
+CONFIG_PREEMPT_RCU=y
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_RCU_BOOST is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_SCHED_AUTOGROUP is not set
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+# CONFIG_RD_XZ is not set
+# CONFIG_RD_LZO is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EXPERT=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_EMBEDDED=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_PERF_USE_VMALLOC=y
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_PERF_EVENTS=y
+# CONFIG_PERF_COUNTERS is not set
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+CONFIG_COMPAT_BRK=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_USE_GENERIC_SMP_HELPERS=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_HW_BREAKPOINT=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_STOP_MACHINE=y
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_SPIN_UNLOCK is not set
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_READ_UNLOCK is not set
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+# CONFIG_INLINE_READ_UNLOCK_IRQ is not set
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_WRITE_UNLOCK is not set
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_FREEZER=y
+
+#
+# System Type
+#
+CONFIG_MMU=y
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_VEXPRESS is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_BCMRING is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CNS3XXX is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+CONFIG_ARCH_MXC=y
+# CONFIG_ARCH_MXS is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_DOVE is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_LPC32XX is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_NUC93X is not set
+# CONFIG_ARCH_TEGRA is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_SHMOBILE is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5P64X0 is not set
+# CONFIG_ARCH_S5PC100 is not set
+# CONFIG_ARCH_S5PV210 is not set
+# CONFIG_ARCH_EXYNOS4 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_TCC_926 is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_U8500 is not set
+# CONFIG_ARCH_NOMADIK is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_PLAT_SPEAR is not set
+# CONFIG_ARCH_VT8500 is not set
+CONFIG_GPIO_PCA953X=y
+# CONFIG_KEYBOARD_GPIO_POLLED is not set
+CONFIG_IMX_HAVE_PLATFORM_DMA=y
+CONFIG_IMX_HAVE_PLATFORM_FEC=y
+CONFIG_IMX_HAVE_PLATFORM_FLEXCAN=y
+CONFIG_IMX_HAVE_PLATFORM_FSL_USB2_UDC=y
+CONFIG_IMX_HAVE_PLATFORM_GPMI_NFC=y
+CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_SNVS_RTC=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_CAAM=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_I2C=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_SSI=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_UART=y
+CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI=y
+CONFIG_IMX_HAVE_PLATFORM_MXC_PWM=y
+CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX=y
+CONFIG_IMX_HAVE_PLATFORM_SPI_IMX=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_IPUV3=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_VPU=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_DVFS=y
+CONFIG_IMX_HAVE_PLATFORM_AHCI=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_OCOTP=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_VIIM=y
+CONFIG_IMX_HAVE_PLATFORM_PERFMON=y
+CONFIG_IMX_HAVE_PLATFORM_LDB=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_SPDIF=y
+CONFIG_IMX_HAVE_PLATFORM_VIV_GPU=y
+CONFIG_IMX_HAVE_PLATFORM_MXC_HDMI=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_ANATOP_THERMAL=y
+CONFIG_IMX_HAVE_PLATFORM_FSL_OTG=y
+CONFIG_IMX_HAVE_PLATFORM_FSL_USB_WAKEUP=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_PM=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_ASRC=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_MIPI_DSI=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_MIPI_CSI2=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_VDOA=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_PCIE=y
+
+#
+# Freescale MXC Implementations
+#
+# CONFIG_ARCH_MX1 is not set
+# CONFIG_ARCH_MX2 is not set
+# CONFIG_ARCH_MX25 is not set
+# CONFIG_ARCH_MX3 is not set
+# CONFIG_ARCH_MX503 is not set
+# CONFIG_ARCH_MX51 is not set
+CONFIG_ARCH_MX6=y
+CONFIG_ARCH_MX6Q=y
+CONFIG_FORCE_MAX_ZONEORDER=14
+CONFIG_SOC_IMX6Q=y
+# CONFIG_MACH_MX6Q_ARM2 is not set
+# CONFIG_MACH_MX6SL_ARM2 is not set
+CONFIG_MACH_MX6Q_SABRELITE=y
+# CONFIG_MACH_MX6Q_SABRESD is not set
+# CONFIG_MACH_MX6Q_SABREAUTO is not set
+
+#
+# MX6 Options:
+#
+CONFIG_IMX_PCIE=y
+CONFIG_USB_EHCI_ARC_H1=y
+# CONFIG_MX6_INTER_LDO_BYPASS is not set
+CONFIG_ISP1504_MXC=y
+# CONFIG_MXC_IRQ_PRIOR is not set
+CONFIG_MXC_PWM=y
+# CONFIG_MXC_DEBUG_BOARD is not set
+CONFIG_MXC_REBOOT_MFGMODE=y
+# CONFIG_MXC_REBOOT_ANDROID_CMD is not set
+CONFIG_ARCH_MXC_IOMUX_V3=y
+CONFIG_ARCH_MXC_AUDMUX_V2=y
+CONFIG_IRAM_ALLOC=y
+CONFIG_CLK_DEBUG=y
+CONFIG_DMA_ZONE_SIZE=184
+
+#
+# System MMU
+#
+
+#
+# Processor Type
+#
+CONFIG_CPU_V7=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_ARM_THUMBEE is not set
+# CONFIG_SWP_EMULATE is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_OUTER_CACHE=y
+CONFIG_OUTER_CACHE_SYNC=y
+CONFIG_CACHE_L2X0=y
+CONFIG_CACHE_PL310=y
+CONFIG_ARM_L1_CACHE_SHIFT=5
+CONFIG_ARM_DMA_MEM_BUFFERABLE=y
+CONFIG_CPU_HAS_PMU=y
+# CONFIG_ARM_ERRATA_430973 is not set
+# CONFIG_ARM_ERRATA_458693 is not set
+# CONFIG_ARM_ERRATA_460075 is not set
+# CONFIG_ARM_ERRATA_742230 is not set
+# CONFIG_ARM_ERRATA_742231 is not set
+# CONFIG_PL310_ERRATA_588369 is not set
+# CONFIG_ARM_ERRATA_720789 is not set
+# CONFIG_PL310_ERRATA_727915 is not set
+CONFIG_ARM_ERRATA_743622=y
+CONFIG_ARM_ERRATA_751472=y
+# CONFIG_ARM_ERRATA_753970 is not set
+CONFIG_ARM_ERRATA_754322=y
+# CONFIG_ARM_ERRATA_754327 is not set
+CONFIG_ARM_GIC=y
+
+#
+# Bus support
+#
+CONFIG_PCI=y
+CONFIG_PCI_SYSCALL=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCI_STUB is not set
+# CONFIG_PCI_IOV is not set
+# CONFIG_PCIEPORTBUS is not set
+# CONFIG_PCCARD is not set
+CONFIG_ARM_ERRATA_764369=y
+# CONFIG_PL310_ERRATA_769419 is not set
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_SMP=y
+CONFIG_SMP_ON_UP=y
+CONFIG_HAVE_ARM_SCU=y
+CONFIG_HAVE_ARM_TWD=y
+# CONFIG_VMSPLIT_3G is not set
+CONFIG_VMSPLIT_2G=y
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0x80000000
+CONFIG_NR_CPUS=4
+CONFIG_HOTPLUG_CPU=y
+CONFIG_LOCAL_TIMERS=y
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+# CONFIG_THUMB2_KERNEL is not set
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_HAVE_ARCH_PFN_VALID=y
+CONFIG_HIGHMEM=y
+# CONFIG_HIGHPTE is not set
+CONFIG_HW_PERF_EVENTS=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_COMPACTION=y
+CONFIG_MIGRATION=y
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_KSM=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+# CONFIG_CLEANCACHE is not set
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
+# CONFIG_SECCOMP is not set
+# CONFIG_CC_STACKPROTECTOR is not set
+# CONFIG_DEPRECATED_PARAM_STRUCT is not set
+
+#
+# Boot options
+#
+# CONFIG_USE_OF is not set
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="noinitrd console=ttymxc0,115200 root=/dev/mtdblock2 rw rootfstype=jffs2 ip=off"
+CONFIG_CMDLINE_FROM_BOOTLOADER=y
+# CONFIG_CMDLINE_EXTEND is not set
+# CONFIG_CMDLINE_FORCE is not set
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+# CONFIG_CRASH_DUMP is not set
+# CONFIG_AUTO_ZRELADDR is not set
+
+#
+# CPU Power Management
+#
+
+#
+# CPU Frequency scaling
+#
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_TABLE=y
+CONFIG_CPU_FREQ_STAT=y
+# CONFIG_CPU_FREQ_STAT_DETAILS is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_INTERACTIVE=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_FREQ_IMX=y
+# CONFIG_CPU_IDLE is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_NEON=y
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+CONFIG_SUSPEND=y
+# CONFIG_PM_TEST_SUSPEND is not set
+CONFIG_SUSPEND_DEVICE_TIME_DEBUG=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_PM_SLEEP=y
+CONFIG_PM_SLEEP_SMP=y
+CONFIG_PM_RUNTIME=y
+CONFIG_PM=y
+CONFIG_PM_DEBUG=y
+# CONFIG_PM_ADVANCED_DEBUG is not set
+CONFIG_CAN_PM_TRACE=y
+CONFIG_APM_EMULATION=y
+CONFIG_PM_RUNTIME_CLK=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE_DEMUX is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_L2TP is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+CONFIG_LLC=y
+CONFIG_LLC2=y
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+# CONFIG_BATMAN_ADV is not set
+CONFIG_RPS=y
+CONFIG_RFS_ACCEL=y
+CONFIG_XPS=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+CONFIG_CAN=y
+CONFIG_CAN_RAW=y
+CONFIG_CAN_BCM=y
+
+#
+# CAN Device Drivers
+#
+CONFIG_CAN_VCAN=y
+# CONFIG_CAN_SLCAN is not set
+CONFIG_CAN_DEV=y
+CONFIG_CAN_CALC_BITTIMING=y
+# CONFIG_CAN_MCP251X is not set
+CONFIG_HAVE_CAN_FLEXCAN=y
+CONFIG_CAN_FLEXCAN=y
+# CONFIG_CAN_SJA1000 is not set
+# CONFIG_CAN_C_CAN is not set
+
+#
+# CAN USB interfaces
+#
+# CONFIG_CAN_EMS_USB is not set
+# CONFIG_CAN_ESD_USB2 is not set
+# CONFIG_CAN_SOFTING is not set
+# CONFIG_CAN_DEBUG_DEVICES is not set
+# CONFIG_IRDA is not set
+CONFIG_BT=y
+CONFIG_BT_L2CAP=y
+CONFIG_BT_SCO=y
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=y
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=y
+
+#
+# Bluetooth device drivers
+#
+# CONFIG_BT_HCIBTUSB is not set
+# CONFIG_BT_HCIBTSDIO is not set
+CONFIG_BT_HCIUART=y
+# CONFIG_BT_HCIUART_H4 is not set
+# CONFIG_BT_HCIUART_BCSP is not set
+# CONFIG_BT_HCIUART_ATH3K is not set
+CONFIG_BT_HCIUART_LL=y
+# CONFIG_BT_HCIBCM203X is not set
+# CONFIG_BT_HCIBPA10X is not set
+# CONFIG_BT_HCIBFUSB is not set
+# CONFIG_BT_HCIVHCI is not set
+# CONFIG_BT_MRVL is not set
+# CONFIG_BT_ATH3K is not set
+# CONFIG_AF_RXRPC is not set
+CONFIG_FIB_RULES=y
+CONFIG_WIRELESS=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_WEXT_CORE=y
+CONFIG_WEXT_PROC=y
+CONFIG_WEXT_SPY=y
+CONFIG_WEXT_PRIV=y
+CONFIG_CFG80211=y
+# CONFIG_NL80211_TESTMODE is not set
+# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
+# CONFIG_CFG80211_REG_DEBUG is not set
+CONFIG_CFG80211_DEFAULT_PS=y
+# CONFIG_CFG80211_DEBUGFS is not set
+# CONFIG_CFG80211_INTERNAL_REGDB is not set
+CONFIG_CFG80211_WEXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+CONFIG_LIB80211=y
+CONFIG_LIB80211_CRYPT_WEP=y
+CONFIG_LIB80211_CRYPT_CCMP=y
+CONFIG_LIB80211_CRYPT_TKIP=y
+# CONFIG_LIB80211_DEBUG is not set
+# CONFIG_CFG80211_ALLOW_RECONNECT is not set
+CONFIG_MAC80211=y
+CONFIG_MAC80211_HAS_RC=y
+# CONFIG_MAC80211_RC_PID is not set
+CONFIG_MAC80211_RC_MINSTREL=y
+CONFIG_MAC80211_RC_MINSTREL_HT=y
+CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
+CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
+# CONFIG_MAC80211_MESH is not set
+# CONFIG_MAC80211_LEDS is not set
+# CONFIG_MAC80211_DEBUGFS is not set
+# CONFIG_MAC80211_DEBUG_MENU is not set
+# CONFIG_WIMAX is not set
+CONFIG_RFKILL=y
+CONFIG_RFKILL_LEDS=y
+CONFIG_RFKILL_INPUT=y
+# CONFIG_RFKILL_REGULATOR is not set
+# CONFIG_RFKILL_GPIO is not set
+# CONFIG_NET_9P is not set
+# CONFIG_CAIF is not set
+# CONFIG_CEPH_LIB is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=y
+CONFIG_PROC_EVENTS=y
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_SM_FTL is not set
+# CONFIG_MTD_OOPS is not set
+# CONFIG_MTD_SWAP is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_DATAFLASH is not set
+CONFIG_MTD_M25P80=y
+CONFIG_M25PXX_USE_FAST_READ=y
+# CONFIG_MTD_SST25L is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND_ECC=y
+# CONFIG_MTD_NAND_ECC_SMC is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_BCH is not set
+# CONFIG_MTD_SM_COMMON is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_GPMI_NAND is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_RESERVE=1
+# CONFIG_MTD_UBI_GLUEBI is not set
+# CONFIG_MTD_UBI_DEBUG is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_DRBD is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MG_DISK is not set
+# CONFIG_BLK_DEV_RBD is not set
+# CONFIG_SENSORS_LIS3LV02D is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_AD525X_DPOT is not set
+# CONFIG_PHANTOM is not set
+# CONFIG_INTEL_MID_PTI is not set
+# CONFIG_SGI_IOC4 is not set
+# CONFIG_TIFM_CORE is not set
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_HP_ILO is not set
+# CONFIG_APDS9802ALS is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_ISL29020 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_SENSORS_BH1780 is not set
+# CONFIG_SENSORS_BH1770 is not set
+# CONFIG_SENSORS_APDS990X is not set
+# CONFIG_HMC6352 is not set
+# CONFIG_SENSORS_AK8975 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_TI_DAC7512 is not set
+# CONFIG_BMP085 is not set
+# CONFIG_PCH_PHUB is not set
+CONFIG_MXS_PERFMON=m
+# CONFIG_WL127X_RFKILL is not set
+# CONFIG_APANIC is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_CB710_CORE is not set
+# CONFIG_IWMC3200TOP is not set
+
+#
+# Texas Instruments shared transport line discipline
+#
+# CONFIG_TI_ST is not set
+# CONFIG_SENSORS_LIS3_SPI is not set
+# CONFIG_SENSORS_LIS3_I2C is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+CONFIG_SCSI_MOD=y
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_ISCSI_BOOT_SYSFS is not set
+# CONFIG_SCSI_CXGB3_ISCSI is not set
+# CONFIG_SCSI_CXGB4_ISCSI is not set
+# CONFIG_SCSI_BNX2_ISCSI is not set
+# CONFIG_SCSI_BNX2X_FCOE is not set
+# CONFIG_BE2ISCSI is not set
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_HPSA is not set
+# CONFIG_SCSI_3W_9XXX is not set
+# CONFIG_SCSI_3W_SAS is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_AIC94XX is not set
+# CONFIG_SCSI_MVSAS is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_ARCMSR is not set
+# CONFIG_MEGARAID_NEWGEN is not set
+# CONFIG_MEGARAID_LEGACY is not set
+# CONFIG_MEGARAID_SAS is not set
+# CONFIG_SCSI_MPT2SAS is not set
+# CONFIG_SCSI_HPTIOP is not set
+# CONFIG_LIBFC is not set
+# CONFIG_LIBFCOE is not set
+# CONFIG_FCOE is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_IPS is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_STEX is not set
+# CONFIG_SCSI_SYM53C8XX_2 is not set
+# CONFIG_SCSI_IPR is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLA_FC is not set
+# CONFIG_SCSI_QLA_ISCSI is not set
+# CONFIG_SCSI_LPFC is not set
+# CONFIG_SCSI_DC395x is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_NSP32 is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_PMCRAID is not set
+# CONFIG_SCSI_PM8001 is not set
+# CONFIG_SCSI_SRP is not set
+# CONFIG_SCSI_BFA_FC is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+CONFIG_ATA=y
+# CONFIG_ATA_NONSTANDARD is not set
+CONFIG_ATA_VERBOSE_ERROR=y
+# CONFIG_SATA_PMP is not set
+
+#
+# Controllers with non-SFF native interface
+#
+# CONFIG_SATA_AHCI is not set
+CONFIG_SATA_AHCI_PLATFORM=y
+# CONFIG_SATA_INIC162X is not set
+# CONFIG_SATA_ACARD_AHCI is not set
+# CONFIG_SATA_SIL24 is not set
+CONFIG_ATA_SFF=y
+
+#
+# SFF controllers with custom DMA interface
+#
+# CONFIG_PDC_ADMA is not set
+# CONFIG_SATA_QSTOR is not set
+# CONFIG_SATA_SX4 is not set
+CONFIG_ATA_BMDMA=y
+
+#
+# SATA SFF controllers with BMDMA
+#
+# CONFIG_ATA_PIIX is not set
+# CONFIG_SATA_MV is not set
+# CONFIG_SATA_NV is not set
+# CONFIG_SATA_PROMISE is not set
+# CONFIG_SATA_SIL is not set
+# CONFIG_SATA_SIS is not set
+# CONFIG_SATA_SVW is not set
+# CONFIG_SATA_ULI is not set
+# CONFIG_SATA_VIA is not set
+# CONFIG_SATA_VITESSE is not set
+
+#
+# PATA SFF controllers with BMDMA
+#
+# CONFIG_PATA_ALI is not set
+# CONFIG_PATA_AMD is not set
+# CONFIG_PATA_ARASAN_CF is not set
+# CONFIG_PATA_ARTOP is not set
+# CONFIG_PATA_ATIIXP is not set
+# CONFIG_PATA_ATP867X is not set
+# CONFIG_PATA_CMD64X is not set
+# CONFIG_PATA_CS5520 is not set
+# CONFIG_PATA_CS5530 is not set
+# CONFIG_PATA_CS5536 is not set
+# CONFIG_PATA_CYPRESS is not set
+# CONFIG_PATA_EFAR is not set
+# CONFIG_PATA_HPT366 is not set
+# CONFIG_PATA_HPT37X is not set
+# CONFIG_PATA_HPT3X2N is not set
+# CONFIG_PATA_HPT3X3 is not set
+# CONFIG_PATA_IT8213 is not set
+# CONFIG_PATA_IT821X is not set
+# CONFIG_PATA_JMICRON is not set
+# CONFIG_PATA_MARVELL is not set
+# CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NINJA32 is not set
+# CONFIG_PATA_NS87415 is not set
+# CONFIG_PATA_OLDPIIX is not set
+# CONFIG_PATA_OPTIDMA is not set
+# CONFIG_PATA_PDC2027X is not set
+# CONFIG_PATA_PDC_OLD is not set
+# CONFIG_PATA_RADISYS is not set
+# CONFIG_PATA_RDC is not set
+# CONFIG_PATA_SC1200 is not set
+# CONFIG_PATA_SCH is not set
+# CONFIG_PATA_SERVERWORKS is not set
+# CONFIG_PATA_SIL680 is not set
+# CONFIG_PATA_SIS is not set
+# CONFIG_PATA_TOSHIBA is not set
+# CONFIG_PATA_TRIFLEX is not set
+# CONFIG_PATA_VIA is not set
+# CONFIG_PATA_WINBOND is not set
+
+#
+# PIO-only SFF controllers
+#
+# CONFIG_PATA_CMD640_PCI is not set
+# CONFIG_PATA_MPIIX is not set
+# CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_OPTI is not set
+# CONFIG_PATA_PLATFORM is not set
+# CONFIG_PATA_RZ1000 is not set
+
+#
+# Generic fallback / legacy drivers
+#
+# CONFIG_ATA_GENERIC is not set
+# CONFIG_PATA_LEGACY is not set
+# CONFIG_MD is not set
+# CONFIG_TARGET_CORE is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_FIREWIRE_NOSY is not set
+# CONFIG_I2O is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+CONFIG_TUN=y
+# CONFIG_VETH is not set
+# CONFIG_ARCNET is not set
+CONFIG_MII=y
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+CONFIG_MICREL_PHY=y
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+# CONFIG_AX88796 is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_ENC28J60 is not set
+# CONFIG_ETHOC is not set
+# CONFIG_SMC911X is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_DNET is not set
+# CONFIG_NET_TULIP is not set
+# CONFIG_HP100 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_NET_PCI is not set
+# CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851 is not set
+# CONFIG_KS8851_MLL is not set
+CONFIG_FEC=y
+# CONFIG_FEC_NAPI is not set
+# CONFIG_FEC_1588 is not set
+# CONFIG_ATL2 is not set
+# CONFIG_FTMAC100 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_TR is not set
+CONFIG_WLAN=y
+# CONFIG_LIBERTAS_THINFIRM is not set
+# CONFIG_ATMEL is not set
+# CONFIG_AT76C50X_USB is not set
+# CONFIG_PRISM54 is not set
+# CONFIG_USB_ZD1201 is not set
+# CONFIG_USB_NET_RNDIS_WLAN is not set
+# CONFIG_RTL8180 is not set
+# CONFIG_RTL8187 is not set
+# CONFIG_ADM8211 is not set
+# CONFIG_MAC80211_HWSIM is not set
+# CONFIG_MWL8K is not set
+# CONFIG_WIFI_CONTROL_FUNC is not set
+# CONFIG_ATH_COMMON is not set
+# CONFIG_B43 is not set
+# CONFIG_B43LEGACY is not set
+# CONFIG_BCM4329 is not set
+# CONFIG_BCMDHD is not set
+CONFIG_HOSTAP=y
+# CONFIG_HOSTAP_FIRMWARE is not set
+# CONFIG_HOSTAP_PLX is not set
+# CONFIG_HOSTAP_PCI is not set
+# CONFIG_IPW2100 is not set
+# CONFIG_IPW2200 is not set
+# CONFIG_IWLAGN is not set
+# CONFIG_IWL4965 is not set
+# CONFIG_IWL3945 is not set
+# CONFIG_IWM is not set
+# CONFIG_LIBERTAS is not set
+# CONFIG_HERMES is not set
+# CONFIG_P54_COMMON is not set
+# CONFIG_RT2X00 is not set
+# CONFIG_RTL8192CE is not set
+# CONFIG_RTL8192SE is not set
+# CONFIG_RTL8192CU is not set
+# CONFIG_WL1251 is not set
+CONFIG_WL12XX_MENU=y
+CONFIG_WL12XX=y
+# CONFIG_WL12XX_HT is not set
+# CONFIG_WL12XX_SPI is not set
+CONFIG_WL12XX_SDIO=m
+# CONFIG_WL12XX_SDIO_TEST is not set
+CONFIG_WL12XX_PLATFORM_DATA=y
+# CONFIG_ZD1211RW is not set
+# CONFIG_MWIFIEX is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_USB_HSO is not set
+# CONFIG_USB_IPHETH is not set
+# CONFIG_WAN is not set
+
+#
+# CAIF transport drivers
+#
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+CONFIG_INPUT_POLLDEV=y
+# CONFIG_INPUT_SPARSEKMAP is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+# CONFIG_INPUT_APMPOWER is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ADP5588 is not set
+# CONFIG_KEYBOARD_ADP5589 is not set
+CONFIG_KEYBOARD_ATKBD=y
+# CONFIG_KEYBOARD_QT1070 is not set
+# CONFIG_KEYBOARD_QT2160 is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_KEYBOARD_TCA6416 is not set
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_KEYBOARD_LM8323 is not set
+# CONFIG_KEYBOARD_MAX7359 is not set
+# CONFIG_KEYBOARD_MCS is not set
+# CONFIG_KEYBOARD_MPR121 is not set
+# CONFIG_KEYBOARD_IMX is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_MXC is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_ADS7846 is not set
+# CONFIG_TOUCHSCREEN_AD7877 is not set
+# CONFIG_TOUCHSCREEN_AD7879 is not set
+# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
+# CONFIG_TOUCHSCREEN_BU21013 is not set
+# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set
+# CONFIG_TOUCHSCREEN_DYNAPRO is not set
+# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
+# CONFIG_TOUCHSCREEN_EETI is not set
+CONFIG_TOUCHSCREEN_EGALAX=y
+# CONFIG_TOUCHSCREEN_ELAN is not set
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_MAX11801 is not set
+CONFIG_TOUCHSCREEN_FT5X06=y
+CONFIG_TOUCHSCREEN_FT5X06_SINGLE_TOUCH=y
+# CONFIG_TOUCHSCREEN_MCS5000 is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_WM97XX is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_TSC2005 is not set
+# CONFIG_TOUCHSCREEN_TSC2007 is not set
+CONFIG_TOUCHSCREEN_TSC2004=y
+# CONFIG_TOUCHSCREEN_W90X900 is not set
+# CONFIG_TOUCHSCREEN_ST1232 is not set
+# CONFIG_TOUCHSCREEN_P1003 is not set
+# CONFIG_TOUCHSCREEN_TPS6507X is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_AD714X is not set
+# CONFIG_INPUT_ATI_REMOTE is not set
+# CONFIG_INPUT_ATI_REMOTE2 is not set
+# CONFIG_INPUT_KEYCHORD is not set
+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
+# CONFIG_INPUT_POWERMATE is not set
+# CONFIG_INPUT_YEALINK is not set
+# CONFIG_INPUT_CM109 is not set
+CONFIG_INPUT_UINPUT=y
+# CONFIG_INPUT_GPIO is not set
+# CONFIG_INPUT_PCF8574 is not set
+# CONFIG_INPUT_PWM_BEEPER is not set
+# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
+# CONFIG_INPUT_ADXL34X is not set
+# CONFIG_INPUT_CMA3000 is not set
+CONFIG_INPUT_ISL29023=y
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+# CONFIG_SERIO_PCIPS2 is not set
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_SERIO_ALTERA_PS2 is not set
+# CONFIG_SERIO_PS2MULT is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
+# CONFIG_N_GSM is not set
+# CONFIG_TRACE_SINK is not set
+CONFIG_DEVMEM=y
+CONFIG_DEVKMEM=y
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_MAX3100 is not set
+# CONFIG_SERIAL_MAX3107 is not set
+# CONFIG_SERIAL_MFD_HSU is not set
+CONFIG_SERIAL_IMX=y
+CONFIG_SERIAL_IMX_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+# CONFIG_SERIAL_TIMBERDALE is not set
+# CONFIG_SERIAL_ALTERA_JTAGUART is not set
+# CONFIG_SERIAL_ALTERA_UART is not set
+# CONFIG_SERIAL_IFX6X60 is not set
+# CONFIG_SERIAL_PCH_UART is not set
+# CONFIG_SERIAL_XILINX_PS_UART is not set
+# CONFIG_TTY_PRINTK is not set
+CONFIG_FSL_OTP=y
+# CONFIG_HVC_DCC is not set
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_HW_RANDOM_TIMERIOMEM is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+# CONFIG_DCC_TTY is not set
+# CONFIG_RAMOOPS is not set
+CONFIG_MXS_VIIM=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_CHARDEV=y
+# CONFIG_I2C_MUX is not set
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# PC SMBus host controller drivers
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_ISCH is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_DESIGNWARE is not set
+# CONFIG_I2C_GPIO is not set
+CONFIG_I2C_IMX=y
+# CONFIG_I2C_INTEL_MID is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_PXA_PCI is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_XILINX is not set
+# CONFIG_I2C_EG20T is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_DIOLAN_U2C is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_ALTERA is not set
+CONFIG_SPI_BITBANG=y
+# CONFIG_SPI_GPIO is not set
+CONFIG_SPI_IMX_VER_2_3=y
+CONFIG_SPI_IMX=y
+# CONFIG_SPI_OC_TINY is not set
+# CONFIG_SPI_PXA2XX_PCI is not set
+# CONFIG_SPI_TOPCLIFF_PCH is not set
+# CONFIG_SPI_XILINX is not set
+# CONFIG_SPI_DESIGNWARE is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+
+#
+# PPS generators support
+#
+
+#
+# PTP clock support
+#
+
+#
+# Enable Device Drivers -> PPS to see the PTP clock options.
+#
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
+
+#
+# Memory mapped GPIO drivers:
+#
+# CONFIG_GPIO_BASIC_MMIO is not set
+# CONFIG_GPIO_IT8761E is not set
+# CONFIG_GPIO_VX855 is not set
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX7300 is not set
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X_IRQ is not set
+# CONFIG_GPIO_PCF857X is not set
+# CONFIG_GPIO_SX150X is not set
+# CONFIG_GPIO_WM8994 is not set
+# CONFIG_GPIO_ADP5588 is not set
+
+#
+# PCI GPIO expanders:
+#
+# CONFIG_GPIO_BT8XX is not set
+# CONFIG_GPIO_ML_IOH is not set
+# CONFIG_GPIO_RDC321X is not set
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_GPIO_MC33880 is not set
+# CONFIG_GPIO_74X164 is not set
+
+#
+# AC97 GPIO expanders:
+#
+
+#
+# MODULbus GPIO expanders:
+#
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_APM_POWER is not set
+# CONFIG_TEST_POWER is not set
+# CONFIG_BATTERY_DS2780 is not set
+# CONFIG_BATTERY_DS2782 is not set
+# CONFIG_BATTERY_BQ20Z75 is not set
+# CONFIG_BATTERY_BQ27x00 is not set
+# CONFIG_BATTERY_MAX17040 is not set
+# CONFIG_BATTERY_MAX17042 is not set
+# CONFIG_CHARGER_ISP1704 is not set
+# CONFIG_CHARGER_MAX8903 is not set
+# CONFIG_CHARGER_GPIO is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Native drivers
+#
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADCXX is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7411 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7475 is not set
+# CONFIG_SENSORS_ASC7621 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS620 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_I5K_AMB is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_G760A is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_GPIO_FAN is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_JC42 is not set
+# CONFIG_SENSORS_LINEAGE is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_LM73 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LTC4151 is not set
+# CONFIG_SENSORS_LTC4215 is not set
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_LTC4261 is not set
+# CONFIG_SENSORS_LM95241 is not set
+# CONFIG_SENSORS_MAX1111 is not set
+# CONFIG_SENSORS_MAX16065 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6639 is not set
+# CONFIG_SENSORS_MAX6642 is not set
+CONFIG_SENSORS_MAX17135=y
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_PMBUS is not set
+# CONFIG_SENSORS_SHT15 is not set
+# CONFIG_SENSORS_SHT21 is not set
+# CONFIG_SENSORS_SIS5595 is not set
+# CONFIG_SENSORS_SMM665 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_EMC1403 is not set
+# CONFIG_SENSORS_EMC2103 is not set
+# CONFIG_SENSORS_EMC6W201 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_SCH5627 is not set
+# CONFIG_SENSORS_ADS1015 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_ADS7871 is not set
+# CONFIG_SENSORS_AMC6821 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_TMP102 is not set
+# CONFIG_SENSORS_TMP401 is not set
+# CONFIG_SENSORS_TMP421 is not set
+# CONFIG_SENSORS_VIA686A is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_VT8231 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83795 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+CONFIG_SENSORS_MAG3110=y
+# CONFIG_MXC_MMA8450 is not set
+CONFIG_MXC_MMA8451=y
+CONFIG_THERMAL=y
+# CONFIG_THERMAL_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+# CONFIG_MPCORE_WATCHDOG is not set
+# CONFIG_MAX63XX_WATCHDOG is not set
+CONFIG_IMX2_WDT=y
+# CONFIG_ALIM7101_WDT is not set
+
+#
+# PCI-based Watchdog Cards
+#
+# CONFIG_PCIPCWATCHDOG is not set
+# CONFIG_WDTPCI is not set
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+CONFIG_BCMA_POSSIBLE=y
+
+#
+# Broadcom specific AMBA
+#
+# CONFIG_BCMA is not set
+CONFIG_MFD_SUPPORT=y
+CONFIG_MFD_CORE=y
+# CONFIG_MFD_88PM860X is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_HTC_I2CPLD is not set
+# CONFIG_UCB1400_CORE is not set
+# CONFIG_TPS6105X is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TPS6507X is not set
+# CONFIG_MFD_TPS6586X is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_STMPE is not set
+# CONFIG_MFD_TC3589X is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_PMIC_ADP5520 is not set
+# CONFIG_MFD_MAX8925 is not set
+# CONFIG_MFD_MAX8997 is not set
+# CONFIG_MFD_MAX8998 is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X_I2C is not set
+# CONFIG_MFD_WM831X_SPI is not set
+# CONFIG_MFD_WM8350_I2C is not set
+CONFIG_MFD_WM8994=y
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_PMIC_DIALOG is not set
+# CONFIG_MFD_MC_PMIC is not set
+# CONFIG_MFD_MC34708 is not set
+CONFIG_MFD_PFUZE=y
+# CONFIG_MFD_MC13XXX is not set
+# CONFIG_ABX500_CORE is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_MFD_TIMBERDALE is not set
+# CONFIG_LPC_SCH is not set
+# CONFIG_MFD_RDC321X is not set
+# CONFIG_MFD_JANZ_CMODIO is not set
+# CONFIG_MFD_VX855 is not set
+# CONFIG_MFD_WL1273_CORE is not set
+# CONFIG_MFD_TPS65910 is not set
+CONFIG_MFD_MAX17135=y
+CONFIG_MFD_MXC_HDMI=y
+CONFIG_REGULATOR=y
+# CONFIG_REGULATOR_DEBUG is not set
+# CONFIG_REGULATOR_DUMMY is not set
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
+# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
+# CONFIG_REGULATOR_BQ24022 is not set
+# CONFIG_REGULATOR_MAX1586 is not set
+# CONFIG_REGULATOR_MAX8649 is not set
+# CONFIG_REGULATOR_MAX8660 is not set
+# CONFIG_REGULATOR_MAX8952 is not set
+# CONFIG_REGULATOR_WM8994 is not set
+# CONFIG_REGULATOR_LP3971 is not set
+# CONFIG_REGULATOR_LP3972 is not set
+# CONFIG_REGULATOR_MC34708 is not set
+CONFIG_REGULATOR_PFUZE100=y
+# CONFIG_REGULATOR_TPS65023 is not set
+# CONFIG_REGULATOR_TPS6507X is not set
+# CONFIG_REGULATOR_ISL6271A is not set
+# CONFIG_REGULATOR_AD5398 is not set
+CONFIG_REGULATOR_ANATOP=y
+# CONFIG_REGULATOR_TPS6524X is not set
+CONFIG_REGULATOR_MAX17135=y
+CONFIG_MEDIA_SUPPORT=y
+
+#
+# Multimedia core support
+#
+# CONFIG_MEDIA_CONTROLLER is not set
+CONFIG_VIDEO_DEV=y
+CONFIG_VIDEO_V4L2_COMMON=y
+# CONFIG_DVB_CORE is not set
+CONFIG_VIDEO_MEDIA=y
+
+#
+# Multimedia drivers
+#
+# CONFIG_RC_CORE is not set
+# CONFIG_MEDIA_ATTACH is not set
+CONFIG_MEDIA_TUNER=y
+# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
+CONFIG_MEDIA_TUNER_SIMPLE=y
+CONFIG_MEDIA_TUNER_TDA8290=y
+CONFIG_MEDIA_TUNER_TDA827X=y
+CONFIG_MEDIA_TUNER_TDA18271=y
+CONFIG_MEDIA_TUNER_TDA9887=y
+CONFIG_MEDIA_TUNER_TEA5761=y
+CONFIG_MEDIA_TUNER_TEA5767=y
+CONFIG_MEDIA_TUNER_MT20XX=y
+CONFIG_MEDIA_TUNER_XC2028=y
+CONFIG_MEDIA_TUNER_XC5000=y
+CONFIG_MEDIA_TUNER_MC44S803=y
+CONFIG_VIDEO_V4L2=y
+CONFIG_VIDEOBUF_GEN=y
+CONFIG_VIDEOBUF_DMA_CONTIG=y
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
+
+#
+# Encoders, decoders, sensors and other helper chips
+#
+
+#
+# Audio decoders, processors and mixers
+#
+# CONFIG_VIDEO_TVAUDIO is not set
+# CONFIG_VIDEO_TDA7432 is not set
+# CONFIG_VIDEO_TDA9840 is not set
+# CONFIG_VIDEO_TEA6415C is not set
+# CONFIG_VIDEO_TEA6420 is not set
+# CONFIG_VIDEO_MSP3400 is not set
+# CONFIG_VIDEO_CS5345 is not set
+# CONFIG_VIDEO_CS53L32A is not set
+# CONFIG_VIDEO_TLV320AIC23B is not set
+# CONFIG_VIDEO_WM8775 is not set
+# CONFIG_VIDEO_WM8739 is not set
+# CONFIG_VIDEO_VP27SMPX is not set
+
+#
+# RDS decoders
+#
+# CONFIG_VIDEO_SAA6588 is not set
+
+#
+# Video decoders
+#
+# CONFIG_VIDEO_ADV7180 is not set
+# CONFIG_VIDEO_BT819 is not set
+# CONFIG_VIDEO_BT856 is not set
+# CONFIG_VIDEO_BT866 is not set
+# CONFIG_VIDEO_KS0127 is not set
+# CONFIG_VIDEO_SAA7110 is not set
+# CONFIG_VIDEO_SAA711X is not set
+# CONFIG_VIDEO_SAA7191 is not set
+# CONFIG_VIDEO_TVP514X is not set
+# CONFIG_VIDEO_TVP5150 is not set
+# CONFIG_VIDEO_TVP7002 is not set
+# CONFIG_VIDEO_VPX3220 is not set
+
+#
+# Video and audio decoders
+#
+# CONFIG_VIDEO_SAA717X is not set
+# CONFIG_VIDEO_CX25840 is not set
+
+#
+# MPEG video encoders
+#
+# CONFIG_VIDEO_CX2341X is not set
+
+#
+# Video encoders
+#
+# CONFIG_VIDEO_SAA7127 is not set
+# CONFIG_VIDEO_SAA7185 is not set
+# CONFIG_VIDEO_ADV7170 is not set
+# CONFIG_VIDEO_ADV7175 is not set
+# CONFIG_VIDEO_ADV7343 is not set
+# CONFIG_VIDEO_AK881X is not set
+
+#
+# Camera sensor devices
+#
+# CONFIG_VIDEO_OV7670 is not set
+# CONFIG_VIDEO_MT9V011 is not set
+# CONFIG_VIDEO_TCM825X is not set
+
+#
+# Video improvement chips
+#
+# CONFIG_VIDEO_UPD64031A is not set
+# CONFIG_VIDEO_UPD64083 is not set
+
+#
+# Miscelaneous helper chips
+#
+# CONFIG_VIDEO_THS7303 is not set
+# CONFIG_VIDEO_M52790 is not set
+# CONFIG_VIDEO_VIVI is not set
+CONFIG_VIDEO_MXC_CAMERA=m
+
+#
+# MXC Camera/V4L2 PRP Features support
+#
+CONFIG_VIDEO_MXC_IPU_CAMERA=y
+# CONFIG_VIDEO_MXC_CSI_CAMERA is not set
+# CONFIG_MXC_CAMERA_MICRON111 is not set
+# CONFIG_MXC_CAMERA_OV2640 is not set
+CONFIG_MXC_CAMERA_OV3640=m
+CONFIG_MXC_CAMERA_OV5640=m
+CONFIG_MXC_CAMERA_OV8820_MIPI=m
+CONFIG_MXC_CAMERA_OV5642=m
+CONFIG_MXC_TVIN_ADV7180=m
+CONFIG_MXC_CAMERA_OV5640_MIPI=m
+CONFIG_MXC_CAMERA_SENSOR_CLK=m
+CONFIG_MXC_IPU_DEVICE_QUEUE_SDC=m
+CONFIG_MXC_IPU_PRP_ENC=m
+CONFIG_MXC_IPU_CSI_ENC=m
+CONFIG_VIDEO_MXC_OUTPUT=y
+CONFIG_VIDEO_MXC_IPU_OUTPUT=y
+# CONFIG_VIDEO_MXC_IPUV1_WVGA_OUTPUT is not set
+# CONFIG_VIDEO_MXC_OPL is not set
+# CONFIG_VIDEO_CPIA2 is not set
+# CONFIG_VIDEO_SAA7134 is not set
+# CONFIG_VIDEO_MXB is not set
+# CONFIG_VIDEO_HEXIUM_ORION is not set
+# CONFIG_VIDEO_HEXIUM_GEMINI is not set
+# CONFIG_VIDEO_TIMBERDALE is not set
+# CONFIG_VIDEO_CAFE_CCIC is not set
+# CONFIG_VIDEO_SR030PC30 is not set
+# CONFIG_VIDEO_NOON010PC30 is not set
+# CONFIG_SOC_CAMERA is not set
+CONFIG_V4L_USB_DRIVERS=y
+CONFIG_USB_VIDEO_CLASS=m
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+CONFIG_USB_GSPCA=m
+# CONFIG_USB_M5602 is not set
+# CONFIG_USB_STV06XX is not set
+# CONFIG_USB_GL860 is not set
+# CONFIG_USB_GSPCA_BENQ is not set
+# CONFIG_USB_GSPCA_CONEX is not set
+# CONFIG_USB_GSPCA_CPIA1 is not set
+# CONFIG_USB_GSPCA_ETOMS is not set
+# CONFIG_USB_GSPCA_FINEPIX is not set
+# CONFIG_USB_GSPCA_JEILINJ is not set
+# CONFIG_USB_GSPCA_KINECT is not set
+# CONFIG_USB_GSPCA_KONICA is not set
+# CONFIG_USB_GSPCA_MARS is not set
+# CONFIG_USB_GSPCA_MR97310A is not set
+# CONFIG_USB_GSPCA_NW80X is not set
+# CONFIG_USB_GSPCA_OV519 is not set
+# CONFIG_USB_GSPCA_OV534 is not set
+# CONFIG_USB_GSPCA_OV534_9 is not set
+# CONFIG_USB_GSPCA_PAC207 is not set
+# CONFIG_USB_GSPCA_PAC7302 is not set
+# CONFIG_USB_GSPCA_PAC7311 is not set
+# CONFIG_USB_GSPCA_SN9C2028 is not set
+# CONFIG_USB_GSPCA_SN9C20X is not set
+# CONFIG_USB_GSPCA_SONIXB is not set
+# CONFIG_USB_GSPCA_SONIXJ is not set
+# CONFIG_USB_GSPCA_SPCA500 is not set
+# CONFIG_USB_GSPCA_SPCA501 is not set
+# CONFIG_USB_GSPCA_SPCA505 is not set
+# CONFIG_USB_GSPCA_SPCA506 is not set
+# CONFIG_USB_GSPCA_SPCA508 is not set
+# CONFIG_USB_GSPCA_SPCA561 is not set
+# CONFIG_USB_GSPCA_SPCA1528 is not set
+# CONFIG_USB_GSPCA_SQ905 is not set
+# CONFIG_USB_GSPCA_SQ905C is not set
+# CONFIG_USB_GSPCA_SQ930X is not set
+# CONFIG_USB_GSPCA_STK014 is not set
+# CONFIG_USB_GSPCA_STV0680 is not set
+# CONFIG_USB_GSPCA_SUNPLUS is not set
+# CONFIG_USB_GSPCA_T613 is not set
+# CONFIG_USB_GSPCA_TV8532 is not set
+# CONFIG_USB_GSPCA_VC032X is not set
+# CONFIG_USB_GSPCA_VICAM is not set
+# CONFIG_USB_GSPCA_XIRLINK_CIT is not set
+# CONFIG_USB_GSPCA_ZC3XX is not set
+# CONFIG_VIDEO_PVRUSB2 is not set
+# CONFIG_VIDEO_HDPVR is not set
+# CONFIG_VIDEO_USBVISION is not set
+# CONFIG_USB_ET61X251 is not set
+# CONFIG_USB_SN9C102 is not set
+# CONFIG_USB_PWC is not set
+# CONFIG_USB_ZR364XX is not set
+# CONFIG_USB_STKWEBCAM is not set
+# CONFIG_USB_S2255 is not set
+# CONFIG_V4L_MEM2MEM_DRIVERS is not set
+# CONFIG_RADIO_ADAPTERS is not set
+
+#
+# Graphics support
+#
+CONFIG_DRM=m
+CONFIG_DRM_VIVANTE=m
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_WMT_GE_ROPS is not set
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+CONFIG_FB_MODE_HELPERS=y
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_CIRRUS is not set
+# CONFIG_FB_PM2 is not set
+# CONFIG_FB_CYBER2000 is not set
+# CONFIG_FB_ASILIANT is not set
+# CONFIG_FB_IMSTT is not set
+# CONFIG_FB_UVESA is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_NVIDIA is not set
+# CONFIG_FB_RIVA is not set
+# CONFIG_FB_MATROX is not set
+# CONFIG_FB_RADEON is not set
+# CONFIG_FB_ATY128 is not set
+# CONFIG_FB_ATY is not set
+# CONFIG_FB_S3 is not set
+# CONFIG_FB_SAVAGE is not set
+# CONFIG_FB_SIS is not set
+# CONFIG_FB_NEOMAGIC is not set
+# CONFIG_FB_KYRO is not set
+# CONFIG_FB_3DFX is not set
+# CONFIG_FB_VOODOO1 is not set
+# CONFIG_FB_VT8623 is not set
+# CONFIG_FB_TRIDENT is not set
+# CONFIG_FB_ARK is not set
+# CONFIG_FB_PM3 is not set
+# CONFIG_FB_CARMINE is not set
+# CONFIG_FB_TMIO is not set
+# CONFIG_FB_UDL is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+# CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_GENERIC is not set
+CONFIG_BACKLIGHT_PWM=y
+# CONFIG_BACKLIGHT_ADP8860 is not set
+# CONFIG_BACKLIGHT_ADP8870 is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+CONFIG_FB_MXC=y
+CONFIG_FB_MXC_EDID=y
+CONFIG_FB_MXC_SYNC_PANEL=y
+# CONFIG_FB_MXC_EPSON_VGA_SYNC_PANEL is not set
+CONFIG_FB_MXC_LDB=y
+CONFIG_FB_MXC_MIPI_DSI=y
+CONFIG_FB_MXC_TRULY_WVGA_SYNC_PANEL=y
+# CONFIG_FB_MXC_CLAA_WVGA_SYNC_PANEL is not set
+# CONFIG_FB_MXC_SEIKO_WVGA_SYNC_PANEL is not set
+# CONFIG_FB_MXC_SII902X is not set
+# CONFIG_FB_MXC_CH7026 is not set
+# CONFIG_FB_MXC_TVOUT_CH7024 is not set
+# CONFIG_FB_MXC_ASYNC_PANEL is not set
+# CONFIG_FB_MXC_EINK_PANEL is not set
+# CONFIG_FB_MXC_SIPIX_PANEL is not set
+# CONFIG_FB_MXC_ELCDIF_FB is not set
+CONFIG_FB_MXC_HDMI=y
+
+#
+# Console display driver support
+#
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+CONFIG_FONTS=y
+# CONFIG_FONT_8x8 is not set
+CONFIG_FONT_8x16=y
+# CONFIG_FONT_6x11 is not set
+# CONFIG_FONT_7x14 is not set
+# CONFIG_FONT_PEARL_8x8 is not set
+# CONFIG_FONT_ACORN_8x8 is not set
+# CONFIG_FONT_MINI_4x6 is not set
+# CONFIG_FONT_SUN8x16 is not set
+# CONFIG_FONT_SUN12x22 is not set
+# CONFIG_FONT_10x18 is not set
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_SOUND=y
+# CONFIG_SOUND_OSS_CORE is not set
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_HWDEP=y
+CONFIG_SND_RAWMIDI=y
+CONFIG_SND_JACK=y
+# CONFIG_SND_SEQUENCER is not set
+# CONFIG_SND_MIXER_OSS is not set
+# CONFIG_SND_PCM_OSS is not set
+# CONFIG_SND_HRTIMER is not set
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+CONFIG_SND_DRIVERS=y
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_ALOOP is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+CONFIG_SND_ARM=y
+CONFIG_SND_SPI=y
+CONFIG_SND_USB=y
+CONFIG_SND_USB_AUDIO=y
+# CONFIG_SND_USB_UA101 is not set
+# CONFIG_SND_USB_CAIAQ is not set
+# CONFIG_SND_USB_6FIRE is not set
+CONFIG_SND_SOC=y
+# CONFIG_SND_SOC_CACHE_LZO is not set
+CONFIG_SND_SOC_AC97_BUS=y
+CONFIG_SND_IMX_SOC=y
+CONFIG_SND_MXC_SOC_MX2=y
+CONFIG_SND_MXC_SOC_SPDIF_DAI=y
+CONFIG_SND_SOC_IMX_SGTL5000=y
+# CONFIG_SND_SOC_IMX_WM8958 is not set
+# CONFIG_SND_SOC_IMX_WM8962 is not set
+# CONFIG_SND_SOC_IMX_SI4763 is not set
+CONFIG_SND_SOC_IMX_SPDIF=y
+CONFIG_SND_SOC_IMX_HDMI=y
+CONFIG_SND_SOC_I2C_AND_SPI=y
+# CONFIG_SND_SOC_ALL_CODECS is not set
+CONFIG_SND_SOC_MXC_HDMI=y
+CONFIG_SND_SOC_MXC_SPDIF=y
+CONFIG_SND_SOC_SGTL5000=y
+# CONFIG_SOUND_PRIME is not set
+CONFIG_AC97_BUS=y
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+CONFIG_HIDRAW=y
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+# CONFIG_USB_HIDDEV is not set
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_ACRUX is not set
+# CONFIG_HID_APPLE is not set
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_PRODIKEYS is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_EMS_FF is not set
+# CONFIG_HID_ELECOM is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_KEYTOUCH is not set
+# CONFIG_HID_KYE is not set
+# CONFIG_HID_UCLOGIC is not set
+# CONFIG_HID_WALTOP is not set
+# CONFIG_HID_GYRATION is not set
+# CONFIG_HID_TWINHAN is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_LCPOWER is not set
+# CONFIG_HID_LOGITECH is not set
+# CONFIG_HID_MAGICMOUSE is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MONTEREY is not set
+# CONFIG_HID_MULTITOUCH is not set
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_ORTEK is not set
+# CONFIG_HID_PANTHERLORD is not set
+# CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_PICOLCD is not set
+CONFIG_HID_QUANTA=y
+# CONFIG_HID_ROCCAT is not set
+# CONFIG_HID_ROCCAT_ARVO is not set
+# CONFIG_HID_ROCCAT_KONE is not set
+# CONFIG_HID_ROCCAT_KONEPLUS is not set
+# CONFIG_HID_ROCCAT_KOVAPLUS is not set
+# CONFIG_HID_ROCCAT_PYRA is not set
+CONFIG_HID_SAMSUNG=m
+CONFIG_HID_SONY=m
+CONFIG_HID_SUNPLUS=m
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_WACOM is not set
+# CONFIG_HID_ZEROPLUS is not set
+# CONFIG_HID_ZYDACRON is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DEVICE_CLASS is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+CONFIG_USB_SUSPEND=y
+CONFIG_USB_OTG=y
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_XHCI_HCD is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ARC=y
+CONFIG_USB_EHCI_ARC_OTG=y
+# CONFIG_USB_EHCI_ARC_HSIC is not set
+# CONFIG_USB_STATIC_IRAM is not set
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+# CONFIG_USB_EHCI_MXC is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+# CONFIG_USB_OHCI_HCD is not set
+# CONFIG_USB_UHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_WHCI_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+# CONFIG_USB_MUSB_HDRC is not set
+
+#
+# USB Device Class drivers
+#
+CONFIG_USB_ACM=y
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_REALTEK is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_STORAGE_ENE_UB6250 is not set
+# CONFIG_USB_UAS is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+CONFIG_USB_SERIAL=y
+# CONFIG_USB_SERIAL_CONSOLE is not set
+# CONFIG_USB_EZUSB is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_AIRCABLE is not set
+# CONFIG_USB_SERIAL_ARK3116 is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_CH341 is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_CP210X is not set
+# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_FUNSOFT is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IPAQ is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
+# CONFIG_USB_SERIAL_GARMIN is not set
+# CONFIG_USB_SERIAL_IPW is not set
+# CONFIG_USB_SERIAL_IUU is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KLSI is not set
+# CONFIG_USB_SERIAL_KOBIL_SCT is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_MOS7720 is not set
+# CONFIG_USB_SERIAL_MOS7840 is not set
+# CONFIG_USB_SERIAL_MOTOROLA is not set
+# CONFIG_USB_SERIAL_NAVMAN is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_OTI6858 is not set
+# CONFIG_USB_SERIAL_QCAUX is not set
+CONFIG_USB_SERIAL_QUALCOMM=y
+# CONFIG_USB_SERIAL_SPCP8X5 is not set
+# CONFIG_USB_SERIAL_HP4X is not set
+# CONFIG_USB_SERIAL_SAFE is not set
+# CONFIG_USB_SERIAL_SIEMENS_MPI is not set
+# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
+# CONFIG_USB_SERIAL_SYMBOL is not set
+# CONFIG_USB_SERIAL_TI is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+CONFIG_USB_SERIAL_WWAN=y
+CONFIG_USB_SERIAL_OPTION=y
+# CONFIG_USB_SERIAL_OMNINET is not set
+# CONFIG_USB_SERIAL_OPTICON is not set
+# CONFIG_USB_SERIAL_VIVOPAY_SERIAL is not set
+# CONFIG_USB_SERIAL_ZIO is not set
+# CONFIG_USB_SERIAL_SSU100 is not set
+# CONFIG_USB_SERIAL_DEBUG is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_YUREX is not set
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+# CONFIG_USB_GADGET_DEBUG_FS is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+CONFIG_USB_GADGET_ARC=y
+# CONFIG_IMX_USB_CHARGER is not set
+CONFIG_USB_ARC=y
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_FUSB300 is not set
+# CONFIG_USB_GADGET_R8A66597 is not set
+# CONFIG_USB_GADGET_PXA_U2O is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_CI13XXX_PCI is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LANGWELL is not set
+# CONFIG_USB_GADGET_EG20T is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+# CONFIG_USB_ZERO is not set
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_ETH is not set
+CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_ETH_EEM is not set
+# CONFIG_USB_G_NCM is not set
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FUNCTIONFS is not set
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_MASS_STORAGE is not set
+CONFIG_USB_G_SERIAL=m
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+CONFIG_USB_G_ANDROID=y
+# CONFIG_USB_CDC_COMPOSITE is not set
+# CONFIG_USB_G_MULTI is not set
+# CONFIG_USB_G_HID is not set
+# CONFIG_USB_G_DBGP is not set
+# CONFIG_USB_G_WEBCAM is not set
+
+#
+# OTG and related infrastructure
+#
+CONFIG_USB_OTG_UTILS=y
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_USB_ULPI is not set
+# CONFIG_NOP_USB_XCEIV is not set
+CONFIG_MXC_OTG=y
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+CONFIG_MMC_UNSAFE_RESUME=y
+# CONFIG_MMC_CLKGATE is not set
+# CONFIG_MMC_EMBEDDED_SDIO is not set
+# CONFIG_MMC_PARANOID_SD_INIT is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_MINORS=8
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_IO_ACCESSORS=y
+# CONFIG_MMC_SDHCI_PCI is not set
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_ESDHC_IMX=y
+# CONFIG_MMC_TIFM_SD is not set
+# CONFIG_MMC_CB710 is not set
+# CONFIG_MMC_VIA_SDMMC is not set
+# CONFIG_MMC_DW is not set
+# CONFIG_MMC_VUB300 is not set
+# CONFIG_MMC_USHC is not set
+# CONFIG_SDHCI_USE_LEDS_CLASS is not set
+# CONFIG_MEMSTICK is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+# CONFIG_LEDS_LM3530 is not set
+# CONFIG_LEDS_PCA9532 is not set
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_GPIO_PLATFORM=y
+# CONFIG_LEDS_LP3944 is not set
+# CONFIG_LEDS_LP5521 is not set
+# CONFIG_LEDS_LP5523 is not set
+# CONFIG_LEDS_PCA955X is not set
+# CONFIG_LEDS_DAC124S085 is not set
+# CONFIG_LEDS_PWM is not set
+# CONFIG_LEDS_REGULATOR is not set
+# CONFIG_LEDS_BD2802 is not set
+# CONFIG_LEDS_LT3593 is not set
+CONFIG_LEDS_TRIGGERS=y
+
+#
+# LED Triggers
+#
+# CONFIG_LEDS_TRIGGER_TIMER is not set
+# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set
+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+
+#
+# iptables trigger is under Netfilter config (LED target)
+#
+
+#
+# LED Triggers
+#
+# CONFIG_NFC_DEVICES is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+CONFIG_RTC_INTF_DEV_UIE_EMUL=y
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_DS3232 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_ISL12022 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_BQ32K is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+# CONFIG_RTC_DRV_EM3027 is not set
+# CONFIG_RTC_DRV_RV3029C2 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T93 is not set
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_MSM6242 is not set
+# CONFIG_RTC_MXC is not set
+# CONFIG_RTC_DRV_MXC_V2 is not set
+CONFIG_RTC_DRV_SNVS=y
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_RP5C01 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_DMADEVICES=y
+# CONFIG_DMADEVICES_DEBUG is not set
+
+#
+# DMA Devices
+#
+# CONFIG_DW_DMAC is not set
+CONFIG_MXC_PXP_V2=y
+CONFIG_MXC_PXP_CLIENT_DEVICE=y
+# CONFIG_TIMB_DMA is not set
+CONFIG_IMX_SDMA=y
+# CONFIG_MXS_DMA is not set
+CONFIG_DMA_ENGINE=y
+
+#
+# DMA Clients
+#
+# CONFIG_NET_DMA is not set
+# CONFIG_ASYNC_TX_DMA is not set
+# CONFIG_DMATEST is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+# CONFIG_STAGING is not set
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_CLKSRC_MMIO=y
+
+#
+# MXC support drivers
+#
+CONFIG_MXC_IPU=y
+CONFIG_MXC_IPU_V3=y
+CONFIG_MXC_IPU_V3H=y
+
+#
+# MXC SSI support
+#
+# CONFIG_MXC_SSI is not set
+
+#
+# MXC Digital Audio Multiplexer support
+#
+# CONFIG_MXC_DAM is not set
+
+#
+# MXC PMIC support
+#
+# CONFIG_MXC_PMIC_MC13783 is not set
+# CONFIG_MXC_PMIC_MC13892 is not set
+# CONFIG_MXC_PMIC_MC34704 is not set
+# CONFIG_MXC_PMIC_MC9SDZ60 is not set
+# CONFIG_MXC_PMIC_MC9S08DZ60 is not set
+
+#
+# MXC Security Drivers
+#
+# CONFIG_MXC_SECURITY_SCC is not set
+# CONFIG_MXC_SECURITY_RNG is not set
+
+#
+# MXC MPEG4 Encoder Kernel module support
+#
+# CONFIG_MXC_HMP4E is not set
+
+#
+# MXC HARDWARE EVENT
+#
+# CONFIG_MXC_HWEVENT is not set
+
+#
+# MXC VPU(Video Processing Unit) support
+#
+CONFIG_MXC_VPU=y
+# CONFIG_MXC_VPU_DEBUG is not set
+
+#
+# MXC Asynchronous Sample Rate Converter support
+#
+CONFIG_MXC_ASRC=y
+
+#
+# MXC Bluetooth support
+#
+
+#
+# Broadcom GPS ioctrl support
+#
+
+#
+# MXC Media Local Bus Driver
+#
+# CONFIG_MXC_MLB150 is not set
+
+#
+# i.MX ADC support
+#
+# CONFIG_IMX_ADC is not set
+
+#
+# MXC Vivante GPU support
+#
+CONFIG_MXC_GPU_VIV=m
+
+#
+# ANATOP_THERMAL
+#
+CONFIG_ANATOP_THERMAL=y
+
+#
+# MXC MIPI Support
+#
+CONFIG_MXC_MIPI_CSI2=y
+
+#
+# MXC HDMI CEC (Consumer Electronics Control) support
+#
+# CONFIG_MXC_HDMI_CEC is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_XATTR=y
+# CONFIG_EXT4_FS_POSIX_ACL is not set
+# CONFIG_EXT4_FS_SECURITY is not set
+# CONFIG_EXT4_DEBUG is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_JBD2=y
+# CONFIG_JBD2_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_FANOTIFY is not set
+# CONFIG_QUOTA is not set
+# CONFIG_QUOTACTL is not set
+CONFIG_AUTOFS4_FS=y
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_TMPFS_XATTR is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_ECRYPT_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_YAFFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+CONFIG_UBIFS_FS=y
+# CONFIG_UBIFS_FS_XATTR is not set
+# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_ZLIB=y
+# CONFIG_UBIFS_FS_DEBUG is not set
+# CONFIG_LOGFS is not set
+CONFIG_CRAMFS=y
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_PSTORE is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_CEPH_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+CONFIG_EFI_PARTITION=y
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_ASCII=m
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=m
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_SECTION_MISMATCH is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_HARDLOCKUP_DETECTOR is not set
+# CONFIG_SPARSE_RCU_POINTER is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_MEMORY_INIT is not set
+CONFIG_RCU_CPU_STALL_TIMEOUT=60
+CONFIG_RCU_CPU_STALL_VERBOSE=y
+# CONFIG_LKDTM is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_DMA_API_DEBUG is not set
+# CONFIG_ATOMIC64_SELFTEST is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_TEST_KSTRTOX is not set
+# CONFIG_STRICT_DEVMEM is not set
+CONFIG_ARM_UNWIND=y
+# CONFIG_DEBUG_USER is not set
+# CONFIG_OC_ETM is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY_DMESG_RESTRICT is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP2=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set
+CONFIG_CRYPTO_GF128MUL=y
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_PCRYPT is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_AUTHENC=y
+CONFIG_CRYPTO_TEST=m
+# CONFIG_CRYPTO_CRYPTODEV is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+CONFIG_CRYPTO_CCM=y
+CONFIG_CRYPTO_GCM=y
+CONFIG_CRYPTO_SEQIV=y
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CTR=y
+CONFIG_CRYPTO_CTS=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_LRW=y
+CONFIG_CRYPTO_PCBC=y
+CONFIG_CRYPTO_XTS=y
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+CONFIG_CRYPTO_GHASH=y
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+CONFIG_CRYPTO_MICHAEL_MIC=y
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+# CONFIG_CRYPTO_ANUBIS is not set
+CONFIG_CRYPTO_ARC4=y
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+# CONFIG_CRYPTO_ZLIB is not set
+CONFIG_CRYPTO_LZO=y
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_USER_API_HASH is not set
+# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_DEV_FSL_CAAM=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE=9
+CONFIG_CRYPTO_DEV_FSL_CAAM_INTC=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_INTC_COUNT_THLD=255
+CONFIG_CRYPTO_DEV_FSL_CAAM_INTC_TIME_THLD=2048
+CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API=y
+# CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API is not set
+CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API=y
+# CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_TEST is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_RATIONAL=y
+CONFIG_CRC_CCITT=m
+CONFIG_CRC16=y
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+# CONFIG_XZ_DEC is not set
+# CONFIG_XZ_DEC_BCJ is not set
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_CPU_RMAP=y
+CONFIG_NLATTR=y
+# CONFIG_AVERAGE is not set
diff --git a/recipes-kernel/linux/linux-imx-3.0.35/imx6qnitrogen6w/support_for_nitrogen6_configuration.patch b/recipes-kernel/linux/linux-imx-3.0.35/imx6qnitrogen6w/support_for_nitrogen6_configuration.patch
new file mode 100644
index 0000000..c09dba4
--- /dev/null
+++ b/recipes-kernel/linux/linux-imx-3.0.35/imx6qnitrogen6w/support_for_nitrogen6_configuration.patch
@@ -0,0 +1,11469 @@
+diff --git a/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt b/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/configs/imx5_defconfig b/arch/arm/configs/imx5_defconfig
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/configs/imx6_defconfig b/arch/arm/configs/imx6_defconfig
+index f9a4eac..495cdf7 100644
+--- a/arch/arm/configs/imx6_defconfig
++++ b/arch/arm/configs/imx6_defconfig
+@@ -306,7 +306,6 @@ CONFIG_FORCE_MAX_ZONEORDER=14
+ CONFIG_SOC_IMX6Q=y
+ CONFIG_MACH_MX6Q_ARM2=y
+ # CONFIG_MACH_MX6SL_ARM2 is not set
+-# CONFIG_MACH_MX6SL_EVK is not set
+ CONFIG_MACH_MX6Q_SABRELITE=y
+ CONFIG_MACH_MX6Q_SABRESD=y
+ CONFIG_MACH_MX6Q_SABREAUTO=y
+@@ -2276,7 +2275,6 @@ CONFIG_MXC_IPU_V3H=y
+ #
+ CONFIG_MXC_VPU=y
+ # CONFIG_MXC_VPU_DEBUG is not set
+-# CONFIG_MX6_VPU_352M is not set
+
+ #
+ # MXC Asynchronous Sample Rate Converter support
+@@ -2671,7 +2669,7 @@ CONFIG_CRYPTO_DEV_FSL_CAAM_INTC=y
+ CONFIG_CRYPTO_DEV_FSL_CAAM_INTC_COUNT_THLD=255
+ CONFIG_CRYPTO_DEV_FSL_CAAM_INTC_TIME_THLD=2048
+ CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API=y
+-CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API=y
++# CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API is not set
+ CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API=y
+ # CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_TEST is not set
+ # CONFIG_BINARY_PRINTF is not set
+diff --git a/arch/arm/configs/imx6s_updater_defconfig b/arch/arm/configs/imx6s_updater_defconfig
+deleted file mode 100644
+index 0bd3bca..0000000
+--- a/arch/arm/configs/imx6s_updater_defconfig
++++ /dev/null
+@@ -1,2376 +0,0 @@
+-#
+-# Automatically generated make config: don't edit
+-# Linux/arm 3.0.35 Kernel Configuration
+-#
+-CONFIG_ARM=y
+-CONFIG_HAVE_PWM=y
+-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+-CONFIG_HAVE_SCHED_CLOCK=y
+-CONFIG_GENERIC_GPIO=y
+-# CONFIG_ARCH_USES_GETTIMEOFFSET is not set
+-CONFIG_GENERIC_CLOCKEVENTS=y
+-CONFIG_KTIME_SCALAR=y
+-CONFIG_HAVE_PROC_CPU=y
+-CONFIG_STACKTRACE_SUPPORT=y
+-CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+-CONFIG_LOCKDEP_SUPPORT=y
+-CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+-CONFIG_HARDIRQS_SW_RESEND=y
+-CONFIG_GENERIC_IRQ_PROBE=y
+-CONFIG_RWSEM_GENERIC_SPINLOCK=y
+-CONFIG_ARCH_HAS_CPUFREQ=y
+-CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y
+-CONFIG_GENERIC_HWEIGHT=y
+-CONFIG_GENERIC_CALIBRATE_DELAY=y
+-CONFIG_ZONE_DMA=y
+-CONFIG_NEED_DMA_MAP_STATE=y
+-CONFIG_FIQ=y
+-CONFIG_VECTORS_BASE=0xffff0000
+-CONFIG_ARM_PATCH_PHYS_VIRT=y
+-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+-CONFIG_HAVE_IRQ_WORK=y
+-CONFIG_IRQ_WORK=y
+-
+-#
+-# General setup
+-#
+-CONFIG_EXPERIMENTAL=y
+-CONFIG_BROKEN_ON_SMP=y
+-CONFIG_INIT_ENV_ARG_LIMIT=32
+-CONFIG_CROSS_COMPILE=""
+-CONFIG_LOCALVERSION=""
+-CONFIG_LOCALVERSION_AUTO=y
+-CONFIG_HAVE_KERNEL_GZIP=y
+-CONFIG_HAVE_KERNEL_LZMA=y
+-CONFIG_HAVE_KERNEL_LZO=y
+-CONFIG_KERNEL_GZIP=y
+-# CONFIG_KERNEL_LZMA is not set
+-# CONFIG_KERNEL_LZO is not set
+-CONFIG_DEFAULT_HOSTNAME="(none)"
+-CONFIG_SWAP=y
+-CONFIG_SYSVIPC=y
+-CONFIG_SYSVIPC_SYSCTL=y
+-# CONFIG_POSIX_MQUEUE is not set
+-# CONFIG_BSD_PROCESS_ACCT is not set
+-# CONFIG_FHANDLE is not set
+-# CONFIG_TASKSTATS is not set
+-# CONFIG_AUDIT is not set
+-CONFIG_HAVE_GENERIC_HARDIRQS=y
+-
+-#
+-# IRQ subsystem
+-#
+-CONFIG_GENERIC_HARDIRQS=y
+-CONFIG_HAVE_SPARSE_IRQ=y
+-CONFIG_GENERIC_IRQ_SHOW=y
+-# CONFIG_SPARSE_IRQ is not set
+-
+-#
+-# RCU Subsystem
+-#
+-CONFIG_TREE_PREEMPT_RCU=y
+-# CONFIG_TINY_RCU is not set
+-# CONFIG_TINY_PREEMPT_RCU is not set
+-CONFIG_PREEMPT_RCU=y
+-# CONFIG_RCU_TRACE is not set
+-CONFIG_RCU_FANOUT=32
+-# CONFIG_RCU_FANOUT_EXACT is not set
+-# CONFIG_TREE_RCU_TRACE is not set
+-# CONFIG_RCU_BOOST is not set
+-CONFIG_IKCONFIG=y
+-CONFIG_IKCONFIG_PROC=y
+-CONFIG_LOG_BUF_SHIFT=14
+-# CONFIG_CGROUPS is not set
+-# CONFIG_NAMESPACES is not set
+-# CONFIG_SCHED_AUTOGROUP is not set
+-# CONFIG_SYSFS_DEPRECATED is not set
+-# CONFIG_RELAY is not set
+-CONFIG_BLK_DEV_INITRD=y
+-CONFIG_INITRAMFS_SOURCE=""
+-CONFIG_RD_GZIP=y
+-# CONFIG_RD_BZIP2 is not set
+-# CONFIG_RD_LZMA is not set
+-# CONFIG_RD_XZ is not set
+-# CONFIG_RD_LZO is not set
+-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+-CONFIG_SYSCTL=y
+-CONFIG_ANON_INODES=y
+-CONFIG_EXPERT=y
+-CONFIG_UID16=y
+-CONFIG_SYSCTL_SYSCALL=y
+-CONFIG_KALLSYMS=y
+-CONFIG_HOTPLUG=y
+-CONFIG_PRINTK=y
+-CONFIG_BUG=y
+-CONFIG_ELF_CORE=y
+-CONFIG_BASE_FULL=y
+-CONFIG_FUTEX=y
+-CONFIG_EPOLL=y
+-CONFIG_SIGNALFD=y
+-CONFIG_TIMERFD=y
+-CONFIG_EVENTFD=y
+-CONFIG_SHMEM=y
+-CONFIG_AIO=y
+-CONFIG_EMBEDDED=y
+-CONFIG_HAVE_PERF_EVENTS=y
+-CONFIG_PERF_USE_VMALLOC=y
+-
+-#
+-# Kernel Performance Events And Counters
+-#
+-CONFIG_PERF_EVENTS=y
+-# CONFIG_PERF_COUNTERS is not set
+-CONFIG_VM_EVENT_COUNTERS=y
+-CONFIG_SLUB_DEBUG=y
+-CONFIG_COMPAT_BRK=y
+-# CONFIG_SLAB is not set
+-CONFIG_SLUB=y
+-# CONFIG_SLOB is not set
+-# CONFIG_PROFILING is not set
+-CONFIG_HAVE_OPROFILE=y
+-# CONFIG_KPROBES is not set
+-CONFIG_HAVE_KPROBES=y
+-CONFIG_HAVE_KRETPROBES=y
+-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
+-CONFIG_HAVE_CLK=y
+-CONFIG_HAVE_DMA_API_DEBUG=y
+-CONFIG_HAVE_HW_BREAKPOINT=y
+-
+-#
+-# GCOV-based kernel profiling
+-#
+-# CONFIG_GCOV_KERNEL is not set
+-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+-CONFIG_SLABINFO=y
+-CONFIG_RT_MUTEXES=y
+-CONFIG_BASE_SMALL=0
+-CONFIG_MODULES=y
+-# CONFIG_MODULE_FORCE_LOAD is not set
+-CONFIG_MODULE_UNLOAD=y
+-CONFIG_MODULE_FORCE_UNLOAD=y
+-CONFIG_MODVERSIONS=y
+-# CONFIG_MODULE_SRCVERSION_ALL is not set
+-CONFIG_BLOCK=y
+-CONFIG_LBDAF=y
+-# CONFIG_BLK_DEV_BSG is not set
+-# CONFIG_BLK_DEV_INTEGRITY is not set
+-
+-#
+-# IO Schedulers
+-#
+-CONFIG_IOSCHED_NOOP=y
+-CONFIG_IOSCHED_DEADLINE=y
+-CONFIG_IOSCHED_CFQ=y
+-# CONFIG_DEFAULT_DEADLINE is not set
+-CONFIG_DEFAULT_CFQ=y
+-# CONFIG_DEFAULT_NOOP is not set
+-CONFIG_DEFAULT_IOSCHED="cfq"
+-# CONFIG_INLINE_SPIN_TRYLOCK is not set
+-# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+-# CONFIG_INLINE_SPIN_LOCK is not set
+-# CONFIG_INLINE_SPIN_LOCK_BH is not set
+-# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+-# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+-# CONFIG_INLINE_SPIN_UNLOCK is not set
+-# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+-# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set
+-# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+-# CONFIG_INLINE_READ_TRYLOCK is not set
+-# CONFIG_INLINE_READ_LOCK is not set
+-# CONFIG_INLINE_READ_LOCK_BH is not set
+-# CONFIG_INLINE_READ_LOCK_IRQ is not set
+-# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+-# CONFIG_INLINE_READ_UNLOCK is not set
+-# CONFIG_INLINE_READ_UNLOCK_BH is not set
+-# CONFIG_INLINE_READ_UNLOCK_IRQ is not set
+-# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+-# CONFIG_INLINE_WRITE_TRYLOCK is not set
+-# CONFIG_INLINE_WRITE_LOCK is not set
+-# CONFIG_INLINE_WRITE_LOCK_BH is not set
+-# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+-# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+-# CONFIG_INLINE_WRITE_UNLOCK is not set
+-# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+-# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set
+-# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+-# CONFIG_MUTEX_SPIN_ON_OWNER is not set
+-CONFIG_FREEZER=y
+-
+-#
+-# System Type
+-#
+-CONFIG_MMU=y
+-# CONFIG_ARCH_INTEGRATOR is not set
+-# CONFIG_ARCH_REALVIEW is not set
+-# CONFIG_ARCH_VERSATILE is not set
+-# CONFIG_ARCH_VEXPRESS is not set
+-# CONFIG_ARCH_AT91 is not set
+-# CONFIG_ARCH_BCMRING is not set
+-# CONFIG_ARCH_CLPS711X is not set
+-# CONFIG_ARCH_CNS3XXX is not set
+-# CONFIG_ARCH_GEMINI is not set
+-# CONFIG_ARCH_EBSA110 is not set
+-# CONFIG_ARCH_EP93XX is not set
+-# CONFIG_ARCH_FOOTBRIDGE is not set
+-CONFIG_ARCH_MXC=y
+-# CONFIG_ARCH_MXS is not set
+-# CONFIG_ARCH_NETX is not set
+-# CONFIG_ARCH_H720X is not set
+-# CONFIG_ARCH_IOP13XX is not set
+-# CONFIG_ARCH_IOP32X is not set
+-# CONFIG_ARCH_IOP33X is not set
+-# CONFIG_ARCH_IXP23XX is not set
+-# CONFIG_ARCH_IXP2000 is not set
+-# CONFIG_ARCH_IXP4XX is not set
+-# CONFIG_ARCH_DOVE is not set
+-# CONFIG_ARCH_KIRKWOOD is not set
+-# CONFIG_ARCH_LOKI is not set
+-# CONFIG_ARCH_LPC32XX is not set
+-# CONFIG_ARCH_MV78XX0 is not set
+-# CONFIG_ARCH_ORION5X is not set
+-# CONFIG_ARCH_MMP is not set
+-# CONFIG_ARCH_KS8695 is not set
+-# CONFIG_ARCH_W90X900 is not set
+-# CONFIG_ARCH_NUC93X is not set
+-# CONFIG_ARCH_TEGRA is not set
+-# CONFIG_ARCH_PNX4008 is not set
+-# CONFIG_ARCH_PXA is not set
+-# CONFIG_ARCH_MSM is not set
+-# CONFIG_ARCH_SHMOBILE is not set
+-# CONFIG_ARCH_RPC is not set
+-# CONFIG_ARCH_SA1100 is not set
+-# CONFIG_ARCH_S3C2410 is not set
+-# CONFIG_ARCH_S3C64XX is not set
+-# CONFIG_ARCH_S5P64X0 is not set
+-# CONFIG_ARCH_S5PC100 is not set
+-# CONFIG_ARCH_S5PV210 is not set
+-# CONFIG_ARCH_EXYNOS4 is not set
+-# CONFIG_ARCH_SHARK is not set
+-# CONFIG_ARCH_TCC_926 is not set
+-# CONFIG_ARCH_U300 is not set
+-# CONFIG_ARCH_U8500 is not set
+-# CONFIG_ARCH_NOMADIK is not set
+-# CONFIG_ARCH_DAVINCI is not set
+-# CONFIG_ARCH_OMAP is not set
+-# CONFIG_PLAT_SPEAR is not set
+-# CONFIG_ARCH_VT8500 is not set
+-CONFIG_GPIO_PCA953X=y
+-CONFIG_IMX_HAVE_PLATFORM_DMA=y
+-CONFIG_IMX_HAVE_PLATFORM_MXC_MLB=y
+-CONFIG_IMX_HAVE_PLATFORM_FEC=y
+-CONFIG_IMX_HAVE_PLATFORM_FLEXCAN=y
+-CONFIG_IMX_HAVE_PLATFORM_FSL_USB2_UDC=y
+-CONFIG_IMX_HAVE_PLATFORM_GPMI_NFC=y
+-CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT=y
+-CONFIG_IMX_HAVE_PLATFORM_IMX_SNVS_RTC=y
+-CONFIG_IMX_HAVE_PLATFORM_IMX_CAAM=y
+-CONFIG_IMX_HAVE_PLATFORM_IMX_I2C=y
+-CONFIG_IMX_HAVE_PLATFORM_IMX_KEYPAD=y
+-CONFIG_IMX_HAVE_PLATFORM_IMX_SSI=y
+-CONFIG_IMX_HAVE_PLATFORM_IMX_ESAI=y
+-CONFIG_IMX_HAVE_PLATFORM_IMX_UART=y
+-CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI=y
+-CONFIG_IMX_HAVE_PLATFORM_MXC_PWM=y
+-CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX=y
+-CONFIG_IMX_HAVE_PLATFORM_SPI_IMX=y
+-CONFIG_IMX_HAVE_PLATFORM_IMX_IPUV3=y
+-CONFIG_IMX_HAVE_PLATFORM_IMX_VPU=y
+-CONFIG_IMX_HAVE_PLATFORM_IMX_DVFS=y
+-CONFIG_IMX_HAVE_PLATFORM_AHCI=y
+-CONFIG_IMX_HAVE_PLATFORM_IMX_OCOTP=y
+-CONFIG_IMX_HAVE_PLATFORM_IMX_VIIM=y
+-CONFIG_IMX_HAVE_PLATFORM_IMX_DCP=y
+-CONFIG_IMX_HAVE_PLATFORM_RANDOM_RNGC=y
+-CONFIG_IMX_HAVE_PLATFORM_PERFMON=y
+-CONFIG_IMX_HAVE_PLATFORM_LDB=y
+-CONFIG_IMX_HAVE_PLATFORM_IMX_PXP=y
+-CONFIG_IMX_HAVE_PLATFORM_IMX_ELCDIF=y
+-CONFIG_IMX_HAVE_PLATFORM_IMX_EPDC=y
+-CONFIG_IMX_HAVE_PLATFORM_IMX_SPDC=y
+-CONFIG_IMX_HAVE_PLATFORM_IMX_SPDIF=y
+-CONFIG_IMX_HAVE_PLATFORM_VIV_GPU=y
+-CONFIG_IMX_HAVE_PLATFORM_MXC_HDMI=y
+-CONFIG_IMX_HAVE_PLATFORM_IMX_ANATOP_THERMAL=y
+-CONFIG_IMX_HAVE_PLATFORM_FSL_OTG=y
+-CONFIG_IMX_HAVE_PLATFORM_FSL_USB_WAKEUP=y
+-CONFIG_IMX_HAVE_PLATFORM_IMX_PM=y
+-CONFIG_IMX_HAVE_PLATFORM_IMX_ASRC=y
+-CONFIG_IMX_HAVE_PLATFORM_IMX_MIPI_DSI=y
+-CONFIG_IMX_HAVE_PLATFORM_IMX_MIPI_CSI2=y
+-CONFIG_IMX_HAVE_PLATFORM_IMX_VDOA=y
+-CONFIG_IMX_HAVE_PLATFORM_IMX_PCIE=y
+-
+-#
+-# Freescale MXC Implementations
+-#
+-# CONFIG_ARCH_MX1 is not set
+-# CONFIG_ARCH_MX2 is not set
+-# CONFIG_ARCH_MX25 is not set
+-# CONFIG_ARCH_MX3 is not set
+-# CONFIG_ARCH_MX503 is not set
+-# CONFIG_ARCH_MX51 is not set
+-CONFIG_ARCH_MX6=y
+-CONFIG_ARCH_MX6Q=y
+-CONFIG_FORCE_MAX_ZONEORDER=13
+-CONFIG_SOC_IMX6Q=y
+-CONFIG_SOC_IMX6SL=y
+-CONFIG_MACH_MX6Q_ARM2=y
+-CONFIG_MACH_MX6SL_ARM2=y
+-CONFIG_MACH_MX6SL_EVK=y
+-CONFIG_MACH_MX6Q_SABRELITE=y
+-CONFIG_MACH_MX6Q_SABRESD=y
+-CONFIG_MACH_MX6Q_SABREAUTO=y
+-
+-#
+-# MX6 Options:
+-#
+-# CONFIG_IMX_PCIE is not set
+-CONFIG_MX6_INTER_LDO_BYPASS=y
+-CONFIG_ISP1504_MXC=y
+-# CONFIG_MXC_IRQ_PRIOR is not set
+-CONFIG_MXC_PWM=y
+-# CONFIG_MXC_DEBUG_BOARD is not set
+-# CONFIG_MXC_REBOOT_MFGMODE is not set
+-# CONFIG_MXC_REBOOT_ANDROID_CMD is not set
+-CONFIG_ARCH_HAS_RNGC=y
+-CONFIG_ARCH_MXC_IOMUX_V3=y
+-CONFIG_ARCH_MXC_AUDMUX_V2=y
+-CONFIG_IRAM_ALLOC=y
+-CONFIG_CLK_DEBUG=y
+-CONFIG_DMA_ZONE_SIZE=184
+-
+-#
+-# System MMU
+-#
+-
+-#
+-# Processor Type
+-#
+-CONFIG_CPU_V7=y
+-CONFIG_CPU_32v6K=y
+-CONFIG_CPU_32v7=y
+-CONFIG_CPU_ABRT_EV7=y
+-CONFIG_CPU_PABRT_V7=y
+-CONFIG_CPU_CACHE_V7=y
+-CONFIG_CPU_CACHE_VIPT=y
+-CONFIG_CPU_COPY_V6=y
+-CONFIG_CPU_TLB_V7=y
+-CONFIG_CPU_HAS_ASID=y
+-CONFIG_CPU_CP15=y
+-CONFIG_CPU_CP15_MMU=y
+-
+-#
+-# Processor Features
+-#
+-CONFIG_ARM_THUMB=y
+-# CONFIG_ARM_THUMBEE is not set
+-# CONFIG_SWP_EMULATE is not set
+-# CONFIG_CPU_ICACHE_DISABLE is not set
+-# CONFIG_CPU_DCACHE_DISABLE is not set
+-# CONFIG_CPU_BPREDICT_DISABLE is not set
+-CONFIG_OUTER_CACHE=y
+-CONFIG_OUTER_CACHE_SYNC=y
+-CONFIG_CACHE_L2X0=y
+-CONFIG_CACHE_PL310=y
+-CONFIG_ARM_L1_CACHE_SHIFT=5
+-CONFIG_ARM_DMA_MEM_BUFFERABLE=y
+-CONFIG_CPU_HAS_PMU=y
+-# CONFIG_ARM_ERRATA_430973 is not set
+-# CONFIG_ARM_ERRATA_458693 is not set
+-# CONFIG_ARM_ERRATA_460075 is not set
+-# CONFIG_PL310_ERRATA_588369 is not set
+-# CONFIG_PL310_ERRATA_727915 is not set
+-CONFIG_ARM_ERRATA_743622=y
+-# CONFIG_ARM_ERRATA_753970 is not set
+-CONFIG_ARM_ERRATA_754322=y
+-CONFIG_ARM_GIC=y
+-
+-#
+-# Bus support
+-#
+-# CONFIG_PCI_SYSCALL is not set
+-# CONFIG_ARCH_SUPPORTS_MSI is not set
+-# CONFIG_PCCARD is not set
+-# CONFIG_PL310_ERRATA_769419 is not set
+-
+-#
+-# Kernel Features
+-#
+-CONFIG_TICK_ONESHOT=y
+-CONFIG_NO_HZ=y
+-CONFIG_HIGH_RES_TIMERS=y
+-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+-# CONFIG_SMP is not set
+-# CONFIG_VMSPLIT_3G is not set
+-CONFIG_VMSPLIT_2G=y
+-# CONFIG_VMSPLIT_1G is not set
+-CONFIG_PAGE_OFFSET=0x80000000
+-# CONFIG_PREEMPT_NONE is not set
+-# CONFIG_PREEMPT_VOLUNTARY is not set
+-CONFIG_PREEMPT=y
+-CONFIG_HZ=100
+-# CONFIG_THUMB2_KERNEL is not set
+-CONFIG_AEABI=y
+-# CONFIG_OABI_COMPAT is not set
+-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+-CONFIG_HAVE_ARCH_PFN_VALID=y
+-CONFIG_HIGHMEM=y
+-# CONFIG_HIGHPTE is not set
+-CONFIG_HW_PERF_EVENTS=y
+-CONFIG_SELECT_MEMORY_MODEL=y
+-CONFIG_FLATMEM_MANUAL=y
+-CONFIG_FLATMEM=y
+-CONFIG_FLAT_NODE_MEM_MAP=y
+-CONFIG_HAVE_MEMBLOCK=y
+-CONFIG_PAGEFLAGS_EXTENDED=y
+-CONFIG_SPLIT_PTLOCK_CPUS=4
+-# CONFIG_COMPACTION is not set
+-# CONFIG_PHYS_ADDR_T_64BIT is not set
+-CONFIG_ZONE_DMA_FLAG=1
+-CONFIG_BOUNCE=y
+-CONFIG_VIRT_TO_BUS=y
+-# CONFIG_KSM is not set
+-CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+-CONFIG_NEED_PER_CPU_KM=y
+-# CONFIG_CLEANCACHE is not set
+-CONFIG_ALIGNMENT_TRAP=y
+-# CONFIG_UACCESS_WITH_MEMCPY is not set
+-# CONFIG_SECCOMP is not set
+-# CONFIG_CC_STACKPROTECTOR is not set
+-# CONFIG_DEPRECATED_PARAM_STRUCT is not set
+-
+-#
+-# Boot options
+-#
+-# CONFIG_USE_OF is not set
+-CONFIG_ZBOOT_ROM_TEXT=0x0
+-CONFIG_ZBOOT_ROM_BSS=0x0
+-CONFIG_CMDLINE="noinitrd console=ttymxc0,115200 root=/dev/mtdblock2 rw rootfstype=jffs2 ip=off"
+-CONFIG_CMDLINE_FROM_BOOTLOADER=y
+-# CONFIG_CMDLINE_EXTEND is not set
+-# CONFIG_CMDLINE_FORCE is not set
+-# CONFIG_XIP_KERNEL is not set
+-# CONFIG_KEXEC is not set
+-# CONFIG_CRASH_DUMP is not set
+-CONFIG_AUTO_ZRELADDR=y
+-
+-#
+-# CPU Power Management
+-#
+-
+-#
+-# CPU Frequency scaling
+-#
+-CONFIG_CPU_FREQ=y
+-CONFIG_CPU_FREQ_TABLE=y
+-CONFIG_CPU_FREQ_STAT=y
+-# CONFIG_CPU_FREQ_STAT_DETAILS is not set
+-# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+-# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+-CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
+-# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+-# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+-# CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE is not set
+-# CONFIG_CPU_FREQ_GOV_PERFORMANCE is not set
+-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+-CONFIG_CPU_FREQ_GOV_USERSPACE=y
+-# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
+-# CONFIG_CPU_FREQ_GOV_INTERACTIVE is not set
+-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+-CONFIG_CPU_FREQ_IMX=y
+-# CONFIG_CPU_IDLE is not set
+-
+-#
+-# Floating point emulation
+-#
+-
+-#
+-# At least one emulation must be selected
+-#
+-CONFIG_VFP=y
+-CONFIG_VFPv3=y
+-CONFIG_NEON=y
+-
+-#
+-# Userspace binary formats
+-#
+-CONFIG_BINFMT_ELF=y
+-# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+-CONFIG_HAVE_AOUT=y
+-# CONFIG_BINFMT_AOUT is not set
+-# CONFIG_BINFMT_MISC is not set
+-
+-#
+-# Power management options
+-#
+-CONFIG_SUSPEND=y
+-# CONFIG_PM_TEST_SUSPEND is not set
+-CONFIG_SUSPEND_DEVICE_TIME_DEBUG=y
+-CONFIG_SUSPEND_FREEZER=y
+-CONFIG_PM_SLEEP=y
+-CONFIG_PM_RUNTIME=y
+-CONFIG_PM=y
+-CONFIG_PM_DEBUG=y
+-# CONFIG_PM_ADVANCED_DEBUG is not set
+-CONFIG_CAN_PM_TRACE=y
+-CONFIG_APM_EMULATION=y
+-CONFIG_PM_RUNTIME_CLK=y
+-CONFIG_ARCH_SUSPEND_POSSIBLE=y
+-CONFIG_NET=y
+-
+-#
+-# Networking options
+-#
+-CONFIG_PACKET=y
+-CONFIG_UNIX=y
+-CONFIG_XFRM=y
+-# CONFIG_XFRM_USER is not set
+-# CONFIG_XFRM_SUB_POLICY is not set
+-# CONFIG_XFRM_MIGRATE is not set
+-# CONFIG_XFRM_STATISTICS is not set
+-# CONFIG_NET_KEY is not set
+-CONFIG_INET=y
+-CONFIG_IP_MULTICAST=y
+-# CONFIG_IP_ADVANCED_ROUTER is not set
+-CONFIG_IP_PNP=y
+-CONFIG_IP_PNP_DHCP=y
+-CONFIG_IP_PNP_BOOTP=y
+-# CONFIG_IP_PNP_RARP is not set
+-# CONFIG_NET_IPIP is not set
+-# CONFIG_NET_IPGRE_DEMUX is not set
+-# CONFIG_IP_MROUTE is not set
+-# CONFIG_ARPD is not set
+-# CONFIG_SYN_COOKIES is not set
+-# CONFIG_INET_AH is not set
+-# CONFIG_INET_ESP is not set
+-# CONFIG_INET_IPCOMP is not set
+-# CONFIG_INET_XFRM_TUNNEL is not set
+-# CONFIG_INET_TUNNEL is not set
+-CONFIG_INET_XFRM_MODE_TRANSPORT=y
+-CONFIG_INET_XFRM_MODE_TUNNEL=y
+-CONFIG_INET_XFRM_MODE_BEET=y
+-# CONFIG_INET_LRO is not set
+-CONFIG_INET_DIAG=y
+-CONFIG_INET_TCP_DIAG=y
+-# CONFIG_TCP_CONG_ADVANCED is not set
+-CONFIG_TCP_CONG_CUBIC=y
+-CONFIG_DEFAULT_TCP_CONG="cubic"
+-# CONFIG_TCP_MD5SIG is not set
+-# CONFIG_IPV6 is not set
+-# CONFIG_NETWORK_SECMARK is not set
+-# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
+-# CONFIG_NETFILTER is not set
+-# CONFIG_IP_DCCP is not set
+-# CONFIG_IP_SCTP is not set
+-# CONFIG_RDS is not set
+-# CONFIG_TIPC is not set
+-# CONFIG_ATM is not set
+-# CONFIG_L2TP is not set
+-# CONFIG_BRIDGE is not set
+-# CONFIG_NET_DSA is not set
+-# CONFIG_VLAN_8021Q is not set
+-# CONFIG_DECNET is not set
+-# CONFIG_LLC2 is not set
+-# CONFIG_IPX is not set
+-# CONFIG_ATALK is not set
+-# CONFIG_X25 is not set
+-# CONFIG_LAPB is not set
+-# CONFIG_ECONET is not set
+-# CONFIG_WAN_ROUTER is not set
+-# CONFIG_PHONET is not set
+-# CONFIG_IEEE802154 is not set
+-# CONFIG_NET_SCHED is not set
+-# CONFIG_DCB is not set
+-# CONFIG_BATMAN_ADV is not set
+-
+-#
+-# Network testing
+-#
+-# CONFIG_NET_PKTGEN is not set
+-# CONFIG_HAMRADIO is not set
+-CONFIG_CAN=y
+-CONFIG_CAN_RAW=y
+-CONFIG_CAN_BCM=y
+-
+-#
+-# CAN Device Drivers
+-#
+-CONFIG_CAN_VCAN=y
+-# CONFIG_CAN_SLCAN is not set
+-# CONFIG_CAN_DEV is not set
+-CONFIG_HAVE_CAN_FLEXCAN=y
+-CONFIG_CAN_DEBUG_DEVICES=y
+-# CONFIG_IRDA is not set
+-CONFIG_BT=y
+-CONFIG_BT_L2CAP=y
+-CONFIG_BT_SCO=y
+-CONFIG_BT_RFCOMM=y
+-CONFIG_BT_RFCOMM_TTY=y
+-CONFIG_BT_BNEP=y
+-CONFIG_BT_BNEP_MC_FILTER=y
+-CONFIG_BT_BNEP_PROTO_FILTER=y
+-CONFIG_BT_HIDP=y
+-
+-#
+-# Bluetooth device drivers
+-#
+-CONFIG_BT_HCIBTUSB=y
+-# CONFIG_BT_HCIBTSDIO is not set
+-# CONFIG_BT_HCIUART is not set
+-# CONFIG_BT_HCIBCM203X is not set
+-# CONFIG_BT_HCIBPA10X is not set
+-# CONFIG_BT_HCIBFUSB is not set
+-CONFIG_BT_HCIVHCI=y
+-# CONFIG_BT_MRVL is not set
+-# CONFIG_BT_ATH3K is not set
+-# CONFIG_AF_RXRPC is not set
+-CONFIG_WIRELESS=y
+-# CONFIG_CFG80211 is not set
+-# CONFIG_LIB80211 is not set
+-
+-#
+-# CFG80211 needs to be enabled for MAC80211
+-#
+-# CONFIG_WIMAX is not set
+-CONFIG_RFKILL=y
+-CONFIG_RFKILL_INPUT=y
+-# CONFIG_RFKILL_REGULATOR is not set
+-# CONFIG_RFKILL_GPIO is not set
+-# CONFIG_NET_9P is not set
+-# CONFIG_CAIF is not set
+-# CONFIG_CEPH_LIB is not set
+-
+-#
+-# Device Drivers
+-#
+-
+-#
+-# Generic Driver Options
+-#
+-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+-# CONFIG_DEVTMPFS is not set
+-CONFIG_STANDALONE=y
+-CONFIG_PREVENT_FIRMWARE_BUILD=y
+-CONFIG_FW_LOADER=y
+-CONFIG_FIRMWARE_IN_KERNEL=y
+-CONFIG_EXTRA_FIRMWARE=""
+-# CONFIG_SYS_HYPERVISOR is not set
+-CONFIG_CONNECTOR=y
+-CONFIG_PROC_EVENTS=y
+-CONFIG_MTD=y
+-# CONFIG_MTD_DEBUG is not set
+-# CONFIG_MTD_TESTS is not set
+-# CONFIG_MTD_REDBOOT_PARTS is not set
+-CONFIG_MTD_CMDLINE_PARTS=y
+-# CONFIG_MTD_AFS_PARTS is not set
+-# CONFIG_MTD_AR7_PARTS is not set
+-
+-#
+-# User Modules And Translation Layers
+-#
+-CONFIG_MTD_CHAR=y
+-CONFIG_MTD_BLKDEVS=y
+-CONFIG_MTD_BLOCK=y
+-# CONFIG_FTL is not set
+-# CONFIG_NFTL is not set
+-# CONFIG_INFTL is not set
+-# CONFIG_RFD_FTL is not set
+-# CONFIG_SSFDC is not set
+-# CONFIG_SM_FTL is not set
+-# CONFIG_MTD_OOPS is not set
+-# CONFIG_MTD_SWAP is not set
+-
+-#
+-# RAM/ROM/Flash chip drivers
+-#
+-# CONFIG_MTD_CFI is not set
+-# CONFIG_MTD_JEDECPROBE is not set
+-CONFIG_MTD_MAP_BANK_WIDTH_1=y
+-CONFIG_MTD_MAP_BANK_WIDTH_2=y
+-CONFIG_MTD_MAP_BANK_WIDTH_4=y
+-# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+-# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+-# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+-CONFIG_MTD_CFI_I1=y
+-CONFIG_MTD_CFI_I2=y
+-# CONFIG_MTD_CFI_I4 is not set
+-# CONFIG_MTD_CFI_I8 is not set
+-# CONFIG_MTD_RAM is not set
+-# CONFIG_MTD_ROM is not set
+-# CONFIG_MTD_ABSENT is not set
+-
+-#
+-# Mapping drivers for chip access
+-#
+-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+-# CONFIG_MTD_PLATRAM is not set
+-
+-#
+-# Self-contained MTD device drivers
+-#
+-# CONFIG_MTD_DATAFLASH is not set
+-CONFIG_MTD_M25P80=y
+-CONFIG_M25PXX_USE_FAST_READ=y
+-# CONFIG_MTD_SST25L is not set
+-# CONFIG_MTD_SLRAM is not set
+-# CONFIG_MTD_PHRAM is not set
+-# CONFIG_MTD_MTDRAM is not set
+-# CONFIG_MTD_BLOCK2MTD is not set
+-
+-#
+-# Disk-On-Chip Device Drivers
+-#
+-# CONFIG_MTD_DOC2000 is not set
+-# CONFIG_MTD_DOC2001 is not set
+-# CONFIG_MTD_DOC2001PLUS is not set
+-CONFIG_MTD_NAND_ECC=y
+-# CONFIG_MTD_NAND_ECC_SMC is not set
+-CONFIG_MTD_NAND=y
+-# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+-# CONFIG_MTD_NAND_ECC_BCH is not set
+-# CONFIG_MTD_SM_COMMON is not set
+-# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+-# CONFIG_MTD_NAND_GPIO is not set
+-CONFIG_MTD_NAND_IDS=y
+-# CONFIG_MTD_NAND_DISKONCHIP is not set
+-# CONFIG_MTD_NAND_NANDSIM is not set
+-# CONFIG_MTD_NAND_GPMI_NAND is not set
+-# CONFIG_MTD_NAND_PLATFORM is not set
+-# CONFIG_MTD_ALAUDA is not set
+-# CONFIG_MTD_ONENAND is not set
+-
+-#
+-# LPDDR flash memory drivers
+-#
+-# CONFIG_MTD_LPDDR is not set
+-CONFIG_MTD_UBI=y
+-CONFIG_MTD_UBI_WL_THRESHOLD=4096
+-CONFIG_MTD_UBI_BEB_RESERVE=1
+-# CONFIG_MTD_UBI_GLUEBI is not set
+-# CONFIG_MTD_UBI_DEBUG is not set
+-# CONFIG_PARPORT is not set
+-CONFIG_BLK_DEV=y
+-# CONFIG_BLK_DEV_COW_COMMON is not set
+-CONFIG_BLK_DEV_LOOP=y
+-# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+-# CONFIG_BLK_DEV_DRBD is not set
+-# CONFIG_BLK_DEV_NBD is not set
+-# CONFIG_BLK_DEV_UB is not set
+-# CONFIG_BLK_DEV_RAM is not set
+-# CONFIG_CDROM_PKTCDVD is not set
+-# CONFIG_ATA_OVER_ETH is not set
+-# CONFIG_MG_DISK is not set
+-# CONFIG_BLK_DEV_RBD is not set
+-# CONFIG_SENSORS_LIS3LV02D is not set
+-# CONFIG_MISC_DEVICES is not set
+-CONFIG_HAVE_IDE=y
+-# CONFIG_IDE is not set
+-
+-#
+-# SCSI device support
+-#
+-CONFIG_SCSI_MOD=y
+-# CONFIG_RAID_ATTRS is not set
+-CONFIG_SCSI=y
+-CONFIG_SCSI_DMA=y
+-# CONFIG_SCSI_TGT is not set
+-# CONFIG_SCSI_NETLINK is not set
+-CONFIG_SCSI_PROC_FS=y
+-
+-#
+-# SCSI support type (disk, tape, CD-ROM)
+-#
+-CONFIG_BLK_DEV_SD=y
+-# CONFIG_CHR_DEV_ST is not set
+-# CONFIG_CHR_DEV_OSST is not set
+-# CONFIG_BLK_DEV_SR is not set
+-# CONFIG_CHR_DEV_SG is not set
+-# CONFIG_CHR_DEV_SCH is not set
+-CONFIG_SCSI_MULTI_LUN=y
+-# CONFIG_SCSI_CONSTANTS is not set
+-# CONFIG_SCSI_LOGGING is not set
+-# CONFIG_SCSI_SCAN_ASYNC is not set
+-CONFIG_SCSI_WAIT_SCAN=m
+-
+-#
+-# SCSI Transports
+-#
+-# CONFIG_SCSI_SPI_ATTRS is not set
+-# CONFIG_SCSI_FC_ATTRS is not set
+-# CONFIG_SCSI_ISCSI_ATTRS is not set
+-# CONFIG_SCSI_SAS_ATTRS is not set
+-# CONFIG_SCSI_SAS_LIBSAS is not set
+-# CONFIG_SCSI_SRP_ATTRS is not set
+-CONFIG_SCSI_LOWLEVEL=y
+-# CONFIG_ISCSI_TCP is not set
+-# CONFIG_ISCSI_BOOT_SYSFS is not set
+-# CONFIG_LIBFC is not set
+-# CONFIG_LIBFCOE is not set
+-# CONFIG_SCSI_DEBUG is not set
+-# CONFIG_SCSI_DH is not set
+-# CONFIG_SCSI_OSD_INITIATOR is not set
+-CONFIG_ATA=m
+-# CONFIG_ATA_NONSTANDARD is not set
+-CONFIG_ATA_VERBOSE_ERROR=y
+-# CONFIG_SATA_PMP is not set
+-
+-#
+-# Controllers with non-SFF native interface
+-#
+-CONFIG_SATA_AHCI_PLATFORM=m
+-CONFIG_ATA_SFF=y
+-
+-#
+-# SFF controllers with custom DMA interface
+-#
+-CONFIG_ATA_BMDMA=y
+-
+-#
+-# SATA SFF controllers with BMDMA
+-#
+-# CONFIG_SATA_MV is not set
+-
+-#
+-# PATA SFF controllers with BMDMA
+-#
+-# CONFIG_PATA_ARASAN_CF is not set
+-
+-#
+-# PIO-only SFF controllers
+-#
+-# CONFIG_PATA_PLATFORM is not set
+-
+-#
+-# Generic fallback / legacy drivers
+-#
+-# CONFIG_MD is not set
+-# CONFIG_TARGET_CORE is not set
+-CONFIG_NETDEVICES=y
+-# CONFIG_DUMMY is not set
+-# CONFIG_BONDING is not set
+-# CONFIG_MACVLAN is not set
+-# CONFIG_EQUALIZER is not set
+-# CONFIG_TUN is not set
+-# CONFIG_VETH is not set
+-CONFIG_MII=y
+-CONFIG_PHYLIB=y
+-
+-#
+-# MII PHY device drivers
+-#
+-# CONFIG_MARVELL_PHY is not set
+-# CONFIG_DAVICOM_PHY is not set
+-# CONFIG_QSEMI_PHY is not set
+-# CONFIG_LXT_PHY is not set
+-# CONFIG_CICADA_PHY is not set
+-# CONFIG_VITESSE_PHY is not set
+-# CONFIG_SMSC_PHY is not set
+-# CONFIG_BROADCOM_PHY is not set
+-# CONFIG_ICPLUS_PHY is not set
+-# CONFIG_REALTEK_PHY is not set
+-# CONFIG_NATIONAL_PHY is not set
+-# CONFIG_STE10XP is not set
+-# CONFIG_LSI_ET1011C_PHY is not set
+-# CONFIG_MICREL_PHY is not set
+-# CONFIG_FIXED_PHY is not set
+-# CONFIG_MDIO_BITBANG is not set
+-CONFIG_NET_ETHERNET=y
+-# CONFIG_AX88796 is not set
+-# CONFIG_SMC91X is not set
+-# CONFIG_DM9000 is not set
+-# CONFIG_ENC28J60 is not set
+-# CONFIG_ETHOC is not set
+-# CONFIG_SMC911X is not set
+-CONFIG_SMSC911X=y
+-# CONFIG_SMSC911X_ARCH_HOOKS is not set
+-# CONFIG_DNET is not set
+-# CONFIG_IBM_NEW_EMAC_ZMII is not set
+-# CONFIG_IBM_NEW_EMAC_RGMII is not set
+-# CONFIG_IBM_NEW_EMAC_TAH is not set
+-# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+-# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+-# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+-# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+-# CONFIG_B44 is not set
+-# CONFIG_KS8842 is not set
+-# CONFIG_KS8851 is not set
+-# CONFIG_KS8851_MLL is not set
+-CONFIG_FEC=y
+-# CONFIG_FEC_NAPI is not set
+-# CONFIG_FEC_1588 is not set
+-# CONFIG_FTMAC100 is not set
+-# CONFIG_NETDEV_1000 is not set
+-# CONFIG_NETDEV_10000 is not set
+-CONFIG_WLAN=y
+-# CONFIG_USB_ZD1201 is not set
+-# CONFIG_HOSTAP is not set
+-
+-#
+-# Enable WiMAX (Networking options) to see the WiMAX drivers
+-#
+-
+-#
+-# USB Network Adapters
+-#
+-# CONFIG_USB_CATC is not set
+-# CONFIG_USB_KAWETH is not set
+-# CONFIG_USB_PEGASUS is not set
+-# CONFIG_USB_RTL8150 is not set
+-# CONFIG_USB_USBNET is not set
+-# CONFIG_USB_HSO is not set
+-# CONFIG_USB_IPHETH is not set
+-# CONFIG_WAN is not set
+-
+-#
+-# CAIF transport drivers
+-#
+-# CONFIG_PPP is not set
+-# CONFIG_SLIP is not set
+-# CONFIG_NETCONSOLE is not set
+-# CONFIG_NETPOLL is not set
+-# CONFIG_NET_POLL_CONTROLLER is not set
+-# CONFIG_ISDN is not set
+-# CONFIG_PHONE is not set
+-
+-#
+-# Input device support
+-#
+-CONFIG_INPUT=y
+-# CONFIG_INPUT_FF_MEMLESS is not set
+-CONFIG_INPUT_POLLDEV=y
+-# CONFIG_INPUT_SPARSEKMAP is not set
+-
+-#
+-# Userland interfaces
+-#
+-CONFIG_INPUT_MOUSEDEV=y
+-CONFIG_INPUT_MOUSEDEV_PSAUX=y
+-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+-# CONFIG_INPUT_JOYDEV is not set
+-CONFIG_INPUT_EVDEV=y
+-# CONFIG_INPUT_EVBUG is not set
+-# CONFIG_INPUT_APMPOWER is not set
+-
+-#
+-# Input Device Drivers
+-#
+-# CONFIG_INPUT_KEYBOARD is not set
+-# CONFIG_INPUT_MOUSE is not set
+-# CONFIG_INPUT_JOYSTICK is not set
+-# CONFIG_INPUT_TABLET is not set
+-CONFIG_INPUT_TOUCHSCREEN=y
+-# CONFIG_TOUCHSCREEN_ADS7846 is not set
+-# CONFIG_TOUCHSCREEN_AD7877 is not set
+-# CONFIG_TOUCHSCREEN_AD7879 is not set
+-# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
+-# CONFIG_TOUCHSCREEN_BU21013 is not set
+-# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set
+-# CONFIG_TOUCHSCREEN_DYNAPRO is not set
+-# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
+-# CONFIG_TOUCHSCREEN_EETI is not set
+-CONFIG_TOUCHSCREEN_EGALAX=y
+-# CONFIG_TOUCHSCREEN_ELAN is not set
+-# CONFIG_TOUCHSCREEN_FUJITSU is not set
+-# CONFIG_TOUCHSCREEN_GUNZE is not set
+-# CONFIG_TOUCHSCREEN_ELO is not set
+-# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+-# CONFIG_TOUCHSCREEN_MAX11801 is not set
+-# CONFIG_TOUCHSCREEN_MCS5000 is not set
+-# CONFIG_TOUCHSCREEN_MTOUCH is not set
+-# CONFIG_TOUCHSCREEN_INEXIO is not set
+-# CONFIG_TOUCHSCREEN_MK712 is not set
+-# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+-# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+-# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+-# CONFIG_TOUCHSCREEN_WM97XX is not set
+-# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+-# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+-# CONFIG_TOUCHSCREEN_TSC2005 is not set
+-# CONFIG_TOUCHSCREEN_TSC2007 is not set
+-# CONFIG_TOUCHSCREEN_W90X900 is not set
+-# CONFIG_TOUCHSCREEN_ST1232 is not set
+-# CONFIG_TOUCHSCREEN_P1003 is not set
+-# CONFIG_TOUCHSCREEN_TPS6507X is not set
+-CONFIG_INPUT_MISC=y
+-# CONFIG_INPUT_AD714X is not set
+-# CONFIG_INPUT_ATI_REMOTE is not set
+-# CONFIG_INPUT_ATI_REMOTE2 is not set
+-# CONFIG_INPUT_KEYSPAN_REMOTE is not set
+-# CONFIG_INPUT_POWERMATE is not set
+-# CONFIG_INPUT_YEALINK is not set
+-# CONFIG_INPUT_CM109 is not set
+-CONFIG_INPUT_UINPUT=y
+-# CONFIG_INPUT_PCF8574 is not set
+-# CONFIG_INPUT_PWM_BEEPER is not set
+-# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
+-# CONFIG_INPUT_ADXL34X is not set
+-# CONFIG_INPUT_CMA3000 is not set
+-# CONFIG_INPUT_ISL29023 is not set
+-
+-#
+-# Hardware I/O ports
+-#
+-# CONFIG_SERIO is not set
+-# CONFIG_GAMEPORT is not set
+-
+-#
+-# Character devices
+-#
+-CONFIG_VT=y
+-CONFIG_CONSOLE_TRANSLATIONS=y
+-CONFIG_VT_CONSOLE=y
+-CONFIG_HW_CONSOLE=y
+-# CONFIG_VT_HW_CONSOLE_BINDING is not set
+-CONFIG_UNIX98_PTYS=y
+-# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+-CONFIG_LEGACY_PTYS=y
+-CONFIG_LEGACY_PTY_COUNT=256
+-# CONFIG_SERIAL_NONSTANDARD is not set
+-# CONFIG_N_GSM is not set
+-# CONFIG_TRACE_SINK is not set
+-CONFIG_DEVKMEM=y
+-
+-#
+-# Serial drivers
+-#
+-# CONFIG_SERIAL_8250 is not set
+-
+-#
+-# Non-8250 serial port support
+-#
+-# CONFIG_SERIAL_MAX3100 is not set
+-# CONFIG_SERIAL_MAX3107 is not set
+-CONFIG_SERIAL_IMX=y
+-CONFIG_SERIAL_IMX_CONSOLE=y
+-CONFIG_SERIAL_CORE=y
+-CONFIG_SERIAL_CORE_CONSOLE=y
+-# CONFIG_SERIAL_TIMBERDALE is not set
+-# CONFIG_SERIAL_ALTERA_JTAGUART is not set
+-# CONFIG_SERIAL_ALTERA_UART is not set
+-# CONFIG_SERIAL_IFX6X60 is not set
+-# CONFIG_SERIAL_XILINX_PS_UART is not set
+-# CONFIG_TTY_PRINTK is not set
+-CONFIG_FSL_OTP=y
+-# CONFIG_HVC_DCC is not set
+-# CONFIG_IPMI_HANDLER is not set
+-CONFIG_HW_RANDOM=y
+-# CONFIG_HW_RANDOM_TIMERIOMEM is not set
+-# CONFIG_HW_RANDOM_FSL_RNGC is not set
+-# CONFIG_R3964 is not set
+-# CONFIG_RAW_DRIVER is not set
+-# CONFIG_TCG_TPM is not set
+-# CONFIG_RAMOOPS is not set
+-CONFIG_MXS_VIIM=y
+-CONFIG_I2C=y
+-CONFIG_I2C_BOARDINFO=y
+-CONFIG_I2C_COMPAT=y
+-CONFIG_I2C_CHARDEV=y
+-# CONFIG_I2C_MUX is not set
+-CONFIG_I2C_HELPER_AUTO=y
+-
+-#
+-# I2C Hardware Bus support
+-#
+-
+-#
+-# I2C system bus drivers (mostly embedded / system-on-chip)
+-#
+-# CONFIG_I2C_DESIGNWARE is not set
+-# CONFIG_I2C_GPIO is not set
+-CONFIG_I2C_IMX=y
+-# CONFIG_I2C_OCORES is not set
+-# CONFIG_I2C_PCA_PLATFORM is not set
+-# CONFIG_I2C_PXA_PCI is not set
+-# CONFIG_I2C_SIMTEC is not set
+-# CONFIG_I2C_XILINX is not set
+-
+-#
+-# External I2C/SMBus adapter drivers
+-#
+-# CONFIG_I2C_DIOLAN_U2C is not set
+-# CONFIG_I2C_PARPORT_LIGHT is not set
+-# CONFIG_I2C_TAOS_EVM is not set
+-# CONFIG_I2C_TINY_USB is not set
+-
+-#
+-# Other I2C/SMBus bus drivers
+-#
+-# CONFIG_I2C_STUB is not set
+-# CONFIG_I2C_DEBUG_CORE is not set
+-# CONFIG_I2C_DEBUG_ALGO is not set
+-# CONFIG_I2C_DEBUG_BUS is not set
+-CONFIG_SPI=y
+-CONFIG_SPI_MASTER=y
+-
+-#
+-# SPI Master Controller Drivers
+-#
+-# CONFIG_SPI_ALTERA is not set
+-CONFIG_SPI_BITBANG=y
+-# CONFIG_SPI_GPIO is not set
+-CONFIG_SPI_IMX_VER_2_3=y
+-CONFIG_SPI_IMX=y
+-# CONFIG_SPI_OC_TINY is not set
+-# CONFIG_SPI_PXA2XX_PCI is not set
+-# CONFIG_SPI_XILINX is not set
+-# CONFIG_SPI_DESIGNWARE is not set
+-
+-#
+-# SPI Protocol Masters
+-#
+-# CONFIG_SPI_SPIDEV is not set
+-# CONFIG_SPI_TLE62X0 is not set
+-
+-#
+-# PPS support
+-#
+-# CONFIG_PPS is not set
+-
+-#
+-# PPS generators support
+-#
+-
+-#
+-# PTP clock support
+-#
+-
+-#
+-# Enable Device Drivers -> PPS to see the PTP clock options.
+-#
+-CONFIG_ARCH_REQUIRE_GPIOLIB=y
+-CONFIG_GPIOLIB=y
+-# CONFIG_GPIO_SYSFS is not set
+-
+-#
+-# Memory mapped GPIO drivers:
+-#
+-# CONFIG_GPIO_BASIC_MMIO is not set
+-# CONFIG_GPIO_IT8761E is not set
+-
+-#
+-# I2C GPIO expanders:
+-#
+-# CONFIG_GPIO_MAX7300 is not set
+-# CONFIG_GPIO_MAX732X is not set
+-# CONFIG_GPIO_PCA953X_IRQ is not set
+-# CONFIG_GPIO_PCF857X is not set
+-# CONFIG_GPIO_SX150X is not set
+-# CONFIG_GPIO_ADP5588 is not set
+-
+-#
+-# PCI GPIO expanders:
+-#
+-
+-#
+-# SPI GPIO expanders:
+-#
+-# CONFIG_GPIO_MAX7301 is not set
+-# CONFIG_GPIO_MCP23S08 is not set
+-# CONFIG_GPIO_MC33880 is not set
+-# CONFIG_GPIO_74X164 is not set
+-
+-#
+-# AC97 GPIO expanders:
+-#
+-
+-#
+-# MODULbus GPIO expanders:
+-#
+-# CONFIG_W1 is not set
+-CONFIG_POWER_SUPPLY=y
+-# CONFIG_POWER_SUPPLY_DEBUG is not set
+-# CONFIG_PDA_POWER is not set
+-# CONFIG_APM_POWER is not set
+-# CONFIG_TEST_POWER is not set
+-# CONFIG_BATTERY_DS2780 is not set
+-# CONFIG_BATTERY_DS2782 is not set
+-# CONFIG_BATTERY_BQ20Z75 is not set
+-# CONFIG_BATTERY_BQ27x00 is not set
+-# CONFIG_BATTERY_MAX17040 is not set
+-# CONFIG_BATTERY_MAX17042 is not set
+-# CONFIG_CHARGER_ISP1704 is not set
+-# CONFIG_CHARGER_MAX8903 is not set
+-# CONFIG_CHARGER_GPIO is not set
+-# CONFIG_HWMON is not set
+-CONFIG_THERMAL=y
+-CONFIG_WATCHDOG=y
+-CONFIG_WATCHDOG_NOWAYOUT=y
+-
+-#
+-# Watchdog Device Drivers
+-#
+-# CONFIG_SOFT_WATCHDOG is not set
+-# CONFIG_MAX63XX_WATCHDOG is not set
+-CONFIG_IMX2_WDT=y
+-
+-#
+-# USB-based Watchdog Cards
+-#
+-# CONFIG_USBPCWATCHDOG is not set
+-CONFIG_SSB_POSSIBLE=y
+-
+-#
+-# Sonics Silicon Backplane
+-#
+-# CONFIG_SSB is not set
+-CONFIG_BCMA_POSSIBLE=y
+-
+-#
+-# Broadcom specific AMBA
+-#
+-# CONFIG_BCMA is not set
+-CONFIG_MFD_SUPPORT=y
+-CONFIG_MFD_CORE=y
+-# CONFIG_MFD_88PM860X is not set
+-# CONFIG_MFD_SM501 is not set
+-# CONFIG_MFD_ASIC3 is not set
+-# CONFIG_HTC_EGPIO is not set
+-# CONFIG_HTC_PASIC3 is not set
+-# CONFIG_HTC_I2CPLD is not set
+-# CONFIG_UCB1400_CORE is not set
+-# CONFIG_TPS6105X is not set
+-# CONFIG_TPS65010 is not set
+-# CONFIG_TPS6507X is not set
+-# CONFIG_MFD_TPS6586X is not set
+-# CONFIG_TWL4030_CORE is not set
+-# CONFIG_MFD_STMPE is not set
+-# CONFIG_MFD_TC3589X is not set
+-# CONFIG_MFD_TMIO is not set
+-# CONFIG_MFD_T7L66XB is not set
+-# CONFIG_MFD_TC6387XB is not set
+-# CONFIG_MFD_TC6393XB is not set
+-# CONFIG_PMIC_DA903X is not set
+-# CONFIG_PMIC_ADP5520 is not set
+-# CONFIG_MFD_MAX8925 is not set
+-# CONFIG_MFD_MAX8997 is not set
+-# CONFIG_MFD_MAX8998 is not set
+-# CONFIG_MFD_WM8400 is not set
+-# CONFIG_MFD_WM831X_I2C is not set
+-# CONFIG_MFD_WM831X_SPI is not set
+-# CONFIG_MFD_WM8350_I2C is not set
+-# CONFIG_MFD_WM8994 is not set
+-# CONFIG_MFD_PCF50633 is not set
+-# CONFIG_PMIC_DIALOG is not set
+-# CONFIG_MFD_MC_PMIC is not set
+-# CONFIG_MFD_MC34708 is not set
+-CONFIG_MFD_PFUZE=y
+-# CONFIG_MFD_MC13XXX is not set
+-# CONFIG_ABX500_CORE is not set
+-# CONFIG_EZX_PCAP is not set
+-# CONFIG_MFD_WL1273_CORE is not set
+-# CONFIG_MFD_TPS65910 is not set
+-CONFIG_MFD_MAX17135=y
+-CONFIG_MFD_MXC_HDMI=y
+-CONFIG_REGULATOR=y
+-# CONFIG_REGULATOR_DEBUG is not set
+-# CONFIG_REGULATOR_DUMMY is not set
+-CONFIG_REGULATOR_FIXED_VOLTAGE=y
+-# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
+-# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
+-# CONFIG_REGULATOR_BQ24022 is not set
+-# CONFIG_REGULATOR_MAX1586 is not set
+-# CONFIG_REGULATOR_MAX8649 is not set
+-# CONFIG_REGULATOR_MAX8660 is not set
+-# CONFIG_REGULATOR_MAX8952 is not set
+-# CONFIG_REGULATOR_LP3971 is not set
+-# CONFIG_REGULATOR_LP3972 is not set
+-# CONFIG_REGULATOR_MC34708 is not set
+-CONFIG_REGULATOR_PFUZE100=y
+-# CONFIG_REGULATOR_TPS65023 is not set
+-# CONFIG_REGULATOR_TPS6507X is not set
+-# CONFIG_REGULATOR_ISL6271A is not set
+-# CONFIG_REGULATOR_AD5398 is not set
+-CONFIG_REGULATOR_ANATOP=y
+-# CONFIG_REGULATOR_TPS6524X is not set
+-CONFIG_REGULATOR_MAX17135=y
+-CONFIG_MEDIA_SUPPORT=y
+-
+-#
+-# Multimedia core support
+-#
+-# CONFIG_MEDIA_CONTROLLER is not set
+-CONFIG_VIDEO_DEV=y
+-CONFIG_VIDEO_V4L2_COMMON=y
+-# CONFIG_DVB_CORE is not set
+-CONFIG_VIDEO_MEDIA=y
+-
+-#
+-# Multimedia drivers
+-#
+-# CONFIG_RC_CORE is not set
+-# CONFIG_MEDIA_ATTACH is not set
+-CONFIG_MEDIA_TUNER=y
+-# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
+-CONFIG_MEDIA_TUNER_SIMPLE=y
+-CONFIG_MEDIA_TUNER_TDA8290=y
+-CONFIG_MEDIA_TUNER_TDA827X=y
+-CONFIG_MEDIA_TUNER_TDA18271=y
+-CONFIG_MEDIA_TUNER_TDA9887=y
+-CONFIG_MEDIA_TUNER_TEA5761=y
+-CONFIG_MEDIA_TUNER_TEA5767=y
+-CONFIG_MEDIA_TUNER_MT20XX=y
+-CONFIG_MEDIA_TUNER_XC2028=y
+-CONFIG_MEDIA_TUNER_XC5000=y
+-CONFIG_MEDIA_TUNER_MC44S803=y
+-CONFIG_VIDEO_V4L2=y
+-CONFIG_VIDEOBUF_GEN=y
+-CONFIG_VIDEOBUF_DMA_CONTIG=y
+-CONFIG_VIDEO_CAPTURE_DRIVERS=y
+-# CONFIG_VIDEO_ADV_DEBUG is not set
+-# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+-# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
+-
+-#
+-# Encoders, decoders, sensors and other helper chips
+-#
+-
+-#
+-# Audio decoders, processors and mixers
+-#
+-# CONFIG_VIDEO_TVAUDIO is not set
+-# CONFIG_VIDEO_TDA7432 is not set
+-# CONFIG_VIDEO_TDA9840 is not set
+-# CONFIG_VIDEO_TEA6415C is not set
+-# CONFIG_VIDEO_TEA6420 is not set
+-# CONFIG_VIDEO_MSP3400 is not set
+-# CONFIG_VIDEO_CS5345 is not set
+-# CONFIG_VIDEO_CS53L32A is not set
+-# CONFIG_VIDEO_TLV320AIC23B is not set
+-# CONFIG_VIDEO_WM8775 is not set
+-# CONFIG_VIDEO_WM8739 is not set
+-# CONFIG_VIDEO_VP27SMPX is not set
+-
+-#
+-# RDS decoders
+-#
+-# CONFIG_VIDEO_SAA6588 is not set
+-
+-#
+-# Video decoders
+-#
+-# CONFIG_VIDEO_ADV7180 is not set
+-# CONFIG_VIDEO_BT819 is not set
+-# CONFIG_VIDEO_BT856 is not set
+-# CONFIG_VIDEO_BT866 is not set
+-# CONFIG_VIDEO_KS0127 is not set
+-# CONFIG_VIDEO_SAA7110 is not set
+-# CONFIG_VIDEO_SAA711X is not set
+-# CONFIG_VIDEO_SAA7191 is not set
+-# CONFIG_VIDEO_TVP514X is not set
+-# CONFIG_VIDEO_TVP5150 is not set
+-# CONFIG_VIDEO_TVP7002 is not set
+-# CONFIG_VIDEO_VPX3220 is not set
+-
+-#
+-# Video and audio decoders
+-#
+-# CONFIG_VIDEO_SAA717X is not set
+-# CONFIG_VIDEO_CX25840 is not set
+-
+-#
+-# MPEG video encoders
+-#
+-# CONFIG_VIDEO_CX2341X is not set
+-
+-#
+-# Video encoders
+-#
+-# CONFIG_VIDEO_SAA7127 is not set
+-# CONFIG_VIDEO_SAA7185 is not set
+-# CONFIG_VIDEO_ADV7170 is not set
+-# CONFIG_VIDEO_ADV7175 is not set
+-# CONFIG_VIDEO_ADV7343 is not set
+-# CONFIG_VIDEO_AK881X is not set
+-
+-#
+-# Camera sensor devices
+-#
+-# CONFIG_VIDEO_OV7670 is not set
+-# CONFIG_VIDEO_MT9V011 is not set
+-# CONFIG_VIDEO_TCM825X is not set
+-
+-#
+-# Video improvement chips
+-#
+-# CONFIG_VIDEO_UPD64031A is not set
+-# CONFIG_VIDEO_UPD64083 is not set
+-
+-#
+-# Miscelaneous helper chips
+-#
+-# CONFIG_VIDEO_THS7303 is not set
+-# CONFIG_VIDEO_M52790 is not set
+-# CONFIG_VIDEO_VIVI is not set
+-# CONFIG_VIDEO_MXC_CAMERA is not set
+-CONFIG_VIDEO_MXC_OUTPUT=y
+-CONFIG_VIDEO_MXC_IPU_OUTPUT=y
+-# CONFIG_VIDEO_MXC_IPUV1_WVGA_OUTPUT is not set
+-# CONFIG_VIDEO_MXC_PXP_V4L2 is not set
+-# CONFIG_VIDEO_MXC_OPL is not set
+-# CONFIG_VIDEO_CPIA2 is not set
+-# CONFIG_VIDEO_TIMBERDALE is not set
+-# CONFIG_VIDEO_SR030PC30 is not set
+-# CONFIG_VIDEO_NOON010PC30 is not set
+-# CONFIG_SOC_CAMERA is not set
+-# CONFIG_V4L_USB_DRIVERS is not set
+-# CONFIG_V4L_MEM2MEM_DRIVERS is not set
+-# CONFIG_RADIO_ADAPTERS is not set
+-
+-#
+-# Graphics support
+-#
+-# CONFIG_DRM is not set
+-# CONFIG_VGASTATE is not set
+-# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+-CONFIG_FB=y
+-# CONFIG_FIRMWARE_EDID is not set
+-# CONFIG_FB_DDC is not set
+-# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+-CONFIG_FB_CFB_FILLRECT=y
+-CONFIG_FB_CFB_COPYAREA=y
+-CONFIG_FB_CFB_IMAGEBLIT=y
+-# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+-# CONFIG_FB_SYS_FILLRECT is not set
+-# CONFIG_FB_SYS_COPYAREA is not set
+-# CONFIG_FB_SYS_IMAGEBLIT is not set
+-# CONFIG_FB_FOREIGN_ENDIAN is not set
+-# CONFIG_FB_SYS_FOPS is not set
+-# CONFIG_FB_WMT_GE_ROPS is not set
+-# CONFIG_FB_SVGALIB is not set
+-# CONFIG_FB_MACMODES is not set
+-# CONFIG_FB_BACKLIGHT is not set
+-CONFIG_FB_MODE_HELPERS=y
+-# CONFIG_FB_TILEBLITTING is not set
+-
+-#
+-# Frame buffer hardware drivers
+-#
+-# CONFIG_FB_UVESA is not set
+-# CONFIG_FB_S1D13XXX is not set
+-# CONFIG_FB_TMIO is not set
+-# CONFIG_FB_UDL is not set
+-# CONFIG_FB_VIRTUAL is not set
+-# CONFIG_FB_METRONOME is not set
+-# CONFIG_FB_BROADSHEET is not set
+-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+-
+-#
+-# Display device support
+-#
+-# CONFIG_DISPLAY_SUPPORT is not set
+-CONFIG_FB_MXC=y
+-CONFIG_FB_MXC_EDID=y
+-CONFIG_FB_MXC_SYNC_PANEL=y
+-# CONFIG_FB_MXC_EPSON_VGA_SYNC_PANEL is not set
+-CONFIG_FB_MXC_LDB=y
+-# CONFIG_FB_MXC_MIPI_DSI is not set
+-# CONFIG_FB_MXC_CLAA_WVGA_SYNC_PANEL is not set
+-# CONFIG_FB_MXC_SEIKO_WVGA_SYNC_PANEL is not set
+-# CONFIG_FB_MXC_SII902X is not set
+-# CONFIG_FB_MXC_CH7026 is not set
+-# CONFIG_FB_MXC_TVOUT_CH7024 is not set
+-# CONFIG_FB_MXC_ASYNC_PANEL is not set
+-# CONFIG_FB_MXC_EINK_PANEL is not set
+-# CONFIG_FB_MXC_SIPIX_PANEL is not set
+-# CONFIG_FB_MXC_ELCDIF_FB is not set
+-CONFIG_FB_MXC_HDMI=y
+-
+-#
+-# Console display driver support
+-#
+-CONFIG_DUMMY_CONSOLE=y
+-CONFIG_FRAMEBUFFER_CONSOLE=y
+-# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+-# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+-CONFIG_FONTS=y
+-# CONFIG_FONT_8x8 is not set
+-CONFIG_FONT_8x16=y
+-# CONFIG_FONT_6x11 is not set
+-# CONFIG_FONT_7x14 is not set
+-# CONFIG_FONT_PEARL_8x8 is not set
+-# CONFIG_FONT_ACORN_8x8 is not set
+-# CONFIG_FONT_MINI_4x6 is not set
+-# CONFIG_FONT_SUN8x16 is not set
+-# CONFIG_FONT_SUN12x22 is not set
+-# CONFIG_FONT_10x18 is not set
+-CONFIG_LOGO=y
+-CONFIG_LOGO_LINUX_MONO=y
+-CONFIG_LOGO_LINUX_VGA16=y
+-CONFIG_LOGO_LINUX_CLUT224=y
+-CONFIG_SOUND=y
+-# CONFIG_SOUND_OSS_CORE is not set
+-CONFIG_SND=y
+-CONFIG_SND_TIMER=y
+-CONFIG_SND_PCM=y
+-CONFIG_SND_JACK=y
+-# CONFIG_SND_SEQUENCER is not set
+-# CONFIG_SND_MIXER_OSS is not set
+-# CONFIG_SND_PCM_OSS is not set
+-# CONFIG_SND_HRTIMER is not set
+-# CONFIG_SND_DYNAMIC_MINORS is not set
+-CONFIG_SND_SUPPORT_OLD_API=y
+-CONFIG_SND_VERBOSE_PROCFS=y
+-# CONFIG_SND_VERBOSE_PRINTK is not set
+-# CONFIG_SND_DEBUG is not set
+-# CONFIG_SND_RAWMIDI_SEQ is not set
+-# CONFIG_SND_OPL3_LIB_SEQ is not set
+-# CONFIG_SND_OPL4_LIB_SEQ is not set
+-# CONFIG_SND_SBAWE_SEQ is not set
+-# CONFIG_SND_EMU10K1_SEQ is not set
+-CONFIG_SND_DRIVERS=y
+-# CONFIG_SND_DUMMY is not set
+-# CONFIG_SND_ALOOP is not set
+-# CONFIG_SND_MTPAV is not set
+-# CONFIG_SND_SERIAL_U16550 is not set
+-# CONFIG_SND_MPU401 is not set
+-CONFIG_SND_ARM=y
+-CONFIG_SND_SPI=y
+-CONFIG_SND_USB=y
+-# CONFIG_SND_USB_AUDIO is not set
+-# CONFIG_SND_USB_UA101 is not set
+-# CONFIG_SND_USB_CAIAQ is not set
+-# CONFIG_SND_USB_6FIRE is not set
+-CONFIG_SND_SOC=y
+-# CONFIG_SND_SOC_CACHE_LZO is not set
+-CONFIG_SND_SOC_AC97_BUS=y
+-CONFIG_SND_IMX_SOC=y
+-CONFIG_SND_MXC_SOC_MX2=y
+-# CONFIG_SND_SOC_IMX_SGTL5000 is not set
+-# CONFIG_SND_SOC_IMX_WM8962 is not set
+-CONFIG_SND_SOC_IMX_CS42888=y
+-# CONFIG_SND_SOC_IMX_SI4763 is not set
+-# CONFIG_SND_SOC_IMX_SPDIF is not set
+-# CONFIG_SND_SOC_IMX_HDMI is not set
+-CONFIG_SND_SOC_I2C_AND_SPI=y
+-# CONFIG_SND_SOC_ALL_CODECS is not set
+-CONFIG_SND_SOC_CS42888=y
+-# CONFIG_SOUND_PRIME is not set
+-CONFIG_AC97_BUS=y
+-CONFIG_HID_SUPPORT=y
+-CONFIG_HID=y
+-# CONFIG_HIDRAW is not set
+-
+-#
+-# USB Input Devices
+-#
+-CONFIG_USB_HID=y
+-# CONFIG_HID_PID is not set
+-# CONFIG_USB_HIDDEV is not set
+-
+-#
+-# Special HID drivers
+-#
+-CONFIG_HID_A4TECH=m
+-# CONFIG_HID_ACRUX is not set
+-CONFIG_HID_APPLE=m
+-CONFIG_HID_BELKIN=m
+-CONFIG_HID_CHERRY=m
+-CONFIG_HID_CHICONY=m
+-# CONFIG_HID_PRODIKEYS is not set
+-CONFIG_HID_CYPRESS=m
+-# CONFIG_HID_DRAGONRISE is not set
+-# CONFIG_HID_EMS_FF is not set
+-# CONFIG_HID_ELECOM is not set
+-CONFIG_HID_EZKEY=m
+-# CONFIG_HID_KEYTOUCH is not set
+-# CONFIG_HID_KYE is not set
+-# CONFIG_HID_UCLOGIC is not set
+-# CONFIG_HID_WALTOP is not set
+-CONFIG_HID_GYRATION=m
+-# CONFIG_HID_TWINHAN is not set
+-# CONFIG_HID_KENSINGTON is not set
+-# CONFIG_HID_LCPOWER is not set
+-CONFIG_HID_LOGITECH=m
+-# CONFIG_LOGITECH_FF is not set
+-# CONFIG_LOGIRUMBLEPAD2_FF is not set
+-# CONFIG_LOGIG940_FF is not set
+-# CONFIG_LOGIWII_FF is not set
+-# CONFIG_HID_MAGICMOUSE is not set
+-CONFIG_HID_MICROSOFT=m
+-CONFIG_HID_MONTEREY=m
+-# CONFIG_HID_MULTITOUCH is not set
+-# CONFIG_HID_NTRIG is not set
+-# CONFIG_HID_ORTEK is not set
+-CONFIG_HID_PANTHERLORD=m
+-# CONFIG_PANTHERLORD_FF is not set
+-CONFIG_HID_PETALYNX=m
+-# CONFIG_HID_PICOLCD is not set
+-# CONFIG_HID_QUANTA is not set
+-# CONFIG_HID_ROCCAT is not set
+-# CONFIG_HID_ROCCAT_ARVO is not set
+-# CONFIG_HID_ROCCAT_KONE is not set
+-# CONFIG_HID_ROCCAT_KONEPLUS is not set
+-# CONFIG_HID_ROCCAT_KOVAPLUS is not set
+-# CONFIG_HID_ROCCAT_PYRA is not set
+-CONFIG_HID_SAMSUNG=m
+-CONFIG_HID_SONY=m
+-CONFIG_HID_SUNPLUS=m
+-# CONFIG_HID_GREENASIA is not set
+-# CONFIG_HID_SMARTJOYPLUS is not set
+-# CONFIG_HID_TOPSEED is not set
+-# CONFIG_HID_THRUSTMASTER is not set
+-# CONFIG_HID_WACOM is not set
+-# CONFIG_HID_ZEROPLUS is not set
+-# CONFIG_HID_ZYDACRON is not set
+-CONFIG_USB_SUPPORT=y
+-CONFIG_USB_ARCH_HAS_HCD=y
+-# CONFIG_USB_ARCH_HAS_OHCI is not set
+-CONFIG_USB_ARCH_HAS_EHCI=y
+-CONFIG_USB=y
+-# CONFIG_USB_DEBUG is not set
+-# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+-
+-#
+-# Miscellaneous USB options
+-#
+-# CONFIG_USB_DEVICEFS is not set
+-# CONFIG_USB_DEVICE_CLASS is not set
+-# CONFIG_USB_DYNAMIC_MINORS is not set
+-CONFIG_USB_SUSPEND=y
+-# CONFIG_USB_OTG is not set
+-# CONFIG_USB_OTG_WHITELIST is not set
+-# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+-# CONFIG_USB_MON is not set
+-# CONFIG_USB_WUSB is not set
+-# CONFIG_USB_WUSB_CBAF is not set
+-
+-#
+-# USB Host Controller Drivers
+-#
+-# CONFIG_USB_C67X00_HCD is not set
+-# CONFIG_USB_EHCI_HCD is not set
+-# CONFIG_USB_OXU210HP_HCD is not set
+-# CONFIG_USB_ISP116X_HCD is not set
+-# CONFIG_USB_ISP1760_HCD is not set
+-# CONFIG_USB_ISP1362_HCD is not set
+-# CONFIG_USB_SL811_HCD is not set
+-# CONFIG_USB_R8A66597_HCD is not set
+-# CONFIG_USB_HWA_HCD is not set
+-# CONFIG_USB_MUSB_HDRC is not set
+-
+-#
+-# USB Device Class drivers
+-#
+-# CONFIG_USB_ACM is not set
+-# CONFIG_USB_PRINTER is not set
+-# CONFIG_USB_WDM is not set
+-# CONFIG_USB_TMC is not set
+-
+-#
+-# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+-#
+-
+-#
+-# also be needed; see USB_STORAGE Help for more info
+-#
+-CONFIG_USB_STORAGE=y
+-# CONFIG_USB_STORAGE_DEBUG is not set
+-# CONFIG_USB_STORAGE_REALTEK is not set
+-# CONFIG_USB_STORAGE_DATAFAB is not set
+-# CONFIG_USB_STORAGE_FREECOM is not set
+-# CONFIG_USB_STORAGE_ISD200 is not set
+-# CONFIG_USB_STORAGE_USBAT is not set
+-# CONFIG_USB_STORAGE_SDDR09 is not set
+-# CONFIG_USB_STORAGE_SDDR55 is not set
+-# CONFIG_USB_STORAGE_JUMPSHOT is not set
+-# CONFIG_USB_STORAGE_ALAUDA is not set
+-# CONFIG_USB_STORAGE_ONETOUCH is not set
+-# CONFIG_USB_STORAGE_KARMA is not set
+-# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+-# CONFIG_USB_STORAGE_ENE_UB6250 is not set
+-# CONFIG_USB_UAS is not set
+-# CONFIG_USB_LIBUSUAL is not set
+-
+-#
+-# USB Imaging devices
+-#
+-# CONFIG_USB_MDC800 is not set
+-# CONFIG_USB_MICROTEK is not set
+-
+-#
+-# USB port drivers
+-#
+-# CONFIG_USB_SERIAL is not set
+-
+-#
+-# USB Miscellaneous drivers
+-#
+-# CONFIG_USB_EMI62 is not set
+-# CONFIG_USB_EMI26 is not set
+-# CONFIG_USB_ADUTUX is not set
+-# CONFIG_USB_SEVSEG is not set
+-# CONFIG_USB_RIO500 is not set
+-# CONFIG_USB_LEGOTOWER is not set
+-# CONFIG_USB_LCD is not set
+-# CONFIG_USB_LED is not set
+-# CONFIG_USB_CYPRESS_CY7C63 is not set
+-# CONFIG_USB_CYTHERM is not set
+-# CONFIG_USB_IDMOUSE is not set
+-# CONFIG_USB_FTDI_ELAN is not set
+-# CONFIG_USB_APPLEDISPLAY is not set
+-# CONFIG_USB_LD is not set
+-# CONFIG_USB_TRANCEVIBRATOR is not set
+-# CONFIG_USB_IOWARRIOR is not set
+-# CONFIG_USB_TEST is not set
+-# CONFIG_USB_ISIGHTFW is not set
+-# CONFIG_USB_YUREX is not set
+-CONFIG_USB_GADGET=y
+-# CONFIG_USB_GADGET_DEBUG_FILES is not set
+-# CONFIG_USB_GADGET_DEBUG_FS is not set
+-CONFIG_USB_GADGET_VBUS_DRAW=2
+-CONFIG_USB_GADGET_SELECTED=y
+-CONFIG_USB_GADGET_ARC=y
+-# CONFIG_IMX_USB_CHARGER is not set
+-CONFIG_USB_ARC=y
+-# CONFIG_USB_GADGET_FSL_USB2 is not set
+-# CONFIG_USB_GADGET_FUSB300 is not set
+-# CONFIG_USB_GADGET_R8A66597 is not set
+-# CONFIG_USB_GADGET_PXA_U2O is not set
+-# CONFIG_USB_GADGET_M66592 is not set
+-# CONFIG_USB_GADGET_DUMMY_HCD is not set
+-CONFIG_USB_GADGET_DUALSPEED=y
+-# CONFIG_USB_ZERO is not set
+-# CONFIG_USB_AUDIO is not set
+-# CONFIG_USB_ETH is not set
+-# CONFIG_USB_G_NCM is not set
+-# CONFIG_USB_GADGETFS is not set
+-# CONFIG_USB_FUNCTIONFS is not set
+-CONFIG_USB_FILE_STORAGE=y
+-CONFIG_FSL_UTP=y
+-# CONFIG_USB_FILE_STORAGE_TEST is not set
+-# CONFIG_USB_MASS_STORAGE is not set
+-# CONFIG_USB_G_SERIAL is not set
+-# CONFIG_USB_MIDI_GADGET is not set
+-# CONFIG_USB_G_PRINTER is not set
+-# CONFIG_USB_CDC_COMPOSITE is not set
+-# CONFIG_USB_G_MULTI is not set
+-# CONFIG_USB_G_HID is not set
+-# CONFIG_USB_G_DBGP is not set
+-# CONFIG_USB_G_WEBCAM is not set
+-
+-#
+-# OTG and related infrastructure
+-#
+-CONFIG_USB_OTG_UTILS=y
+-# CONFIG_USB_GPIO_VBUS is not set
+-# CONFIG_USB_ULPI is not set
+-# CONFIG_NOP_USB_XCEIV is not set
+-CONFIG_MMC=y
+-# CONFIG_MMC_DEBUG is not set
+-CONFIG_MMC_UNSAFE_RESUME=y
+-# CONFIG_MMC_CLKGATE is not set
+-
+-#
+-# MMC/SD/SDIO Card Drivers
+-#
+-CONFIG_MMC_BLOCK=y
+-CONFIG_MMC_BLOCK_MINORS=8
+-CONFIG_MMC_BLOCK_BOUNCE=y
+-# CONFIG_SDIO_UART is not set
+-# CONFIG_MMC_TEST is not set
+-
+-#
+-# MMC/SD/SDIO Host Controller Drivers
+-#
+-CONFIG_MMC_SDHCI=y
+-CONFIG_MMC_SDHCI_IO_ACCESSORS=y
+-CONFIG_MMC_SDHCI_PLTFM=y
+-CONFIG_MMC_SDHCI_ESDHC_IMX=y
+-# CONFIG_MMC_DW is not set
+-# CONFIG_MMC_VUB300 is not set
+-# CONFIG_MMC_USHC is not set
+-# CONFIG_MEMSTICK is not set
+-# CONFIG_NEW_LEDS is not set
+-# CONFIG_NFC_DEVICES is not set
+-# CONFIG_ACCESSIBILITY is not set
+-CONFIG_RTC_LIB=y
+-CONFIG_RTC_CLASS=y
+-CONFIG_RTC_HCTOSYS=y
+-CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+-# CONFIG_RTC_DEBUG is not set
+-
+-#
+-# RTC interfaces
+-#
+-CONFIG_RTC_INTF_SYSFS=y
+-CONFIG_RTC_INTF_PROC=y
+-CONFIG_RTC_INTF_DEV=y
+-CONFIG_RTC_INTF_DEV_UIE_EMUL=y
+-# CONFIG_RTC_DRV_TEST is not set
+-
+-#
+-# I2C RTC drivers
+-#
+-# CONFIG_RTC_DRV_DS1307 is not set
+-# CONFIG_RTC_DRV_DS1374 is not set
+-# CONFIG_RTC_DRV_DS1672 is not set
+-# CONFIG_RTC_DRV_DS3232 is not set
+-# CONFIG_RTC_DRV_MAX6900 is not set
+-# CONFIG_RTC_DRV_RS5C372 is not set
+-# CONFIG_RTC_DRV_ISL1208 is not set
+-# CONFIG_RTC_DRV_ISL12022 is not set
+-# CONFIG_RTC_DRV_X1205 is not set
+-# CONFIG_RTC_DRV_PCF8563 is not set
+-# CONFIG_RTC_DRV_PCF8583 is not set
+-# CONFIG_RTC_DRV_M41T80 is not set
+-# CONFIG_RTC_DRV_BQ32K is not set
+-# CONFIG_RTC_DRV_S35390A is not set
+-# CONFIG_RTC_DRV_FM3130 is not set
+-# CONFIG_RTC_DRV_RX8581 is not set
+-# CONFIG_RTC_DRV_RX8025 is not set
+-# CONFIG_RTC_DRV_EM3027 is not set
+-# CONFIG_RTC_DRV_RV3029C2 is not set
+-
+-#
+-# SPI RTC drivers
+-#
+-# CONFIG_RTC_DRV_M41T93 is not set
+-# CONFIG_RTC_DRV_M41T94 is not set
+-# CONFIG_RTC_DRV_DS1305 is not set
+-# CONFIG_RTC_DRV_DS1390 is not set
+-# CONFIG_RTC_DRV_MAX6902 is not set
+-# CONFIG_RTC_DRV_R9701 is not set
+-# CONFIG_RTC_DRV_RS5C348 is not set
+-# CONFIG_RTC_DRV_DS3234 is not set
+-# CONFIG_RTC_DRV_PCF2123 is not set
+-
+-#
+-# Platform RTC drivers
+-#
+-# CONFIG_RTC_DRV_CMOS is not set
+-# CONFIG_RTC_DRV_DS1286 is not set
+-# CONFIG_RTC_DRV_DS1511 is not set
+-# CONFIG_RTC_DRV_DS1553 is not set
+-# CONFIG_RTC_DRV_DS1742 is not set
+-# CONFIG_RTC_DRV_STK17TA8 is not set
+-# CONFIG_RTC_DRV_M48T86 is not set
+-# CONFIG_RTC_DRV_M48T35 is not set
+-# CONFIG_RTC_DRV_M48T59 is not set
+-# CONFIG_RTC_DRV_MSM6242 is not set
+-# CONFIG_RTC_MXC is not set
+-# CONFIG_RTC_DRV_MXC_V2 is not set
+-CONFIG_RTC_DRV_SNVS=y
+-# CONFIG_RTC_DRV_BQ4802 is not set
+-# CONFIG_RTC_DRV_RP5C01 is not set
+-# CONFIG_RTC_DRV_V3020 is not set
+-
+-#
+-# on-CPU RTC drivers
+-#
+-CONFIG_DMADEVICES=y
+-# CONFIG_DMADEVICES_DEBUG is not set
+-
+-#
+-# DMA Devices
+-#
+-# CONFIG_DW_DMAC is not set
+-# CONFIG_MXC_PXP_V2 is not set
+-# CONFIG_TIMB_DMA is not set
+-CONFIG_IMX_SDMA=y
+-# CONFIG_MXS_DMA is not set
+-CONFIG_DMA_ENGINE=y
+-
+-#
+-# DMA Clients
+-#
+-# CONFIG_NET_DMA is not set
+-# CONFIG_ASYNC_TX_DMA is not set
+-# CONFIG_DMATEST is not set
+-# CONFIG_AUXDISPLAY is not set
+-# CONFIG_UIO is not set
+-CONFIG_STAGING=y
+-# CONFIG_USBIP_CORE is not set
+-# CONFIG_ECHO is not set
+-# CONFIG_BRCMUTIL is not set
+-# CONFIG_ASUS_OLED is not set
+-# CONFIG_R8712U is not set
+-# CONFIG_TRANZPORT is not set
+-# CONFIG_POHMELFS is not set
+-# CONFIG_LINE6_USB is not set
+-# CONFIG_VT6656 is not set
+-# CONFIG_IIO is not set
+-# CONFIG_XVMALLOC is not set
+-# CONFIG_ZRAM is not set
+-# CONFIG_FB_SM7XX is not set
+-# CONFIG_EASYCAP is not set
+-CONFIG_MACH_NO_WESTBRIDGE=y
+-# CONFIG_USB_ENESTORAGE is not set
+-# CONFIG_BCM_WIMAX is not set
+-# CONFIG_FT1000 is not set
+-
+-#
+-# Speakup console speech
+-#
+-# CONFIG_SPEAKUP is not set
+-# CONFIG_TOUCHSCREEN_CLEARPAD_TM1217 is not set
+-# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set
+-
+-#
+-# Altera FPGA firmware download module
+-#
+-# CONFIG_ALTERA_STAPL is not set
+-CONFIG_CLKDEV_LOOKUP=y
+-CONFIG_CLKSRC_MMIO=y
+-
+-#
+-# MXC support drivers
+-#
+-CONFIG_MXC_IPU=y
+-CONFIG_MXC_IPU_V3=y
+-CONFIG_MXC_IPU_V3H=y
+-
+-#
+-# MXC SSI support
+-#
+-# CONFIG_MXC_SSI is not set
+-
+-#
+-# MXC Digital Audio Multiplexer support
+-#
+-# CONFIG_MXC_DAM is not set
+-
+-#
+-# MXC PMIC support
+-#
+-# CONFIG_MXC_PMIC_MC13783 is not set
+-# CONFIG_MXC_PMIC_MC13892 is not set
+-# CONFIG_MXC_PMIC_MC34704 is not set
+-# CONFIG_MXC_PMIC_MC9SDZ60 is not set
+-# CONFIG_MXC_PMIC_MC9S08DZ60 is not set
+-
+-#
+-# MXC Security Drivers
+-#
+-# CONFIG_MXC_SECURITY_SCC is not set
+-# CONFIG_MXC_SECURITY_RNG is not set
+-
+-#
+-# MXC MPEG4 Encoder Kernel module support
+-#
+-# CONFIG_MXC_HMP4E is not set
+-
+-#
+-# MXC HARDWARE EVENT
+-#
+-# CONFIG_MXC_HWEVENT is not set
+-
+-#
+-# MXC VPU(Video Processing Unit) support
+-#
+-CONFIG_MXC_VPU=y
+-# CONFIG_MXC_VPU_DEBUG is not set
+-# CONFIG_MX6_VPU_352M is not set
+-
+-#
+-# MXC Asynchronous Sample Rate Converter support
+-#
+-CONFIG_MXC_ASRC=y
+-
+-#
+-# MXC Bluetooth support
+-#
+-
+-#
+-# Broadcom GPS ioctrl support
+-#
+-
+-#
+-# MXC Media Local Bus Driver
+-#
+-# CONFIG_MXC_MLB150 is not set
+-
+-#
+-# i.MX ADC support
+-#
+-# CONFIG_IMX_ADC is not set
+-
+-#
+-# MXC Vivante GPU support
+-#
+-# CONFIG_MXC_GPU_VIV is not set
+-
+-#
+-# ANATOP_THERMAL
+-#
+-# CONFIG_ANATOP_THERMAL is not set
+-
+-#
+-# MXC MIPI Support
+-#
+-# CONFIG_MXC_MIPI_CSI2 is not set
+-
+-#
+-# MXC HDMI CEC (Consumer Electronics Control) support
+-#
+-# CONFIG_MXC_HDMI_CEC is not set
+-
+-#
+-# File systems
+-#
+-CONFIG_EXT2_FS=y
+-# CONFIG_EXT2_FS_XATTR is not set
+-# CONFIG_EXT2_FS_XIP is not set
+-CONFIG_EXT3_FS=y
+-# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+-CONFIG_EXT3_FS_XATTR=y
+-# CONFIG_EXT3_FS_POSIX_ACL is not set
+-# CONFIG_EXT3_FS_SECURITY is not set
+-CONFIG_EXT4_FS=y
+-CONFIG_EXT4_FS_XATTR=y
+-# CONFIG_EXT4_FS_POSIX_ACL is not set
+-# CONFIG_EXT4_FS_SECURITY is not set
+-# CONFIG_EXT4_DEBUG is not set
+-CONFIG_JBD=y
+-# CONFIG_JBD_DEBUG is not set
+-CONFIG_JBD2=y
+-# CONFIG_JBD2_DEBUG is not set
+-CONFIG_FS_MBCACHE=y
+-# CONFIG_REISERFS_FS is not set
+-# CONFIG_JFS_FS is not set
+-# CONFIG_XFS_FS is not set
+-# CONFIG_GFS2_FS is not set
+-# CONFIG_BTRFS_FS is not set
+-# CONFIG_NILFS2_FS is not set
+-# CONFIG_FS_POSIX_ACL is not set
+-CONFIG_FILE_LOCKING=y
+-CONFIG_FSNOTIFY=y
+-CONFIG_DNOTIFY=y
+-CONFIG_INOTIFY_USER=y
+-# CONFIG_FANOTIFY is not set
+-# CONFIG_QUOTA is not set
+-# CONFIG_QUOTACTL is not set
+-CONFIG_AUTOFS4_FS=m
+-# CONFIG_FUSE_FS is not set
+-
+-#
+-# Caches
+-#
+-# CONFIG_FSCACHE is not set
+-
+-#
+-# CD-ROM/DVD Filesystems
+-#
+-# CONFIG_ISO9660_FS is not set
+-# CONFIG_UDF_FS is not set
+-
+-#
+-# DOS/FAT/NT Filesystems
+-#
+-CONFIG_FAT_FS=y
+-CONFIG_MSDOS_FS=y
+-CONFIG_VFAT_FS=y
+-CONFIG_FAT_DEFAULT_CODEPAGE=437
+-CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+-# CONFIG_NTFS_FS is not set
+-
+-#
+-# Pseudo filesystems
+-#
+-CONFIG_PROC_FS=y
+-CONFIG_PROC_SYSCTL=y
+-CONFIG_PROC_PAGE_MONITOR=y
+-CONFIG_SYSFS=y
+-CONFIG_TMPFS=y
+-# CONFIG_TMPFS_POSIX_ACL is not set
+-# CONFIG_TMPFS_XATTR is not set
+-# CONFIG_HUGETLB_PAGE is not set
+-# CONFIG_CONFIGFS_FS is not set
+-CONFIG_MISC_FILESYSTEMS=y
+-# CONFIG_ADFS_FS is not set
+-# CONFIG_AFFS_FS is not set
+-# CONFIG_HFS_FS is not set
+-# CONFIG_HFSPLUS_FS is not set
+-# CONFIG_BEFS_FS is not set
+-# CONFIG_BFS_FS is not set
+-# CONFIG_EFS_FS is not set
+-CONFIG_JFFS2_FS=y
+-CONFIG_JFFS2_FS_DEBUG=0
+-CONFIG_JFFS2_FS_WRITEBUFFER=y
+-# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+-# CONFIG_JFFS2_SUMMARY is not set
+-# CONFIG_JFFS2_FS_XATTR is not set
+-# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+-CONFIG_JFFS2_ZLIB=y
+-# CONFIG_JFFS2_LZO is not set
+-CONFIG_JFFS2_RTIME=y
+-# CONFIG_JFFS2_RUBIN is not set
+-CONFIG_UBIFS_FS=y
+-# CONFIG_UBIFS_FS_XATTR is not set
+-# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
+-CONFIG_UBIFS_FS_LZO=y
+-CONFIG_UBIFS_FS_ZLIB=y
+-# CONFIG_UBIFS_FS_DEBUG is not set
+-# CONFIG_LOGFS is not set
+-CONFIG_CRAMFS=y
+-# CONFIG_SQUASHFS is not set
+-# CONFIG_VXFS_FS is not set
+-# CONFIG_MINIX_FS is not set
+-# CONFIG_OMFS_FS is not set
+-# CONFIG_HPFS_FS is not set
+-# CONFIG_QNX4FS_FS is not set
+-# CONFIG_ROMFS_FS is not set
+-# CONFIG_PSTORE is not set
+-# CONFIG_SYSV_FS is not set
+-# CONFIG_UFS_FS is not set
+-CONFIG_NETWORK_FILESYSTEMS=y
+-CONFIG_NFS_FS=y
+-CONFIG_NFS_V3=y
+-# CONFIG_NFS_V3_ACL is not set
+-# CONFIG_NFS_V4 is not set
+-CONFIG_ROOT_NFS=y
+-# CONFIG_NFSD is not set
+-CONFIG_LOCKD=y
+-CONFIG_LOCKD_V4=y
+-CONFIG_NFS_COMMON=y
+-CONFIG_SUNRPC=y
+-# CONFIG_CEPH_FS is not set
+-# CONFIG_CIFS is not set
+-# CONFIG_NCP_FS is not set
+-# CONFIG_CODA_FS is not set
+-# CONFIG_AFS_FS is not set
+-
+-#
+-# Partition Types
+-#
+-CONFIG_PARTITION_ADVANCED=y
+-# CONFIG_ACORN_PARTITION is not set
+-# CONFIG_OSF_PARTITION is not set
+-# CONFIG_AMIGA_PARTITION is not set
+-# CONFIG_ATARI_PARTITION is not set
+-# CONFIG_MAC_PARTITION is not set
+-CONFIG_MSDOS_PARTITION=y
+-# CONFIG_BSD_DISKLABEL is not set
+-# CONFIG_MINIX_SUBPARTITION is not set
+-# CONFIG_SOLARIS_X86_PARTITION is not set
+-# CONFIG_UNIXWARE_DISKLABEL is not set
+-# CONFIG_LDM_PARTITION is not set
+-# CONFIG_SGI_PARTITION is not set
+-# CONFIG_ULTRIX_PARTITION is not set
+-# CONFIG_SUN_PARTITION is not set
+-# CONFIG_KARMA_PARTITION is not set
+-CONFIG_EFI_PARTITION=y
+-# CONFIG_SYSV68_PARTITION is not set
+-CONFIG_NLS=y
+-CONFIG_NLS_DEFAULT="iso8859-1"
+-CONFIG_NLS_CODEPAGE_437=y
+-# CONFIG_NLS_CODEPAGE_737 is not set
+-# CONFIG_NLS_CODEPAGE_775 is not set
+-# CONFIG_NLS_CODEPAGE_850 is not set
+-# CONFIG_NLS_CODEPAGE_852 is not set
+-# CONFIG_NLS_CODEPAGE_855 is not set
+-# CONFIG_NLS_CODEPAGE_857 is not set
+-# CONFIG_NLS_CODEPAGE_860 is not set
+-# CONFIG_NLS_CODEPAGE_861 is not set
+-# CONFIG_NLS_CODEPAGE_862 is not set
+-# CONFIG_NLS_CODEPAGE_863 is not set
+-# CONFIG_NLS_CODEPAGE_864 is not set
+-# CONFIG_NLS_CODEPAGE_865 is not set
+-# CONFIG_NLS_CODEPAGE_866 is not set
+-# CONFIG_NLS_CODEPAGE_869 is not set
+-# CONFIG_NLS_CODEPAGE_936 is not set
+-# CONFIG_NLS_CODEPAGE_950 is not set
+-# CONFIG_NLS_CODEPAGE_932 is not set
+-# CONFIG_NLS_CODEPAGE_949 is not set
+-# CONFIG_NLS_CODEPAGE_874 is not set
+-# CONFIG_NLS_ISO8859_8 is not set
+-# CONFIG_NLS_CODEPAGE_1250 is not set
+-# CONFIG_NLS_CODEPAGE_1251 is not set
+-CONFIG_NLS_ASCII=m
+-CONFIG_NLS_ISO8859_1=y
+-# CONFIG_NLS_ISO8859_2 is not set
+-# CONFIG_NLS_ISO8859_3 is not set
+-# CONFIG_NLS_ISO8859_4 is not set
+-# CONFIG_NLS_ISO8859_5 is not set
+-# CONFIG_NLS_ISO8859_6 is not set
+-# CONFIG_NLS_ISO8859_7 is not set
+-# CONFIG_NLS_ISO8859_9 is not set
+-# CONFIG_NLS_ISO8859_13 is not set
+-# CONFIG_NLS_ISO8859_14 is not set
+-# CONFIG_NLS_ISO8859_15 is not set
+-# CONFIG_NLS_KOI8_R is not set
+-# CONFIG_NLS_KOI8_U is not set
+-CONFIG_NLS_UTF8=m
+-
+-#
+-# Kernel hacking
+-#
+-# CONFIG_PRINTK_TIME is not set
+-CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
+-CONFIG_ENABLE_WARN_DEPRECATED=y
+-CONFIG_ENABLE_MUST_CHECK=y
+-CONFIG_FRAME_WARN=1024
+-# CONFIG_MAGIC_SYSRQ is not set
+-# CONFIG_STRIP_ASM_SYMS is not set
+-# CONFIG_UNUSED_SYMBOLS is not set
+-CONFIG_DEBUG_FS=y
+-# CONFIG_HEADERS_CHECK is not set
+-# CONFIG_DEBUG_SECTION_MISMATCH is not set
+-# CONFIG_DEBUG_KERNEL is not set
+-# CONFIG_HARDLOCKUP_DETECTOR is not set
+-# CONFIG_SLUB_DEBUG_ON is not set
+-# CONFIG_SLUB_STATS is not set
+-# CONFIG_SPARSE_RCU_POINTER is not set
+-CONFIG_DEBUG_BUGVERBOSE=y
+-# CONFIG_DEBUG_MEMORY_INIT is not set
+-CONFIG_RCU_CPU_STALL_TIMEOUT=60
+-CONFIG_RCU_CPU_STALL_VERBOSE=y
+-# CONFIG_LKDTM is not set
+-CONFIG_SYSCTL_SYSCALL_CHECK=y
+-CONFIG_HAVE_FUNCTION_TRACER=y
+-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+-CONFIG_HAVE_DYNAMIC_FTRACE=y
+-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+-CONFIG_HAVE_C_RECORDMCOUNT=y
+-CONFIG_TRACING_SUPPORT=y
+-# CONFIG_FTRACE is not set
+-# CONFIG_DYNAMIC_DEBUG is not set
+-# CONFIG_DMA_API_DEBUG is not set
+-# CONFIG_ATOMIC64_SELFTEST is not set
+-# CONFIG_SAMPLES is not set
+-CONFIG_HAVE_ARCH_KGDB=y
+-# CONFIG_TEST_KSTRTOX is not set
+-# CONFIG_STRICT_DEVMEM is not set
+-CONFIG_ARM_UNWIND=y
+-# CONFIG_DEBUG_USER is not set
+-# CONFIG_OC_ETM is not set
+-
+-#
+-# Security options
+-#
+-# CONFIG_KEYS is not set
+-# CONFIG_SECURITY_DMESG_RESTRICT is not set
+-# CONFIG_SECURITY is not set
+-# CONFIG_SECURITYFS is not set
+-CONFIG_DEFAULT_SECURITY_DAC=y
+-CONFIG_DEFAULT_SECURITY=""
+-CONFIG_CRYPTO=y
+-
+-#
+-# Crypto core or helper
+-#
+-CONFIG_CRYPTO_ALGAPI=y
+-CONFIG_CRYPTO_ALGAPI2=y
+-CONFIG_CRYPTO_AEAD2=y
+-CONFIG_CRYPTO_BLKCIPHER=y
+-CONFIG_CRYPTO_BLKCIPHER2=y
+-CONFIG_CRYPTO_HASH2=y
+-CONFIG_CRYPTO_RNG2=y
+-CONFIG_CRYPTO_PCOMP2=y
+-CONFIG_CRYPTO_MANAGER=y
+-CONFIG_CRYPTO_MANAGER2=y
+-CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
+-# CONFIG_CRYPTO_GF128MUL is not set
+-# CONFIG_CRYPTO_NULL is not set
+-CONFIG_CRYPTO_WORKQUEUE=y
+-# CONFIG_CRYPTO_CRYPTD is not set
+-# CONFIG_CRYPTO_AUTHENC is not set
+-CONFIG_CRYPTO_TEST=m
+-CONFIG_CRYPTO_CRYPTODEV=y
+-
+-#
+-# Authenticated Encryption with Associated Data
+-#
+-# CONFIG_CRYPTO_CCM is not set
+-# CONFIG_CRYPTO_GCM is not set
+-# CONFIG_CRYPTO_SEQIV is not set
+-
+-#
+-# Block modes
+-#
+-CONFIG_CRYPTO_CBC=y
+-# CONFIG_CRYPTO_CTR is not set
+-# CONFIG_CRYPTO_CTS is not set
+-CONFIG_CRYPTO_ECB=y
+-# CONFIG_CRYPTO_LRW is not set
+-# CONFIG_CRYPTO_PCBC is not set
+-# CONFIG_CRYPTO_XTS is not set
+-
+-#
+-# Hash modes
+-#
+-# CONFIG_CRYPTO_HMAC is not set
+-# CONFIG_CRYPTO_XCBC is not set
+-# CONFIG_CRYPTO_VMAC is not set
+-
+-#
+-# Digest
+-#
+-# CONFIG_CRYPTO_CRC32C is not set
+-# CONFIG_CRYPTO_GHASH is not set
+-# CONFIG_CRYPTO_MD4 is not set
+-# CONFIG_CRYPTO_MD5 is not set
+-# CONFIG_CRYPTO_MICHAEL_MIC is not set
+-# CONFIG_CRYPTO_RMD128 is not set
+-# CONFIG_CRYPTO_RMD160 is not set
+-# CONFIG_CRYPTO_RMD256 is not set
+-# CONFIG_CRYPTO_RMD320 is not set
+-# CONFIG_CRYPTO_SHA1 is not set
+-# CONFIG_CRYPTO_SHA256 is not set
+-# CONFIG_CRYPTO_SHA512 is not set
+-# CONFIG_CRYPTO_TGR192 is not set
+-# CONFIG_CRYPTO_WP512 is not set
+-
+-#
+-# Ciphers
+-#
+-CONFIG_CRYPTO_AES=y
+-# CONFIG_CRYPTO_ANUBIS is not set
+-# CONFIG_CRYPTO_ARC4 is not set
+-# CONFIG_CRYPTO_BLOWFISH is not set
+-# CONFIG_CRYPTO_CAMELLIA is not set
+-# CONFIG_CRYPTO_CAST5 is not set
+-# CONFIG_CRYPTO_CAST6 is not set
+-# CONFIG_CRYPTO_DES is not set
+-# CONFIG_CRYPTO_FCRYPT is not set
+-# CONFIG_CRYPTO_KHAZAD is not set
+-# CONFIG_CRYPTO_SALSA20 is not set
+-# CONFIG_CRYPTO_SEED is not set
+-# CONFIG_CRYPTO_SERPENT is not set
+-# CONFIG_CRYPTO_TEA is not set
+-# CONFIG_CRYPTO_TWOFISH is not set
+-
+-#
+-# Compression
+-#
+-CONFIG_CRYPTO_DEFLATE=y
+-# CONFIG_CRYPTO_ZLIB is not set
+-CONFIG_CRYPTO_LZO=y
+-
+-#
+-# Random Number Generation
+-#
+-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+-# CONFIG_CRYPTO_USER_API_HASH is not set
+-# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
+-CONFIG_CRYPTO_HW=y
+-# CONFIG_CRYPTO_DEV_FSL_CAAM is not set
+-# CONFIG_CRYPTO_DEV_DCP is not set
+-# CONFIG_BINARY_PRINTF is not set
+-
+-#
+-# Library routines
+-#
+-CONFIG_BITREVERSE=y
+-CONFIG_RATIONAL=y
+-CONFIG_CRC_CCITT=m
+-CONFIG_CRC16=y
+-# CONFIG_CRC_T10DIF is not set
+-# CONFIG_CRC_ITU_T is not set
+-CONFIG_CRC32=y
+-# CONFIG_CRC7 is not set
+-# CONFIG_LIBCRC32C is not set
+-CONFIG_ZLIB_INFLATE=y
+-CONFIG_ZLIB_DEFLATE=y
+-CONFIG_LZO_COMPRESS=y
+-CONFIG_LZO_DECOMPRESS=y
+-# CONFIG_XZ_DEC is not set
+-# CONFIG_XZ_DEC_BCJ is not set
+-CONFIG_DECOMPRESS_GZIP=y
+-CONFIG_GENERIC_ALLOCATOR=y
+-CONFIG_HAS_IOMEM=y
+-CONFIG_HAS_IOPORT=y
+-CONFIG_HAS_DMA=y
+-CONFIG_NLATTR=y
+-# CONFIG_AVERAGE is not set
+diff --git a/arch/arm/configs/nitrogen6x_defconfig b/arch/arm/configs/nitrogen6x_defconfig
+new file mode 100644
+index 0000000..35e4cc3
+--- /dev/null
++++ b/arch/arm/configs/nitrogen6x_defconfig
+@@ -0,0 +1,3020 @@
++#
++# Automatically generated make config: don't edit
++# Linux/arm 3.0.35 Kernel Configuration
++#
++CONFIG_ARM=y
++CONFIG_HAVE_PWM=y
++CONFIG_SYS_SUPPORTS_APM_EMULATION=y
++CONFIG_HAVE_SCHED_CLOCK=y
++CONFIG_GENERIC_GPIO=y
++# CONFIG_ARCH_USES_GETTIMEOFFSET is not set
++CONFIG_GENERIC_CLOCKEVENTS=y
++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
++CONFIG_KTIME_SCALAR=y
++CONFIG_HAVE_PROC_CPU=y
++CONFIG_STACKTRACE_SUPPORT=y
++CONFIG_LOCKDEP_SUPPORT=y
++CONFIG_TRACE_IRQFLAGS_SUPPORT=y
++CONFIG_HARDIRQS_SW_RESEND=y
++CONFIG_GENERIC_IRQ_PROBE=y
++CONFIG_GENERIC_LOCKBREAK=y
++CONFIG_RWSEM_GENERIC_SPINLOCK=y
++CONFIG_ARCH_HAS_CPUFREQ=y
++CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y
++CONFIG_GENERIC_HWEIGHT=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_ZONE_DMA=y
++CONFIG_NEED_DMA_MAP_STATE=y
++CONFIG_FIQ=y
++CONFIG_VECTORS_BASE=0xffff0000
++# CONFIG_ARM_PATCH_PHYS_VIRT is not set
++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
++CONFIG_HAVE_IRQ_WORK=y
++CONFIG_IRQ_WORK=y
++
++#
++# General setup
++#
++CONFIG_EXPERIMENTAL=y
++CONFIG_INIT_ENV_ARG_LIMIT=32
++CONFIG_CROSS_COMPILE=""
++CONFIG_LOCALVERSION=""
++CONFIG_LOCALVERSION_AUTO=y
++CONFIG_HAVE_KERNEL_GZIP=y
++CONFIG_HAVE_KERNEL_LZMA=y
++CONFIG_HAVE_KERNEL_LZO=y
++CONFIG_KERNEL_GZIP=y
++# CONFIG_KERNEL_LZMA is not set
++# CONFIG_KERNEL_LZO is not set
++CONFIG_DEFAULT_HOSTNAME="(none)"
++CONFIG_SWAP=y
++CONFIG_SYSVIPC=y
++CONFIG_SYSVIPC_SYSCTL=y
++# CONFIG_POSIX_MQUEUE is not set
++# CONFIG_BSD_PROCESS_ACCT is not set
++# CONFIG_FHANDLE is not set
++# CONFIG_TASKSTATS is not set
++# CONFIG_AUDIT is not set
++CONFIG_HAVE_GENERIC_HARDIRQS=y
++
++#
++# IRQ subsystem
++#
++CONFIG_GENERIC_HARDIRQS=y
++CONFIG_HAVE_SPARSE_IRQ=y
++CONFIG_GENERIC_IRQ_SHOW=y
++# CONFIG_SPARSE_IRQ is not set
++
++#
++# RCU Subsystem
++#
++CONFIG_TREE_PREEMPT_RCU=y
++CONFIG_PREEMPT_RCU=y
++# CONFIG_RCU_TRACE is not set
++CONFIG_RCU_FANOUT=32
++# CONFIG_RCU_FANOUT_EXACT is not set
++# CONFIG_TREE_RCU_TRACE is not set
++# CONFIG_RCU_BOOST is not set
++CONFIG_IKCONFIG=y
++CONFIG_IKCONFIG_PROC=y
++CONFIG_LOG_BUF_SHIFT=14
++# CONFIG_CGROUPS is not set
++# CONFIG_NAMESPACES is not set
++# CONFIG_SCHED_AUTOGROUP is not set
++# CONFIG_SYSFS_DEPRECATED is not set
++# CONFIG_RELAY is not set
++CONFIG_BLK_DEV_INITRD=y
++CONFIG_INITRAMFS_SOURCE=""
++CONFIG_RD_GZIP=y
++# CONFIG_RD_BZIP2 is not set
++# CONFIG_RD_LZMA is not set
++# CONFIG_RD_XZ is not set
++# CONFIG_RD_LZO is not set
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
++CONFIG_SYSCTL=y
++CONFIG_ANON_INODES=y
++CONFIG_EXPERT=y
++CONFIG_UID16=y
++CONFIG_SYSCTL_SYSCALL=y
++CONFIG_KALLSYMS=y
++CONFIG_HOTPLUG=y
++CONFIG_PRINTK=y
++CONFIG_BUG=y
++CONFIG_ELF_CORE=y
++CONFIG_BASE_FULL=y
++CONFIG_FUTEX=y
++CONFIG_EPOLL=y
++CONFIG_SIGNALFD=y
++CONFIG_TIMERFD=y
++CONFIG_EVENTFD=y
++CONFIG_SHMEM=y
++CONFIG_AIO=y
++CONFIG_EMBEDDED=y
++CONFIG_HAVE_PERF_EVENTS=y
++CONFIG_PERF_USE_VMALLOC=y
++
++#
++# Kernel Performance Events And Counters
++#
++CONFIG_PERF_EVENTS=y
++# CONFIG_PERF_COUNTERS is not set
++CONFIG_VM_EVENT_COUNTERS=y
++CONFIG_SLUB_DEBUG=y
++CONFIG_COMPAT_BRK=y
++# CONFIG_SLAB is not set
++CONFIG_SLUB=y
++# CONFIG_SLOB is not set
++# CONFIG_PROFILING is not set
++CONFIG_HAVE_OPROFILE=y
++# CONFIG_KPROBES is not set
++CONFIG_HAVE_KPROBES=y
++CONFIG_HAVE_KRETPROBES=y
++CONFIG_USE_GENERIC_SMP_HELPERS=y
++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
++CONFIG_HAVE_CLK=y
++CONFIG_HAVE_DMA_API_DEBUG=y
++CONFIG_HAVE_HW_BREAKPOINT=y
++
++#
++# GCOV-based kernel profiling
++#
++# CONFIG_GCOV_KERNEL is not set
++CONFIG_HAVE_GENERIC_DMA_COHERENT=y
++CONFIG_SLABINFO=y
++CONFIG_RT_MUTEXES=y
++CONFIG_BASE_SMALL=0
++CONFIG_MODULES=y
++# CONFIG_MODULE_FORCE_LOAD is not set
++CONFIG_MODULE_UNLOAD=y
++CONFIG_MODULE_FORCE_UNLOAD=y
++CONFIG_MODVERSIONS=y
++# CONFIG_MODULE_SRCVERSION_ALL is not set
++CONFIG_STOP_MACHINE=y
++CONFIG_BLOCK=y
++CONFIG_LBDAF=y
++# CONFIG_BLK_DEV_BSG is not set
++# CONFIG_BLK_DEV_INTEGRITY is not set
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++CONFIG_IOSCHED_DEADLINE=y
++CONFIG_IOSCHED_CFQ=y
++# CONFIG_DEFAULT_DEADLINE is not set
++CONFIG_DEFAULT_CFQ=y
++# CONFIG_DEFAULT_NOOP is not set
++CONFIG_DEFAULT_IOSCHED="cfq"
++# CONFIG_INLINE_SPIN_TRYLOCK is not set
++# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
++# CONFIG_INLINE_SPIN_LOCK is not set
++# CONFIG_INLINE_SPIN_LOCK_BH is not set
++# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
++# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
++# CONFIG_INLINE_SPIN_UNLOCK is not set
++# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
++# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set
++# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
++# CONFIG_INLINE_READ_TRYLOCK is not set
++# CONFIG_INLINE_READ_LOCK is not set
++# CONFIG_INLINE_READ_LOCK_BH is not set
++# CONFIG_INLINE_READ_LOCK_IRQ is not set
++# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
++# CONFIG_INLINE_READ_UNLOCK is not set
++# CONFIG_INLINE_READ_UNLOCK_BH is not set
++# CONFIG_INLINE_READ_UNLOCK_IRQ is not set
++# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
++# CONFIG_INLINE_WRITE_TRYLOCK is not set
++# CONFIG_INLINE_WRITE_LOCK is not set
++# CONFIG_INLINE_WRITE_LOCK_BH is not set
++# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
++# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
++# CONFIG_INLINE_WRITE_UNLOCK is not set
++# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
++# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set
++# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
++CONFIG_MUTEX_SPIN_ON_OWNER=y
++CONFIG_FREEZER=y
++
++#
++# System Type
++#
++CONFIG_MMU=y
++# CONFIG_ARCH_INTEGRATOR is not set
++# CONFIG_ARCH_REALVIEW is not set
++# CONFIG_ARCH_VERSATILE is not set
++# CONFIG_ARCH_VEXPRESS is not set
++# CONFIG_ARCH_AT91 is not set
++# CONFIG_ARCH_BCMRING is not set
++# CONFIG_ARCH_CLPS711X is not set
++# CONFIG_ARCH_CNS3XXX is not set
++# CONFIG_ARCH_GEMINI is not set
++# CONFIG_ARCH_EBSA110 is not set
++# CONFIG_ARCH_EP93XX is not set
++# CONFIG_ARCH_FOOTBRIDGE is not set
++CONFIG_ARCH_MXC=y
++# CONFIG_ARCH_MXS is not set
++# CONFIG_ARCH_NETX is not set
++# CONFIG_ARCH_H720X is not set
++# CONFIG_ARCH_IOP13XX is not set
++# CONFIG_ARCH_IOP32X is not set
++# CONFIG_ARCH_IOP33X is not set
++# CONFIG_ARCH_IXP23XX is not set
++# CONFIG_ARCH_IXP2000 is not set
++# CONFIG_ARCH_IXP4XX is not set
++# CONFIG_ARCH_DOVE is not set
++# CONFIG_ARCH_KIRKWOOD is not set
++# CONFIG_ARCH_LOKI is not set
++# CONFIG_ARCH_LPC32XX is not set
++# CONFIG_ARCH_MV78XX0 is not set
++# CONFIG_ARCH_ORION5X is not set
++# CONFIG_ARCH_MMP is not set
++# CONFIG_ARCH_KS8695 is not set
++# CONFIG_ARCH_W90X900 is not set
++# CONFIG_ARCH_NUC93X is not set
++# CONFIG_ARCH_TEGRA is not set
++# CONFIG_ARCH_PNX4008 is not set
++# CONFIG_ARCH_PXA is not set
++# CONFIG_ARCH_MSM is not set
++# CONFIG_ARCH_SHMOBILE is not set
++# CONFIG_ARCH_RPC is not set
++# CONFIG_ARCH_SA1100 is not set
++# CONFIG_ARCH_S3C2410 is not set
++# CONFIG_ARCH_S3C64XX is not set
++# CONFIG_ARCH_S5P64X0 is not set
++# CONFIG_ARCH_S5PC100 is not set
++# CONFIG_ARCH_S5PV210 is not set
++# CONFIG_ARCH_EXYNOS4 is not set
++# CONFIG_ARCH_SHARK is not set
++# CONFIG_ARCH_TCC_926 is not set
++# CONFIG_ARCH_U300 is not set
++# CONFIG_ARCH_U8500 is not set
++# CONFIG_ARCH_NOMADIK is not set
++# CONFIG_ARCH_DAVINCI is not set
++# CONFIG_ARCH_OMAP is not set
++# CONFIG_PLAT_SPEAR is not set
++# CONFIG_ARCH_VT8500 is not set
++CONFIG_GPIO_PCA953X=y
++# CONFIG_KEYBOARD_GPIO_POLLED is not set
++CONFIG_IMX_HAVE_PLATFORM_DMA=y
++CONFIG_IMX_HAVE_PLATFORM_FEC=y
++CONFIG_IMX_HAVE_PLATFORM_FLEXCAN=y
++CONFIG_IMX_HAVE_PLATFORM_FSL_USB2_UDC=y
++CONFIG_IMX_HAVE_PLATFORM_GPMI_NFC=y
++CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT=y
++CONFIG_IMX_HAVE_PLATFORM_IMX_SNVS_RTC=y
++CONFIG_IMX_HAVE_PLATFORM_IMX_CAAM=y
++CONFIG_IMX_HAVE_PLATFORM_IMX_I2C=y
++CONFIG_IMX_HAVE_PLATFORM_IMX_SSI=y
++CONFIG_IMX_HAVE_PLATFORM_IMX_UART=y
++CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI=y
++CONFIG_IMX_HAVE_PLATFORM_MXC_PWM=y
++CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX=y
++CONFIG_IMX_HAVE_PLATFORM_SPI_IMX=y
++CONFIG_IMX_HAVE_PLATFORM_IMX_IPUV3=y
++CONFIG_IMX_HAVE_PLATFORM_IMX_VPU=y
++CONFIG_IMX_HAVE_PLATFORM_IMX_DVFS=y
++CONFIG_IMX_HAVE_PLATFORM_AHCI=y
++CONFIG_IMX_HAVE_PLATFORM_IMX_OCOTP=y
++CONFIG_IMX_HAVE_PLATFORM_IMX_VIIM=y
++CONFIG_IMX_HAVE_PLATFORM_PERFMON=y
++CONFIG_IMX_HAVE_PLATFORM_LDB=y
++CONFIG_IMX_HAVE_PLATFORM_IMX_SPDIF=y
++CONFIG_IMX_HAVE_PLATFORM_VIV_GPU=y
++CONFIG_IMX_HAVE_PLATFORM_MXC_HDMI=y
++CONFIG_IMX_HAVE_PLATFORM_IMX_ANATOP_THERMAL=y
++CONFIG_IMX_HAVE_PLATFORM_FSL_OTG=y
++CONFIG_IMX_HAVE_PLATFORM_FSL_USB_WAKEUP=y
++CONFIG_IMX_HAVE_PLATFORM_IMX_PM=y
++CONFIG_IMX_HAVE_PLATFORM_IMX_ASRC=y
++CONFIG_IMX_HAVE_PLATFORM_IMX_MIPI_DSI=y
++CONFIG_IMX_HAVE_PLATFORM_IMX_MIPI_CSI2=y
++CONFIG_IMX_HAVE_PLATFORM_IMX_VDOA=y
++CONFIG_IMX_HAVE_PLATFORM_IMX_PCIE=y
++
++#
++# Freescale MXC Implementations
++#
++# CONFIG_ARCH_MX1 is not set
++# CONFIG_ARCH_MX2 is not set
++# CONFIG_ARCH_MX25 is not set
++# CONFIG_ARCH_MX3 is not set
++# CONFIG_ARCH_MX503 is not set
++# CONFIG_ARCH_MX51 is not set
++CONFIG_ARCH_MX6=y
++CONFIG_ARCH_MX6Q=y
++CONFIG_FORCE_MAX_ZONEORDER=14
++CONFIG_SOC_IMX6Q=y
++# CONFIG_MACH_MX6Q_ARM2 is not set
++# CONFIG_MACH_MX6SL_ARM2 is not set
++CONFIG_MACH_MX6Q_SABRELITE=y
++# CONFIG_MACH_MX6Q_SABRESD is not set
++# CONFIG_MACH_MX6Q_SABREAUTO is not set
++
++#
++# MX6 Options:
++#
++CONFIG_IMX_PCIE=y
++CONFIG_USB_EHCI_ARC_H1=y
++# CONFIG_MX6_INTER_LDO_BYPASS is not set
++CONFIG_ISP1504_MXC=y
++# CONFIG_MXC_IRQ_PRIOR is not set
++CONFIG_MXC_PWM=y
++# CONFIG_MXC_DEBUG_BOARD is not set
++CONFIG_MXC_REBOOT_MFGMODE=y
++# CONFIG_MXC_REBOOT_ANDROID_CMD is not set
++CONFIG_ARCH_MXC_IOMUX_V3=y
++CONFIG_ARCH_MXC_AUDMUX_V2=y
++CONFIG_IRAM_ALLOC=y
++CONFIG_CLK_DEBUG=y
++CONFIG_DMA_ZONE_SIZE=184
++
++#
++# System MMU
++#
++
++#
++# Processor Type
++#
++CONFIG_CPU_V7=y
++CONFIG_CPU_32v6K=y
++CONFIG_CPU_32v7=y
++CONFIG_CPU_ABRT_EV7=y
++CONFIG_CPU_PABRT_V7=y
++CONFIG_CPU_CACHE_V7=y
++CONFIG_CPU_CACHE_VIPT=y
++CONFIG_CPU_COPY_V6=y
++CONFIG_CPU_TLB_V7=y
++CONFIG_CPU_HAS_ASID=y
++CONFIG_CPU_CP15=y
++CONFIG_CPU_CP15_MMU=y
++
++#
++# Processor Features
++#
++CONFIG_ARM_THUMB=y
++# CONFIG_ARM_THUMBEE is not set
++# CONFIG_SWP_EMULATE is not set
++# CONFIG_CPU_ICACHE_DISABLE is not set
++# CONFIG_CPU_DCACHE_DISABLE is not set
++# CONFIG_CPU_BPREDICT_DISABLE is not set
++CONFIG_OUTER_CACHE=y
++CONFIG_OUTER_CACHE_SYNC=y
++CONFIG_CACHE_L2X0=y
++CONFIG_CACHE_PL310=y
++CONFIG_ARM_L1_CACHE_SHIFT=5
++CONFIG_ARM_DMA_MEM_BUFFERABLE=y
++CONFIG_CPU_HAS_PMU=y
++# CONFIG_ARM_ERRATA_430973 is not set
++# CONFIG_ARM_ERRATA_458693 is not set
++# CONFIG_ARM_ERRATA_460075 is not set
++# CONFIG_ARM_ERRATA_742230 is not set
++# CONFIG_ARM_ERRATA_742231 is not set
++# CONFIG_PL310_ERRATA_588369 is not set
++# CONFIG_ARM_ERRATA_720789 is not set
++# CONFIG_PL310_ERRATA_727915 is not set
++CONFIG_ARM_ERRATA_743622=y
++CONFIG_ARM_ERRATA_751472=y
++# CONFIG_ARM_ERRATA_753970 is not set
++CONFIG_ARM_ERRATA_754322=y
++# CONFIG_ARM_ERRATA_754327 is not set
++CONFIG_ARM_GIC=y
++
++#
++# Bus support
++#
++CONFIG_PCI=y
++CONFIG_PCI_SYSCALL=y
++# CONFIG_ARCH_SUPPORTS_MSI is not set
++# CONFIG_PCI_STUB is not set
++# CONFIG_PCI_IOV is not set
++# CONFIG_PCIEPORTBUS is not set
++# CONFIG_PCCARD is not set
++CONFIG_ARM_ERRATA_764369=y
++# CONFIG_PL310_ERRATA_769419 is not set
++
++#
++# Kernel Features
++#
++CONFIG_TICK_ONESHOT=y
++CONFIG_NO_HZ=y
++CONFIG_HIGH_RES_TIMERS=y
++CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
++CONFIG_SMP=y
++CONFIG_SMP_ON_UP=y
++CONFIG_HAVE_ARM_SCU=y
++CONFIG_HAVE_ARM_TWD=y
++# CONFIG_VMSPLIT_3G is not set
++CONFIG_VMSPLIT_2G=y
++# CONFIG_VMSPLIT_1G is not set
++CONFIG_PAGE_OFFSET=0x80000000
++CONFIG_NR_CPUS=4
++CONFIG_HOTPLUG_CPU=y
++CONFIG_LOCAL_TIMERS=y
++# CONFIG_PREEMPT_NONE is not set
++# CONFIG_PREEMPT_VOLUNTARY is not set
++CONFIG_PREEMPT=y
++CONFIG_HZ=100
++# CONFIG_THUMB2_KERNEL is not set
++CONFIG_AEABI=y
++# CONFIG_OABI_COMPAT is not set
++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
++CONFIG_HAVE_ARCH_PFN_VALID=y
++CONFIG_HIGHMEM=y
++# CONFIG_HIGHPTE is not set
++CONFIG_HW_PERF_EVENTS=y
++CONFIG_SELECT_MEMORY_MODEL=y
++CONFIG_FLATMEM_MANUAL=y
++CONFIG_FLATMEM=y
++CONFIG_FLAT_NODE_MEM_MAP=y
++CONFIG_HAVE_MEMBLOCK=y
++CONFIG_PAGEFLAGS_EXTENDED=y
++CONFIG_SPLIT_PTLOCK_CPUS=4
++CONFIG_COMPACTION=y
++CONFIG_MIGRATION=y
++# CONFIG_PHYS_ADDR_T_64BIT is not set
++CONFIG_ZONE_DMA_FLAG=1
++CONFIG_BOUNCE=y
++CONFIG_VIRT_TO_BUS=y
++CONFIG_KSM=y
++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
++# CONFIG_CLEANCACHE is not set
++CONFIG_ALIGNMENT_TRAP=y
++# CONFIG_UACCESS_WITH_MEMCPY is not set
++# CONFIG_SECCOMP is not set
++# CONFIG_CC_STACKPROTECTOR is not set
++# CONFIG_DEPRECATED_PARAM_STRUCT is not set
++
++#
++# Boot options
++#
++# CONFIG_USE_OF is not set
++CONFIG_ZBOOT_ROM_TEXT=0x0
++CONFIG_ZBOOT_ROM_BSS=0x0
++CONFIG_CMDLINE="noinitrd console=ttymxc0,115200 root=/dev/mtdblock2 rw rootfstype=jffs2 ip=off"
++CONFIG_CMDLINE_FROM_BOOTLOADER=y
++# CONFIG_CMDLINE_EXTEND is not set
++# CONFIG_CMDLINE_FORCE is not set
++# CONFIG_XIP_KERNEL is not set
++# CONFIG_KEXEC is not set
++# CONFIG_CRASH_DUMP is not set
++# CONFIG_AUTO_ZRELADDR is not set
++
++#
++# CPU Power Management
++#
++
++#
++# CPU Frequency scaling
++#
++CONFIG_CPU_FREQ=y
++CONFIG_CPU_FREQ_TABLE=y
++CONFIG_CPU_FREQ_STAT=y
++# CONFIG_CPU_FREQ_STAT_DETAILS is not set
++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
++# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
++CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
++CONFIG_CPU_FREQ_GOV_POWERSAVE=y
++CONFIG_CPU_FREQ_GOV_USERSPACE=y
++CONFIG_CPU_FREQ_GOV_ONDEMAND=y
++CONFIG_CPU_FREQ_GOV_INTERACTIVE=y
++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
++CONFIG_CPU_FREQ_IMX=y
++# CONFIG_CPU_IDLE is not set
++
++#
++# Floating point emulation
++#
++
++#
++# At least one emulation must be selected
++#
++CONFIG_VFP=y
++CONFIG_VFPv3=y
++CONFIG_NEON=y
++
++#
++# Userspace binary formats
++#
++CONFIG_BINFMT_ELF=y
++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
++CONFIG_HAVE_AOUT=y
++# CONFIG_BINFMT_AOUT is not set
++# CONFIG_BINFMT_MISC is not set
++
++#
++# Power management options
++#
++CONFIG_SUSPEND=y
++# CONFIG_PM_TEST_SUSPEND is not set
++CONFIG_SUSPEND_DEVICE_TIME_DEBUG=y
++CONFIG_SUSPEND_FREEZER=y
++CONFIG_PM_SLEEP=y
++CONFIG_PM_SLEEP_SMP=y
++CONFIG_PM_RUNTIME=y
++CONFIG_PM=y
++CONFIG_PM_DEBUG=y
++# CONFIG_PM_ADVANCED_DEBUG is not set
++CONFIG_CAN_PM_TRACE=y
++CONFIG_APM_EMULATION=y
++CONFIG_PM_RUNTIME_CLK=y
++CONFIG_ARCH_SUSPEND_POSSIBLE=y
++CONFIG_NET=y
++
++#
++# Networking options
++#
++CONFIG_PACKET=y
++CONFIG_UNIX=y
++CONFIG_XFRM=y
++# CONFIG_XFRM_USER is not set
++# CONFIG_XFRM_SUB_POLICY is not set
++# CONFIG_XFRM_MIGRATE is not set
++# CONFIG_XFRM_STATISTICS is not set
++# CONFIG_NET_KEY is not set
++CONFIG_INET=y
++CONFIG_IP_MULTICAST=y
++# CONFIG_IP_ADVANCED_ROUTER is not set
++CONFIG_IP_PNP=y
++CONFIG_IP_PNP_DHCP=y
++CONFIG_IP_PNP_BOOTP=y
++# CONFIG_IP_PNP_RARP is not set
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE_DEMUX is not set
++# CONFIG_IP_MROUTE is not set
++# CONFIG_ARPD is not set
++# CONFIG_SYN_COOKIES is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_XFRM_TUNNEL is not set
++# CONFIG_INET_TUNNEL is not set
++CONFIG_INET_XFRM_MODE_TRANSPORT=y
++CONFIG_INET_XFRM_MODE_TUNNEL=y
++CONFIG_INET_XFRM_MODE_BEET=y
++# CONFIG_INET_LRO is not set
++CONFIG_INET_DIAG=y
++CONFIG_INET_TCP_DIAG=y
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_CUBIC=y
++CONFIG_DEFAULT_TCP_CONG="cubic"
++# CONFIG_TCP_MD5SIG is not set
++# CONFIG_IPV6 is not set
++# CONFIG_NETWORK_SECMARK is not set
++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
++# CONFIG_NETFILTER is not set
++# CONFIG_IP_DCCP is not set
++# CONFIG_IP_SCTP is not set
++# CONFIG_RDS is not set
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_L2TP is not set
++# CONFIG_BRIDGE is not set
++# CONFIG_NET_DSA is not set
++# CONFIG_VLAN_8021Q is not set
++# CONFIG_DECNET is not set
++CONFIG_LLC=y
++CONFIG_LLC2=y
++# CONFIG_IPX is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_ECONET is not set
++# CONFIG_WAN_ROUTER is not set
++# CONFIG_PHONET is not set
++# CONFIG_IEEE802154 is not set
++# CONFIG_NET_SCHED is not set
++# CONFIG_DCB is not set
++# CONFIG_BATMAN_ADV is not set
++CONFIG_RPS=y
++CONFIG_RFS_ACCEL=y
++CONFIG_XPS=y
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# CONFIG_HAMRADIO is not set
++CONFIG_CAN=y
++CONFIG_CAN_RAW=y
++CONFIG_CAN_BCM=y
++
++#
++# CAN Device Drivers
++#
++CONFIG_CAN_VCAN=y
++# CONFIG_CAN_SLCAN is not set
++CONFIG_CAN_DEV=y
++CONFIG_CAN_CALC_BITTIMING=y
++# CONFIG_CAN_MCP251X is not set
++CONFIG_HAVE_CAN_FLEXCAN=y
++CONFIG_CAN_FLEXCAN=y
++# CONFIG_CAN_SJA1000 is not set
++# CONFIG_CAN_C_CAN is not set
++
++#
++# CAN USB interfaces
++#
++# CONFIG_CAN_EMS_USB is not set
++# CONFIG_CAN_ESD_USB2 is not set
++# CONFIG_CAN_SOFTING is not set
++# CONFIG_CAN_DEBUG_DEVICES is not set
++# CONFIG_IRDA is not set
++CONFIG_BT=y
++CONFIG_BT_L2CAP=y
++CONFIG_BT_SCO=y
++CONFIG_BT_RFCOMM=y
++CONFIG_BT_RFCOMM_TTY=y
++CONFIG_BT_BNEP=y
++CONFIG_BT_BNEP_MC_FILTER=y
++CONFIG_BT_BNEP_PROTO_FILTER=y
++CONFIG_BT_HIDP=y
++
++#
++# Bluetooth device drivers
++#
++# CONFIG_BT_HCIBTUSB is not set
++# CONFIG_BT_HCIBTSDIO is not set
++CONFIG_BT_HCIUART=y
++# CONFIG_BT_HCIUART_H4 is not set
++# CONFIG_BT_HCIUART_BCSP is not set
++# CONFIG_BT_HCIUART_ATH3K is not set
++CONFIG_BT_HCIUART_LL=y
++# CONFIG_BT_HCIBCM203X is not set
++# CONFIG_BT_HCIBPA10X is not set
++# CONFIG_BT_HCIBFUSB is not set
++# CONFIG_BT_HCIVHCI is not set
++# CONFIG_BT_MRVL is not set
++# CONFIG_BT_ATH3K is not set
++# CONFIG_AF_RXRPC is not set
++CONFIG_FIB_RULES=y
++CONFIG_WIRELESS=y
++CONFIG_WIRELESS_EXT=y
++CONFIG_WEXT_CORE=y
++CONFIG_WEXT_PROC=y
++CONFIG_WEXT_SPY=y
++CONFIG_WEXT_PRIV=y
++CONFIG_CFG80211=y
++# CONFIG_NL80211_TESTMODE is not set
++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
++# CONFIG_CFG80211_REG_DEBUG is not set
++CONFIG_CFG80211_DEFAULT_PS=y
++# CONFIG_CFG80211_DEBUGFS is not set
++# CONFIG_CFG80211_INTERNAL_REGDB is not set
++CONFIG_CFG80211_WEXT=y
++CONFIG_WIRELESS_EXT_SYSFS=y
++CONFIG_LIB80211=y
++CONFIG_LIB80211_CRYPT_WEP=y
++CONFIG_LIB80211_CRYPT_CCMP=y
++CONFIG_LIB80211_CRYPT_TKIP=y
++# CONFIG_LIB80211_DEBUG is not set
++# CONFIG_CFG80211_ALLOW_RECONNECT is not set
++CONFIG_MAC80211=y
++CONFIG_MAC80211_HAS_RC=y
++# CONFIG_MAC80211_RC_PID is not set
++CONFIG_MAC80211_RC_MINSTREL=y
++CONFIG_MAC80211_RC_MINSTREL_HT=y
++CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
++CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
++# CONFIG_MAC80211_MESH is not set
++# CONFIG_MAC80211_LEDS is not set
++# CONFIG_MAC80211_DEBUGFS is not set
++# CONFIG_MAC80211_DEBUG_MENU is not set
++# CONFIG_WIMAX is not set
++CONFIG_RFKILL=y
++CONFIG_RFKILL_LEDS=y
++CONFIG_RFKILL_INPUT=y
++# CONFIG_RFKILL_REGULATOR is not set
++# CONFIG_RFKILL_GPIO is not set
++# CONFIG_NET_9P is not set
++# CONFIG_CAIF is not set
++# CONFIG_CEPH_LIB is not set
++
++#
++# Device Drivers
++#
++
++#
++# Generic Driver Options
++#
++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
++# CONFIG_DEVTMPFS is not set
++CONFIG_STANDALONE=y
++CONFIG_PREVENT_FIRMWARE_BUILD=y
++CONFIG_FW_LOADER=y
++CONFIG_FIRMWARE_IN_KERNEL=y
++CONFIG_EXTRA_FIRMWARE=""
++# CONFIG_SYS_HYPERVISOR is not set
++CONFIG_CONNECTOR=y
++CONFIG_PROC_EVENTS=y
++CONFIG_MTD=y
++# CONFIG_MTD_DEBUG is not set
++# CONFIG_MTD_TESTS is not set
++# CONFIG_MTD_REDBOOT_PARTS is not set
++CONFIG_MTD_CMDLINE_PARTS=y
++# CONFIG_MTD_AFS_PARTS is not set
++# CONFIG_MTD_AR7_PARTS is not set
++
++#
++# User Modules And Translation Layers
++#
++CONFIG_MTD_CHAR=y
++CONFIG_MTD_BLKDEVS=y
++CONFIG_MTD_BLOCK=y
++# CONFIG_FTL is not set
++# CONFIG_NFTL is not set
++# CONFIG_INFTL is not set
++# CONFIG_RFD_FTL is not set
++# CONFIG_SSFDC is not set
++# CONFIG_SM_FTL is not set
++# CONFIG_MTD_OOPS is not set
++# CONFIG_MTD_SWAP is not set
++
++#
++# RAM/ROM/Flash chip drivers
++#
++# CONFIG_MTD_CFI is not set
++# CONFIG_MTD_JEDECPROBE is not set
++CONFIG_MTD_MAP_BANK_WIDTH_1=y
++CONFIG_MTD_MAP_BANK_WIDTH_2=y
++CONFIG_MTD_MAP_BANK_WIDTH_4=y
++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
++CONFIG_MTD_CFI_I1=y
++CONFIG_MTD_CFI_I2=y
++# CONFIG_MTD_CFI_I4 is not set
++# CONFIG_MTD_CFI_I8 is not set
++# CONFIG_MTD_RAM is not set
++# CONFIG_MTD_ROM is not set
++# CONFIG_MTD_ABSENT is not set
++
++#
++# Mapping drivers for chip access
++#
++# CONFIG_MTD_COMPLEX_MAPPINGS is not set
++# CONFIG_MTD_PLATRAM is not set
++
++#
++# Self-contained MTD device drivers
++#
++# CONFIG_MTD_DATAFLASH is not set
++CONFIG_MTD_M25P80=y
++CONFIG_M25PXX_USE_FAST_READ=y
++# CONFIG_MTD_SST25L is not set
++# CONFIG_MTD_SLRAM is not set
++# CONFIG_MTD_PHRAM is not set
++# CONFIG_MTD_MTDRAM is not set
++# CONFIG_MTD_BLOCK2MTD is not set
++
++#
++# Disk-On-Chip Device Drivers
++#
++# CONFIG_MTD_DOC2000 is not set
++# CONFIG_MTD_DOC2001 is not set
++# CONFIG_MTD_DOC2001PLUS is not set
++CONFIG_MTD_NAND_ECC=y
++# CONFIG_MTD_NAND_ECC_SMC is not set
++CONFIG_MTD_NAND=y
++# CONFIG_MTD_NAND_VERIFY_WRITE is not set
++# CONFIG_MTD_NAND_ECC_BCH is not set
++# CONFIG_MTD_SM_COMMON is not set
++# CONFIG_MTD_NAND_MUSEUM_IDS is not set
++# CONFIG_MTD_NAND_GPIO is not set
++CONFIG_MTD_NAND_IDS=y
++# CONFIG_MTD_NAND_DISKONCHIP is not set
++# CONFIG_MTD_NAND_NANDSIM is not set
++# CONFIG_MTD_NAND_GPMI_NAND is not set
++# CONFIG_MTD_NAND_PLATFORM is not set
++# CONFIG_MTD_ALAUDA is not set
++# CONFIG_MTD_ONENAND is not set
++
++#
++# LPDDR flash memory drivers
++#
++# CONFIG_MTD_LPDDR is not set
++CONFIG_MTD_UBI=y
++CONFIG_MTD_UBI_WL_THRESHOLD=4096
++CONFIG_MTD_UBI_BEB_RESERVE=1
++# CONFIG_MTD_UBI_GLUEBI is not set
++# CONFIG_MTD_UBI_DEBUG is not set
++# CONFIG_PARPORT is not set
++CONFIG_BLK_DEV=y
++# CONFIG_BLK_DEV_COW_COMMON is not set
++CONFIG_BLK_DEV_LOOP=y
++# CONFIG_BLK_DEV_CRYPTOLOOP is not set
++# CONFIG_BLK_DEV_DRBD is not set
++# CONFIG_BLK_DEV_NBD is not set
++# CONFIG_BLK_DEV_UB is not set
++# CONFIG_BLK_DEV_RAM is not set
++# CONFIG_CDROM_PKTCDVD is not set
++# CONFIG_ATA_OVER_ETH is not set
++# CONFIG_MG_DISK is not set
++# CONFIG_BLK_DEV_RBD is not set
++# CONFIG_SENSORS_LIS3LV02D is not set
++CONFIG_MISC_DEVICES=y
++# CONFIG_AD525X_DPOT is not set
++# CONFIG_PHANTOM is not set
++# CONFIG_INTEL_MID_PTI is not set
++# CONFIG_SGI_IOC4 is not set
++# CONFIG_TIFM_CORE is not set
++# CONFIG_ICS932S401 is not set
++# CONFIG_ENCLOSURE_SERVICES is not set
++# CONFIG_HP_ILO is not set
++# CONFIG_APDS9802ALS is not set
++# CONFIG_ISL29003 is not set
++# CONFIG_ISL29020 is not set
++# CONFIG_SENSORS_TSL2550 is not set
++# CONFIG_SENSORS_BH1780 is not set
++# CONFIG_SENSORS_BH1770 is not set
++# CONFIG_SENSORS_APDS990X is not set
++# CONFIG_HMC6352 is not set
++# CONFIG_SENSORS_AK8975 is not set
++# CONFIG_DS1682 is not set
++# CONFIG_TI_DAC7512 is not set
++# CONFIG_BMP085 is not set
++# CONFIG_PCH_PHUB is not set
++CONFIG_MXS_PERFMON=m
++# CONFIG_WL127X_RFKILL is not set
++# CONFIG_APANIC is not set
++# CONFIG_C2PORT is not set
++
++#
++# EEPROM support
++#
++# CONFIG_EEPROM_AT24 is not set
++# CONFIG_EEPROM_AT25 is not set
++# CONFIG_EEPROM_LEGACY is not set
++# CONFIG_EEPROM_MAX6875 is not set
++# CONFIG_EEPROM_93CX6 is not set
++# CONFIG_CB710_CORE is not set
++# CONFIG_IWMC3200TOP is not set
++
++#
++# Texas Instruments shared transport line discipline
++#
++# CONFIG_TI_ST is not set
++# CONFIG_SENSORS_LIS3_SPI is not set
++# CONFIG_SENSORS_LIS3_I2C is not set
++CONFIG_HAVE_IDE=y
++# CONFIG_IDE is not set
++
++#
++# SCSI device support
++#
++CONFIG_SCSI_MOD=y
++# CONFIG_RAID_ATTRS is not set
++CONFIG_SCSI=y
++CONFIG_SCSI_DMA=y
++# CONFIG_SCSI_TGT is not set
++# CONFIG_SCSI_NETLINK is not set
++CONFIG_SCSI_PROC_FS=y
++
++#
++# SCSI support type (disk, tape, CD-ROM)
++#
++CONFIG_BLK_DEV_SD=y
++# CONFIG_CHR_DEV_ST is not set
++# CONFIG_CHR_DEV_OSST is not set
++# CONFIG_BLK_DEV_SR is not set
++# CONFIG_CHR_DEV_SG is not set
++# CONFIG_CHR_DEV_SCH is not set
++CONFIG_SCSI_MULTI_LUN=y
++# CONFIG_SCSI_CONSTANTS is not set
++# CONFIG_SCSI_LOGGING is not set
++# CONFIG_SCSI_SCAN_ASYNC is not set
++CONFIG_SCSI_WAIT_SCAN=m
++
++#
++# SCSI Transports
++#
++# CONFIG_SCSI_SPI_ATTRS is not set
++# CONFIG_SCSI_FC_ATTRS is not set
++# CONFIG_SCSI_ISCSI_ATTRS is not set
++# CONFIG_SCSI_SAS_ATTRS is not set
++# CONFIG_SCSI_SAS_LIBSAS is not set
++# CONFIG_SCSI_SRP_ATTRS is not set
++CONFIG_SCSI_LOWLEVEL=y
++# CONFIG_ISCSI_TCP is not set
++# CONFIG_ISCSI_BOOT_SYSFS is not set
++# CONFIG_SCSI_CXGB3_ISCSI is not set
++# CONFIG_SCSI_CXGB4_ISCSI is not set
++# CONFIG_SCSI_BNX2_ISCSI is not set
++# CONFIG_SCSI_BNX2X_FCOE is not set
++# CONFIG_BE2ISCSI is not set
++# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
++# CONFIG_SCSI_HPSA is not set
++# CONFIG_SCSI_3W_9XXX is not set
++# CONFIG_SCSI_3W_SAS is not set
++# CONFIG_SCSI_ACARD is not set
++# CONFIG_SCSI_AACRAID is not set
++# CONFIG_SCSI_AIC7XXX is not set
++# CONFIG_SCSI_AIC7XXX_OLD is not set
++# CONFIG_SCSI_AIC79XX is not set
++# CONFIG_SCSI_AIC94XX is not set
++# CONFIG_SCSI_MVSAS is not set
++# CONFIG_SCSI_DPT_I2O is not set
++# CONFIG_SCSI_ADVANSYS is not set
++# CONFIG_SCSI_ARCMSR is not set
++# CONFIG_MEGARAID_NEWGEN is not set
++# CONFIG_MEGARAID_LEGACY is not set
++# CONFIG_MEGARAID_SAS is not set
++# CONFIG_SCSI_MPT2SAS is not set
++# CONFIG_SCSI_HPTIOP is not set
++# CONFIG_LIBFC is not set
++# CONFIG_LIBFCOE is not set
++# CONFIG_FCOE is not set
++# CONFIG_SCSI_DMX3191D is not set
++# CONFIG_SCSI_FUTURE_DOMAIN is not set
++# CONFIG_SCSI_IPS is not set
++# CONFIG_SCSI_INITIO is not set
++# CONFIG_SCSI_INIA100 is not set
++# CONFIG_SCSI_STEX is not set
++# CONFIG_SCSI_SYM53C8XX_2 is not set
++# CONFIG_SCSI_IPR is not set
++# CONFIG_SCSI_QLOGIC_1280 is not set
++# CONFIG_SCSI_QLA_FC is not set
++# CONFIG_SCSI_QLA_ISCSI is not set
++# CONFIG_SCSI_LPFC is not set
++# CONFIG_SCSI_DC395x is not set
++# CONFIG_SCSI_DC390T is not set
++# CONFIG_SCSI_NSP32 is not set
++# CONFIG_SCSI_DEBUG is not set
++# CONFIG_SCSI_PMCRAID is not set
++# CONFIG_SCSI_PM8001 is not set
++# CONFIG_SCSI_SRP is not set
++# CONFIG_SCSI_BFA_FC is not set
++# CONFIG_SCSI_DH is not set
++# CONFIG_SCSI_OSD_INITIATOR is not set
++CONFIG_ATA=y
++# CONFIG_ATA_NONSTANDARD is not set
++CONFIG_ATA_VERBOSE_ERROR=y
++# CONFIG_SATA_PMP is not set
++
++#
++# Controllers with non-SFF native interface
++#
++# CONFIG_SATA_AHCI is not set
++CONFIG_SATA_AHCI_PLATFORM=y
++# CONFIG_SATA_INIC162X is not set
++# CONFIG_SATA_ACARD_AHCI is not set
++# CONFIG_SATA_SIL24 is not set
++CONFIG_ATA_SFF=y
++
++#
++# SFF controllers with custom DMA interface
++#
++# CONFIG_PDC_ADMA is not set
++# CONFIG_SATA_QSTOR is not set
++# CONFIG_SATA_SX4 is not set
++CONFIG_ATA_BMDMA=y
++
++#
++# SATA SFF controllers with BMDMA
++#
++# CONFIG_ATA_PIIX is not set
++# CONFIG_SATA_MV is not set
++# CONFIG_SATA_NV is not set
++# CONFIG_SATA_PROMISE is not set
++# CONFIG_SATA_SIL is not set
++# CONFIG_SATA_SIS is not set
++# CONFIG_SATA_SVW is not set
++# CONFIG_SATA_ULI is not set
++# CONFIG_SATA_VIA is not set
++# CONFIG_SATA_VITESSE is not set
++
++#
++# PATA SFF controllers with BMDMA
++#
++# CONFIG_PATA_ALI is not set
++# CONFIG_PATA_AMD is not set
++# CONFIG_PATA_ARASAN_CF is not set
++# CONFIG_PATA_ARTOP is not set
++# CONFIG_PATA_ATIIXP is not set
++# CONFIG_PATA_ATP867X is not set
++# CONFIG_PATA_CMD64X is not set
++# CONFIG_PATA_CS5520 is not set
++# CONFIG_PATA_CS5530 is not set
++# CONFIG_PATA_CS5536 is not set
++# CONFIG_PATA_CYPRESS is not set
++# CONFIG_PATA_EFAR is not set
++# CONFIG_PATA_HPT366 is not set
++# CONFIG_PATA_HPT37X is not set
++# CONFIG_PATA_HPT3X2N is not set
++# CONFIG_PATA_HPT3X3 is not set
++# CONFIG_PATA_IT8213 is not set
++# CONFIG_PATA_IT821X is not set
++# CONFIG_PATA_JMICRON is not set
++# CONFIG_PATA_MARVELL is not set
++# CONFIG_PATA_NETCELL is not set
++# CONFIG_PATA_NINJA32 is not set
++# CONFIG_PATA_NS87415 is not set
++# CONFIG_PATA_OLDPIIX is not set
++# CONFIG_PATA_OPTIDMA is not set
++# CONFIG_PATA_PDC2027X is not set
++# CONFIG_PATA_PDC_OLD is not set
++# CONFIG_PATA_RADISYS is not set
++# CONFIG_PATA_RDC is not set
++# CONFIG_PATA_SC1200 is not set
++# CONFIG_PATA_SCH is not set
++# CONFIG_PATA_SERVERWORKS is not set
++# CONFIG_PATA_SIL680 is not set
++# CONFIG_PATA_SIS is not set
++# CONFIG_PATA_TOSHIBA is not set
++# CONFIG_PATA_TRIFLEX is not set
++# CONFIG_PATA_VIA is not set
++# CONFIG_PATA_WINBOND is not set
++
++#
++# PIO-only SFF controllers
++#
++# CONFIG_PATA_CMD640_PCI is not set
++# CONFIG_PATA_MPIIX is not set
++# CONFIG_PATA_NS87410 is not set
++# CONFIG_PATA_OPTI is not set
++# CONFIG_PATA_PLATFORM is not set
++# CONFIG_PATA_RZ1000 is not set
++
++#
++# Generic fallback / legacy drivers
++#
++# CONFIG_ATA_GENERIC is not set
++# CONFIG_PATA_LEGACY is not set
++# CONFIG_MD is not set
++# CONFIG_TARGET_CORE is not set
++# CONFIG_FUSION is not set
++
++#
++# IEEE 1394 (FireWire) support
++#
++# CONFIG_FIREWIRE is not set
++# CONFIG_FIREWIRE_NOSY is not set
++# CONFIG_I2O is not set
++CONFIG_NETDEVICES=y
++# CONFIG_DUMMY is not set
++# CONFIG_BONDING is not set
++# CONFIG_MACVLAN is not set
++# CONFIG_EQUALIZER is not set
++CONFIG_TUN=y
++# CONFIG_VETH is not set
++# CONFIG_ARCNET is not set
++CONFIG_MII=y
++CONFIG_PHYLIB=y
++
++#
++# MII PHY device drivers
++#
++# CONFIG_MARVELL_PHY is not set
++# CONFIG_DAVICOM_PHY is not set
++# CONFIG_QSEMI_PHY is not set
++# CONFIG_LXT_PHY is not set
++# CONFIG_CICADA_PHY is not set
++# CONFIG_VITESSE_PHY is not set
++# CONFIG_SMSC_PHY is not set
++# CONFIG_BROADCOM_PHY is not set
++# CONFIG_ICPLUS_PHY is not set
++# CONFIG_REALTEK_PHY is not set
++# CONFIG_NATIONAL_PHY is not set
++# CONFIG_STE10XP is not set
++# CONFIG_LSI_ET1011C_PHY is not set
++CONFIG_MICREL_PHY=y
++# CONFIG_FIXED_PHY is not set
++# CONFIG_MDIO_BITBANG is not set
++CONFIG_NET_ETHERNET=y
++# CONFIG_AX88796 is not set
++# CONFIG_HAPPYMEAL is not set
++# CONFIG_SUNGEM is not set
++# CONFIG_CASSINI is not set
++# CONFIG_NET_VENDOR_3COM is not set
++# CONFIG_SMC91X is not set
++# CONFIG_DM9000 is not set
++# CONFIG_ENC28J60 is not set
++# CONFIG_ETHOC is not set
++# CONFIG_SMC911X is not set
++# CONFIG_SMSC911X is not set
++# CONFIG_DNET is not set
++# CONFIG_NET_TULIP is not set
++# CONFIG_HP100 is not set
++# CONFIG_IBM_NEW_EMAC_ZMII is not set
++# CONFIG_IBM_NEW_EMAC_RGMII is not set
++# CONFIG_IBM_NEW_EMAC_TAH is not set
++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
++# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
++# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
++# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
++# CONFIG_NET_PCI is not set
++# CONFIG_B44 is not set
++# CONFIG_KS8842 is not set
++# CONFIG_KS8851 is not set
++# CONFIG_KS8851_MLL is not set
++CONFIG_FEC=y
++# CONFIG_FEC_NAPI is not set
++# CONFIG_FEC_1588 is not set
++# CONFIG_ATL2 is not set
++# CONFIG_FTMAC100 is not set
++# CONFIG_NETDEV_1000 is not set
++# CONFIG_NETDEV_10000 is not set
++# CONFIG_TR is not set
++CONFIG_WLAN=y
++# CONFIG_LIBERTAS_THINFIRM is not set
++# CONFIG_ATMEL is not set
++# CONFIG_AT76C50X_USB is not set
++# CONFIG_PRISM54 is not set
++# CONFIG_USB_ZD1201 is not set
++# CONFIG_USB_NET_RNDIS_WLAN is not set
++# CONFIG_RTL8180 is not set
++# CONFIG_RTL8187 is not set
++# CONFIG_ADM8211 is not set
++# CONFIG_MAC80211_HWSIM is not set
++# CONFIG_MWL8K is not set
++# CONFIG_WIFI_CONTROL_FUNC is not set
++# CONFIG_ATH_COMMON is not set
++# CONFIG_B43 is not set
++# CONFIG_B43LEGACY is not set
++# CONFIG_BCM4329 is not set
++# CONFIG_BCMDHD is not set
++CONFIG_HOSTAP=y
++# CONFIG_HOSTAP_FIRMWARE is not set
++# CONFIG_HOSTAP_PLX is not set
++# CONFIG_HOSTAP_PCI is not set
++# CONFIG_IPW2100 is not set
++# CONFIG_IPW2200 is not set
++# CONFIG_IWLAGN is not set
++# CONFIG_IWL4965 is not set
++# CONFIG_IWL3945 is not set
++# CONFIG_IWM is not set
++# CONFIG_LIBERTAS is not set
++# CONFIG_HERMES is not set
++# CONFIG_P54_COMMON is not set
++# CONFIG_RT2X00 is not set
++# CONFIG_RTL8192CE is not set
++# CONFIG_RTL8192SE is not set
++# CONFIG_RTL8192CU is not set
++# CONFIG_WL1251 is not set
++CONFIG_WL12XX_MENU=y
++CONFIG_WL12XX=y
++# CONFIG_WL12XX_HT is not set
++# CONFIG_WL12XX_SPI is not set
++CONFIG_WL12XX_SDIO=m
++# CONFIG_WL12XX_SDIO_TEST is not set
++CONFIG_WL12XX_PLATFORM_DATA=y
++# CONFIG_ZD1211RW is not set
++# CONFIG_MWIFIEX is not set
++
++#
++# Enable WiMAX (Networking options) to see the WiMAX drivers
++#
++
++#
++# USB Network Adapters
++#
++# CONFIG_USB_CATC is not set
++# CONFIG_USB_KAWETH is not set
++# CONFIG_USB_PEGASUS is not set
++# CONFIG_USB_RTL8150 is not set
++# CONFIG_USB_USBNET is not set
++# CONFIG_USB_HSO is not set
++# CONFIG_USB_IPHETH is not set
++# CONFIG_WAN is not set
++
++#
++# CAIF transport drivers
++#
++# CONFIG_PPP is not set
++# CONFIG_SLIP is not set
++# CONFIG_NETCONSOLE is not set
++# CONFIG_NETPOLL is not set
++# CONFIG_NET_POLL_CONTROLLER is not set
++# CONFIG_ISDN is not set
++# CONFIG_PHONE is not set
++
++#
++# Input device support
++#
++CONFIG_INPUT=y
++# CONFIG_INPUT_FF_MEMLESS is not set
++CONFIG_INPUT_POLLDEV=y
++# CONFIG_INPUT_SPARSEKMAP is not set
++
++#
++# Userland interfaces
++#
++CONFIG_INPUT_MOUSEDEV=y
++CONFIG_INPUT_MOUSEDEV_PSAUX=y
++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
++# CONFIG_INPUT_JOYDEV is not set
++CONFIG_INPUT_EVDEV=y
++# CONFIG_INPUT_EVBUG is not set
++# CONFIG_INPUT_APMPOWER is not set
++
++#
++# Input Device Drivers
++#
++CONFIG_INPUT_KEYBOARD=y
++# CONFIG_KEYBOARD_ADP5588 is not set
++# CONFIG_KEYBOARD_ADP5589 is not set
++CONFIG_KEYBOARD_ATKBD=y
++# CONFIG_KEYBOARD_QT1070 is not set
++# CONFIG_KEYBOARD_QT2160 is not set
++# CONFIG_KEYBOARD_LKKBD is not set
++CONFIG_KEYBOARD_GPIO=y
++# CONFIG_KEYBOARD_TCA6416 is not set
++# CONFIG_KEYBOARD_MATRIX is not set
++# CONFIG_KEYBOARD_LM8323 is not set
++# CONFIG_KEYBOARD_MAX7359 is not set
++# CONFIG_KEYBOARD_MCS is not set
++# CONFIG_KEYBOARD_MPR121 is not set
++# CONFIG_KEYBOARD_IMX is not set
++# CONFIG_KEYBOARD_NEWTON is not set
++# CONFIG_KEYBOARD_OPENCORES is not set
++# CONFIG_KEYBOARD_STOWAWAY is not set
++# CONFIG_KEYBOARD_SUNKBD is not set
++# CONFIG_KEYBOARD_XTKBD is not set
++# CONFIG_KEYBOARD_MXC is not set
++# CONFIG_INPUT_MOUSE is not set
++# CONFIG_INPUT_JOYSTICK is not set
++# CONFIG_INPUT_TABLET is not set
++CONFIG_INPUT_TOUCHSCREEN=y
++# CONFIG_TOUCHSCREEN_ADS7846 is not set
++# CONFIG_TOUCHSCREEN_AD7877 is not set
++# CONFIG_TOUCHSCREEN_AD7879 is not set
++# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
++# CONFIG_TOUCHSCREEN_BU21013 is not set
++# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set
++# CONFIG_TOUCHSCREEN_DYNAPRO is not set
++# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
++# CONFIG_TOUCHSCREEN_EETI is not set
++CONFIG_TOUCHSCREEN_EGALAX=y
++# CONFIG_TOUCHSCREEN_ELAN is not set
++# CONFIG_TOUCHSCREEN_FUJITSU is not set
++# CONFIG_TOUCHSCREEN_GUNZE is not set
++# CONFIG_TOUCHSCREEN_ELO is not set
++# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
++# CONFIG_TOUCHSCREEN_MAX11801 is not set
++CONFIG_TOUCHSCREEN_FT5X06=y
++CONFIG_TOUCHSCREEN_FT5X06_SINGLE_TOUCH=y
++# CONFIG_TOUCHSCREEN_MCS5000 is not set
++# CONFIG_TOUCHSCREEN_MTOUCH is not set
++# CONFIG_TOUCHSCREEN_INEXIO is not set
++# CONFIG_TOUCHSCREEN_MK712 is not set
++# CONFIG_TOUCHSCREEN_PENMOUNT is not set
++# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI is not set
++# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
++# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
++# CONFIG_TOUCHSCREEN_WM97XX is not set
++# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
++# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
++# CONFIG_TOUCHSCREEN_TSC2005 is not set
++# CONFIG_TOUCHSCREEN_TSC2007 is not set
++CONFIG_TOUCHSCREEN_TSC2004=y
++# CONFIG_TOUCHSCREEN_W90X900 is not set
++# CONFIG_TOUCHSCREEN_ST1232 is not set
++# CONFIG_TOUCHSCREEN_P1003 is not set
++# CONFIG_TOUCHSCREEN_TPS6507X is not set
++CONFIG_INPUT_MISC=y
++# CONFIG_INPUT_AD714X is not set
++# CONFIG_INPUT_ATI_REMOTE is not set
++# CONFIG_INPUT_ATI_REMOTE2 is not set
++# CONFIG_INPUT_KEYCHORD is not set
++# CONFIG_INPUT_KEYSPAN_REMOTE is not set
++# CONFIG_INPUT_POWERMATE is not set
++# CONFIG_INPUT_YEALINK is not set
++# CONFIG_INPUT_CM109 is not set
++CONFIG_INPUT_UINPUT=y
++# CONFIG_INPUT_GPIO is not set
++# CONFIG_INPUT_PCF8574 is not set
++# CONFIG_INPUT_PWM_BEEPER is not set
++# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
++# CONFIG_INPUT_ADXL34X is not set
++# CONFIG_INPUT_CMA3000 is not set
++CONFIG_INPUT_ISL29023=y
++
++#
++# Hardware I/O ports
++#
++CONFIG_SERIO=y
++CONFIG_SERIO_SERPORT=y
++# CONFIG_SERIO_PCIPS2 is not set
++CONFIG_SERIO_LIBPS2=y
++# CONFIG_SERIO_RAW is not set
++# CONFIG_SERIO_ALTERA_PS2 is not set
++# CONFIG_SERIO_PS2MULT is not set
++# CONFIG_GAMEPORT is not set
++
++#
++# Character devices
++#
++CONFIG_VT=y
++CONFIG_CONSOLE_TRANSLATIONS=y
++CONFIG_VT_CONSOLE=y
++CONFIG_HW_CONSOLE=y
++CONFIG_VT_HW_CONSOLE_BINDING=y
++CONFIG_UNIX98_PTYS=y
++# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
++CONFIG_LEGACY_PTYS=y
++CONFIG_LEGACY_PTY_COUNT=256
++# CONFIG_SERIAL_NONSTANDARD is not set
++# CONFIG_NOZOMI is not set
++# CONFIG_N_GSM is not set
++# CONFIG_TRACE_SINK is not set
++CONFIG_DEVMEM=y
++CONFIG_DEVKMEM=y
++
++#
++# Serial drivers
++#
++# CONFIG_SERIAL_8250 is not set
++
++#
++# Non-8250 serial port support
++#
++# CONFIG_SERIAL_MAX3100 is not set
++# CONFIG_SERIAL_MAX3107 is not set
++# CONFIG_SERIAL_MFD_HSU is not set
++CONFIG_SERIAL_IMX=y
++CONFIG_SERIAL_IMX_CONSOLE=y
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++# CONFIG_SERIAL_JSM is not set
++# CONFIG_SERIAL_TIMBERDALE is not set
++# CONFIG_SERIAL_ALTERA_JTAGUART is not set
++# CONFIG_SERIAL_ALTERA_UART is not set
++# CONFIG_SERIAL_IFX6X60 is not set
++# CONFIG_SERIAL_PCH_UART is not set
++# CONFIG_SERIAL_XILINX_PS_UART is not set
++# CONFIG_TTY_PRINTK is not set
++CONFIG_FSL_OTP=y
++# CONFIG_HVC_DCC is not set
++# CONFIG_IPMI_HANDLER is not set
++CONFIG_HW_RANDOM=y
++# CONFIG_HW_RANDOM_TIMERIOMEM is not set
++# CONFIG_R3964 is not set
++# CONFIG_APPLICOM is not set
++# CONFIG_RAW_DRIVER is not set
++# CONFIG_TCG_TPM is not set
++CONFIG_DEVPORT=y
++# CONFIG_DCC_TTY is not set
++# CONFIG_RAMOOPS is not set
++CONFIG_MXS_VIIM=y
++CONFIG_I2C=y
++CONFIG_I2C_BOARDINFO=y
++CONFIG_I2C_COMPAT=y
++CONFIG_I2C_CHARDEV=y
++# CONFIG_I2C_MUX is not set
++CONFIG_I2C_HELPER_AUTO=y
++
++#
++# I2C Hardware Bus support
++#
++
++#
++# PC SMBus host controller drivers
++#
++# CONFIG_I2C_ALI1535 is not set
++# CONFIG_I2C_ALI1563 is not set
++# CONFIG_I2C_ALI15X3 is not set
++# CONFIG_I2C_AMD756 is not set
++# CONFIG_I2C_AMD8111 is not set
++# CONFIG_I2C_I801 is not set
++# CONFIG_I2C_ISCH is not set
++# CONFIG_I2C_PIIX4 is not set
++# CONFIG_I2C_NFORCE2 is not set
++# CONFIG_I2C_SIS5595 is not set
++# CONFIG_I2C_SIS630 is not set
++# CONFIG_I2C_SIS96X is not set
++# CONFIG_I2C_VIA is not set
++# CONFIG_I2C_VIAPRO is not set
++
++#
++# I2C system bus drivers (mostly embedded / system-on-chip)
++#
++# CONFIG_I2C_DESIGNWARE is not set
++# CONFIG_I2C_GPIO is not set
++CONFIG_I2C_IMX=y
++# CONFIG_I2C_INTEL_MID is not set
++# CONFIG_I2C_OCORES is not set
++# CONFIG_I2C_PCA_PLATFORM is not set
++# CONFIG_I2C_PXA_PCI is not set
++# CONFIG_I2C_SIMTEC is not set
++# CONFIG_I2C_XILINX is not set
++# CONFIG_I2C_EG20T is not set
++
++#
++# External I2C/SMBus adapter drivers
++#
++# CONFIG_I2C_DIOLAN_U2C is not set
++# CONFIG_I2C_PARPORT_LIGHT is not set
++# CONFIG_I2C_TAOS_EVM is not set
++# CONFIG_I2C_TINY_USB is not set
++
++#
++# Other I2C/SMBus bus drivers
++#
++# CONFIG_I2C_STUB is not set
++# CONFIG_I2C_DEBUG_CORE is not set
++# CONFIG_I2C_DEBUG_ALGO is not set
++# CONFIG_I2C_DEBUG_BUS is not set
++CONFIG_SPI=y
++CONFIG_SPI_MASTER=y
++
++#
++# SPI Master Controller Drivers
++#
++# CONFIG_SPI_ALTERA is not set
++CONFIG_SPI_BITBANG=y
++# CONFIG_SPI_GPIO is not set
++CONFIG_SPI_IMX_VER_2_3=y
++CONFIG_SPI_IMX=y
++# CONFIG_SPI_OC_TINY is not set
++# CONFIG_SPI_PXA2XX_PCI is not set
++# CONFIG_SPI_TOPCLIFF_PCH is not set
++# CONFIG_SPI_XILINX is not set
++# CONFIG_SPI_DESIGNWARE is not set
++
++#
++# SPI Protocol Masters
++#
++# CONFIG_SPI_SPIDEV is not set
++# CONFIG_SPI_TLE62X0 is not set
++
++#
++# PPS support
++#
++# CONFIG_PPS is not set
++
++#
++# PPS generators support
++#
++
++#
++# PTP clock support
++#
++
++#
++# Enable Device Drivers -> PPS to see the PTP clock options.
++#
++CONFIG_ARCH_REQUIRE_GPIOLIB=y
++CONFIG_GPIOLIB=y
++CONFIG_GPIO_SYSFS=y
++
++#
++# Memory mapped GPIO drivers:
++#
++# CONFIG_GPIO_BASIC_MMIO is not set
++# CONFIG_GPIO_IT8761E is not set
++# CONFIG_GPIO_VX855 is not set
++
++#
++# I2C GPIO expanders:
++#
++# CONFIG_GPIO_MAX7300 is not set
++# CONFIG_GPIO_MAX732X is not set
++# CONFIG_GPIO_PCA953X_IRQ is not set
++# CONFIG_GPIO_PCF857X is not set
++# CONFIG_GPIO_SX150X is not set
++# CONFIG_GPIO_WM8994 is not set
++# CONFIG_GPIO_ADP5588 is not set
++
++#
++# PCI GPIO expanders:
++#
++# CONFIG_GPIO_BT8XX is not set
++# CONFIG_GPIO_ML_IOH is not set
++# CONFIG_GPIO_RDC321X is not set
++
++#
++# SPI GPIO expanders:
++#
++# CONFIG_GPIO_MAX7301 is not set
++# CONFIG_GPIO_MCP23S08 is not set
++# CONFIG_GPIO_MC33880 is not set
++# CONFIG_GPIO_74X164 is not set
++
++#
++# AC97 GPIO expanders:
++#
++
++#
++# MODULbus GPIO expanders:
++#
++# CONFIG_W1 is not set
++CONFIG_POWER_SUPPLY=y
++# CONFIG_POWER_SUPPLY_DEBUG is not set
++# CONFIG_PDA_POWER is not set
++# CONFIG_APM_POWER is not set
++# CONFIG_TEST_POWER is not set
++# CONFIG_BATTERY_DS2780 is not set
++# CONFIG_BATTERY_DS2782 is not set
++# CONFIG_BATTERY_BQ20Z75 is not set
++# CONFIG_BATTERY_BQ27x00 is not set
++# CONFIG_BATTERY_MAX17040 is not set
++# CONFIG_BATTERY_MAX17042 is not set
++# CONFIG_CHARGER_ISP1704 is not set
++# CONFIG_CHARGER_MAX8903 is not set
++# CONFIG_CHARGER_GPIO is not set
++CONFIG_HWMON=y
++# CONFIG_HWMON_VID is not set
++# CONFIG_HWMON_DEBUG_CHIP is not set
++
++#
++# Native drivers
++#
++# CONFIG_SENSORS_AD7414 is not set
++# CONFIG_SENSORS_AD7418 is not set
++# CONFIG_SENSORS_ADCXX is not set
++# CONFIG_SENSORS_ADM1021 is not set
++# CONFIG_SENSORS_ADM1025 is not set
++# CONFIG_SENSORS_ADM1026 is not set
++# CONFIG_SENSORS_ADM1029 is not set
++# CONFIG_SENSORS_ADM1031 is not set
++# CONFIG_SENSORS_ADM9240 is not set
++# CONFIG_SENSORS_ADT7411 is not set
++# CONFIG_SENSORS_ADT7462 is not set
++# CONFIG_SENSORS_ADT7470 is not set
++# CONFIG_SENSORS_ADT7475 is not set
++# CONFIG_SENSORS_ASC7621 is not set
++# CONFIG_SENSORS_ATXP1 is not set
++# CONFIG_SENSORS_DS620 is not set
++# CONFIG_SENSORS_DS1621 is not set
++# CONFIG_SENSORS_I5K_AMB is not set
++# CONFIG_SENSORS_F71805F is not set
++# CONFIG_SENSORS_F71882FG is not set
++# CONFIG_SENSORS_F75375S is not set
++# CONFIG_SENSORS_G760A is not set
++# CONFIG_SENSORS_GL518SM is not set
++# CONFIG_SENSORS_GL520SM is not set
++# CONFIG_SENSORS_GPIO_FAN is not set
++# CONFIG_SENSORS_IT87 is not set
++# CONFIG_SENSORS_JC42 is not set
++# CONFIG_SENSORS_LINEAGE is not set
++# CONFIG_SENSORS_LM63 is not set
++# CONFIG_SENSORS_LM70 is not set
++# CONFIG_SENSORS_LM73 is not set
++# CONFIG_SENSORS_LM75 is not set
++# CONFIG_SENSORS_LM77 is not set
++# CONFIG_SENSORS_LM78 is not set
++# CONFIG_SENSORS_LM80 is not set
++# CONFIG_SENSORS_LM83 is not set
++# CONFIG_SENSORS_LM85 is not set
++# CONFIG_SENSORS_LM87 is not set
++# CONFIG_SENSORS_LM90 is not set
++# CONFIG_SENSORS_LM92 is not set
++# CONFIG_SENSORS_LM93 is not set
++# CONFIG_SENSORS_LTC4151 is not set
++# CONFIG_SENSORS_LTC4215 is not set
++# CONFIG_SENSORS_LTC4245 is not set
++# CONFIG_SENSORS_LTC4261 is not set
++# CONFIG_SENSORS_LM95241 is not set
++# CONFIG_SENSORS_MAX1111 is not set
++# CONFIG_SENSORS_MAX16065 is not set
++# CONFIG_SENSORS_MAX1619 is not set
++# CONFIG_SENSORS_MAX6639 is not set
++# CONFIG_SENSORS_MAX6642 is not set
++CONFIG_SENSORS_MAX17135=y
++# CONFIG_SENSORS_MAX6650 is not set
++# CONFIG_SENSORS_PC87360 is not set
++# CONFIG_SENSORS_PC87427 is not set
++# CONFIG_SENSORS_PCF8591 is not set
++# CONFIG_PMBUS is not set
++# CONFIG_SENSORS_SHT15 is not set
++# CONFIG_SENSORS_SHT21 is not set
++# CONFIG_SENSORS_SIS5595 is not set
++# CONFIG_SENSORS_SMM665 is not set
++# CONFIG_SENSORS_DME1737 is not set
++# CONFIG_SENSORS_EMC1403 is not set
++# CONFIG_SENSORS_EMC2103 is not set
++# CONFIG_SENSORS_EMC6W201 is not set
++# CONFIG_SENSORS_SMSC47M1 is not set
++# CONFIG_SENSORS_SMSC47M192 is not set
++# CONFIG_SENSORS_SMSC47B397 is not set
++# CONFIG_SENSORS_SCH5627 is not set
++# CONFIG_SENSORS_ADS1015 is not set
++# CONFIG_SENSORS_ADS7828 is not set
++# CONFIG_SENSORS_ADS7871 is not set
++# CONFIG_SENSORS_AMC6821 is not set
++# CONFIG_SENSORS_THMC50 is not set
++# CONFIG_SENSORS_TMP102 is not set
++# CONFIG_SENSORS_TMP401 is not set
++# CONFIG_SENSORS_TMP421 is not set
++# CONFIG_SENSORS_VIA686A is not set
++# CONFIG_SENSORS_VT1211 is not set
++# CONFIG_SENSORS_VT8231 is not set
++# CONFIG_SENSORS_W83781D is not set
++# CONFIG_SENSORS_W83791D is not set
++# CONFIG_SENSORS_W83792D is not set
++# CONFIG_SENSORS_W83793 is not set
++# CONFIG_SENSORS_W83795 is not set
++# CONFIG_SENSORS_W83L785TS is not set
++# CONFIG_SENSORS_W83L786NG is not set
++# CONFIG_SENSORS_W83627HF is not set
++# CONFIG_SENSORS_W83627EHF is not set
++CONFIG_SENSORS_MAG3110=y
++# CONFIG_MXC_MMA8450 is not set
++CONFIG_MXC_MMA8451=y
++CONFIG_THERMAL=y
++# CONFIG_THERMAL_HWMON is not set
++CONFIG_WATCHDOG=y
++CONFIG_WATCHDOG_NOWAYOUT=y
++
++#
++# Watchdog Device Drivers
++#
++# CONFIG_SOFT_WATCHDOG is not set
++# CONFIG_MPCORE_WATCHDOG is not set
++# CONFIG_MAX63XX_WATCHDOG is not set
++CONFIG_IMX2_WDT=y
++# CONFIG_ALIM7101_WDT is not set
++
++#
++# PCI-based Watchdog Cards
++#
++# CONFIG_PCIPCWATCHDOG is not set
++# CONFIG_WDTPCI is not set
++
++#
++# USB-based Watchdog Cards
++#
++# CONFIG_USBPCWATCHDOG is not set
++CONFIG_SSB_POSSIBLE=y
++
++#
++# Sonics Silicon Backplane
++#
++# CONFIG_SSB is not set
++CONFIG_BCMA_POSSIBLE=y
++
++#
++# Broadcom specific AMBA
++#
++# CONFIG_BCMA is not set
++CONFIG_MFD_SUPPORT=y
++CONFIG_MFD_CORE=y
++# CONFIG_MFD_88PM860X is not set
++# CONFIG_MFD_SM501 is not set
++# CONFIG_MFD_ASIC3 is not set
++# CONFIG_HTC_EGPIO is not set
++# CONFIG_HTC_PASIC3 is not set
++# CONFIG_HTC_I2CPLD is not set
++# CONFIG_UCB1400_CORE is not set
++# CONFIG_TPS6105X is not set
++# CONFIG_TPS65010 is not set
++# CONFIG_TPS6507X is not set
++# CONFIG_MFD_TPS6586X is not set
++# CONFIG_TWL4030_CORE is not set
++# CONFIG_MFD_STMPE is not set
++# CONFIG_MFD_TC3589X is not set
++# CONFIG_MFD_TMIO is not set
++# CONFIG_MFD_T7L66XB is not set
++# CONFIG_MFD_TC6387XB is not set
++# CONFIG_MFD_TC6393XB is not set
++# CONFIG_PMIC_DA903X is not set
++# CONFIG_PMIC_ADP5520 is not set
++# CONFIG_MFD_MAX8925 is not set
++# CONFIG_MFD_MAX8997 is not set
++# CONFIG_MFD_MAX8998 is not set
++# CONFIG_MFD_WM8400 is not set
++# CONFIG_MFD_WM831X_I2C is not set
++# CONFIG_MFD_WM831X_SPI is not set
++# CONFIG_MFD_WM8350_I2C is not set
++CONFIG_MFD_WM8994=y
++# CONFIG_MFD_PCF50633 is not set
++# CONFIG_PMIC_DIALOG is not set
++# CONFIG_MFD_MC_PMIC is not set
++# CONFIG_MFD_MC34708 is not set
++CONFIG_MFD_PFUZE=y
++# CONFIG_MFD_MC13XXX is not set
++# CONFIG_ABX500_CORE is not set
++# CONFIG_EZX_PCAP is not set
++# CONFIG_MFD_TIMBERDALE is not set
++# CONFIG_LPC_SCH is not set
++# CONFIG_MFD_RDC321X is not set
++# CONFIG_MFD_JANZ_CMODIO is not set
++# CONFIG_MFD_VX855 is not set
++# CONFIG_MFD_WL1273_CORE is not set
++# CONFIG_MFD_TPS65910 is not set
++CONFIG_MFD_MAX17135=y
++CONFIG_MFD_MXC_HDMI=y
++CONFIG_REGULATOR=y
++# CONFIG_REGULATOR_DEBUG is not set
++# CONFIG_REGULATOR_DUMMY is not set
++CONFIG_REGULATOR_FIXED_VOLTAGE=y
++# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
++# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
++# CONFIG_REGULATOR_BQ24022 is not set
++# CONFIG_REGULATOR_MAX1586 is not set
++# CONFIG_REGULATOR_MAX8649 is not set
++# CONFIG_REGULATOR_MAX8660 is not set
++# CONFIG_REGULATOR_MAX8952 is not set
++# CONFIG_REGULATOR_WM8994 is not set
++# CONFIG_REGULATOR_LP3971 is not set
++# CONFIG_REGULATOR_LP3972 is not set
++# CONFIG_REGULATOR_MC34708 is not set
++CONFIG_REGULATOR_PFUZE100=y
++# CONFIG_REGULATOR_TPS65023 is not set
++# CONFIG_REGULATOR_TPS6507X is not set
++# CONFIG_REGULATOR_ISL6271A is not set
++# CONFIG_REGULATOR_AD5398 is not set
++CONFIG_REGULATOR_ANATOP=y
++# CONFIG_REGULATOR_TPS6524X is not set
++CONFIG_REGULATOR_MAX17135=y
++CONFIG_MEDIA_SUPPORT=y
++
++#
++# Multimedia core support
++#
++# CONFIG_MEDIA_CONTROLLER is not set
++CONFIG_VIDEO_DEV=y
++CONFIG_VIDEO_V4L2_COMMON=y
++# CONFIG_DVB_CORE is not set
++CONFIG_VIDEO_MEDIA=y
++
++#
++# Multimedia drivers
++#
++# CONFIG_RC_CORE is not set
++# CONFIG_MEDIA_ATTACH is not set
++CONFIG_MEDIA_TUNER=y
++# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
++CONFIG_MEDIA_TUNER_SIMPLE=y
++CONFIG_MEDIA_TUNER_TDA8290=y
++CONFIG_MEDIA_TUNER_TDA827X=y
++CONFIG_MEDIA_TUNER_TDA18271=y
++CONFIG_MEDIA_TUNER_TDA9887=y
++CONFIG_MEDIA_TUNER_TEA5761=y
++CONFIG_MEDIA_TUNER_TEA5767=y
++CONFIG_MEDIA_TUNER_MT20XX=y
++CONFIG_MEDIA_TUNER_XC2028=y
++CONFIG_MEDIA_TUNER_XC5000=y
++CONFIG_MEDIA_TUNER_MC44S803=y
++CONFIG_VIDEO_V4L2=y
++CONFIG_VIDEOBUF_GEN=y
++CONFIG_VIDEOBUF_DMA_CONTIG=y
++CONFIG_VIDEO_CAPTURE_DRIVERS=y
++# CONFIG_VIDEO_ADV_DEBUG is not set
++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
++# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
++
++#
++# Encoders, decoders, sensors and other helper chips
++#
++
++#
++# Audio decoders, processors and mixers
++#
++# CONFIG_VIDEO_TVAUDIO is not set
++# CONFIG_VIDEO_TDA7432 is not set
++# CONFIG_VIDEO_TDA9840 is not set
++# CONFIG_VIDEO_TEA6415C is not set
++# CONFIG_VIDEO_TEA6420 is not set
++# CONFIG_VIDEO_MSP3400 is not set
++# CONFIG_VIDEO_CS5345 is not set
++# CONFIG_VIDEO_CS53L32A is not set
++# CONFIG_VIDEO_TLV320AIC23B is not set
++# CONFIG_VIDEO_WM8775 is not set
++# CONFIG_VIDEO_WM8739 is not set
++# CONFIG_VIDEO_VP27SMPX is not set
++
++#
++# RDS decoders
++#
++# CONFIG_VIDEO_SAA6588 is not set
++
++#
++# Video decoders
++#
++# CONFIG_VIDEO_ADV7180 is not set
++# CONFIG_VIDEO_BT819 is not set
++# CONFIG_VIDEO_BT856 is not set
++# CONFIG_VIDEO_BT866 is not set
++# CONFIG_VIDEO_KS0127 is not set
++# CONFIG_VIDEO_SAA7110 is not set
++# CONFIG_VIDEO_SAA711X is not set
++# CONFIG_VIDEO_SAA7191 is not set
++# CONFIG_VIDEO_TVP514X is not set
++# CONFIG_VIDEO_TVP5150 is not set
++# CONFIG_VIDEO_TVP7002 is not set
++# CONFIG_VIDEO_VPX3220 is not set
++
++#
++# Video and audio decoders
++#
++# CONFIG_VIDEO_SAA717X is not set
++# CONFIG_VIDEO_CX25840 is not set
++
++#
++# MPEG video encoders
++#
++# CONFIG_VIDEO_CX2341X is not set
++
++#
++# Video encoders
++#
++# CONFIG_VIDEO_SAA7127 is not set
++# CONFIG_VIDEO_SAA7185 is not set
++# CONFIG_VIDEO_ADV7170 is not set
++# CONFIG_VIDEO_ADV7175 is not set
++# CONFIG_VIDEO_ADV7343 is not set
++# CONFIG_VIDEO_AK881X is not set
++
++#
++# Camera sensor devices
++#
++# CONFIG_VIDEO_OV7670 is not set
++# CONFIG_VIDEO_MT9V011 is not set
++# CONFIG_VIDEO_TCM825X is not set
++
++#
++# Video improvement chips
++#
++# CONFIG_VIDEO_UPD64031A is not set
++# CONFIG_VIDEO_UPD64083 is not set
++
++#
++# Miscelaneous helper chips
++#
++# CONFIG_VIDEO_THS7303 is not set
++# CONFIG_VIDEO_M52790 is not set
++# CONFIG_VIDEO_VIVI is not set
++CONFIG_VIDEO_MXC_CAMERA=m
++
++#
++# MXC Camera/V4L2 PRP Features support
++#
++CONFIG_VIDEO_MXC_IPU_CAMERA=y
++# CONFIG_VIDEO_MXC_CSI_CAMERA is not set
++# CONFIG_MXC_CAMERA_MICRON111 is not set
++# CONFIG_MXC_CAMERA_OV2640 is not set
++CONFIG_MXC_CAMERA_OV3640=m
++CONFIG_MXC_CAMERA_OV5640=m
++CONFIG_MXC_CAMERA_OV8820_MIPI=m
++CONFIG_MXC_CAMERA_OV5642=m
++CONFIG_MXC_TVIN_ADV7180=m
++CONFIG_MXC_CAMERA_OV5640_MIPI=m
++CONFIG_MXC_CAMERA_SENSOR_CLK=m
++CONFIG_MXC_IPU_DEVICE_QUEUE_SDC=m
++CONFIG_MXC_IPU_PRP_ENC=m
++CONFIG_MXC_IPU_CSI_ENC=m
++CONFIG_VIDEO_MXC_OUTPUT=y
++CONFIG_VIDEO_MXC_IPU_OUTPUT=y
++# CONFIG_VIDEO_MXC_IPUV1_WVGA_OUTPUT is not set
++# CONFIG_VIDEO_MXC_OPL is not set
++# CONFIG_VIDEO_CPIA2 is not set
++# CONFIG_VIDEO_SAA7134 is not set
++# CONFIG_VIDEO_MXB is not set
++# CONFIG_VIDEO_HEXIUM_ORION is not set
++# CONFIG_VIDEO_HEXIUM_GEMINI is not set
++# CONFIG_VIDEO_TIMBERDALE is not set
++# CONFIG_VIDEO_CAFE_CCIC is not set
++# CONFIG_VIDEO_SR030PC30 is not set
++# CONFIG_VIDEO_NOON010PC30 is not set
++# CONFIG_SOC_CAMERA is not set
++CONFIG_V4L_USB_DRIVERS=y
++CONFIG_USB_VIDEO_CLASS=m
++CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
++CONFIG_USB_GSPCA=m
++# CONFIG_USB_M5602 is not set
++# CONFIG_USB_STV06XX is not set
++# CONFIG_USB_GL860 is not set
++# CONFIG_USB_GSPCA_BENQ is not set
++# CONFIG_USB_GSPCA_CONEX is not set
++# CONFIG_USB_GSPCA_CPIA1 is not set
++# CONFIG_USB_GSPCA_ETOMS is not set
++# CONFIG_USB_GSPCA_FINEPIX is not set
++# CONFIG_USB_GSPCA_JEILINJ is not set
++# CONFIG_USB_GSPCA_KINECT is not set
++# CONFIG_USB_GSPCA_KONICA is not set
++# CONFIG_USB_GSPCA_MARS is not set
++# CONFIG_USB_GSPCA_MR97310A is not set
++# CONFIG_USB_GSPCA_NW80X is not set
++# CONFIG_USB_GSPCA_OV519 is not set
++# CONFIG_USB_GSPCA_OV534 is not set
++# CONFIG_USB_GSPCA_OV534_9 is not set
++# CONFIG_USB_GSPCA_PAC207 is not set
++# CONFIG_USB_GSPCA_PAC7302 is not set
++# CONFIG_USB_GSPCA_PAC7311 is not set
++# CONFIG_USB_GSPCA_SN9C2028 is not set
++# CONFIG_USB_GSPCA_SN9C20X is not set
++# CONFIG_USB_GSPCA_SONIXB is not set
++# CONFIG_USB_GSPCA_SONIXJ is not set
++# CONFIG_USB_GSPCA_SPCA500 is not set
++# CONFIG_USB_GSPCA_SPCA501 is not set
++# CONFIG_USB_GSPCA_SPCA505 is not set
++# CONFIG_USB_GSPCA_SPCA506 is not set
++# CONFIG_USB_GSPCA_SPCA508 is not set
++# CONFIG_USB_GSPCA_SPCA561 is not set
++# CONFIG_USB_GSPCA_SPCA1528 is not set
++# CONFIG_USB_GSPCA_SQ905 is not set
++# CONFIG_USB_GSPCA_SQ905C is not set
++# CONFIG_USB_GSPCA_SQ930X is not set
++# CONFIG_USB_GSPCA_STK014 is not set
++# CONFIG_USB_GSPCA_STV0680 is not set
++# CONFIG_USB_GSPCA_SUNPLUS is not set
++# CONFIG_USB_GSPCA_T613 is not set
++# CONFIG_USB_GSPCA_TV8532 is not set
++# CONFIG_USB_GSPCA_VC032X is not set
++# CONFIG_USB_GSPCA_VICAM is not set
++# CONFIG_USB_GSPCA_XIRLINK_CIT is not set
++# CONFIG_USB_GSPCA_ZC3XX is not set
++# CONFIG_VIDEO_PVRUSB2 is not set
++# CONFIG_VIDEO_HDPVR is not set
++# CONFIG_VIDEO_USBVISION is not set
++# CONFIG_USB_ET61X251 is not set
++# CONFIG_USB_SN9C102 is not set
++# CONFIG_USB_PWC is not set
++# CONFIG_USB_ZR364XX is not set
++# CONFIG_USB_STKWEBCAM is not set
++# CONFIG_USB_S2255 is not set
++# CONFIG_V4L_MEM2MEM_DRIVERS is not set
++# CONFIG_RADIO_ADAPTERS is not set
++
++#
++# Graphics support
++#
++CONFIG_DRM=m
++CONFIG_DRM_VIVANTE=m
++# CONFIG_VGASTATE is not set
++# CONFIG_VIDEO_OUTPUT_CONTROL is not set
++CONFIG_FB=y
++# CONFIG_FIRMWARE_EDID is not set
++# CONFIG_FB_DDC is not set
++# CONFIG_FB_BOOT_VESA_SUPPORT is not set
++CONFIG_FB_CFB_FILLRECT=y
++CONFIG_FB_CFB_COPYAREA=y
++CONFIG_FB_CFB_IMAGEBLIT=y
++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
++# CONFIG_FB_SYS_FILLRECT is not set
++# CONFIG_FB_SYS_COPYAREA is not set
++# CONFIG_FB_SYS_IMAGEBLIT is not set
++# CONFIG_FB_FOREIGN_ENDIAN is not set
++# CONFIG_FB_SYS_FOPS is not set
++# CONFIG_FB_WMT_GE_ROPS is not set
++CONFIG_FB_DEFERRED_IO=y
++# CONFIG_FB_SVGALIB is not set
++# CONFIG_FB_MACMODES is not set
++# CONFIG_FB_BACKLIGHT is not set
++CONFIG_FB_MODE_HELPERS=y
++# CONFIG_FB_TILEBLITTING is not set
++
++#
++# Frame buffer hardware drivers
++#
++# CONFIG_FB_CIRRUS is not set
++# CONFIG_FB_PM2 is not set
++# CONFIG_FB_CYBER2000 is not set
++# CONFIG_FB_ASILIANT is not set
++# CONFIG_FB_IMSTT is not set
++# CONFIG_FB_UVESA is not set
++# CONFIG_FB_S1D13XXX is not set
++# CONFIG_FB_NVIDIA is not set
++# CONFIG_FB_RIVA is not set
++# CONFIG_FB_MATROX is not set
++# CONFIG_FB_RADEON is not set
++# CONFIG_FB_ATY128 is not set
++# CONFIG_FB_ATY is not set
++# CONFIG_FB_S3 is not set
++# CONFIG_FB_SAVAGE is not set
++# CONFIG_FB_SIS is not set
++# CONFIG_FB_NEOMAGIC is not set
++# CONFIG_FB_KYRO is not set
++# CONFIG_FB_3DFX is not set
++# CONFIG_FB_VOODOO1 is not set
++# CONFIG_FB_VT8623 is not set
++# CONFIG_FB_TRIDENT is not set
++# CONFIG_FB_ARK is not set
++# CONFIG_FB_PM3 is not set
++# CONFIG_FB_CARMINE is not set
++# CONFIG_FB_TMIO is not set
++# CONFIG_FB_UDL is not set
++# CONFIG_FB_VIRTUAL is not set
++# CONFIG_FB_METRONOME is not set
++# CONFIG_FB_MB862XX is not set
++# CONFIG_FB_BROADSHEET is not set
++CONFIG_BACKLIGHT_LCD_SUPPORT=y
++# CONFIG_LCD_CLASS_DEVICE is not set
++CONFIG_BACKLIGHT_CLASS_DEVICE=y
++# CONFIG_BACKLIGHT_GENERIC is not set
++CONFIG_BACKLIGHT_PWM=y
++# CONFIG_BACKLIGHT_ADP8860 is not set
++# CONFIG_BACKLIGHT_ADP8870 is not set
++
++#
++# Display device support
++#
++# CONFIG_DISPLAY_SUPPORT is not set
++CONFIG_FB_MXC=y
++CONFIG_FB_MXC_EDID=y
++CONFIG_FB_MXC_SYNC_PANEL=y
++# CONFIG_FB_MXC_EPSON_VGA_SYNC_PANEL is not set
++CONFIG_FB_MXC_LDB=y
++CONFIG_FB_MXC_MIPI_DSI=y
++CONFIG_FB_MXC_TRULY_WVGA_SYNC_PANEL=y
++# CONFIG_FB_MXC_CLAA_WVGA_SYNC_PANEL is not set
++# CONFIG_FB_MXC_SEIKO_WVGA_SYNC_PANEL is not set
++# CONFIG_FB_MXC_SII902X is not set
++# CONFIG_FB_MXC_CH7026 is not set
++# CONFIG_FB_MXC_TVOUT_CH7024 is not set
++# CONFIG_FB_MXC_ASYNC_PANEL is not set
++# CONFIG_FB_MXC_EINK_PANEL is not set
++# CONFIG_FB_MXC_SIPIX_PANEL is not set
++# CONFIG_FB_MXC_ELCDIF_FB is not set
++CONFIG_FB_MXC_HDMI=y
++
++#
++# Console display driver support
++#
++CONFIG_DUMMY_CONSOLE=y
++CONFIG_FRAMEBUFFER_CONSOLE=y
++# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
++# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
++CONFIG_FONTS=y
++# CONFIG_FONT_8x8 is not set
++CONFIG_FONT_8x16=y
++# CONFIG_FONT_6x11 is not set
++# CONFIG_FONT_7x14 is not set
++# CONFIG_FONT_PEARL_8x8 is not set
++# CONFIG_FONT_ACORN_8x8 is not set
++# CONFIG_FONT_MINI_4x6 is not set
++# CONFIG_FONT_SUN8x16 is not set
++# CONFIG_FONT_SUN12x22 is not set
++# CONFIG_FONT_10x18 is not set
++CONFIG_LOGO=y
++CONFIG_LOGO_LINUX_MONO=y
++CONFIG_LOGO_LINUX_VGA16=y
++CONFIG_LOGO_LINUX_CLUT224=y
++CONFIG_SOUND=y
++# CONFIG_SOUND_OSS_CORE is not set
++CONFIG_SND=y
++CONFIG_SND_TIMER=y
++CONFIG_SND_PCM=y
++CONFIG_SND_HWDEP=y
++CONFIG_SND_RAWMIDI=y
++CONFIG_SND_JACK=y
++# CONFIG_SND_SEQUENCER is not set
++# CONFIG_SND_MIXER_OSS is not set
++# CONFIG_SND_PCM_OSS is not set
++# CONFIG_SND_HRTIMER is not set
++# CONFIG_SND_DYNAMIC_MINORS is not set
++CONFIG_SND_SUPPORT_OLD_API=y
++CONFIG_SND_VERBOSE_PROCFS=y
++# CONFIG_SND_VERBOSE_PRINTK is not set
++# CONFIG_SND_DEBUG is not set
++# CONFIG_SND_RAWMIDI_SEQ is not set
++# CONFIG_SND_OPL3_LIB_SEQ is not set
++# CONFIG_SND_OPL4_LIB_SEQ is not set
++# CONFIG_SND_SBAWE_SEQ is not set
++# CONFIG_SND_EMU10K1_SEQ is not set
++CONFIG_SND_DRIVERS=y
++# CONFIG_SND_DUMMY is not set
++# CONFIG_SND_ALOOP is not set
++# CONFIG_SND_MTPAV is not set
++# CONFIG_SND_SERIAL_U16550 is not set
++# CONFIG_SND_MPU401 is not set
++CONFIG_SND_ARM=y
++CONFIG_SND_SPI=y
++CONFIG_SND_USB=y
++CONFIG_SND_USB_AUDIO=y
++# CONFIG_SND_USB_UA101 is not set
++# CONFIG_SND_USB_CAIAQ is not set
++# CONFIG_SND_USB_6FIRE is not set
++CONFIG_SND_SOC=y
++# CONFIG_SND_SOC_CACHE_LZO is not set
++CONFIG_SND_SOC_AC97_BUS=y
++CONFIG_SND_IMX_SOC=y
++CONFIG_SND_MXC_SOC_MX2=y
++CONFIG_SND_MXC_SOC_SPDIF_DAI=y
++CONFIG_SND_SOC_IMX_SGTL5000=y
++# CONFIG_SND_SOC_IMX_WM8958 is not set
++# CONFIG_SND_SOC_IMX_WM8962 is not set
++# CONFIG_SND_SOC_IMX_SI4763 is not set
++CONFIG_SND_SOC_IMX_SPDIF=y
++CONFIG_SND_SOC_IMX_HDMI=y
++CONFIG_SND_SOC_I2C_AND_SPI=y
++# CONFIG_SND_SOC_ALL_CODECS is not set
++CONFIG_SND_SOC_MXC_HDMI=y
++CONFIG_SND_SOC_MXC_SPDIF=y
++CONFIG_SND_SOC_SGTL5000=y
++# CONFIG_SOUND_PRIME is not set
++CONFIG_AC97_BUS=y
++CONFIG_HID_SUPPORT=y
++CONFIG_HID=y
++CONFIG_HIDRAW=y
++
++#
++# USB Input Devices
++#
++CONFIG_USB_HID=y
++# CONFIG_HID_PID is not set
++# CONFIG_USB_HIDDEV is not set
++
++#
++# Special HID drivers
++#
++# CONFIG_HID_A4TECH is not set
++# CONFIG_HID_ACRUX is not set
++# CONFIG_HID_APPLE is not set
++# CONFIG_HID_BELKIN is not set
++# CONFIG_HID_CHERRY is not set
++# CONFIG_HID_CHICONY is not set
++# CONFIG_HID_PRODIKEYS is not set
++# CONFIG_HID_CYPRESS is not set
++# CONFIG_HID_DRAGONRISE is not set
++# CONFIG_HID_EMS_FF is not set
++# CONFIG_HID_ELECOM is not set
++# CONFIG_HID_EZKEY is not set
++# CONFIG_HID_KEYTOUCH is not set
++# CONFIG_HID_KYE is not set
++# CONFIG_HID_UCLOGIC is not set
++# CONFIG_HID_WALTOP is not set
++# CONFIG_HID_GYRATION is not set
++# CONFIG_HID_TWINHAN is not set
++# CONFIG_HID_KENSINGTON is not set
++# CONFIG_HID_LCPOWER is not set
++# CONFIG_HID_LOGITECH is not set
++# CONFIG_HID_MAGICMOUSE is not set
++# CONFIG_HID_MICROSOFT is not set
++# CONFIG_HID_MONTEREY is not set
++# CONFIG_HID_MULTITOUCH is not set
++# CONFIG_HID_NTRIG is not set
++# CONFIG_HID_ORTEK is not set
++# CONFIG_HID_PANTHERLORD is not set
++# CONFIG_HID_PETALYNX is not set
++# CONFIG_HID_PICOLCD is not set
++CONFIG_HID_QUANTA=y
++# CONFIG_HID_ROCCAT is not set
++# CONFIG_HID_ROCCAT_ARVO is not set
++# CONFIG_HID_ROCCAT_KONE is not set
++# CONFIG_HID_ROCCAT_KONEPLUS is not set
++# CONFIG_HID_ROCCAT_KOVAPLUS is not set
++# CONFIG_HID_ROCCAT_PYRA is not set
++CONFIG_HID_SAMSUNG=m
++CONFIG_HID_SONY=m
++CONFIG_HID_SUNPLUS=m
++# CONFIG_HID_GREENASIA is not set
++# CONFIG_HID_SMARTJOYPLUS is not set
++# CONFIG_HID_TOPSEED is not set
++# CONFIG_HID_THRUSTMASTER is not set
++# CONFIG_HID_WACOM is not set
++# CONFIG_HID_ZEROPLUS is not set
++# CONFIG_HID_ZYDACRON is not set
++CONFIG_USB_SUPPORT=y
++CONFIG_USB_ARCH_HAS_HCD=y
++# CONFIG_USB_ARCH_HAS_OHCI is not set
++CONFIG_USB_ARCH_HAS_EHCI=y
++CONFIG_USB=y
++# CONFIG_USB_DEBUG is not set
++# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
++
++#
++# Miscellaneous USB options
++#
++CONFIG_USB_DEVICEFS=y
++# CONFIG_USB_DEVICE_CLASS is not set
++# CONFIG_USB_DYNAMIC_MINORS is not set
++CONFIG_USB_SUSPEND=y
++CONFIG_USB_OTG=y
++# CONFIG_USB_OTG_WHITELIST is not set
++# CONFIG_USB_OTG_BLACKLIST_HUB is not set
++# CONFIG_USB_MON is not set
++# CONFIG_USB_WUSB is not set
++# CONFIG_USB_WUSB_CBAF is not set
++
++#
++# USB Host Controller Drivers
++#
++# CONFIG_USB_C67X00_HCD is not set
++# CONFIG_USB_XHCI_HCD is not set
++CONFIG_USB_EHCI_HCD=y
++CONFIG_USB_EHCI_ARC=y
++CONFIG_USB_EHCI_ARC_OTG=y
++# CONFIG_USB_EHCI_ARC_HSIC is not set
++# CONFIG_USB_STATIC_IRAM is not set
++CONFIG_USB_EHCI_ROOT_HUB_TT=y
++# CONFIG_USB_EHCI_TT_NEWSCHED is not set
++# CONFIG_USB_EHCI_MXC is not set
++# CONFIG_USB_OXU210HP_HCD is not set
++# CONFIG_USB_ISP116X_HCD is not set
++# CONFIG_USB_ISP1760_HCD is not set
++# CONFIG_USB_ISP1362_HCD is not set
++# CONFIG_USB_OHCI_HCD is not set
++# CONFIG_USB_UHCI_HCD is not set
++# CONFIG_USB_SL811_HCD is not set
++# CONFIG_USB_R8A66597_HCD is not set
++# CONFIG_USB_WHCI_HCD is not set
++# CONFIG_USB_HWA_HCD is not set
++# CONFIG_USB_MUSB_HDRC is not set
++
++#
++# USB Device Class drivers
++#
++CONFIG_USB_ACM=y
++# CONFIG_USB_PRINTER is not set
++# CONFIG_USB_WDM is not set
++# CONFIG_USB_TMC is not set
++
++#
++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
++#
++
++#
++# also be needed; see USB_STORAGE Help for more info
++#
++CONFIG_USB_STORAGE=y
++# CONFIG_USB_STORAGE_DEBUG is not set
++# CONFIG_USB_STORAGE_REALTEK is not set
++# CONFIG_USB_STORAGE_DATAFAB is not set
++# CONFIG_USB_STORAGE_FREECOM is not set
++# CONFIG_USB_STORAGE_ISD200 is not set
++# CONFIG_USB_STORAGE_USBAT is not set
++# CONFIG_USB_STORAGE_SDDR09 is not set
++# CONFIG_USB_STORAGE_SDDR55 is not set
++# CONFIG_USB_STORAGE_JUMPSHOT is not set
++# CONFIG_USB_STORAGE_ALAUDA is not set
++# CONFIG_USB_STORAGE_ONETOUCH is not set
++# CONFIG_USB_STORAGE_KARMA is not set
++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
++# CONFIG_USB_STORAGE_ENE_UB6250 is not set
++# CONFIG_USB_UAS is not set
++# CONFIG_USB_LIBUSUAL is not set
++
++#
++# USB Imaging devices
++#
++# CONFIG_USB_MDC800 is not set
++# CONFIG_USB_MICROTEK is not set
++
++#
++# USB port drivers
++#
++CONFIG_USB_SERIAL=y
++# CONFIG_USB_SERIAL_CONSOLE is not set
++# CONFIG_USB_EZUSB is not set
++# CONFIG_USB_SERIAL_GENERIC is not set
++# CONFIG_USB_SERIAL_AIRCABLE is not set
++# CONFIG_USB_SERIAL_ARK3116 is not set
++# CONFIG_USB_SERIAL_BELKIN is not set
++# CONFIG_USB_SERIAL_CH341 is not set
++# CONFIG_USB_SERIAL_WHITEHEAT is not set
++# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
++# CONFIG_USB_SERIAL_CP210X is not set
++# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
++# CONFIG_USB_SERIAL_EMPEG is not set
++# CONFIG_USB_SERIAL_FTDI_SIO is not set
++# CONFIG_USB_SERIAL_FUNSOFT is not set
++# CONFIG_USB_SERIAL_VISOR is not set
++# CONFIG_USB_SERIAL_IPAQ is not set
++# CONFIG_USB_SERIAL_IR is not set
++# CONFIG_USB_SERIAL_EDGEPORT is not set
++# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
++# CONFIG_USB_SERIAL_GARMIN is not set
++# CONFIG_USB_SERIAL_IPW is not set
++# CONFIG_USB_SERIAL_IUU is not set
++# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
++# CONFIG_USB_SERIAL_KEYSPAN is not set
++# CONFIG_USB_SERIAL_KLSI is not set
++# CONFIG_USB_SERIAL_KOBIL_SCT is not set
++# CONFIG_USB_SERIAL_MCT_U232 is not set
++# CONFIG_USB_SERIAL_MOS7720 is not set
++# CONFIG_USB_SERIAL_MOS7840 is not set
++# CONFIG_USB_SERIAL_MOTOROLA is not set
++# CONFIG_USB_SERIAL_NAVMAN is not set
++# CONFIG_USB_SERIAL_PL2303 is not set
++# CONFIG_USB_SERIAL_OTI6858 is not set
++# CONFIG_USB_SERIAL_QCAUX is not set
++CONFIG_USB_SERIAL_QUALCOMM=y
++# CONFIG_USB_SERIAL_SPCP8X5 is not set
++# CONFIG_USB_SERIAL_HP4X is not set
++# CONFIG_USB_SERIAL_SAFE is not set
++# CONFIG_USB_SERIAL_SIEMENS_MPI is not set
++# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
++# CONFIG_USB_SERIAL_SYMBOL is not set
++# CONFIG_USB_SERIAL_TI is not set
++# CONFIG_USB_SERIAL_CYBERJACK is not set
++# CONFIG_USB_SERIAL_XIRCOM is not set
++CONFIG_USB_SERIAL_WWAN=y
++CONFIG_USB_SERIAL_OPTION=y
++# CONFIG_USB_SERIAL_OMNINET is not set
++# CONFIG_USB_SERIAL_OPTICON is not set
++# CONFIG_USB_SERIAL_VIVOPAY_SERIAL is not set
++# CONFIG_USB_SERIAL_ZIO is not set
++# CONFIG_USB_SERIAL_SSU100 is not set
++# CONFIG_USB_SERIAL_DEBUG is not set
++
++#
++# USB Miscellaneous drivers
++#
++# CONFIG_USB_EMI62 is not set
++# CONFIG_USB_EMI26 is not set
++# CONFIG_USB_ADUTUX is not set
++# CONFIG_USB_SEVSEG is not set
++# CONFIG_USB_RIO500 is not set
++# CONFIG_USB_LEGOTOWER is not set
++# CONFIG_USB_LCD is not set
++# CONFIG_USB_LED is not set
++# CONFIG_USB_CYPRESS_CY7C63 is not set
++# CONFIG_USB_CYTHERM is not set
++# CONFIG_USB_IDMOUSE is not set
++# CONFIG_USB_FTDI_ELAN is not set
++# CONFIG_USB_APPLEDISPLAY is not set
++# CONFIG_USB_SISUSBVGA is not set
++# CONFIG_USB_LD is not set
++# CONFIG_USB_TRANCEVIBRATOR is not set
++# CONFIG_USB_IOWARRIOR is not set
++# CONFIG_USB_TEST is not set
++# CONFIG_USB_ISIGHTFW is not set
++# CONFIG_USB_YUREX is not set
++CONFIG_USB_GADGET=y
++# CONFIG_USB_GADGET_DEBUG_FILES is not set
++# CONFIG_USB_GADGET_DEBUG_FS is not set
++CONFIG_USB_GADGET_VBUS_DRAW=2
++CONFIG_USB_GADGET_SELECTED=y
++CONFIG_USB_GADGET_ARC=y
++# CONFIG_IMX_USB_CHARGER is not set
++CONFIG_USB_ARC=y
++# CONFIG_USB_GADGET_FSL_USB2 is not set
++# CONFIG_USB_GADGET_FUSB300 is not set
++# CONFIG_USB_GADGET_R8A66597 is not set
++# CONFIG_USB_GADGET_PXA_U2O is not set
++# CONFIG_USB_GADGET_M66592 is not set
++# CONFIG_USB_GADGET_AMD5536UDC is not set
++# CONFIG_USB_GADGET_CI13XXX_PCI is not set
++# CONFIG_USB_GADGET_NET2280 is not set
++# CONFIG_USB_GADGET_GOKU is not set
++# CONFIG_USB_GADGET_LANGWELL is not set
++# CONFIG_USB_GADGET_EG20T is not set
++# CONFIG_USB_GADGET_DUMMY_HCD is not set
++CONFIG_USB_GADGET_DUALSPEED=y
++# CONFIG_USB_ZERO is not set
++# CONFIG_USB_AUDIO is not set
++# CONFIG_USB_ETH is not set
++CONFIG_USB_ETH_RNDIS=y
++# CONFIG_USB_ETH_EEM is not set
++# CONFIG_USB_G_NCM is not set
++# CONFIG_USB_GADGETFS is not set
++# CONFIG_USB_FUNCTIONFS is not set
++CONFIG_USB_FILE_STORAGE=m
++# CONFIG_USB_MASS_STORAGE is not set
++CONFIG_USB_G_SERIAL=m
++# CONFIG_USB_MIDI_GADGET is not set
++# CONFIG_USB_G_PRINTER is not set
++CONFIG_USB_G_ANDROID=y
++# CONFIG_USB_CDC_COMPOSITE is not set
++# CONFIG_USB_G_MULTI is not set
++# CONFIG_USB_G_HID is not set
++# CONFIG_USB_G_DBGP is not set
++# CONFIG_USB_G_WEBCAM is not set
++
++#
++# OTG and related infrastructure
++#
++CONFIG_USB_OTG_UTILS=y
++# CONFIG_USB_GPIO_VBUS is not set
++# CONFIG_USB_ULPI is not set
++# CONFIG_NOP_USB_XCEIV is not set
++CONFIG_MXC_OTG=y
++CONFIG_MMC=y
++# CONFIG_MMC_DEBUG is not set
++CONFIG_MMC_UNSAFE_RESUME=y
++# CONFIG_MMC_CLKGATE is not set
++# CONFIG_MMC_EMBEDDED_SDIO is not set
++# CONFIG_MMC_PARANOID_SD_INIT is not set
++
++#
++# MMC/SD/SDIO Card Drivers
++#
++CONFIG_MMC_BLOCK=y
++CONFIG_MMC_BLOCK_MINORS=8
++CONFIG_MMC_BLOCK_BOUNCE=y
++# CONFIG_SDIO_UART is not set
++# CONFIG_MMC_TEST is not set
++
++#
++# MMC/SD/SDIO Host Controller Drivers
++#
++CONFIG_MMC_SDHCI=y
++CONFIG_MMC_SDHCI_IO_ACCESSORS=y
++# CONFIG_MMC_SDHCI_PCI is not set
++CONFIG_MMC_SDHCI_PLTFM=y
++CONFIG_MMC_SDHCI_ESDHC_IMX=y
++# CONFIG_MMC_TIFM_SD is not set
++# CONFIG_MMC_CB710 is not set
++# CONFIG_MMC_VIA_SDMMC is not set
++# CONFIG_MMC_DW is not set
++# CONFIG_MMC_VUB300 is not set
++# CONFIG_MMC_USHC is not set
++# CONFIG_SDHCI_USE_LEDS_CLASS is not set
++# CONFIG_MEMSTICK is not set
++CONFIG_NEW_LEDS=y
++CONFIG_LEDS_CLASS=y
++
++#
++# LED drivers
++#
++# CONFIG_LEDS_LM3530 is not set
++# CONFIG_LEDS_PCA9532 is not set
++CONFIG_LEDS_GPIO=y
++CONFIG_LEDS_GPIO_PLATFORM=y
++# CONFIG_LEDS_LP3944 is not set
++# CONFIG_LEDS_LP5521 is not set
++# CONFIG_LEDS_LP5523 is not set
++# CONFIG_LEDS_PCA955X is not set
++# CONFIG_LEDS_DAC124S085 is not set
++# CONFIG_LEDS_PWM is not set
++# CONFIG_LEDS_REGULATOR is not set
++# CONFIG_LEDS_BD2802 is not set
++# CONFIG_LEDS_LT3593 is not set
++CONFIG_LEDS_TRIGGERS=y
++
++#
++# LED Triggers
++#
++# CONFIG_LEDS_TRIGGER_TIMER is not set
++# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set
++# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
++CONFIG_LEDS_TRIGGER_GPIO=y
++CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
++
++#
++# iptables trigger is under Netfilter config (LED target)
++#
++
++#
++# LED Triggers
++#
++# CONFIG_NFC_DEVICES is not set
++# CONFIG_ACCESSIBILITY is not set
++CONFIG_RTC_LIB=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_HCTOSYS=y
++CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
++# CONFIG_RTC_DEBUG is not set
++
++#
++# RTC interfaces
++#
++CONFIG_RTC_INTF_SYSFS=y
++CONFIG_RTC_INTF_PROC=y
++CONFIG_RTC_INTF_DEV=y
++CONFIG_RTC_INTF_DEV_UIE_EMUL=y
++# CONFIG_RTC_DRV_TEST is not set
++
++#
++# I2C RTC drivers
++#
++# CONFIG_RTC_DRV_DS1307 is not set
++# CONFIG_RTC_DRV_DS1374 is not set
++# CONFIG_RTC_DRV_DS1672 is not set
++# CONFIG_RTC_DRV_DS3232 is not set
++# CONFIG_RTC_DRV_MAX6900 is not set
++# CONFIG_RTC_DRV_RS5C372 is not set
++# CONFIG_RTC_DRV_ISL1208 is not set
++# CONFIG_RTC_DRV_ISL12022 is not set
++# CONFIG_RTC_DRV_X1205 is not set
++# CONFIG_RTC_DRV_PCF8563 is not set
++# CONFIG_RTC_DRV_PCF8583 is not set
++# CONFIG_RTC_DRV_M41T80 is not set
++# CONFIG_RTC_DRV_BQ32K is not set
++# CONFIG_RTC_DRV_S35390A is not set
++# CONFIG_RTC_DRV_FM3130 is not set
++# CONFIG_RTC_DRV_RX8581 is not set
++# CONFIG_RTC_DRV_RX8025 is not set
++# CONFIG_RTC_DRV_EM3027 is not set
++# CONFIG_RTC_DRV_RV3029C2 is not set
++
++#
++# SPI RTC drivers
++#
++# CONFIG_RTC_DRV_M41T93 is not set
++# CONFIG_RTC_DRV_M41T94 is not set
++# CONFIG_RTC_DRV_DS1305 is not set
++# CONFIG_RTC_DRV_DS1390 is not set
++# CONFIG_RTC_DRV_MAX6902 is not set
++# CONFIG_RTC_DRV_R9701 is not set
++# CONFIG_RTC_DRV_RS5C348 is not set
++# CONFIG_RTC_DRV_DS3234 is not set
++# CONFIG_RTC_DRV_PCF2123 is not set
++
++#
++# Platform RTC drivers
++#
++# CONFIG_RTC_DRV_CMOS is not set
++# CONFIG_RTC_DRV_DS1286 is not set
++# CONFIG_RTC_DRV_DS1511 is not set
++# CONFIG_RTC_DRV_DS1553 is not set
++# CONFIG_RTC_DRV_DS1742 is not set
++# CONFIG_RTC_DRV_STK17TA8 is not set
++# CONFIG_RTC_DRV_M48T86 is not set
++# CONFIG_RTC_DRV_M48T35 is not set
++# CONFIG_RTC_DRV_M48T59 is not set
++# CONFIG_RTC_DRV_MSM6242 is not set
++# CONFIG_RTC_MXC is not set
++# CONFIG_RTC_DRV_MXC_V2 is not set
++CONFIG_RTC_DRV_SNVS=y
++# CONFIG_RTC_DRV_BQ4802 is not set
++# CONFIG_RTC_DRV_RP5C01 is not set
++# CONFIG_RTC_DRV_V3020 is not set
++
++#
++# on-CPU RTC drivers
++#
++CONFIG_DMADEVICES=y
++# CONFIG_DMADEVICES_DEBUG is not set
++
++#
++# DMA Devices
++#
++# CONFIG_DW_DMAC is not set
++CONFIG_MXC_PXP_V2=y
++CONFIG_MXC_PXP_CLIENT_DEVICE=y
++# CONFIG_TIMB_DMA is not set
++CONFIG_IMX_SDMA=y
++# CONFIG_MXS_DMA is not set
++CONFIG_DMA_ENGINE=y
++
++#
++# DMA Clients
++#
++# CONFIG_NET_DMA is not set
++# CONFIG_ASYNC_TX_DMA is not set
++# CONFIG_DMATEST is not set
++# CONFIG_AUXDISPLAY is not set
++# CONFIG_UIO is not set
++# CONFIG_STAGING is not set
++CONFIG_CLKDEV_LOOKUP=y
++CONFIG_CLKSRC_MMIO=y
++
++#
++# MXC support drivers
++#
++CONFIG_MXC_IPU=y
++CONFIG_MXC_IPU_V3=y
++CONFIG_MXC_IPU_V3H=y
++
++#
++# MXC SSI support
++#
++# CONFIG_MXC_SSI is not set
++
++#
++# MXC Digital Audio Multiplexer support
++#
++# CONFIG_MXC_DAM is not set
++
++#
++# MXC PMIC support
++#
++# CONFIG_MXC_PMIC_MC13783 is not set
++# CONFIG_MXC_PMIC_MC13892 is not set
++# CONFIG_MXC_PMIC_MC34704 is not set
++# CONFIG_MXC_PMIC_MC9SDZ60 is not set
++# CONFIG_MXC_PMIC_MC9S08DZ60 is not set
++
++#
++# MXC Security Drivers
++#
++# CONFIG_MXC_SECURITY_SCC is not set
++# CONFIG_MXC_SECURITY_RNG is not set
++
++#
++# MXC MPEG4 Encoder Kernel module support
++#
++# CONFIG_MXC_HMP4E is not set
++
++#
++# MXC HARDWARE EVENT
++#
++# CONFIG_MXC_HWEVENT is not set
++
++#
++# MXC VPU(Video Processing Unit) support
++#
++CONFIG_MXC_VPU=y
++# CONFIG_MXC_VPU_DEBUG is not set
++
++#
++# MXC Asynchronous Sample Rate Converter support
++#
++CONFIG_MXC_ASRC=y
++
++#
++# MXC Bluetooth support
++#
++
++#
++# Broadcom GPS ioctrl support
++#
++
++#
++# MXC Media Local Bus Driver
++#
++# CONFIG_MXC_MLB150 is not set
++
++#
++# i.MX ADC support
++#
++# CONFIG_IMX_ADC is not set
++
++#
++# MXC Vivante GPU support
++#
++CONFIG_MXC_GPU_VIV=m
++
++#
++# ANATOP_THERMAL
++#
++CONFIG_ANATOP_THERMAL=y
++
++#
++# MXC MIPI Support
++#
++CONFIG_MXC_MIPI_CSI2=y
++
++#
++# MXC HDMI CEC (Consumer Electronics Control) support
++#
++# CONFIG_MXC_HDMI_CEC is not set
++
++#
++# File systems
++#
++CONFIG_EXT2_FS=y
++# CONFIG_EXT2_FS_XATTR is not set
++# CONFIG_EXT2_FS_XIP is not set
++CONFIG_EXT3_FS=y
++# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
++CONFIG_EXT3_FS_XATTR=y
++# CONFIG_EXT3_FS_POSIX_ACL is not set
++# CONFIG_EXT3_FS_SECURITY is not set
++CONFIG_EXT4_FS=y
++CONFIG_EXT4_FS_XATTR=y
++# CONFIG_EXT4_FS_POSIX_ACL is not set
++# CONFIG_EXT4_FS_SECURITY is not set
++# CONFIG_EXT4_DEBUG is not set
++CONFIG_JBD=y
++# CONFIG_JBD_DEBUG is not set
++CONFIG_JBD2=y
++# CONFIG_JBD2_DEBUG is not set
++CONFIG_FS_MBCACHE=y
++# CONFIG_REISERFS_FS is not set
++# CONFIG_JFS_FS is not set
++# CONFIG_XFS_FS is not set
++# CONFIG_GFS2_FS is not set
++# CONFIG_BTRFS_FS is not set
++# CONFIG_NILFS2_FS is not set
++# CONFIG_FS_POSIX_ACL is not set
++CONFIG_FILE_LOCKING=y
++CONFIG_FSNOTIFY=y
++CONFIG_DNOTIFY=y
++CONFIG_INOTIFY_USER=y
++# CONFIG_FANOTIFY is not set
++# CONFIG_QUOTA is not set
++# CONFIG_QUOTACTL is not set
++CONFIG_AUTOFS4_FS=y
++# CONFIG_FUSE_FS is not set
++
++#
++# Caches
++#
++# CONFIG_FSCACHE is not set
++
++#
++# CD-ROM/DVD Filesystems
++#
++# CONFIG_ISO9660_FS is not set
++# CONFIG_UDF_FS is not set
++
++#
++# DOS/FAT/NT Filesystems
++#
++CONFIG_FAT_FS=y
++CONFIG_MSDOS_FS=y
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_CODEPAGE=437
++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
++# CONFIG_NTFS_FS is not set
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++CONFIG_PROC_SYSCTL=y
++CONFIG_PROC_PAGE_MONITOR=y
++CONFIG_SYSFS=y
++CONFIG_TMPFS=y
++# CONFIG_TMPFS_POSIX_ACL is not set
++# CONFIG_TMPFS_XATTR is not set
++# CONFIG_HUGETLB_PAGE is not set
++# CONFIG_CONFIGFS_FS is not set
++CONFIG_MISC_FILESYSTEMS=y
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_ECRYPT_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++# CONFIG_YAFFS_FS is not set
++CONFIG_JFFS2_FS=y
++CONFIG_JFFS2_FS_DEBUG=0
++CONFIG_JFFS2_FS_WRITEBUFFER=y
++# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
++# CONFIG_JFFS2_SUMMARY is not set
++# CONFIG_JFFS2_FS_XATTR is not set
++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
++CONFIG_JFFS2_ZLIB=y
++# CONFIG_JFFS2_LZO is not set
++CONFIG_JFFS2_RTIME=y
++# CONFIG_JFFS2_RUBIN is not set
++CONFIG_UBIFS_FS=y
++# CONFIG_UBIFS_FS_XATTR is not set
++# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
++CONFIG_UBIFS_FS_LZO=y
++CONFIG_UBIFS_FS_ZLIB=y
++# CONFIG_UBIFS_FS_DEBUG is not set
++# CONFIG_LOGFS is not set
++CONFIG_CRAMFS=y
++# CONFIG_SQUASHFS is not set
++# CONFIG_VXFS_FS is not set
++# CONFIG_MINIX_FS is not set
++# CONFIG_OMFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_ROMFS_FS is not set
++# CONFIG_PSTORE is not set
++# CONFIG_SYSV_FS is not set
++# CONFIG_UFS_FS is not set
++CONFIG_NETWORK_FILESYSTEMS=y
++CONFIG_NFS_FS=y
++CONFIG_NFS_V3=y
++# CONFIG_NFS_V3_ACL is not set
++# CONFIG_NFS_V4 is not set
++CONFIG_ROOT_NFS=y
++# CONFIG_NFSD is not set
++CONFIG_LOCKD=y
++CONFIG_LOCKD_V4=y
++CONFIG_NFS_COMMON=y
++CONFIG_SUNRPC=y
++# CONFIG_CEPH_FS is not set
++# CONFIG_CIFS is not set
++# CONFIG_NCP_FS is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
++
++#
++# Partition Types
++#
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_ACORN_PARTITION is not set
++# CONFIG_OSF_PARTITION is not set
++# CONFIG_AMIGA_PARTITION is not set
++# CONFIG_ATARI_PARTITION is not set
++# CONFIG_MAC_PARTITION is not set
++CONFIG_MSDOS_PARTITION=y
++# CONFIG_BSD_DISKLABEL is not set
++# CONFIG_MINIX_SUBPARTITION is not set
++# CONFIG_SOLARIS_X86_PARTITION is not set
++# CONFIG_UNIXWARE_DISKLABEL is not set
++# CONFIG_LDM_PARTITION is not set
++# CONFIG_SGI_PARTITION is not set
++# CONFIG_ULTRIX_PARTITION is not set
++# CONFIG_SUN_PARTITION is not set
++# CONFIG_KARMA_PARTITION is not set
++CONFIG_EFI_PARTITION=y
++# CONFIG_SYSV68_PARTITION is not set
++CONFIG_NLS=y
++CONFIG_NLS_DEFAULT="iso8859-1"
++CONFIG_NLS_CODEPAGE_437=y
++# CONFIG_NLS_CODEPAGE_737 is not set
++# CONFIG_NLS_CODEPAGE_775 is not set
++# CONFIG_NLS_CODEPAGE_850 is not set
++# CONFIG_NLS_CODEPAGE_852 is not set
++# CONFIG_NLS_CODEPAGE_855 is not set
++# CONFIG_NLS_CODEPAGE_857 is not set
++# CONFIG_NLS_CODEPAGE_860 is not set
++# CONFIG_NLS_CODEPAGE_861 is not set
++# CONFIG_NLS_CODEPAGE_862 is not set
++# CONFIG_NLS_CODEPAGE_863 is not set
++# CONFIG_NLS_CODEPAGE_864 is not set
++# CONFIG_NLS_CODEPAGE_865 is not set
++# CONFIG_NLS_CODEPAGE_866 is not set
++# CONFIG_NLS_CODEPAGE_869 is not set
++# CONFIG_NLS_CODEPAGE_936 is not set
++# CONFIG_NLS_CODEPAGE_950 is not set
++# CONFIG_NLS_CODEPAGE_932 is not set
++# CONFIG_NLS_CODEPAGE_949 is not set
++# CONFIG_NLS_CODEPAGE_874 is not set
++# CONFIG_NLS_ISO8859_8 is not set
++# CONFIG_NLS_CODEPAGE_1250 is not set
++# CONFIG_NLS_CODEPAGE_1251 is not set
++CONFIG_NLS_ASCII=m
++CONFIG_NLS_ISO8859_1=y
++# CONFIG_NLS_ISO8859_2 is not set
++# CONFIG_NLS_ISO8859_3 is not set
++# CONFIG_NLS_ISO8859_4 is not set
++# CONFIG_NLS_ISO8859_5 is not set
++# CONFIG_NLS_ISO8859_6 is not set
++# CONFIG_NLS_ISO8859_7 is not set
++# CONFIG_NLS_ISO8859_9 is not set
++# CONFIG_NLS_ISO8859_13 is not set
++# CONFIG_NLS_ISO8859_14 is not set
++# CONFIG_NLS_ISO8859_15 is not set
++# CONFIG_NLS_KOI8_R is not set
++# CONFIG_NLS_KOI8_U is not set
++CONFIG_NLS_UTF8=m
++
++#
++# Kernel hacking
++#
++# CONFIG_PRINTK_TIME is not set
++CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
++CONFIG_ENABLE_WARN_DEPRECATED=y
++CONFIG_ENABLE_MUST_CHECK=y
++CONFIG_FRAME_WARN=1024
++CONFIG_MAGIC_SYSRQ=y
++# CONFIG_STRIP_ASM_SYMS is not set
++# CONFIG_UNUSED_SYMBOLS is not set
++CONFIG_DEBUG_FS=y
++# CONFIG_HEADERS_CHECK is not set
++# CONFIG_DEBUG_SECTION_MISMATCH is not set
++# CONFIG_DEBUG_KERNEL is not set
++# CONFIG_HARDLOCKUP_DETECTOR is not set
++# CONFIG_SPARSE_RCU_POINTER is not set
++CONFIG_DEBUG_BUGVERBOSE=y
++# CONFIG_DEBUG_MEMORY_INIT is not set
++CONFIG_RCU_CPU_STALL_TIMEOUT=60
++CONFIG_RCU_CPU_STALL_VERBOSE=y
++# CONFIG_LKDTM is not set
++CONFIG_SYSCTL_SYSCALL_CHECK=y
++CONFIG_HAVE_FUNCTION_TRACER=y
++CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
++CONFIG_HAVE_DYNAMIC_FTRACE=y
++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
++CONFIG_HAVE_C_RECORDMCOUNT=y
++CONFIG_TRACING_SUPPORT=y
++# CONFIG_FTRACE is not set
++# CONFIG_DYNAMIC_DEBUG is not set
++# CONFIG_DMA_API_DEBUG is not set
++# CONFIG_ATOMIC64_SELFTEST is not set
++# CONFIG_SAMPLES is not set
++CONFIG_HAVE_ARCH_KGDB=y
++# CONFIG_TEST_KSTRTOX is not set
++# CONFIG_STRICT_DEVMEM is not set
++CONFIG_ARM_UNWIND=y
++# CONFIG_DEBUG_USER is not set
++# CONFIG_OC_ETM is not set
++
++#
++# Security options
++#
++# CONFIG_KEYS is not set
++# CONFIG_SECURITY_DMESG_RESTRICT is not set
++# CONFIG_SECURITY is not set
++# CONFIG_SECURITYFS is not set
++CONFIG_DEFAULT_SECURITY_DAC=y
++CONFIG_DEFAULT_SECURITY=""
++CONFIG_CRYPTO=y
++
++#
++# Crypto core or helper
++#
++CONFIG_CRYPTO_ALGAPI=y
++CONFIG_CRYPTO_ALGAPI2=y
++CONFIG_CRYPTO_AEAD=y
++CONFIG_CRYPTO_AEAD2=y
++CONFIG_CRYPTO_BLKCIPHER=y
++CONFIG_CRYPTO_BLKCIPHER2=y
++CONFIG_CRYPTO_HASH=y
++CONFIG_CRYPTO_HASH2=y
++CONFIG_CRYPTO_RNG=y
++CONFIG_CRYPTO_RNG2=y
++CONFIG_CRYPTO_PCOMP2=y
++CONFIG_CRYPTO_MANAGER=y
++CONFIG_CRYPTO_MANAGER2=y
++# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set
++CONFIG_CRYPTO_GF128MUL=y
++# CONFIG_CRYPTO_NULL is not set
++# CONFIG_CRYPTO_PCRYPT is not set
++CONFIG_CRYPTO_WORKQUEUE=y
++# CONFIG_CRYPTO_CRYPTD is not set
++CONFIG_CRYPTO_AUTHENC=y
++CONFIG_CRYPTO_TEST=m
++# CONFIG_CRYPTO_CRYPTODEV is not set
++
++#
++# Authenticated Encryption with Associated Data
++#
++CONFIG_CRYPTO_CCM=y
++CONFIG_CRYPTO_GCM=y
++CONFIG_CRYPTO_SEQIV=y
++
++#
++# Block modes
++#
++CONFIG_CRYPTO_CBC=y
++CONFIG_CRYPTO_CTR=y
++CONFIG_CRYPTO_CTS=y
++CONFIG_CRYPTO_ECB=y
++CONFIG_CRYPTO_LRW=y
++CONFIG_CRYPTO_PCBC=y
++CONFIG_CRYPTO_XTS=y
++
++#
++# Hash modes
++#
++# CONFIG_CRYPTO_HMAC is not set
++# CONFIG_CRYPTO_XCBC is not set
++# CONFIG_CRYPTO_VMAC is not set
++
++#
++# Digest
++#
++# CONFIG_CRYPTO_CRC32C is not set
++CONFIG_CRYPTO_GHASH=y
++# CONFIG_CRYPTO_MD4 is not set
++# CONFIG_CRYPTO_MD5 is not set
++CONFIG_CRYPTO_MICHAEL_MIC=y
++# CONFIG_CRYPTO_RMD128 is not set
++# CONFIG_CRYPTO_RMD160 is not set
++# CONFIG_CRYPTO_RMD256 is not set
++# CONFIG_CRYPTO_RMD320 is not set
++# CONFIG_CRYPTO_SHA1 is not set
++# CONFIG_CRYPTO_SHA256 is not set
++# CONFIG_CRYPTO_SHA512 is not set
++# CONFIG_CRYPTO_TGR192 is not set
++# CONFIG_CRYPTO_WP512 is not set
++
++#
++# Ciphers
++#
++CONFIG_CRYPTO_AES=y
++# CONFIG_CRYPTO_ANUBIS is not set
++CONFIG_CRYPTO_ARC4=y
++# CONFIG_CRYPTO_BLOWFISH is not set
++# CONFIG_CRYPTO_CAMELLIA is not set
++# CONFIG_CRYPTO_CAST5 is not set
++# CONFIG_CRYPTO_CAST6 is not set
++CONFIG_CRYPTO_DES=y
++# CONFIG_CRYPTO_FCRYPT is not set
++# CONFIG_CRYPTO_KHAZAD is not set
++# CONFIG_CRYPTO_SALSA20 is not set
++# CONFIG_CRYPTO_SEED is not set
++# CONFIG_CRYPTO_SERPENT is not set
++# CONFIG_CRYPTO_TEA is not set
++# CONFIG_CRYPTO_TWOFISH is not set
++
++#
++# Compression
++#
++CONFIG_CRYPTO_DEFLATE=y
++# CONFIG_CRYPTO_ZLIB is not set
++CONFIG_CRYPTO_LZO=y
++
++#
++# Random Number Generation
++#
++# CONFIG_CRYPTO_ANSI_CPRNG is not set
++# CONFIG_CRYPTO_USER_API_HASH is not set
++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
++CONFIG_CRYPTO_HW=y
++CONFIG_CRYPTO_DEV_FSL_CAAM=y
++CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE=9
++CONFIG_CRYPTO_DEV_FSL_CAAM_INTC=y
++CONFIG_CRYPTO_DEV_FSL_CAAM_INTC_COUNT_THLD=255
++CONFIG_CRYPTO_DEV_FSL_CAAM_INTC_TIME_THLD=2048
++CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API=y
++# CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API is not set
++CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API=y
++# CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_TEST is not set
++# CONFIG_BINARY_PRINTF is not set
++
++#
++# Library routines
++#
++CONFIG_BITREVERSE=y
++CONFIG_RATIONAL=y
++CONFIG_CRC_CCITT=m
++CONFIG_CRC16=y
++# CONFIG_CRC_T10DIF is not set
++# CONFIG_CRC_ITU_T is not set
++CONFIG_CRC32=y
++# CONFIG_CRC7 is not set
++# CONFIG_LIBCRC32C is not set
++CONFIG_ZLIB_INFLATE=y
++CONFIG_ZLIB_DEFLATE=y
++CONFIG_LZO_COMPRESS=y
++CONFIG_LZO_DECOMPRESS=y
++# CONFIG_XZ_DEC is not set
++# CONFIG_XZ_DEC_BCJ is not set
++CONFIG_GENERIC_ALLOCATOR=y
++CONFIG_HAS_IOMEM=y
++CONFIG_HAS_IOPORT=y
++CONFIG_HAS_DMA=y
++CONFIG_CPU_RMAP=y
++CONFIG_NLATTR=y
++# CONFIG_AVERAGE is not set
+diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/mach-mx5/board-mx50_rdp.c b/arch/arm/mach-mx5/board-mx50_rdp.c
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/mach-mx5/board-mx53_ard.c b/arch/arm/mach-mx5/board-mx53_ard.c
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/mach-mx5/board-mx53_evk.c b/arch/arm/mach-mx5/board-mx53_evk.c
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/mach-mx5/board-mx53_loco.c b/arch/arm/mach-mx5/board-mx53_loco.c
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/mach-mx5/board-mx53_smd.c b/arch/arm/mach-mx5/board-mx53_smd.c
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/mach-mx5/bus_freq.c b/arch/arm/mach-mx5/bus_freq.c
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/mach-mx5/clock.c b/arch/arm/mach-mx5/clock.c
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/mach-mx5/clock_mx50.c b/arch/arm/mach-mx5/clock_mx50.c
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/mach-mx5/cpu_op-mx50.c b/arch/arm/mach-mx5/cpu_op-mx50.c
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/mach-mx5/cpu_op-mx50.h b/arch/arm/mach-mx5/cpu_op-mx50.h
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/mach-mx5/cpu_op-mx51.c b/arch/arm/mach-mx5/cpu_op-mx51.c
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/mach-mx5/cpu_op-mx51.h b/arch/arm/mach-mx5/cpu_op-mx51.h
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/mach-mx5/cpu_op-mx53.c b/arch/arm/mach-mx5/cpu_op-mx53.c
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/mach-mx5/cpu_op-mx53.h b/arch/arm/mach-mx5/cpu_op-mx53.h
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/mach-mx5/crm_regs.h b/arch/arm/mach-mx5/crm_regs.h
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/mach-mx5/devices-imx50.h b/arch/arm/mach-mx5/devices-imx50.h
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/mach-mx5/devices-imx51.h b/arch/arm/mach-mx5/devices-imx51.h
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/mach-mx5/devices-imx53.h b/arch/arm/mach-mx5/devices-imx53.h
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/mach-mx5/devices.h b/arch/arm/mach-mx5/devices.h
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/mach-mx5/imx_bt_rfkill.c b/arch/arm/mach-mx5/imx_bt_rfkill.c
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/mach-mx5/mx50_ddr_freq.S b/arch/arm/mach-mx5/mx50_ddr_freq.S
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/mach-mx5/mx50_freq.c b/arch/arm/mach-mx5/mx50_freq.c
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/mach-mx5/mx50_suspend.S b/arch/arm/mach-mx5/mx50_suspend.S
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/mach-mx5/mx50_wfi.S b/arch/arm/mach-mx5/mx50_wfi.S
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/mach-mx5/mx53_loco_pmic_da9053.c b/arch/arm/mach-mx5/mx53_loco_pmic_da9053.c
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/mach-mx5/mx53_smd_pmic_da9053.c b/arch/arm/mach-mx5/mx53_smd_pmic_da9053.c
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/mach-mx5/pm.c b/arch/arm/mach-mx5/pm.c
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/mach-mx5/sdram_autogating.c b/arch/arm/mach-mx5/sdram_autogating.c
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/mach-mx5/suspend.S b/arch/arm/mach-mx5/suspend.S
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/mach-mx5/system.c b/arch/arm/mach-mx5/system.c
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/mach-mx5/usb.h b/arch/arm/mach-mx5/usb.h
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/mach-mx5/usb_dr.c b/arch/arm/mach-mx5/usb_dr.c
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/mach-mx5/usb_h1.c b/arch/arm/mach-mx5/usb_h1.c
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/mach-mx5/usb_h2.c b/arch/arm/mach-mx5/usb_h2.c
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/mach-mx6/Kconfig b/arch/arm/mach-mx6/Kconfig
+index 45ae9ea..fad950e 100644
+--- a/arch/arm/mach-mx6/Kconfig
++++ b/arch/arm/mach-mx6/Kconfig
+@@ -173,6 +173,10 @@ config MACH_MX6Q_SABRELITE
+ select IMX_HAVE_PLATFORM_IMX_ASRC
+ select IMX_HAVE_PLATFORM_FLEXCAN
+ select IMX_HAVE_PLATFORM_IMX_CAAM
++ select IMX_HAVE_PLATFORM_IMX_DVFS
++ select IMX_HAVE_PLATFORM_IMX_MIPI_CSI2
++ select IMX_HAVE_PLATFORM_IMX_PCIE
++ select IMX_HAVE_PLATFORM_PERFMON
+ help
+ Include support for i.MX 6Quad SABRE Lite platform. This includes specific
+ configurations for the board and its peripherals.
+diff --git a/arch/arm/mach-mx6/board-mx6q_arm2.c b/arch/arm/mach-mx6/board-mx6q_arm2.c
+index 81612e5..29911a2 100644
+--- a/arch/arm/mach-mx6/board-mx6q_arm2.c
++++ b/arch/arm/mach-mx6/board-mx6q_arm2.c
+@@ -1562,7 +1562,7 @@ static const struct pm_platform_data mx6_arm2_pm_data __initconst = {
+ .suspend_exit = arm2_suspend_exit,
+ };
+
+-static const struct asrc_p2p_params esai_p2p = {
++static const struct asrc_p2p_params esai_p2p __initconst = {
+ .p2p_rate = 44100,
+ .p2p_width = ASRC_WIDTH_24_BIT,
+ };
+diff --git a/arch/arm/mach-mx6/board-mx6q_sabreauto.c b/arch/arm/mach-mx6/board-mx6q_sabreauto.c
+index 926bdce..eb9fb30 100644
+--- a/arch/arm/mach-mx6/board-mx6q_sabreauto.c
++++ b/arch/arm/mach-mx6/board-mx6q_sabreauto.c
+@@ -1363,7 +1363,6 @@ static void __init mx6_board_init(void)
+ iomux_v3_cfg_t *tuner_pads = NULL;
+ iomux_v3_cfg_t *spinor_pads = NULL;
+ iomux_v3_cfg_t *weimnor_pads = NULL;
+- iomux_v3_cfg_t *extra_pads = NULL;
+
+ int common_pads_cnt;
+ int can0_pads_cnt;
+@@ -1373,7 +1372,6 @@ static void __init mx6_board_init(void)
+ int tuner_pads_cnt;
+ int spinor_pads_cnt;
+ int weimnor_pads_cnt;
+- int extra_pads_cnt;
+
+ if (cpu_is_mx6q()) {
+ common_pads = mx6q_sabreauto_pads;
+@@ -1394,15 +1392,9 @@ static void __init mx6_board_init(void)
+ if (board_is_mx6_reva()) {
+ i2c3_pads = mx6q_i2c3_pads_rev_a;
+ i2c3_pads_cnt = ARRAY_SIZE(mx6q_i2c3_pads_rev_a);
+- mxc_iomux_v3_setup_multiple_pads(i2c3_pads,
+- i2c3_pads_cnt);
+ } else {
+ i2c3_pads = mx6q_i2c3_pads_rev_b;
+ i2c3_pads_cnt = ARRAY_SIZE(mx6q_i2c3_pads_rev_b);
+- extra_pads = mx6q_extra_pads_rev_b;
+- extra_pads_cnt = ARRAY_SIZE(mx6q_extra_pads_rev_b);
+- mxc_iomux_v3_setup_multiple_pads(extra_pads,
+- extra_pads_cnt);
+ }
+ } else if (cpu_is_mx6dl()) {
+ common_pads = mx6dl_sabreauto_pads;
+@@ -1424,23 +1416,16 @@ static void __init mx6_board_init(void)
+ if (board_is_mx6_reva()) {
+ i2c3_pads = mx6dl_i2c3_pads_rev_a;
+ i2c3_pads_cnt = ARRAY_SIZE(mx6dl_i2c3_pads_rev_a);
+- mxc_iomux_v3_setup_multiple_pads(i2c3_pads,
+- i2c3_pads_cnt);
+ } else {
+ i2c3_pads = mx6dl_i2c3_pads_rev_b;
+ i2c3_pads_cnt = ARRAY_SIZE(mx6dl_i2c3_pads_rev_b);
+- extra_pads = mx6dl_extra_pads_rev_b;
+- extra_pads_cnt = ARRAY_SIZE(mx6dl_extra_pads_rev_b);
+- mxc_iomux_v3_setup_multiple_pads(extra_pads,
+- extra_pads_cnt);
+ }
+ }
+
+ BUG_ON(!common_pads);
+ mxc_iomux_v3_setup_multiple_pads(common_pads, common_pads_cnt);
+
+- /*If at least one NOR memory is selected we don't
+- * configure IC23 PADS for rev B */
++ /*If at least one NOR memory is selected we don't configure IC23 PADS*/
+ if (spinor_en) {
+ BUG_ON(!spinor_pads);
+ mxc_iomux_v3_setup_multiple_pads(spinor_pads, spinor_pads_cnt);
+@@ -1449,21 +1434,16 @@ static void __init mx6_board_init(void)
+ mxc_iomux_v3_setup_multiple_pads(weimnor_pads,
+ weimnor_pads_cnt);
+ } else {
+- if (!board_is_mx6_reva()) {
+- BUG_ON(!i2c3_pads);
+- mxc_iomux_v3_setup_multiple_pads(i2c3_pads,
+- i2c3_pads_cnt);
+- }
++ BUG_ON(!i2c3_pads);
++ mxc_iomux_v3_setup_multiple_pads(i2c3_pads, i2c3_pads_cnt);
+ }
+-
+ if (can0_enable) {
+ BUG_ON(!can0_pads);
+ mxc_iomux_v3_setup_multiple_pads(can0_pads,
+ can0_pads_cnt);
+ }
+-
+- BUG_ON(!can1_pads);
+- mxc_iomux_v3_setup_multiple_pads(can1_pads, can1_pads_cnt);
++ BUG_ON(!can1_pads);
++ mxc_iomux_v3_setup_multiple_pads(can1_pads, can1_pads_cnt);
+
+ if (tuner_en) {
+ BUG_ON(!tuner_pads);
+@@ -1488,7 +1468,7 @@ static void __init mx6_board_init(void)
+ gpio_request(SABREAUTO_WEIM_NOR_WDOG1, "nor-reset");
+ gpio_direction_output(SABREAUTO_WEIM_NOR_WDOG1, 1);
+ } else
+- gpio_direction_output(SABREAUTO_I2C3_STEER, 1);
++ gpio_direction_output(SABREAUTO_I2C3_STEER, 1);
+ /* Set GPIO_16 input for IEEE-1588 ts_clk and
+ * RMII reference clk
+ * For MX6 GPR1 bit21 meaning:
+diff --git a/arch/arm/mach-mx6/board-mx6q_sabreauto.h b/arch/arm/mach-mx6/board-mx6q_sabreauto.h
+index c087de6..477078c 100644
+--- a/arch/arm/mach-mx6/board-mx6q_sabreauto.h
++++ b/arch/arm/mach-mx6/board-mx6q_sabreauto.h
+@@ -282,16 +282,16 @@ static iomux_v3_cfg_t mx6q_i2c3_pads_rev_a[] __initdata = {
+ static iomux_v3_cfg_t mx6q_i2c3_pads_rev_b[] __initdata = {
+ MX6Q_PAD_GPIO_3__I2C3_SCL,
+ MX6Q_PAD_EIM_D18__I2C3_SDA,
++ MX6Q_PAD_EIM_A24__GPIO_5_4,
++ MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT,
+ };
+ static iomux_v3_cfg_t mx6q_tuner_pads[] __initdata = {
+ MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC,
+ MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS,
+ MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD,
++
+ };
+-static iomux_v3_cfg_t mx6q_extra_pads_rev_b[] __initdata = {
+- MX6Q_PAD_EIM_A24__GPIO_5_4,
+- MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT,
+-};
++
+ static iomux_v3_cfg_t mx6q_spinor_pads[] __initdata = {
+ /* eCSPI1 */
+ MX6Q_PAD_EIM_D16__ECSPI1_SCLK,
+diff --git a/arch/arm/mach-mx6/board-mx6q_sabrelite.c b/arch/arm/mach-mx6/board-mx6q_sabrelite.c
+index eff81ac..867f6df 100644
+--- a/arch/arm/mach-mx6/board-mx6q_sabrelite.c
++++ b/arch/arm/mach-mx6/board-mx6q_sabrelite.c
+@@ -62,6 +62,8 @@
+ #include <mach/ipu-v3.h>
+ #include <mach/mxc_hdmi.h>
+ #include <mach/mxc_asrc.h>
++#include <linux/i2c/tsc2007.h>
++#include <linux/wl12xx.h>
+
+ #include <asm/irq.h>
+ #include <asm/setup.h>
+@@ -81,9 +83,11 @@
+ #define MX6Q_SABRELITE_ECSPI1_CS1 IMX_GPIO_NR(3, 19)
+ #define MX6Q_SABRELITE_USB_OTG_PWR IMX_GPIO_NR(3, 22)
+ #define MX6Q_SABRELITE_CAP_TCH_INT1 IMX_GPIO_NR(1, 9)
++#define MX6Q_SABRELITE_DRGB_IRQGPIO IMX_GPIO_NR(4, 20)
+ #define MX6Q_SABRELITE_USB_HUB_RESET IMX_GPIO_NR(7, 12)
+ #define MX6Q_SABRELITE_CAN1_STBY IMX_GPIO_NR(1, 2)
+ #define MX6Q_SABRELITE_CAN1_EN IMX_GPIO_NR(1, 4)
++#define MX6Q_SABRELITE_CAN1_ERR IMX_GPIO_NR(1, 7)
+ #define MX6Q_SABRELITE_MENU_KEY IMX_GPIO_NR(2, 1)
+ #define MX6Q_SABRELITE_BACK_KEY IMX_GPIO_NR(2, 2)
+ #define MX6Q_SABRELITE_ONOFF_KEY IMX_GPIO_NR(2, 3)
+@@ -92,11 +96,33 @@
+ #define MX6Q_SABRELITE_VOL_DOWN_KEY IMX_GPIO_NR(4, 5)
+ #define MX6Q_SABRELITE_CSI0_RST IMX_GPIO_NR(1, 8)
+ #define MX6Q_SABRELITE_CSI0_PWN IMX_GPIO_NR(1, 6)
++#define MX6Q_SABRELITE_ENET_PHY_INT IMX_GPIO_NR(1, 28)
+
++#define N6_WL1271_WL_IRQ IMX_GPIO_NR(6, 14)
++#define N6_WL1271_WL_EN IMX_GPIO_NR(6, 15)
++#define N6_WL1271_BT_EN IMX_GPIO_NR(6, 16)
++
++#define MX6Q_SABRELITE_WL_IRQ_TEST_PADCFG (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
++#define MX6Q_SABRELITE_WL_IRQ_PADCFG (PAD_CTL_PUE | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
++#define MX6Q_SABRELITE_WL_EN_PADCFG (PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
++
++#define MX6Q_SABRELITE_CAN1_ERR_TEST_PADCFG (PAD_CTL_PKE | PAD_CTL_PUE | \
++ PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
++ PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
++#define MX6Q_SABRELITE_CAN1_ERR_PADCFG (PAD_CTL_PUE | \
++ PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
++ PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+ #define MX6Q_SABRELITE_SD3_WP_PADCFG (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
++#define WEAK_PULLUP (PAD_CTL_HYS | PAD_CTL_PKE \
++ | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
++
++#define N6_IRQ_TEST_PADCFG (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
++#define N6_IRQ_PADCFG (PAD_CTL_PUE | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
++#define N6_EN_PADCFG (PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
++
+ void __init early_console_setup(unsigned long base, struct clk *clk);
+ static struct clk *sata_clk;
+
+@@ -108,19 +134,50 @@ extern struct regulator *(*get_cpu_regulator)(void);
+ extern void (*put_cpu_regulator)(void);
+ extern void mx6_cpu_regulator_init(void);
+
++struct gpio n6w_wl1271_gpios[] __initdata = {
++ {.label = "wl1271_int", .gpio = N6_WL1271_WL_IRQ, .flags = GPIOF_DIR_IN},
++ {.label = "wl1271_bt_en", .gpio = N6_WL1271_BT_EN, .flags = 0},
++ {.label = "wl1271_wl_en", .gpio = N6_WL1271_WL_EN, .flags = 0},
++};
++
++int is_nitrogen6w(void)
++{
++ int ret = gpio_request_array(n6w_wl1271_gpios,
++ ARRAY_SIZE(n6w_wl1271_gpios));
++ if (ret) {
++ printk(KERN_ERR "%s gpio_request_array failed("
++ "%d) for n6w_wl1271_gpios\n", __func__, ret);
++ return ret;
++ }
++ ret = gpio_get_value(N6_WL1271_WL_IRQ);
++ if (ret <= 0) {
++ /* Sabrelite, not nitrogen6w */
++ gpio_free(N6_WL1271_WL_IRQ);
++ gpio_free(N6_WL1271_WL_EN);
++ gpio_free(N6_WL1271_BT_EN);
++ ret = 0;
++ }
++ return ret;
++}
++
+ static iomux_v3_cfg_t mx6q_sabrelite_pads[] = {
+ /* AUDMUX */
+ MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD,
+ MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC,
+ MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD,
+ MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS,
++ MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD,
++ MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC,
++ MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD,
++ MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS,
+
+ /* CAN1 */
+ MX6Q_PAD_KEY_ROW2__CAN1_RXCAN,
+ MX6Q_PAD_KEY_COL2__CAN1_TXCAN,
+ MX6Q_PAD_GPIO_2__GPIO_1_2, /* STNDBY */
+- MX6Q_PAD_GPIO_7__GPIO_1_7, /* NERR */
+ MX6Q_PAD_GPIO_4__GPIO_1_4, /* Enable */
++ /* NERR */
++ NEW_PAD_CTRL(MX6Q_PAD_GPIO_7__GPIO_1_7, MX6Q_SABRELITE_CAN1_ERR_TEST_PADCFG),
+
+ /* CCM */
+ MX6Q_PAD_GPIO_0__CCM_CLKO, /* SGTL500 sys_mclk */
+@@ -149,7 +206,6 @@ static iomux_v3_cfg_t mx6q_sabrelite_pads[] = {
+ MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3,
+ MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL,
+ MX6Q_PAD_ENET_TX_EN__GPIO_1_28, /* Micrel RGMII Phy Interrupt */
+- MX6Q_PAD_EIM_D23__GPIO_3_23, /* RGMII reset */
+
+ /* GPIO1 */
+ MX6Q_PAD_ENET_RX_ER__GPIO_1_24, /* J9 - Microphone Detect */
+@@ -200,6 +256,11 @@ static iomux_v3_cfg_t mx6q_sabrelite_pads[] = {
+ /* GPIO6 */
+ MX6Q_PAD_EIM_A23__GPIO_6_6, /* J12 - Boot Mode Select */
+
++ /* NANDF_CS1/2/3 are unused for sabrelite */
++ NEW_PAD_CTRL(MX6Q_PAD_NANDF_CS1__GPIO_6_14, N6_IRQ_TEST_PADCFG), /* wl1271 wl_irq */
++ NEW_PAD_CTRL(MX6Q_PAD_NANDF_CS2__GPIO_6_15, N6_EN_PADCFG), /* wl1271 wl_en */
++ NEW_PAD_CTRL(MX6Q_PAD_NANDF_CS3__GPIO_6_16, N6_EN_PADCFG), /* wl1271 bt_en */
++
+ /* GPIO7 */
+ MX6Q_PAD_GPIO_17__GPIO_7_12, /* USB Hub Reset */
+ MX6Q_PAD_GPIO_18__GPIO_7_13, /* J14 - Volume Up */
+@@ -225,7 +286,8 @@ static iomux_v3_cfg_t mx6q_sabrelite_pads[] = {
+ MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* DE */
+ MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2, /* HSync */
+ MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3, /* VSync */
+- MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4, /* Contrast */
++ NEW_PAD_CTRL(MX6Q_PAD_DI0_PIN4__GPIO_4_20,
++ WEAK_PULLUP), /* I2C Touch IRQ */
+ MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
+ MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
+ MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
+@@ -275,6 +337,18 @@ static iomux_v3_cfg_t mx6q_sabrelite_pads[] = {
+ MX6Q_PAD_EIM_D26__UART2_TXD,
+ MX6Q_PAD_EIM_D27__UART2_RXD,
+
++ /* WL127X pads */
++ NEW_PAD_CTRL(MX6Q_PAD_NANDF_CS1__GPIO_6_14, MX6Q_SABRELITE_WL_IRQ_PADCFG), /* wl1271 wl_irq */
++ NEW_PAD_CTRL(MX6Q_PAD_NANDF_CS2__GPIO_6_15, MX6Q_SABRELITE_WL_EN_PADCFG), /* wl1271 wl_en */
++ NEW_PAD_CTRL(MX6Q_PAD_NANDF_CS3__GPIO_6_16, MX6Q_SABRELITE_WL_EN_PADCFG), /* wl1271 bt_en */
++ MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT, /* wl1271 clock */
++
++ /* UART3 for wl1271 */
++ MX6Q_PAD_EIM_D24__UART3_TXD,
++ MX6Q_PAD_EIM_D25__UART3_RXD,
++ MX6Q_PAD_EIM_D23__UART3_CTS,
++ MX6Q_PAD_EIM_D31__UART3_RTS,
++
+ /* USBOTG ID pin */
+ MX6Q_PAD_GPIO_1__USBOTG_ID,
+
+@@ -282,6 +356,14 @@ static iomux_v3_cfg_t mx6q_sabrelite_pads[] = {
+ MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC,
+ MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC,
+
++ /* USDHC2 */
++ MX6Q_PAD_SD2_CLK__USDHC2_CLK_50MHZ,
++ MX6Q_PAD_SD2_CMD__USDHC2_CMD_50MHZ,
++ MX6Q_PAD_SD2_DAT0__USDHC2_DAT0_50MHZ,
++ MX6Q_PAD_SD2_DAT1__USDHC2_DAT1_50MHZ,
++ MX6Q_PAD_SD2_DAT2__USDHC2_DAT2_50MHZ,
++ MX6Q_PAD_SD2_DAT3__USDHC2_DAT3_50MHZ,
++
+ /* USDHC3 */
+ MX6Q_PAD_SD3_CLK__USDHC3_CLK_50MHZ,
+ MX6Q_PAD_SD3_CMD__USDHC3_CMD_50MHZ,
+@@ -348,6 +430,9 @@ mx6q_sd##id##_##speed##mhz[] = { \
+ MX6Q_PAD_SD##id##_DAT3__USDHC##id##_DAT3_##speed##MHZ, \
+ }
+
++static iomux_v3_cfg_t MX6Q_USDHC_PAD_SETTING(2, 50);
++static iomux_v3_cfg_t MX6Q_USDHC_PAD_SETTING(2, 100);
++static iomux_v3_cfg_t MX6Q_USDHC_PAD_SETTING(2, 200);
+ static iomux_v3_cfg_t MX6Q_USDHC_PAD_SETTING(3, 50);
+ static iomux_v3_cfg_t MX6Q_USDHC_PAD_SETTING(3, 100);
+ static iomux_v3_cfg_t MX6Q_USDHC_PAD_SETTING(3, 200);
+@@ -375,6 +460,15 @@ static int plt_sd_pad_change(unsigned int index, int clock)
+ u32 sd_pads_50mhz_cnt;
+
+ switch (index) {
++ case 1:
++ sd_pads_200mhz = mx6q_sd2_200mhz;
++ sd_pads_100mhz = mx6q_sd2_100mhz;
++ sd_pads_50mhz = mx6q_sd2_50mhz;
++
++ sd_pads_200mhz_cnt = ARRAY_SIZE(mx6q_sd2_200mhz);
++ sd_pads_100mhz_cnt = ARRAY_SIZE(mx6q_sd2_100mhz);
++ sd_pads_50mhz_cnt = ARRAY_SIZE(mx6q_sd2_50mhz);
++ break;
+ case 2:
+ sd_pads_200mhz = mx6q_sd3_200mhz;
+ sd_pads_100mhz = mx6q_sd3_100mhz;
+@@ -422,7 +516,16 @@ static int plt_sd_pad_change(unsigned int index, int clock)
+ }
+ }
+
+-static const struct esdhc_platform_data mx6q_sabrelite_sd3_data __initconst = {
++static struct esdhc_platform_data mx6q_sabrelite_sd2_data = {
++ .always_present = 1,
++ .cd_gpio = -1,
++ .wp_gpio = -1,
++ .keep_power_at_suspend = 0,
++ .caps = MMC_CAP_POWER_OFF_CARD,
++ .platform_pad_change = plt_sd_pad_change,
++};
++
++static struct esdhc_platform_data mx6q_sabrelite_sd3_data = {
+ .cd_gpio = MX6Q_SABRELITE_SD3_CD,
+ .wp_gpio = MX6Q_SABRELITE_SD3_WP,
+ .keep_power_at_suspend = 1,
+@@ -431,7 +534,7 @@ static const struct esdhc_platform_data mx6q_sabrelite_sd3_data __initconst = {
+
+ static const struct esdhc_platform_data mx6q_sabrelite_sd4_data __initconst = {
+ .cd_gpio = MX6Q_SABRELITE_SD4_CD,
+- .wp_gpio = MX6Q_SABRELITE_SD4_WP,
++ .wp_gpio = -1,
+ .keep_power_at_suspend = 1,
+ .platform_pad_change = plt_sd_pad_change,
+ };
+@@ -441,21 +544,25 @@ static const struct anatop_thermal_platform_data
+ .name = "anatop_thermal",
+ };
+
+-static inline void mx6q_sabrelite_init_uart(void)
+-{
+- imx6q_add_imx_uart(0, NULL);
+- imx6q_add_imx_uart(1, NULL);
+-}
++static const struct imxuart_platform_data mx6_arm2_uart2_data __initconst = {
++ .flags = IMXUART_HAVE_RTSCTS | IMXUART_SDMA,
++ .dma_req_rx = MX6Q_DMA_REQ_UART3_RX,
++ .dma_req_tx = MX6Q_DMA_REQ_UART3_TX,
++};
+
+ static int mx6q_sabrelite_fec_phy_init(struct phy_device *phydev)
+ {
+- /* prefer master mode, disable 1000 Base-T capable */
+- phy_write(phydev, 0x9, 0x1c00);
++ /* prefer master mode */
++ phy_write(phydev, 0x9, 0x1f00);
+
+ /* min rx data delay */
+ phy_write(phydev, 0x0b, 0x8105);
+ phy_write(phydev, 0x0c, 0x0000);
+
++ /* min tx data delay */
++ phy_write(phydev, 0x0b, 0x8106);
++ phy_write(phydev, 0x0c, 0x0000);
++
+ /* max rx/tx clock delay, min rx/tx control delay */
+ phy_write(phydev, 0x0b, 0x8104);
+ phy_write(phydev, 0x0c, 0xf0f0);
+@@ -467,6 +574,7 @@ static int mx6q_sabrelite_fec_phy_init(struct phy_device *phydev)
+ static struct fec_platform_data fec_data __initdata = {
+ .init = mx6q_sabrelite_fec_phy_init,
+ .phy = PHY_INTERFACE_MODE_RGMII,
++ .phy_irq = gpio_to_irq(MX6Q_SABRELITE_ENET_PHY_INT)
+ };
+
+ static int mx6q_sabrelite_spi_cs[] = {
+@@ -483,10 +591,15 @@ static struct mtd_partition imx6_sabrelite_spi_nor_partitions[] = {
+ {
+ .name = "bootloader",
+ .offset = 0,
+- .size = 0x00100000,
++ .size = 768*1024,
++ },
++ {
++ .name = "ubparams",
++ .offset = MTDPART_OFS_APPEND,
++ .size = 8*1024,
+ },
+ {
+- .name = "kernel",
++ .name = "unused",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ },
+@@ -637,11 +750,28 @@ static struct i2c_board_info mxc_i2c1_board_info[] __initdata = {
+ },
+ };
+
++static struct tsc2007_platform_data tsc2007_info = {
++ .model = 2004,
++ .x_plate_ohms = 500,
++};
++
+ static struct i2c_board_info mxc_i2c2_board_info[] __initdata = {
+ {
+ I2C_BOARD_INFO("egalax_ts", 0x4),
+ .irq = gpio_to_irq(MX6Q_SABRELITE_CAP_TCH_INT1),
+ },
++ {
++ I2C_BOARD_INFO("tsc2004", 0x48),
++ .platform_data = &tsc2007_info,
++ .irq = gpio_to_irq(MX6Q_SABRELITE_DRGB_IRQGPIO),
++ },
++#if defined(CONFIG_TOUCHSCREEN_FT5X06) \
++ || defined(CONFIG_TOUCHSCREEN_FT5X06_MODULE)
++ {
++ I2C_BOARD_INFO("ft5x06-ts", 0x38),
++ .irq = gpio_to_irq(MX6Q_SABRELITE_CAP_TCH_INT1),
++ },
++#endif
+ };
+
+ static void imx6q_sabrelite_usbotg_vbus(bool on)
+@@ -746,24 +876,30 @@ static struct ahci_platform_data mx6q_sabrelite_sata_data = {
+ };
+
+ static struct gpio mx6q_sabrelite_flexcan_gpios[] = {
++ { MX6Q_SABRELITE_CAN1_ERR, GPIOF_DIR_IN, "flexcan1-err" },
+ { MX6Q_SABRELITE_CAN1_EN, GPIOF_OUT_INIT_LOW, "flexcan1-en" },
+ { MX6Q_SABRELITE_CAN1_STBY, GPIOF_OUT_INIT_LOW, "flexcan1-stby" },
+ };
+
+-static void mx6q_sabrelite_flexcan0_switch(int enable)
++static void mx6q_sabrelite_flexcan0_mc33902_switch(int enable)
+ {
+- if (enable) {
+- gpio_set_value(MX6Q_SABRELITE_CAN1_EN, 1);
+- gpio_set_value(MX6Q_SABRELITE_CAN1_STBY, 1);
+- } else {
+- gpio_set_value(MX6Q_SABRELITE_CAN1_EN, 0);
+- gpio_set_value(MX6Q_SABRELITE_CAN1_STBY, 0);
+- }
++ gpio_set_value(MX6Q_SABRELITE_CAN1_EN, enable);
++ gpio_set_value(MX6Q_SABRELITE_CAN1_STBY, enable);
++}
++
++static void mx6q_sabrelite_flexcan0_tja1040_switch(int enable)
++{
++ gpio_set_value(MX6Q_SABRELITE_CAN1_STBY, enable ^ 1);
+ }
+
+ static const struct flexcan_platform_data
+- mx6q_sabrelite_flexcan0_pdata __initconst = {
+- .transceiver_switch = mx6q_sabrelite_flexcan0_switch,
++ mx6q_sabrelite_flexcan0_mc33902_pdata __initconst = {
++ .transceiver_switch = mx6q_sabrelite_flexcan0_mc33902_switch,
++};
++
++static const struct flexcan_platform_data
++ mx6q_sabrelite_flexcan0_tja1040_pdata __initconst = {
++ .transceiver_switch = mx6q_sabrelite_flexcan0_tja1040_switch,
+ };
+
+ static struct viv_gpu_platform_data imx6q_gpu_pdata __initdata = {
+@@ -852,7 +988,7 @@ static struct fsl_mxc_hdmi_platform_data hdmi_data = {
+
+ static struct fsl_mxc_hdmi_core_platform_data hdmi_core_data = {
+ .ipu_id = 0,
+- .disp_id = 0,
++ .disp_id = 1,
+ };
+
+ static struct fsl_mxc_lcd_platform_data lcdif_data = {
+@@ -952,6 +1088,54 @@ static void __init sabrelite_add_device_buttons(void)
+ static void __init sabrelite_add_device_buttons(void) {}
+ #endif
+
++#ifdef CONFIG_WL12XX_PLATFORM_DATA
++static void wl1271_set_power(bool enable)
++{
++ if (0 == enable) {
++ gpio_set_value(N6_WL1271_WL_EN, 0); /* momentarily disable */
++ mdelay(2);
++ gpio_set_value(N6_WL1271_WL_EN, 1);
++ }
++}
++
++struct wl12xx_platform_data n6q_wlan_data __initdata = {
++ .irq = gpio_to_irq(N6_WL1271_WL_IRQ),
++ .board_ref_clock = WL12XX_REFCLOCK_38, /* 38.4 MHz */
++ .set_power = wl1271_set_power,
++};
++
++static struct regulator_consumer_supply n6q_vwl1271_consumers[] = {
++ REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.1"),
++};
++
++static struct regulator_init_data n6q_vwl1271_init = {
++ .constraints = {
++ .name = "VDD_1.8V",
++ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
++ },
++ .num_consumer_supplies = ARRAY_SIZE(n6q_vwl1271_consumers),
++ .consumer_supplies = n6q_vwl1271_consumers,
++};
++
++static struct fixed_voltage_config n6q_vwl1271_reg_config = {
++ .supply_name = "vwl1271",
++ .microvolts = 1800000, /* 1.80V */
++ .gpio = N6_WL1271_WL_EN,
++ .startup_delay = 70000, /* 70ms */
++ .enable_high = 1,
++ .enabled_at_boot = 0,
++ .init_data = &n6q_vwl1271_init,
++};
++
++static struct platform_device n6q_vwl1271_reg_devices = {
++ .name = "reg-fixed-voltage",
++ .id = 4,
++ .dev = {
++ .platform_data = &n6q_vwl1271_reg_config,
++ },
++};
++#endif
++
+ static struct regulator_consumer_supply sabrelite_vmmc_consumers[] = {
+ REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.2"),
+ REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.3"),
+@@ -1069,6 +1253,15 @@ static int imx6q_init_audio(void)
+ return 0;
+ }
+
++/* PWM0_PWMO: backlight control on DRGB connector */
++static struct platform_pwm_backlight_data mx6_sabrelite_pwm0_backlight_data = {
++ .pwm_id = 0,
++ .max_brightness = 255,
++ .dft_brightness = 255,
++ .pwm_period_ns = 1000000000/32768,
++};
++
++/* PWM3_PWMO: backlight control on LDB connector */
+ static struct platform_pwm_backlight_data mx6_sabrelite_pwm_backlight_data = {
+ .pwm_id = 3,
+ .max_brightness = 255,
+@@ -1115,6 +1308,13 @@ static struct mipi_csi2_platform_data mipi_csi2_pdata = {
+ .pixel_clk = "emi_clk",
+ };
+
++static const struct imx_pcie_platform_data pcie_data __initconst = {
++ .pcie_pwr_en = -EINVAL,
++ .pcie_rst = -EINVAL, //MX6Q_SABRELITE_CAP_TCH_INT1,
++ .pcie_wake_up = -EINVAL,
++ .pcie_dis = -EINVAL,
++};
++
+ /*!
+ * Board specific initialization.
+ */
+@@ -1125,10 +1325,20 @@ static void __init mx6_sabrelite_board_init(void)
+ struct clk *clko2;
+ struct clk *new_parent;
+ int rate;
++ int isn6 ;
+
+ mxc_iomux_v3_setup_multiple_pads(mx6q_sabrelite_pads,
+ ARRAY_SIZE(mx6q_sabrelite_pads));
+
++ isn6 = is_nitrogen6w();
++ if (isn6) {
++ mx6_sabrelite_audio_data.ext_port = 3;
++ mx6q_sabrelite_sd3_data.wp_gpio = -1 ;
++ }
++
++ printk(KERN_ERR "------------ Board type %s\n",
++ isn6 ? "Nitrogen6X/W" : "Sabre Lite");
++
+ #ifdef CONFIG_FEC_1588
+ /* Set GPIO_16 input for IEEE-1588 ts_clk and RMII reference clock
+ * For MX6 GPR1 bit21 meaning:
+@@ -1141,7 +1351,12 @@ static void __init mx6_sabrelite_board_init(void)
+ gp_reg_id = sabrelite_dvfscore_data.reg_id;
+ soc_reg_id = sabrelite_dvfscore_data.soc_id;
+ pu_reg_id = sabrelite_dvfscore_data.pu_id;
+- mx6q_sabrelite_init_uart();
++
++ imx6q_add_imx_uart(0, NULL);
++ imx6q_add_imx_uart(1, NULL);
++ if (isn6)
++ imx6q_add_imx_uart(2, &mx6_arm2_uart2_data);
++
+ imx6q_add_mxc_hdmi_core(&hdmi_core_data);
+
+ imx6q_add_ipuv3(0, &ipu_data[0]);
+@@ -1180,8 +1395,8 @@ static void __init mx6_sabrelite_board_init(void)
+ imx6q_add_anatop_thermal_imx(1, &mx6q_sabrelite_anatop_thermal_data);
+ imx6_init_fec(fec_data);
+ imx6q_add_pm_imx(0, &mx6q_sabrelite_pm_data);
+- imx6q_add_sdhci_usdhc_imx(3, &mx6q_sabrelite_sd4_data);
+ imx6q_add_sdhci_usdhc_imx(2, &mx6q_sabrelite_sd3_data);
++ imx6q_add_sdhci_usdhc_imx(3, &mx6q_sabrelite_sd4_data);
+ imx_add_viv_gpu(&imx6_gpu_data, &imx6q_gpu_pdata);
+ imx6q_sabrelite_init_usb();
+ imx6q_add_ahci(0, &mx6q_sabrelite_sata_data);
+@@ -1199,6 +1414,7 @@ static void __init mx6_sabrelite_board_init(void)
+ imx6q_add_mxc_pwm(1);
+ imx6q_add_mxc_pwm(2);
+ imx6q_add_mxc_pwm(3);
++ imx6q_add_mxc_pwm_backlight(0, &mx6_sabrelite_pwm0_backlight_data);
+ imx6q_add_mxc_pwm_backlight(3, &mx6_sabrelite_pwm_backlight_data);
+
+ imx6q_add_otp();
+@@ -1216,10 +1432,22 @@ static void __init mx6_sabrelite_board_init(void)
+
+ ret = gpio_request_array(mx6q_sabrelite_flexcan_gpios,
+ ARRAY_SIZE(mx6q_sabrelite_flexcan_gpios));
+- if (ret)
++ if (ret) {
+ pr_err("failed to request flexcan1-gpios: %d\n", ret);
+- else
+- imx6q_add_flexcan0(&mx6q_sabrelite_flexcan0_pdata);
++ } else {
++ int ret = gpio_get_value(MX6Q_SABRELITE_CAN1_ERR);
++ if (ret == 0) {
++ imx6q_add_flexcan0(&mx6q_sabrelite_flexcan0_tja1040_pdata);
++ pr_info("Flexcan NXP tja1040\n");
++ } else if (ret == 1) {
++ iomux_v3_cfg_t err_pad = NEW_PAD_CTRL(MX6Q_PAD_GPIO_7__GPIO_1_7, MX6Q_SABRELITE_CAN1_ERR_PADCFG);
++ imx6q_add_flexcan0(&mx6q_sabrelite_flexcan0_mc33902_pdata);
++ mxc_iomux_v3_setup_pad(err_pad);
++ pr_info("Flexcan Freescale mc33902\n");
++ } else {
++ pr_info("Flexcan gpio_get_value CAN1_ERR failed\n");
++ }
++ }
+
+ clko2 = clk_get(NULL, "clko2_clk");
+ if (IS_ERR(clko2))
+@@ -1235,6 +1463,28 @@ static void __init mx6_sabrelite_board_init(void)
+ clk_enable(clko2);
+ imx6q_add_busfreq();
+
++#ifdef CONFIG_WL12XX_PLATFORM_DATA
++ if (isn6) {
++ imx6q_add_sdhci_usdhc_imx(1, &mx6q_sabrelite_sd2_data);
++ /* WL12xx WLAN Init */
++ if (wl12xx_set_platform_data(&n6q_wlan_data))
++ pr_err("error setting wl12xx data\n");
++ platform_device_register(&n6q_vwl1271_reg_devices);
++
++ gpio_set_value(N6_WL1271_WL_EN, 1); /* momentarily enable */
++ gpio_set_value(N6_WL1271_BT_EN, 1);
++ mdelay(2);
++ gpio_set_value(N6_WL1271_WL_EN, 0);
++ gpio_set_value(N6_WL1271_BT_EN, 0);
++
++ gpio_free(N6_WL1271_WL_EN);
++ gpio_free(N6_WL1271_BT_EN);
++ mdelay(1);
++ }
++#endif
++
++ imx6q_add_pcie(&pcie_data);
++
+ imx6q_add_perfmon(0);
+ imx6q_add_perfmon(1);
+ imx6q_add_perfmon(2);
+diff --git a/arch/arm/mach-mx6/board-mx6q_sabresd.c b/arch/arm/mach-mx6/board-mx6q_sabresd.c
+index e198617..1da30f1 100644
+--- a/arch/arm/mach-mx6/board-mx6q_sabresd.c
++++ b/arch/arm/mach-mx6/board-mx6q_sabresd.c
+@@ -1575,20 +1575,19 @@ static void __init imx6q_add_device_buttons(void) {}
+
+ static struct platform_pwm_backlight_data mx6_sabresd_pwm_backlight_data = {
+ .pwm_id = 0,
+- .max_brightness = 248,
++ .max_brightness = 255,
+ .dft_brightness = 128,
+ .pwm_period_ns = 50000,
+ };
+
+ static struct mxc_dvfs_platform_data sabresd_dvfscore_data = {
+-#ifdef CONFIG_MX6_INTER_LDO_BYPASS
++ #ifdef CONFIG_MX6_INTER_LDO_BYPASS
+ .reg_id = "VDDCORE",
+- .soc_id = "VDDSOC",
+-#else
++ #else
+ .reg_id = "cpu_vddgp",
+ .soc_id = "cpu_vddsoc",
+ .pu_id = "cpu_vddvpu",
+-#endif
++ #endif
+ .clk1_id = "cpu_clk",
+ .clk2_id = "gpc_dvfs_clk",
+ .gpc_cntr_offset = MXC_GPC_CNTR_OFFSET,
+@@ -1802,9 +1801,9 @@ static void __init mx6_sabresd_board_init(void)
+ imx6q_add_dma();
+
+ imx6q_add_dvfs_core(&sabresd_dvfscore_data);
+-#ifndef CONFIG_MX6_INTER_LDO_BYPASS
++ #ifndef CONFIG_MX6_INTER_LDO_BYPASS
+ mx6_cpu_regulator_init();
+-#endif
++ #endif
+ imx6q_add_device_buttons();
+
+ /* enable sensor 3v3 and 1v8 */
+diff --git a/arch/arm/mach-mx6/board-mx6sl_arm2.c b/arch/arm/mach-mx6/board-mx6sl_arm2.c
+index 4302b68..45b33c9 100755
+--- a/arch/arm/mach-mx6/board-mx6sl_arm2.c
++++ b/arch/arm/mach-mx6/board-mx6sl_arm2.c
+@@ -580,14 +580,13 @@ static struct i2c_board_info mxc_i2c2_board_info[] __initdata = {
+ };
+
+ static struct mxc_dvfs_platform_data mx6sl_arm2_dvfscore_data = {
+-#ifdef CONFIG_MX6_INTER_LDO_BYPASS
++ #ifdef CONFIG_MX6_INTER_LDO_BYPASS
+ .reg_id = "VDDCORE",
+- .soc_id = "VDDSOC",
+-#else
++ #else
+ .reg_id = "cpu_vddgp",
+ .soc_id = "cpu_vddsoc",
+ .pu_id = "cpu_vddvpu",
+-#endif
++ #endif
+ .clk1_id = "cpu_clk",
+ .clk2_id = "gpc_dvfs_clk",
+ .gpc_cntr_offset = MXC_GPC_CNTR_OFFSET,
+@@ -1188,15 +1187,14 @@ static void __init mx6_arm2_init(void)
+
+ elan_ts_init();
+
+-#ifdef CONFIG_MX6_INTER_LDO_BYPASS
++ #ifdef CONFIG_MX6_INTER_LDO_BYPASS
+ gp_reg_id = mx6sl_arm2_dvfscore_data.reg_id;
+- soc_reg_id = mx6sl_arm2_dvfscore_data.soc_id;
+-#else
++ #else
+ gp_reg_id = mx6sl_arm2_dvfscore_data.reg_id;
+ soc_reg_id = mx6sl_arm2_dvfscore_data.soc_id;
+ pu_reg_id = mx6sl_arm2_dvfscore_data.pu_id;
+ mx6_cpu_regulator_init();
+-#endif
++ #endif
+
+ imx6q_add_imx_snvs_rtc();
+
+diff --git a/arch/arm/mach-mx6/board-mx6sl_evk.c b/arch/arm/mach-mx6/board-mx6sl_evk.c
+index 81654a0..40c05c4 100644
+--- a/arch/arm/mach-mx6/board-mx6sl_evk.c
++++ b/arch/arm/mach-mx6/board-mx6sl_evk.c
+@@ -593,14 +593,13 @@ static struct i2c_board_info mxc_i2c2_board_info[] __initdata = {
+ };
+
+ static struct mxc_dvfs_platform_data mx6sl_evk_dvfscore_data = {
+-#ifdef CONFIG_MX6_INTER_LDO_BYPASS
++ #ifdef CONFIG_MX6_INTER_LDO_BYPASS
+ .reg_id = "VDDCORE",
+- .soc_id = "VDDSOC",
+-#else
++ #else
+ .reg_id = "cpu_vddgp",
+ .soc_id = "cpu_vddsoc",
+ .pu_id = "cpu_vddvpu",
+-#endif
++ #endif
+ .clk1_id = "cpu_clk",
+ .clk2_id = "gpc_dvfs_clk",
+ .gpc_cntr_offset = MXC_GPC_CNTR_OFFSET,
+@@ -1195,15 +1194,14 @@ static void __init mx6_evk_init(void)
+
+ elan_ts_init();
+
+-#ifdef CONFIG_MX6_INTER_LDO_BYPASS
++ #ifdef CONFIG_MX6_INTER_LDO_BYPASS
+ gp_reg_id = mx6sl_evk_dvfscore_data.reg_id;
+- soc_reg_id = mx6sl_evk_dvfscore_data.soc_id;
+-#else
++ #else
+ gp_reg_id = mx6sl_evk_dvfscore_data.reg_id;
+ soc_reg_id = mx6sl_evk_dvfscore_data.soc_id;
+ pu_reg_id = mx6sl_evk_dvfscore_data.pu_id;
+ mx6_cpu_regulator_init();
+-#endif
++ #endif
+
+ imx6q_add_imx_snvs_rtc();
+
+diff --git a/arch/arm/mach-mx6/board-mx6solo_sabreauto.h b/arch/arm/mach-mx6/board-mx6solo_sabreauto.h
+index 9111e6b..2e9e495 100644
+--- a/arch/arm/mach-mx6/board-mx6solo_sabreauto.h
++++ b/arch/arm/mach-mx6/board-mx6solo_sabreauto.h
+@@ -283,16 +283,15 @@ static iomux_v3_cfg_t mx6dl_i2c3_pads_rev_a[] __initdata = {
+ static iomux_v3_cfg_t mx6dl_i2c3_pads_rev_b[] __initdata = {
+ MX6DL_PAD_GPIO_3__I2C3_SCL,
+ MX6DL_PAD_EIM_D18__I2C3_SDA,
++ MX6DL_PAD_EIM_A24__GPIO_5_4,
++ MX6DL_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT,
+ };
+ static iomux_v3_cfg_t mx6dl_tuner_pads[] __initdata = {
+ MX6DL_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC,
+ MX6DL_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS,
+ MX6DL_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD,
+ };
+-static iomux_v3_cfg_t mx6dl_extra_pads_rev_b[] __initdata = {
+- MX6DL_PAD_EIM_A24__GPIO_5_4,
+- MX6DL_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT,
+-};
++
+ static iomux_v3_cfg_t mx6dl_spinor_pads[] __initdata = {
+ /* eCSPI1 */
+ MX6DL_PAD_EIM_D16__ECSPI1_SCLK,
+diff --git a/arch/arm/mach-mx6/bus_freq.c b/arch/arm/mach-mx6/bus_freq.c
+index 9d18423..8c04e51 100644
+--- a/arch/arm/mach-mx6/bus_freq.c
++++ b/arch/arm/mach-mx6/bus_freq.c
+@@ -115,8 +115,19 @@ static struct clk *pll3_540;
+
+ static struct delayed_work low_bus_freq_handler;
+
+-void reduce_bus_freq(void)
++static void reduce_bus_freq_handler(struct work_struct *work)
+ {
++ mutex_lock(&bus_freq_mutex);
++ if (low_bus_freq_mode || !low_freq_bus_used()) {
++ mutex_unlock(&bus_freq_mutex);
++ return;
++ }
++
++ if (audio_bus_freq_mode && lp_audio_freq) {
++ mutex_unlock(&bus_freq_mutex);
++ return;
++ }
++
+ if (!cpu_is_mx6sl()) {
+ if (cpu_is_mx6dl() &&
+ (clk_get_parent(axi_clk) != periph_clk))
+@@ -185,10 +196,6 @@ void reduce_bus_freq(void)
+ reg = __raw_writel(org_arm_podf, MXC_CCM_CACRR);
+ while (__raw_readl(MXC_CCM_CDHIPR))
+ ;
+- /* We have enabled PLL1 in the code below when
+- * ARM is from PLL1, so disable it here.
+- */
+- clk_disable(pll1);
+ }
+ low_bus_freq_mode = 0;
+ audio_bus_freq_mode = 1;
+@@ -201,10 +208,6 @@ void reduce_bus_freq(void)
+ * lowest possible freq.
+ */
+ org_arm_podf = __raw_readl(MXC_CCM_CACRR);
+- /* Need to enable PLL1 before setting its rate. */
+- clk_enable(pll1);
+- clk_set_rate(pll1,
+- cpu_op_tbl[cpu_op_nr - 1].pll_lpm_rate);
+ div = clk_get_rate(pll1) /
+ cpu_op_tbl[cpu_op_nr - 1].cpu_rate;
+
+@@ -223,35 +226,6 @@ void reduce_bus_freq(void)
+ spin_unlock_irqrestore(&freq_lock, flags);
+ }
+ high_bus_freq_mode = 0;
+-
+-}
+-
+-static void reduce_bus_freq_handler(struct work_struct *work)
+-{
+- mutex_lock(&bus_freq_mutex);
+-
+- if (!low_freq_bus_used()) {
+- mutex_unlock(&bus_freq_mutex);
+- return;
+- }
+- /* If we are already in audio bus freq mode,
+- * just return if lp_audio_freq is true.
+- */
+- if (audio_bus_freq_mode && lp_audio_freq) {
+- mutex_unlock(&bus_freq_mutex);
+- return;
+- }
+-
+- /* If we dont want to transition from low bus to
+- * audio bus mode and are already in
+- *low bus mode, then return.
+- */
+- if (!lp_audio_freq && low_bus_freq_mode) {
+- mutex_unlock(&bus_freq_mutex);
+- return;
+- }
+- reduce_bus_freq();
+-
+ mutex_unlock(&bus_freq_mutex);
+ }
+
+@@ -267,19 +241,10 @@ int set_low_bus_freq(void)
+ if (!bus_freq_scaling_initialized || !bus_freq_scaling_is_active)
+ return 0;
+
+- /* Check to see if we need to got from
+- * low bus freq mode to audio bus freq mode.
+- * If so, the change needs to be done immediately.
++ /* Don't lower the frequency immediately. Instead scheduled a delayed
++ * work and drop the freq if the conditions still remain the same.
+ */
+- if (lp_audio_freq && low_bus_freq_mode)
+- reduce_bus_freq();
+- else
+- /* Don't lower the frequency immediately. Instead
+- * scheduled a delayed work and drop the freq if
+- * the conditions still remain the same.
+- */
+- schedule_delayed_work(&low_bus_freq_handler,
+- usecs_to_jiffies(3000000));
++ schedule_delayed_work(&low_bus_freq_handler, usecs_to_jiffies(3000000));
+ return 0;
+ }
+
+@@ -343,7 +308,6 @@ int set_high_bus_freq(int high_bus_freq)
+ reg = __raw_writel(org_arm_podf, MXC_CCM_CACRR);
+ while (__raw_readl(MXC_CCM_CDHIPR))
+ ;
+- clk_disable(pll1);
+ }
+ high_bus_freq_mode = 1;
+ low_bus_freq_mode = 0;
+@@ -426,8 +390,13 @@ void bus_freq_update(struct clk *clk, bool flag)
+ && (clk_get_usecount(clk) == 0)) {
+ if (!(clk->flags &
+ (AHB_HIGH_SET_POINT | AHB_MED_SET_POINT))) {
+- if (low_freq_bus_used())
+- set_low_bus_freq();
++ if (low_freq_bus_used()) {
++ if ((clk->flags & AHB_AUDIO_SET_POINT) &
++ !audio_bus_freq_mode)
++ set_low_bus_freq();
++ else if (!low_bus_freq_mode)
++ set_low_bus_freq();
++ }
+ } else {
+ if ((clk->flags & AHB_MED_SET_POINT)
+ && !med_bus_freq_mode) {
+@@ -527,8 +496,6 @@ static int busfreq_suspend(struct platform_device *pdev, pm_message_t message)
+ static int bus_freq_pm_notify(struct notifier_block *nb, unsigned long event,
+ void *dummy)
+ {
+- mutex_lock(&bus_freq_mutex);
+-
+ if (event == PM_SUSPEND_PREPARE) {
+ set_high_bus_freq(1);
+ busfreq_suspended = 1;
+@@ -536,8 +503,6 @@ static int bus_freq_pm_notify(struct notifier_block *nb, unsigned long event,
+ busfreq_suspended = 0;
+ }
+
+- mutex_unlock(&bus_freq_mutex);
+-
+ return NOTIFY_OK;
+ }
+ static int busfreq_resume(struct platform_device *pdev)
+diff --git a/arch/arm/mach-mx6/clock.c b/arch/arm/mach-mx6/clock.c
+index a3dc7e4..e0348e4 100644
+--- a/arch/arm/mach-mx6/clock.c
++++ b/arch/arm/mach-mx6/clock.c
+@@ -1261,16 +1261,7 @@ static int _clk_arm_set_rate(struct clk *clk, unsigned long rate)
+ * PLL2_PFD_400M.
+ */
+ if (pll1_sw_clk.parent != &pll2_pfd_400M) {
+- if (pll2_pfd_400M.usecount == 0) {
+- /* Check if PLL2 needs to be enabled also. */
+- if (pll2_528_bus_main_clk.usecount == 0)
+- pll2_528_bus_main_clk.enable(&pll2_528_bus_main_clk);
+- /* Ensure parent usecount is
+- * also incremented.
+- */
+- pll2_528_bus_main_clk.usecount++;
+- pll2_pfd_400M.enable(&pll2_pfd_400M);
+- }
++ pll2_pfd_400M.enable(&pll2_pfd_400M);
+ pll2_pfd_400M.usecount++;
+ arm_needs_pll2_400 = true;
+ pll1_sw_clk.set_parent(&pll1_sw_clk, &pll2_pfd_400M);
+@@ -1297,19 +1288,11 @@ static int _clk_arm_set_rate(struct clk *clk, unsigned long rate)
+ /* Make sure pll1_sw_clk is from pll1_sys_main_clk */
+ pll1_sw_clk.set_parent(&pll1_sw_clk, &pll1_sys_main_clk);
+ pll1_sw_clk.parent = &pll1_sys_main_clk;
+- if (arm_needs_pll2_400) {
++ if (arm_needs_pll2_400)
+ pll2_pfd_400M.usecount--;
+- if (pll2_pfd_400M.usecount == 0) {
+- pll2_pfd_400M.disable(&pll2_pfd_400M);
+- /* Ensure parent usecount is
+- * also decremented.
+- */
+- pll2_528_bus_main_clk.usecount--;
+- if (pll2_528_bus_main_clk.usecount == 0)
+- pll2_528_bus_main_clk.disable(&pll2_528_bus_main_clk);
+- }
+- }
+ arm_needs_pll2_400 = false;
++ if (pll2_pfd_400M.usecount == 0)
++ pll2_pfd_400M.disable(&pll2_pfd_400M);
+ }
+ parent_rate = clk_get_rate(clk->parent);
+ div = parent_rate / rate;
+@@ -1334,6 +1317,9 @@ static int _clk_arm_set_rate(struct clk *clk, unsigned long rate)
+ spin_unlock_irqrestore(&clk_lock, flags);
+ return -1;
+ }
++ /* Need PLL1-MAIN to be ON to write to ARM-PODF bit. */
++ if (!pll1_enabled)
++ pll1_sys_main_clk.enable(&pll1_sys_main_clk);
+
+ cur_arm_podf = div;
+
+@@ -5426,8 +5412,6 @@ int __init mx6_clocks_init(unsigned long ckil, unsigned long osc,
+ /* on mx6dl gpu2d_axi_clk source from mmdc0 directly */
+ clk_set_parent(&gpu2d_axi_clk, &mmdc_ch0_axi_clk[0]);
+
+- clk_set_rate(&pll3_pfd_540M, 540000000);
+-
+ clk_set_parent(&ipu1_clk, &pll3_pfd_540M);
+ /* pxp & epdc */
+ clk_set_parent(&ipu2_clk, &pll2_pfd_400M);
+diff --git a/arch/arm/mach-mx6/clock_mx6sl.c b/arch/arm/mach-mx6/clock_mx6sl.c
+index 6160991..4839f15 100755
+--- a/arch/arm/mach-mx6/clock_mx6sl.c
++++ b/arch/arm/mach-mx6/clock_mx6sl.c
+@@ -1167,18 +1167,9 @@ static int _clk_arm_set_rate(struct clk *clk, unsigned long rate)
+ * PLL2_PFD2_400M.
+ */
+ if (pll1_sw_clk.parent != &pll2_pfd2_400M) {
+- if (pll2_pfd2_400M.usecount == 0) {
+- /* Check if PLL2 needs to be enabled also. */
+- if (pll2_528_bus_main_clk.usecount == 0)
+- pll2_528_bus_main_clk.enable(&pll2_528_bus_main_clk);
+- /* Ensure parent usecount is
+- * also incremented.
+- */
+- pll2_528_bus_main_clk.usecount++;
+- pll2_pfd2_400M.enable(&pll2_pfd2_400M);
+- }
+- arm_needs_pll2_400 = true;
++ pll2_pfd2_400M.enable(&pll2_pfd2_400M);
+ pll2_pfd2_400M.usecount++;
++ arm_needs_pll2_400 = true;
+ pll1_sw_clk.set_parent(&pll1_sw_clk, &pll2_pfd2_400M);
+ pll1_sw_clk.parent = &pll2_pfd2_400M;
+ }
+@@ -1201,19 +1192,11 @@ static int _clk_arm_set_rate(struct clk *clk, unsigned long rate)
+ pll1_sw_clk.set_parent(&pll1_sw_clk, &pll1_sys_main_clk);
+ pll1_sw_clk.parent = &pll1_sys_main_clk;
+
+- if (arm_needs_pll2_400) {
++ if (arm_needs_pll2_400)
+ pll2_pfd2_400M.usecount--;
+- if (pll2_pfd2_400M.usecount == 0) {
+- pll2_pfd2_400M.disable(&pll2_pfd2_400M);
+- /* Ensure parent usecount is
+- * also decremented.
+- */
+- pll2_528_bus_main_clk.usecount--;
+- if (pll2_528_bus_main_clk.usecount == 0)
+- pll2_528_bus_main_clk.disable(&pll2_528_bus_main_clk);
+- }
+- }
+ arm_needs_pll2_400 = false;
++ if (pll2_pfd2_400M.usecount == 0)
++ pll2_pfd2_400M.disable(&pll2_pfd2_400M);
+ }
+ parent_rate = clk_get_rate(clk->parent);
+ div = parent_rate / rate;
+@@ -1239,6 +1222,9 @@ static int _clk_arm_set_rate(struct clk *clk, unsigned long rate)
+ return -1;
+ }
+
++ if (!pll1_enabled)
++ pll1_sys_main_clk.enable(&pll1_sys_main_clk);
++
+ cur_arm_podf = div;
+
+ __raw_writel(div - 1, MXC_CCM_CACRR);
+@@ -1532,6 +1518,16 @@ static struct clk ipg_clk = {
+ .get_rate = _clk_ipg_get_rate,
+ };
+
++static struct clk tzasc1_clk = {
++ __INIT_CLK_DEBUG(tzasc1_clk)
++ .id = 0,
++ .parent = &ipg_clk,
++ .enable_reg = MXC_CCM_CCGR2,
++ .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
++ .enable = _clk_enable,
++ .disable = _clk_disable_inwait,
++};
++
+ static struct clk tzasc2_clk = {
+ __INIT_CLK_DEBUG(tzasc2_clk)
+ .id = 0,
+@@ -1563,6 +1559,16 @@ static struct clk mx6per1_clk = {
+ .disable = _clk_disable_inwait,
+ };
+
++static struct clk mx6per2_clk = {
++ __INIT_CLK_DEBUG(mx6per2_clk)
++ .id = 0,
++ .parent = &ahb_clk,
++ .enable_reg = MXC_CCM_CCGR4,
++ .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
++ .enable = _clk_enable,
++ .disable = _clk_disable_inwait,
++};
++
+ static int _clk_mmdc_ch1_axi_set_parent(struct clk *clk,
+ struct clk *parent)
+ {
+@@ -1684,7 +1690,7 @@ static struct clk mmdc_ch1_axi_clk[] = {
+ .secondary = &tzasc2_clk,
+ },
+ };
+-#if defined(CONFIG_SDMA_IRAM) || defined(CONFIG_SND_MXC_SOC_IRAM)
++
+ static struct clk ocram_clk = {
+ __INIT_CLK_DEBUG(ocram_clk)
+ .id = 0,
+@@ -1694,7 +1700,7 @@ static struct clk ocram_clk = {
+ .enable = _clk_enable,
+ .disable = _clk_disable_inwait,
+ };
+-#endif
++
+ static unsigned long _clk_ipg_perclk_get_rate(struct clk *clk)
+ {
+ u32 reg, div;
+@@ -1783,7 +1789,7 @@ static struct clk sdma_clk[] = {
+ },
+ };
+
+-static unsigned long mx6_timer_rate(void)
++static unsigned long mx6_timer_rate()
+ {
+ u32 parent_rate = clk_get_rate(&osc_clk);
+
+diff --git a/arch/arm/mach-mx6/cpu_op-mx6.c b/arch/arm/mach-mx6/cpu_op-mx6.c
+index 7e054c1..3415f01 100644
+--- a/arch/arm/mach-mx6/cpu_op-mx6.c
++++ b/arch/arm/mach-mx6/cpu_op-mx6.c
+@@ -29,8 +29,8 @@ static struct cpu_op mx6q_cpu_op_1_2G[] = {
+ .pll_rate = 1200000000,
+ .cpu_rate = 1200000000,
+ .cpu_podf = 0,
+- .pu_voltage = 1275000,
+- .soc_voltage = 1275000,
++ .pu_voltage = 1250000,
++ .soc_voltage = 1250000,
+ .cpu_voltage = 1275000,},
+ {
+ .pll_rate = 792000000,
+@@ -38,13 +38,13 @@ static struct cpu_op mx6q_cpu_op_1_2G[] = {
+ .cpu_podf = 0,
+ #ifdef CONFIG_MX6_VPU_352M
+ /*VPU 352Mhz need voltage 1.25V*/
+- .pu_voltage = 1250000,
+- .soc_voltage = 1250000,
++ .pu_voltage = 1250000,
++ .soc_voltage = 1250000,
+ #else
+- .pu_voltage = 1175000,
+- .soc_voltage = 1175000,
++ .pu_voltage = 1150000,
++ .soc_voltage = 1150000,
+ #endif
+- .cpu_voltage = 1150000,},
++ .cpu_voltage = 1100000,},
+ #ifdef CONFIG_MX6_VPU_352M
+ /*pll2_pfd_400M will be fix on 352M,to avoid modify other code
+ which assume ARM clock sourcing from pll2_pfd_400M, change cpu
+@@ -55,15 +55,15 @@ static struct cpu_op mx6q_cpu_op_1_2G[] = {
+ .cpu_podf = 0,
+ .pu_voltage = 1250000,
+ .soc_voltage = 1250000,
+- .cpu_voltage = 950000,},
++ .cpu_voltage = 925000,},
+ #else
+ {
+ .pll_rate = 396000000,
+ .cpu_rate = 396000000,
+ .cpu_podf = 0,
+- .pu_voltage = 1175000,
+- .soc_voltage = 1175000,
+- .cpu_voltage = 950000,},
++ .pu_voltage = 1150000,
++ .soc_voltage = 1150000,
++ .cpu_voltage = 925000,},
+ #endif
+ };
+
+@@ -73,9 +73,9 @@ static struct cpu_op mx6q_cpu_op_1G[] = {
+ .pll_rate = 996000000,
+ .cpu_rate = 996000000,
+ .cpu_podf = 0,
+- .pu_voltage = 1250000,
+- .soc_voltage = 1250000,
+- .cpu_voltage = 1250000,},
++ .pu_voltage = 1200000,
++ .soc_voltage = 1200000,
++ .cpu_voltage = 1225000,},
+ {
+ .pll_rate = 792000000,
+ .cpu_rate = 792000000,
+@@ -85,10 +85,10 @@ static struct cpu_op mx6q_cpu_op_1G[] = {
+ .pu_voltage = 1250000,
+ .soc_voltage = 1250000,
+ #else
+- .pu_voltage = 1175000,
+- .soc_voltage = 1175000,
++ .pu_voltage = 1150000,
++ .soc_voltage = 1150000,
+ #endif
+- .cpu_voltage = 1150000,},
++ .cpu_voltage = 1100000,},
+ #ifdef CONFIG_MX6_VPU_352M
+ /*pll2_pfd_400M will be fix on 352M,to avoid modify other code
+ which assume ARM clock sourcing from pll2_pfd_400M, change cpu
+@@ -99,15 +99,15 @@ static struct cpu_op mx6q_cpu_op_1G[] = {
+ .cpu_podf = 0,
+ .pu_voltage = 1250000,
+ .soc_voltage = 1250000,
+- .cpu_voltage = 950000,},
++ .cpu_voltage = 925000,},
+ #else
+ {
+ .pll_rate = 396000000,
+ .cpu_rate = 396000000,
+ .cpu_podf = 0,
+- .pu_voltage = 1175000,
+- .soc_voltage = 1175000,
+- .cpu_voltage = 950000,},
++ .pu_voltage = 1150000,
++ .soc_voltage = 1150000,
++ .cpu_voltage = 925000,},
+ #endif
+ };
+
+@@ -121,10 +121,10 @@ static struct cpu_op mx6q_cpu_op[] = {
+ .pu_voltage = 1250000,
+ .soc_voltage = 1250000,
+ #else
+- .pu_voltage = 1175000,
+- .soc_voltage = 1175000,
++ .pu_voltage = 1150000,
++ .soc_voltage = 1150000,
+ #endif
+- .cpu_voltage = 1150000,},
++ .cpu_voltage = 1100000,},
+ #ifdef CONFIG_MX6_VPU_352M
+ /*pll2_pfd_400M will be fix on 352M,to avoid modify other code
+ which assume ARM clock sourcing from pll2_pfd_400M, change cpu
+@@ -135,15 +135,15 @@ static struct cpu_op mx6q_cpu_op[] = {
+ .cpu_podf = 0,
+ .pu_voltage = 1250000,
+ .soc_voltage = 1250000,
+- .cpu_voltage = 950000,},
++ .cpu_voltage = 925000,},
+ #else
+ {
+ .pll_rate = 396000000,
+ .cpu_rate = 396000000,
+ .cpu_podf = 0,
+- .pu_voltage = 1175000,
+- .soc_voltage = 1175000,
+- .cpu_voltage = 950000,},
++ .pu_voltage = 1150000,
++ .soc_voltage = 1150000,
++ .cpu_voltage = 925000,},
+ #endif
+ };
+
+@@ -153,23 +153,30 @@ static struct cpu_op mx6dl_cpu_op_1_2G[] = {
+ .pll_rate = 1200000000,
+ .cpu_rate = 1200000000,
+ .cpu_podf = 0,
+- .pu_voltage = 1275000,
+- .soc_voltage = 1275000,
++ .pu_voltage = 1250000,
++ .soc_voltage = 1250000,
+ .cpu_voltage = 1275000,},
+ {
+ .pll_rate = 792000000,
+ .cpu_rate = 792000000,
+ .cpu_podf = 0,
+- .pu_voltage = 1175000,
+- .soc_voltage = 1175000,
+- .cpu_voltage = 1150000,},
++ .pu_voltage = 1150000,
++ .soc_voltage = 1150000,
++ .cpu_voltage = 1100000,},
+ {
+ .pll_rate = 396000000,
+ .cpu_rate = 396000000,
+ .cpu_podf = 0,
+- .pu_voltage = 1175000,
+- .soc_voltage = 1175000,
+- .cpu_voltage = 1075000,},
++ .pu_voltage = 1150000,
++ .soc_voltage = 1150000,
++ .cpu_voltage = 1025000,},
++ {
++ .pll_rate = 396000000,
++ .cpu_rate = 198000000,
++ .cpu_podf = 1,
++ .pu_voltage = 1150000,
++ .soc_voltage = 1150000,
++ .cpu_voltage = 1025000,},
+ };
+ /* working point(wp): 0 - 1GHz; 1 - 800MHz, 2 - 400MHz, 3 - 200MHz */
+ static struct cpu_op mx6dl_cpu_op_1G[] = {
+@@ -177,39 +184,53 @@ static struct cpu_op mx6dl_cpu_op_1G[] = {
+ .pll_rate = 996000000,
+ .cpu_rate = 996000000,
+ .cpu_podf = 0,
+- .pu_voltage = 1250000,
+- .soc_voltage = 1250000,
+- .cpu_voltage = 1250000,},
++ .pu_voltage = 1200000,
++ .soc_voltage = 1200000,
++ .cpu_voltage = 1225000,},
+ {
+ .pll_rate = 792000000,
+ .cpu_rate = 792000000,
+ .cpu_podf = 0,
+- .pu_voltage = 1175000,
+- .soc_voltage = 1175000,
+- .cpu_voltage = 1150000,},
++ .pu_voltage = 1150000,
++ .soc_voltage = 1150000,
++ .cpu_voltage = 1100000,},
+ {
+ .pll_rate = 396000000,
+ .cpu_rate = 396000000,
+ .cpu_podf = 0,
+- .pu_voltage = 1175000,
+- .soc_voltage = 1175000,
+- .cpu_voltage = 1075000,},
++ .pu_voltage = 1150000,
++ .soc_voltage = 1150000,
++ .cpu_voltage = 1025000,},
++ {
++ .pll_rate = 396000000,
++ .cpu_rate = 198000000,
++ .cpu_podf = 1,
++ .pu_voltage = 1150000,
++ .soc_voltage = 1150000,
++ .cpu_voltage = 1025000,},
+ };
+ static struct cpu_op mx6dl_cpu_op[] = {
+ {
+ .pll_rate = 792000000,
+ .cpu_rate = 792000000,
+ .cpu_podf = 0,
+- .pu_voltage = 1175000,
+- .soc_voltage = 1175000,
+- .cpu_voltage = 1150000,},
++ .pu_voltage = 1150000,
++ .soc_voltage = 1150000,
++ .cpu_voltage = 1100000,},
+ {
+ .pll_rate = 396000000,
+ .cpu_rate = 396000000,
+ .cpu_podf = 0,
+- .pu_voltage = 1175000,
+- .soc_voltage = 1175000,
+- .cpu_voltage = 1075000,},
++ .pu_voltage = 1150000,
++ .soc_voltage = 1150000,
++ .cpu_voltage = 1025000,},
++ {
++ .pll_rate = 396000000,
++ .cpu_rate = 198000000,
++ .cpu_podf = 1,
++ .pu_voltage = 1150000,
++ .soc_voltage = 1150000,
++ .cpu_voltage = 1025000,},
+ };
+
+ static struct cpu_op mx6sl_cpu_op_1G[] = {
+@@ -229,7 +250,6 @@ static struct cpu_op mx6sl_cpu_op_1G[] = {
+ .cpu_voltage = 1200000,},
+ {
+ .pll_rate = 396000000,
+- .pll_lpm_rate = 792000000,
+ .cpu_rate = 396000000,
+ .cpu_podf = 0,
+ .pu_voltage = 1050000,
+@@ -237,7 +257,6 @@ static struct cpu_op mx6sl_cpu_op_1G[] = {
+ .cpu_voltage = 1100000,},
+ {
+ .pll_rate = 396000000,
+- .pll_lpm_rate = 792000000,
+ .cpu_rate = 198000000,
+ .cpu_podf = 1,
+ .pu_voltage = 1050000,
+@@ -255,7 +274,6 @@ static struct cpu_op mx6sl_cpu_op[] = {
+ .cpu_voltage = 1200000,},
+ {
+ .pll_rate = 396000000,
+- .pll_lpm_rate = 792000000,
+ .cpu_rate = 396000000,
+ .cpu_podf = 0,
+ .pu_voltage = 1050000,
+@@ -263,7 +281,6 @@ static struct cpu_op mx6sl_cpu_op[] = {
+ .cpu_voltage = 1100000,},
+ {
+ .pll_rate = 396000000,
+- .pll_lpm_rate = 792000000,
+ .cpu_rate = 198000000,
+ .cpu_podf = 1,
+ .pu_voltage = 1050000,
+diff --git a/arch/arm/mach-mx6/devices-imx6q.h b/arch/arm/mach-mx6/devices-imx6q.h
+index ec724ff..f91369f 100644
+--- a/arch/arm/mach-mx6/devices-imx6q.h
++++ b/arch/arm/mach-mx6/devices-imx6q.h
+@@ -158,6 +158,10 @@ extern const struct imx_imx_asrc_data imx6q_imx_asrc_data[] __initconst;
+ #define imx6q_add_asrc(pdata) \
+ imx_add_imx_asrc(imx6q_imx_asrc_data, pdata)
+
++extern const struct imx_spi_imx_data imx6q_ecspi_data[] __initconst;
++#define imx6q_add_ecspi(id, pdata) \
++ imx_add_spi_imx(&imx6q_ecspi_data[id], pdata)
++
+ extern const struct imx_dvfs_core_data imx6q_dvfs_core_data __initconst;
+ #define imx6q_add_dvfs_core(pdata) \
+ imx_add_dvfs_core(&imx6q_dvfs_core_data, pdata)
+diff --git a/arch/arm/mach-mx6/irq.c b/arch/arm/mach-mx6/irq.c
+index e865b45..a079c37 100644
+--- a/arch/arm/mach-mx6/irq.c
++++ b/arch/arm/mach-mx6/irq.c
+@@ -103,9 +103,7 @@ void mx6_init_irq(void)
+ void __iomem *gpc_base = IO_ADDRESS(GPC_BASE_ADDR);
+ struct irq_desc *desc;
+ unsigned int i;
+-#ifdef CONFIG_MX6_INTER_LDO_BYPASS
+ u32 reg;
+-#endif
+
+ /* start offset if private timer irq id, which is 29.
+ * ID table:
+diff --git a/arch/arm/mach-mx6/mx6_suspend.S b/arch/arm/mach-mx6/mx6_suspend.S
+index 0533ad1..59b6760 100644
+--- a/arch/arm/mach-mx6/mx6_suspend.S
++++ b/arch/arm/mach-mx6/mx6_suspend.S
+@@ -85,7 +85,8 @@ r2: suspend_iram_base
+ ldr r4, [r1, #0x330] /* DRAM_SDCKE0 */
+ ldr r5, [r1, #0x334] /* DRAM_SDCKE1 */
+ ldr r6, [r1, #0x320] /* DRAM_RESET */
+- stmfd r0!, {r4-r6}
++ ldr r7, [r1, #0x5c8] /* GPR_CTLDS */
++ stmfd r0!, {r4-r7}
+
+ .endm
+
+@@ -121,10 +122,11 @@ r2: suspend_iram_base
+ str r6, [r1, #0x33c] /* DRAM_SODT0*/
+ str r7, [r1, #0x340] /* DRAM_SODT1*/
+
+- ldmea r0!, {r4-r6}
++ ldmea r0!, {r4-r7}
+ str r4, [r1, #0x330] /* DRAM_SDCKE0 */
+ str r5, [r1, #0x334] /* DRAM_SDCKE1 */
+ str r6, [r1, #0x320] /* DRAM_RESET */
++ str r7, [r1, #0x5c8] /* GPR_CTLDS */
+
+ .endm
+
+@@ -136,13 +138,6 @@ r2: suspend_iram_base
+ str r0, [r1, #0x314] /* DRAM_DQM2 */
+ str r0, [r1, #0x318] /* DRAM_DQM3 */
+
+- /* Make sure the Pull Ups are enabled.
+- * So only reduce the drive stength, but
+- * leave the pull-ups in the original state.
+- * This is required for LPDDR2.
+- */
+- ldr r0, [r1, #0x344]
+- orr r0, r0, #0x3000
+ str r0, [r1, #0x344] /* DRAM_SDQS0 */
+ str r0, [r1, #0x348] /* DRAM_SDQS1 */
+ str r0, [r1, #0x34c] /* DRAM_SDQS2 */
+@@ -163,6 +158,7 @@ r2: suspend_iram_base
+ str r0, [r1, #0x33c] /* DRAM_SODT0*/
+ str r0, [r1, #0x340] /* DRAM_SODT1*/
+
++ str r0, [r1, #0x5c8] /* GPR_CTLDS */
+ mov r0, #0x80000
+ str r0, [r1, #0x320] /* DRAM_RESET */
+ mov r0, #0x1000
+@@ -777,22 +773,6 @@ ddr_io_save_done:
+ /****************************************************************
+ set ddr iomux to low power mode
+ ****************************************************************/
+- /* Make sure TLBs are primed. */
+- ldr r1, =MX6Q_IOMUXC_BASE_ADDR
+- add r1, r1, #PERIPBASE_VIRT
+- ldr r0, [r1]
+- ldr r1, =SRC_BASE_ADDR
+- add r1, r1, #PERIPBASE_VIRT
+- ldr r0, [r1]
+-#ifdef CONFIG_MX6_INTER_LDO_BYPASS
+- ldr r1, =ANATOP_BASE_ADDR
+- add r1, r1, #PERIPBASE_VIRT
+- ldr r0, [r1]
+-#endif
+-
+- /* Do a DSB to drain the buffers. */
+- dsb
+-
+ ldr r1, =MMDC_P0_BASE_ADDR
+ add r1, r1, #PERIPBASE_VIRT
+ ldr r0, [r1, #MMDC_MAPSR_OFFSET]
+@@ -833,12 +813,12 @@ save resume pointer into SRC_GPR1
+ add r1, r1, #PERIPBASE_VIRT
+ str r3, [r1, #SRC_GPR1_OFFSET]
+ #ifdef CONFIG_MX6_INTER_LDO_BYPASS
+- ldr r1, =ANATOP_BASE_ADDR
++ ldr r1, =0x20c8140
+ add r1, r1, #PERIPBASE_VIRT
+- ldr r3, [r1, #0x140]
++ ldr r3, [r1]
+ bic r3, r3, #0x1f
+ orr r3, r3, #0x1e
+- str r3, [r1, #0x140]
++ str r3, [r1]
+ #endif
+ /****************************************************************
+ execute a wfi instruction to let SOC go into stop mode.
+@@ -854,14 +834,6 @@ execute a wfi instruction to let SOC go into stop mode.
+ if go here, means there is a wakeup irq pending, we should resume
+ system immediately.
+ ****************************************************************/
+-#ifdef CONFIG_MX6_INTER_LDO_BYPASS
+- ldr r1, =ANATOP_BASE_ADDR
+- add r1, r1, #PERIPBASE_VIRT
+- ldr r3, [r1, #0x140]
+- orr r3, r3, #0x1f
+- str r3, [r1, #0x140]
+-#endif
+-
+ mov r0, r2 /* get suspend_iram_base */
+ add r0, r0, #IRAM_SUSPEND_SIZE /* 4K */
+
+@@ -884,40 +856,6 @@ sl_io_restore:
+ sl_ddr_io_restore
+
+ ddr_io_restore_done:
+- /* Add enough nops so that the
+- * prefetcher will not get instructions
+- * from DDR before its IO pads
+- * are restored.
+- */
+- nop
+- nop
+- nop
+- nop
+- nop
+-
+- nop
+- nop
+- nop
+- nop
+- nop
+-
+- nop
+- nop
+- nop
+- nop
+- nop
+-
+- nop
+- nop
+- nop
+- nop
+- nop
+-
+- nop
+- nop
+- nop
+- nop
+- nop
+
+ mrc p15, 0, r1, c1, c0, 0
+ orr r1, r1, #(1 << 2) @ Enable the C bit
+@@ -931,10 +869,10 @@ are running with MMU off.
+ ****************************************************************/
+ resume:
+ #ifdef CONFIG_MX6_INTER_LDO_BYPASS
+- ldr r1, =ANATOP_BASE_ADDR
+- ldr r3, [r1, #0x140]
++ ldr r1, =0x20c8140
++ ldr r3, [r1]
+ orr r3, r3, #0x1f
+- str r3, [r1, #0x140]
++ str r3, [r1]
+ #endif
+ /* Invalidate L1 I-cache first */
+ mov r1, #0x0
+diff --git a/arch/arm/mach-mx6/mx6q_sabreauto_pmic_pfuze100.c b/arch/arm/mach-mx6/mx6q_sabreauto_pmic_pfuze100.c
+index 8cb4ffc..cc12a02 100644
+--- a/arch/arm/mach-mx6/mx6q_sabreauto_pmic_pfuze100.c
++++ b/arch/arm/mach-mx6/mx6q_sabreauto_pmic_pfuze100.c
+@@ -41,13 +41,13 @@
+
+ /*SWBST*/
+ #define PFUZE100_SW1ASTANDBY 33
+-#define PFUZE100_SW1ASTANDBY_STBY_VAL (0x19)
++#define PFUZE100_SW1ASTANDBY_STBY_VAL (0x18)
+ #define PFUZE100_SW1ASTANDBY_STBY_M (0x3f<<0)
+ #define PFUZE100_SW1BSTANDBY 40
+-#define PFUZE100_SW1BSTANDBY_STBY_VAL (0x19)
++#define PFUZE100_SW1BSTANDBY_STBY_VAL (0x18)
+ #define PFUZE100_SW1BSTANDBY_STBY_M (0x3f<<0)
+ #define PFUZE100_SW1CSTANDBY 47
+-#define PFUZE100_SW1CSTANDBY_STBY_VAL (0x19)
++#define PFUZE100_SW1CSTANDBY_STBY_VAL (0x18)
+ #define PFUZE100_SW1CSTANDBY_STBY_M (0x3f<<0)
+ #define PFUZE100_SW2STANDBY 54
+ #define PFUZE100_SW2STANDBY_STBY_VAL 0x0
+diff --git a/arch/arm/mach-mx6/mx6q_sabresd_pmic_pfuze100.c b/arch/arm/mach-mx6/mx6q_sabresd_pmic_pfuze100.c
+index cbde449..f7e7099 100644
+--- a/arch/arm/mach-mx6/mx6q_sabresd_pmic_pfuze100.c
++++ b/arch/arm/mach-mx6/mx6q_sabresd_pmic_pfuze100.c
+@@ -48,13 +48,13 @@
+ #define PFUZE100_SW1CVOL 46
+ #define PFUZE100_SW1CVOL_VSEL_M (0x3f<<0)
+ #define PFUZE100_SW1ASTANDBY 33
+-#define PFUZE100_SW1ASTANDBY_STBY_VAL (0x19)
++#define PFUZE100_SW1ASTANDBY_STBY_VAL (0x18)
+ #define PFUZE100_SW1ASTANDBY_STBY_M (0x3f<<0)
+ #define PFUZE100_SW1BSTANDBY 40
+-#define PFUZE100_SW1BSTANDBY_STBY_VAL (0x19)
++#define PFUZE100_SW1BSTANDBY_STBY_VAL (0x18)
+ #define PFUZE100_SW1BSTANDBY_STBY_M (0x3f<<0)
+ #define PFUZE100_SW1CSTANDBY 47
+-#define PFUZE100_SW1CSTANDBY_STBY_VAL (0x19)
++#define PFUZE100_SW1CSTANDBY_STBY_VAL (0x18)
+ #define PFUZE100_SW1CSTANDBY_STBY_M (0x3f<<0)
+ #define PFUZE100_SW2STANDBY 54
+ #define PFUZE100_SW2STANDBY_STBY_VAL 0x0
+@@ -74,9 +74,6 @@
+ #define PFUZE100_SW1ACON 36
+ #define PFUZE100_SW1ACON_SPEED_VAL (0x1<<6) /*default */
+ #define PFUZE100_SW1ACON_SPEED_M (0x3<<6)
+-#define PFUZE100_SW1CCON 49
+-#define PFUZE100_SW1CCON_SPEED_VAL (0x1<<6) /*default */
+-#define PFUZE100_SW1CCON_SPEED_M (0x3<<6)
+
+ extern u32 arm_max_freq;
+
+@@ -86,11 +83,6 @@ static struct regulator_consumer_supply sw1_consumers[] = {
+ .supply = "VDDCORE",
+ }
+ };
+-static struct regulator_consumer_supply sw1c_consumers[] = {
+- {
+- .supply = "VDDSOC",
+- },
+-};
+ #endif
+
+ static struct regulator_consumer_supply sw2_consumers[] = {
+@@ -168,10 +160,10 @@ static struct regulator_init_data sw1a_init = {
+ .always_on = 1,
+ },
+
+-#ifdef CONFIG_MX6_INTER_LDO_BYPASS
++ #ifdef CONFIG_MX6_INTER_LDO_BYPASS
+ .num_consumer_supplies = ARRAY_SIZE(sw1_consumers),
+ .consumer_supplies = sw1_consumers,
+-#endif
++ #endif
+ };
+
+ static struct regulator_init_data sw1b_init = {
+@@ -196,10 +188,6 @@ static struct regulator_init_data sw1c_init = {
+ .always_on = 1,
+ .boot_on = 1,
+ },
+-#ifdef CONFIG_MX6_INTER_LDO_BYPASS
+- .num_consumer_supplies = ARRAY_SIZE(sw1c_consumers),
+- .consumer_supplies = sw1c_consumers,
+-#endif
+ };
+
+ static struct regulator_init_data sw2_init = {
+@@ -402,16 +390,16 @@ static int pfuze100_init(struct mc_pfuze *pfuze)
+ int ret;
+ unsigned int reg;
+ if (arm_max_freq == CPU_AT_1_2GHz) {
+- /*VDDARM_IN 1.475V*/
++ /*VDDARM_IN 1.425V*/
+ ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1AVOL,
+ PFUZE100_SW1AVOL_VSEL_M,
+- 0x2f);
++ 0x2d);
+ if (ret)
+ goto err;
+- /*VDDSOC_IN 1.475V*/
++ /*VDDSOC_IN 1.425V*/
+ ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1CVOL,
+ PFUZE100_SW1CVOL_VSEL_M,
+- 0x2f);
++ 0x2d);
+ if (ret)
+ goto err;
+ /*set VDDSOC&VDDPU to 1.25V*/
+@@ -433,17 +421,12 @@ static int pfuze100_init(struct mc_pfuze *pfuze)
+ PFUZE100_SW1CSTANDBY_STBY_VAL);
+ if (ret)
+ goto err;
+- /*set SW1AB/1C DVSPEED as 25mV step each 4us,quick than 16us before.*/
++ /*set SW1ABDVSPEED as 25mV step each 4us,quick than 16us before.*/
+ ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1ACON,
+ PFUZE100_SW1ACON_SPEED_M,
+ PFUZE100_SW1ACON_SPEED_VAL);
+ if (ret)
+ goto err;
+- ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1CCON,
+- PFUZE100_SW1CCON_SPEED_M,
+- PFUZE100_SW1CCON_SPEED_VAL);
+- if (ret)
+- goto err;
+ return 0;
+ err:
+ printk(KERN_ERR "pfuze100 init error!\n");
+diff --git a/arch/arm/mach-mx6/mx6sl_arm2_pmic_pfuze100.c b/arch/arm/mach-mx6/mx6sl_arm2_pmic_pfuze100.c
+index 134700a..eaa9721 100644
+--- a/arch/arm/mach-mx6/mx6sl_arm2_pmic_pfuze100.c
++++ b/arch/arm/mach-mx6/mx6sl_arm2_pmic_pfuze100.c
+@@ -66,9 +66,6 @@
+ #define PFUZE100_SW1ACON 36
+ #define PFUZE100_SW1ACON_SPEED_VAL (0x1<<6) /*default */
+ #define PFUZE100_SW1ACON_SPEED_M (0x3<<6)
+-#define PFUZE100_SW1CCON 49
+-#define PFUZE100_SW1CCON_SPEED_VAL (0x1<<6) /*default */
+-#define PFUZE100_SW1CCON_SPEED_M (0x3<<6)
+
+
+ #ifdef CONFIG_MX6_INTER_LDO_BYPASS
+@@ -77,11 +74,6 @@ static struct regulator_consumer_supply sw1_consumers[] = {
+ .supply = "VDDCORE",
+ }
+ };
+-static struct regulator_consumer_supply sw1c_consumers[] = {
+- {
+- .supply = "VDDSOC",
+- },
+-};
+ #endif
+
+ static struct regulator_consumer_supply sw2_consumers[] = {
+@@ -159,10 +151,10 @@ static struct regulator_init_data sw1a_init = {
+ .boot_on = 1,
+ .always_on = 1,
+ },
+-#ifdef CONFIG_MX6_INTER_LDO_BYPASS
++ #ifdef CONFIG_MX6_INTER_LDO_BYPASS
+ .num_consumer_supplies = ARRAY_SIZE(sw1_consumers),
+ .consumer_supplies = sw1_consumers,
+-#endif
++ #endif
+ };
+
+ static struct regulator_init_data sw1b_init = {
+@@ -187,10 +179,6 @@ static struct regulator_init_data sw1c_init = {
+ .always_on = 1,
+ .boot_on = 1,
+ },
+- #ifdef CONFIG_MX6_INTER_LDO_BYPASS
+- .num_consumer_supplies = ARRAY_SIZE(sw1c_consumers),
+- .consumer_supplies = sw1c_consumers,
+- #endif
+ };
+
+ static struct regulator_init_data sw2_init = {
+@@ -403,17 +391,12 @@ static int pfuze100_init(struct mc_pfuze *pfuze)
+ PFUZE100_SW1CSTANDBY_STBY_VAL);
+ if (ret)
+ goto err;
+- /*set SW1AB/SW1C DVSPEED as 25mV step each 4us,quick than 16us before.*/
++ /*set SW1ABDVSPEED as 25mV step each 4us,quick than 16us before.*/
+ ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1ACON,
+ PFUZE100_SW1ACON_SPEED_M,
+ PFUZE100_SW1ACON_SPEED_VAL);
+ if (ret)
+ goto err;
+- ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1CCON,
+- PFUZE100_SW1CCON_SPEED_M,
+- PFUZE100_SW1CCON_SPEED_VAL);
+- if (ret)
+- goto err;
+ return 0;
+ err:
+ printk(KERN_ERR "pfuze100 init error!\n");
+diff --git a/arch/arm/mach-mx6/mx6sl_evk_pmic_pfuze100.c b/arch/arm/mach-mx6/mx6sl_evk_pmic_pfuze100.c
+index ee66541..958f8a0 100644
+--- a/arch/arm/mach-mx6/mx6sl_evk_pmic_pfuze100.c
++++ b/arch/arm/mach-mx6/mx6sl_evk_pmic_pfuze100.c
+@@ -66,9 +66,7 @@
+ #define PFUZE100_SW1ACON 36
+ #define PFUZE100_SW1ACON_SPEED_VAL (0x1<<6) /*default */
+ #define PFUZE100_SW1ACON_SPEED_M (0x3<<6)
+-#define PFUZE100_SW1CCON 49
+-#define PFUZE100_SW1CCON_SPEED_VAL (0x1<<6) /*default */
+-#define PFUZE100_SW1CCON_SPEED_M (0x3<<6)
++
+
+ #ifdef CONFIG_MX6_INTER_LDO_BYPASS
+ static struct regulator_consumer_supply sw1_consumers[] = {
+@@ -76,11 +74,6 @@ static struct regulator_consumer_supply sw1_consumers[] = {
+ .supply = "VDDCORE",
+ }
+ };
+-static struct regulator_consumer_supply sw1c_consumers[] = {
+- {
+- .supply = "VDDSOC",
+- },
+-};
+ #endif
+
+ static struct regulator_consumer_supply sw2_consumers[] = {
+@@ -133,7 +126,7 @@ static struct regulator_consumer_supply vgen3_consumers[] = {
+ };
+ static struct regulator_consumer_supply vgen4_consumers[] = {
+ {
+- .supply = "VGEN4_1V8",
++ .supply = "VGEN4_1V58",
+ }
+ };
+ static struct regulator_consumer_supply vgen5_consumers[] = {
+@@ -162,10 +155,10 @@ static struct regulator_init_data sw1a_init = {
+ .boot_on = 1,
+ .always_on = 1,
+ },
+-#ifdef CONFIG_MX6_INTER_LDO_BYPASS
++ #ifdef CONFIG_MX6_INTER_LDO_BYPASS
+ .num_consumer_supplies = ARRAY_SIZE(sw1_consumers),
+ .consumer_supplies = sw1_consumers,
+-#endif
++ #endif
+ };
+
+ static struct regulator_init_data sw1b_init = {
+@@ -190,10 +183,6 @@ static struct regulator_init_data sw1c_init = {
+ .always_on = 1,
+ .boot_on = 1,
+ },
+-#ifdef CONFIG_MX6_INTER_LDO_BYPASS
+- .num_consumer_supplies = ARRAY_SIZE(sw1c_consumers),
+- .consumer_supplies = sw1c_consumers,
+-#endif
+ };
+
+ static struct regulator_init_data sw2_init = {
+@@ -408,17 +397,12 @@ static int pfuze100_init(struct mc_pfuze *pfuze)
+ PFUZE100_SW1CSTANDBY_STBY_VAL);
+ if (ret)
+ goto err;
+- /*set SW1AB/SW1CDVSPEED as 25mV step each 4us,quick than 16us before.*/
++ /*set SW1ABDVSPEED as 25mV step each 4us,quick than 16us before.*/
+ ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1ACON,
+ PFUZE100_SW1ACON_SPEED_M,
+ PFUZE100_SW1ACON_SPEED_VAL);
+ if (ret)
+ goto err;
+- ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1CCON,
+- PFUZE100_SW1CCON_SPEED_M,
+- PFUZE100_SW1CCON_SPEED_VAL);
+- if (ret)
+- goto err;
+ return 0;
+ err:
+ printk(KERN_ERR "pfuze100 init error!\n");
+diff --git a/arch/arm/mach-mx6/mx6sl_wfi.S b/arch/arm/mach-mx6/mx6sl_wfi.S
+index 89fe4e2..d2d9103 100644
+--- a/arch/arm/mach-mx6/mx6sl_wfi.S
++++ b/arch/arm/mach-mx6/mx6sl_wfi.S
+@@ -109,13 +109,6 @@
+ str r4, [r1, #0x314] /* DRAM_DQM2 */
+ str r4, [r1, #0x318] /* DRAM_DQM3 */
+
+- /* Make sure the Pull Ups are enabled.
+- * So only reduce the drive stength, but
+- * leave the pull-ups in the original state.
+- * This is required for LPDDR2.
+- */
+- ldr r4, [r1, #0x344]
+- orr r4, r4, #0x3000
+ str r4, [r1, #0x344] /* DRAM_SDQS0 */
+ str r4, [r1, #0x348] /* DRAM_SDQS1 */
+ str r4, [r1, #0x34c] /* DRAM_SDQS2 */
+@@ -136,6 +129,7 @@
+ str r4, [r1, #0x33c] /* DRAM_SODT0*/
+ str r4, [r1, #0x340] /* DRAM_SODT1*/
+
++ str r4, [r1, #0x5c8] /* GPR_CTLDS */
+ mov r4, #0x80000
+ str r4, [r1, #0x320] /* DRAM_RESET */
+ mov r4, #0x1000
+@@ -354,42 +348,6 @@ poll_dvfs_clear_1:
+ cmp r6, #0x2000000
+ beq poll_dvfs_clear_1
+
+- /* Add these nops so that the
+- * prefetcher will not try to get
+- * any instructions from DDR.
+- * The prefetch depth is about 23
+- * on A9, so adding 25 nops.
+- */
+- nop
+- nop
+- nop
+- nop
+- nop
+-
+- nop
+- nop
+- nop
+- nop
+- nop
+-
+- nop
+- nop
+- nop
+- nop
+- nop
+-
+- nop
+- nop
+- nop
+- nop
+- nop
+-
+- nop
+- nop
+- nop
+- nop
+- nop
+-
+ /* Enable Automatic power savings. */
+ ldr r6, [r8, #0x404]
+ bic r6, r6, #0x01
+diff --git a/arch/arm/mach-mx6/pm.c b/arch/arm/mach-mx6/pm.c
+index 45b2e6f..dd5db57 100644
+--- a/arch/arm/mach-mx6/pm.c
++++ b/arch/arm/mach-mx6/pm.c
+@@ -73,8 +73,6 @@ static struct clk *cpu_clk;
+ static struct clk *axi_clk;
+ static struct clk *periph_clk;
+ static struct clk *axi_org_parent;
+-static struct clk *gpu2d_core_clk;
+-static struct clk *pll3_usb_otg_main_clk;
+
+ static struct pm_platform_data *pm_data;
+
+@@ -110,8 +108,6 @@ static u32 ccm_ccr, ccm_clpcr, scu_ctrl;
+ static u32 gpc_imr[4], gpc_cpu_pup, gpc_cpu_pdn, gpc_cpu, gpc_ctr, gpc_disp;
+ static u32 anatop[2], ccgr1, ccgr2, ccgr3, ccgr6;
+ static u32 ccm_analog_pfd528;
+-static u32 ccm_analog_pll3_480;
+-static u32 ccm_anadig_ana_misc2;
+ static bool usb_vbus_wakeup_enabled;
+
+
+@@ -203,7 +199,6 @@ static void gpu_power_down(void)
+ static void gpu_power_up(void)
+ {
+ int reg;
+- int i;
+ /* power on pu */
+ reg = __raw_readl(anatop_base + ANATOP_REG_CORE_OFFSET);
+ reg &= ~0x0003fe00;
+@@ -216,24 +211,6 @@ static void gpu_power_up(void)
+ __raw_writel(ccm_analog_pfd528 &
+ ~ANADIG_PFD0_CLKGATE &
+ ~ANADIG_PFD1_CLKGATE, PFD_528_BASE_ADDR);
+-
+- /* PLL3 480M clock enable which may be used by gpu2d*/
+- if (clk_get_parent(gpu2d_core_clk) == pll3_usb_otg_main_clk) {
+- __raw_writel(ccm_analog_pll3_480 |
+- ANADIG_PLL_POWER_DOWN, PLL3_480_USB1_BASE_ADDR);
+- __raw_writel(ccm_anadig_ana_misc2 &
+- (~BM_ANADIG_ANA_MISC2_CONTROL0),
+- MXC_PLL_BASE + HW_ANADIG_ANA_MISC2);
+- for (i = 0; i < 100; i++) {
+- if (!(__raw_readl(PLL3_480_USB1_BASE_ADDR) & ANADIG_PLL_LOCK))
+- udelay(1);
+- else
+- break;
+- }
+- __raw_writel((ccm_analog_pll3_480 & (~ANADIG_PLL_BYPASS)) |
+- ANADIG_PLL_ENABLE | ANADIG_PLL_POWER_DOWN,
+- PLL3_480_USB1_BASE_ADDR);
+- }
+ /* gpu3d and gpu2d clock enable */
+ __raw_writel(ccgr1 |
+ MXC_CCM_CCGRx_CG12_MASK |
+@@ -284,8 +261,6 @@ static void mx6_suspend_store(void)
+ ccm_ccr = __raw_readl(MXC_CCM_CCR);
+ ccm_clpcr = __raw_readl(MXC_CCM_CLPCR);
+ ccm_analog_pfd528 = __raw_readl(PFD_528_BASE_ADDR);
+- ccm_analog_pll3_480 = __raw_readl(PLL3_480_USB1_BASE_ADDR);
+- ccm_anadig_ana_misc2 = __raw_readl(MXC_PLL_BASE + HW_ANADIG_ANA_MISC2);
+ ccgr1 = __raw_readl(MXC_CCM_CCGR1);
+ ccgr2 = __raw_readl(MXC_CCM_CCGR2);
+ ccgr3 = __raw_readl(MXC_CCM_CCGR3);
+@@ -333,8 +308,6 @@ static void mx6_suspend_restore(void)
+ __raw_writel(ccgr3, MXC_CCM_CCGR3);
+ __raw_writel(ccgr6, MXC_CCM_CCGR6);
+ __raw_writel(ccm_analog_pfd528, PFD_528_BASE_ADDR);
+- __raw_writel(ccm_analog_pll3_480, PLL3_480_USB1_BASE_ADDR);
+- __raw_writel(ccm_anadig_ana_misc2, MXC_PLL_BASE + HW_ANADIG_ANA_MISC2);
+ }
+
+ static int mx6_suspend_enter(suspend_state_t state)
+@@ -548,16 +521,6 @@ static int __init pm_init(void)
+ printk(KERN_DEBUG "%s: failed to get periph_clk\n", __func__);
+ return PTR_ERR(periph_clk);
+ }
+- gpu2d_core_clk = clk_get(NULL, "gpu2d_clk");
+- if (IS_ERR(gpu2d_core_clk)) {
+- printk(KERN_DEBUG "%s: failed to get gpu2d_clk\n", __func__);
+- return PTR_ERR(periph_clk);
+- }
+- pll3_usb_otg_main_clk = clk_get(NULL, "pll3_main_clk");
+- if (IS_ERR(pll3_usb_otg_main_clk)) {
+- printk(KERN_DEBUG "%s: failed to get pll3_main_clk\n", __func__);
+- return PTR_ERR(pll3_usb_otg_main_clk);
+- }
+
+ printk(KERN_INFO "PM driver module loaded\n");
+
+diff --git a/arch/arm/mach-mx6/system.c b/arch/arm/mach-mx6/system.c
+index 800c7cc..686c58c 100644
+--- a/arch/arm/mach-mx6/system.c
++++ b/arch/arm/mach-mx6/system.c
+@@ -195,7 +195,7 @@ void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
+ __raw_writel(__raw_readl(MXC_CCM_CCR) &
+ (~MXC_CCM_CCR_WB_COUNT_MASK) &
+ (~MXC_CCM_CCR_REG_BYPASS_CNT_MASK), MXC_CCM_CCR);
+- udelay(80);
++ udelay(60);
+ /* Reconfigurate WB and RBC counter */
+ __raw_writel(__raw_readl(MXC_CCM_CCR) |
+ (0x1 << MXC_CCM_CCR_WB_COUNT_OFFSET) |
+diff --git a/arch/arm/mach-mx6/usb_dr.c b/arch/arm/mach-mx6/usb_dr.c
+index 8fe9700..8cfcb27 100644
+--- a/arch/arm/mach-mx6/usb_dr.c
++++ b/arch/arm/mach-mx6/usb_dr.c
+@@ -442,18 +442,18 @@ static void _host_platform_rh_resume_swfix(struct fsl_usb2_platform_data *pdata)
+ {
+ u32 index = 0;
+
+- if ((UOG_PORTSC1 & (PORTSC_PORT_SPEED_MASK)) != PORTSC_PORT_SPEED_HIGH)
++ if ((UOG_PORTSC1 & (3 << 26)) != (2 << 26))
+ return ;
++
+ while ((UOG_PORTSC1 & PORTSC_PORT_FORCE_RESUME)
+ && (index < 1000)) {
+ udelay(500);
+ index++;
+ }
++
+ if (index >= 1000)
+- printk(KERN_ERR "failed to wait for the resume finished in %s() line:%d\n",
+- __func__, __LINE__);
+- /* We should add some delay to wait for the device switch to
+- * High-Speed 45ohm termination resistors mode. */
++ printk(KERN_INFO "%s big error\n", __func__);
++
+ udelay(500);
+ fsl_platform_otg_set_usb_phy_dis(pdata, 1);
+ }
+@@ -469,24 +469,9 @@ static void _host_platform_rh_suspend(struct fsl_usb2_platform_data *pdata)
+
+ static void _host_platform_rh_resume(struct fsl_usb2_platform_data *pdata)
+ {
+- u32 index = 0;
+-
+ /*for mx6sl ,we do not need any sw fix*/
+ if (cpu_is_mx6sl())
+ return ;
+- if ((UOG_PORTSC1 & (PORTSC_PORT_SPEED_MASK)) != PORTSC_PORT_SPEED_HIGH)
+- return ;
+- while ((UOG_PORTSC1 & PORTSC_PORT_FORCE_RESUME)
+- && (index < 1000)) {
+- udelay(500);
+- index++;
+- }
+- if (index >= 1000)
+- printk(KERN_ERR "failed to wait for the resume finished in %s() line:%d\n",
+- __func__, __LINE__);
+- /* We should add some delay to wait for the device switch to
+- * High-Speed 45ohm termination resistors mode. */
+- udelay(500);
+ __raw_writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT,
+ MX6_IO_ADDRESS(pdata->phy_regs)
+ + HW_USBPHY_CTRL_SET);
+diff --git a/arch/arm/mach-mx6/usb_h1.c b/arch/arm/mach-mx6/usb_h1.c
+index bece29f..3e2f50a 100644
+--- a/arch/arm/mach-mx6/usb_h1.c
++++ b/arch/arm/mach-mx6/usb_h1.c
+@@ -244,18 +244,18 @@ static void usbh1_platform_rh_resume_swfix(struct fsl_usb2_platform_data *pdata)
+ {
+ u32 index = 0;
+
+- if ((UOG_PORTSC1 & (PORTSC_PORT_SPEED_MASK)) != PORTSC_PORT_SPEED_HIGH)
++ if ((UH1_PORTSC1 & (3 << 26)) != (2 << 26))
+ return ;
++
+ while ((UH1_PORTSC1 & PORTSC_PORT_FORCE_RESUME)
+ && (index < 1000)) {
+ udelay(500);
+ index++;
+ }
++
+ if (index >= 1000)
+- printk(KERN_ERR "failed to wait for the resume finished in %s() line:%d\n",
+- __func__, __LINE__);
+- /* We should add some delay to wait for the device switch to
+- * High-Speed 45ohm termination resistors mode. */
++ printk(KERN_INFO "%s big error\n", __func__);
++
+ udelay(500);
+ fsl_platform_h1_set_usb_phy_dis(pdata, 1);
+ }
+@@ -272,24 +272,9 @@ static void usbh1_platform_rh_suspend(struct fsl_usb2_platform_data *pdata)
+
+ static void usbh1_platform_rh_resume(struct fsl_usb2_platform_data *pdata)
+ {
+- u32 index = 0;
+-
+ /*for mx6sl ,we do not need any sw fix*/
+ if (cpu_is_mx6sl())
+ return ;
+- if ((UOG_PORTSC1 & (PORTSC_PORT_SPEED_MASK)) != PORTSC_PORT_SPEED_HIGH)
+- return ;
+- while ((UH1_PORTSC1 & PORTSC_PORT_FORCE_RESUME)
+- && (index < 1000)) {
+- udelay(500);
+- index++;
+- }
+- if (index >= 1000)
+- printk(KERN_ERR "failed to wait for the resume finished in %s() line:%d\n",
+- __func__, __LINE__);
+- /* We should add some delay to wait for the device switch to
+- * High-Speed 45ohm termination resistors mode. */
+- udelay(500);
+ __raw_writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT,
+ MX6_IO_ADDRESS(pdata->phy_regs)
+ + HW_USBPHY_CTRL_SET);
+diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/plat-mxc/clock.c b/arch/arm/plat-mxc/clock.c
+old mode 100755
+new mode 100644
+index 93347eb..ee4ea63
+--- a/arch/arm/plat-mxc/clock.c
++++ b/arch/arm/plat-mxc/clock.c
+@@ -225,18 +225,10 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
+ IS_ERR(parent) || clk->set_parent == NULL)
+ return ret;
+
+- mutex_lock(&clocks_mutex);
+-
+- if (clk->usecount) {
+- if (in_interrupt()) {
+- printk(KERN_ERR " clk_enable cannot be called in an interrupt context\n");
+- dump_stack();
+- mutex_unlock(&clocks_mutex);
+- BUG();
+- }
+- __clk_enable(parent);
+- }
++ if (clk->usecount)
++ clk_enable(parent);
+
++ mutex_lock(&clocks_mutex);
+ ret = clk->set_parent(clk, parent);
+ if (ret == 0) {
+ old = clk->parent;
+@@ -244,11 +236,11 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
+ } else {
+ old = parent;
+ }
+- if (clk->usecount)
+- __clk_disable(old);
+-
+ mutex_unlock(&clocks_mutex);
+
++ if (clk->usecount)
++ clk_disable(old);
++
+ return ret;
+ }
+ EXPORT_SYMBOL(clk_set_parent);
+diff --git a/arch/arm/plat-mxc/cpu.c b/arch/arm/plat-mxc/cpu.c
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/plat-mxc/cpufreq.c b/arch/arm/plat-mxc/cpufreq.c
+old mode 100755
+new mode 100644
+index e7278d9..b6c1e28
+--- a/arch/arm/plat-mxc/cpufreq.c
++++ b/arch/arm/plat-mxc/cpufreq.c
+@@ -42,6 +42,7 @@ static int cpu_freq_suspend_in;
+ static struct mutex set_cpufreq_lock;
+ #endif
+
++static int soc_regulator_set;
+ static int cpu_freq_khz_min;
+ static int cpu_freq_khz_max;
+
+@@ -91,21 +92,20 @@ int set_cpu_freq(int freq)
+ /* Check if the bus freq needs to be increased first */
+ bus_freq_update(cpu_clk, true);
+
+- if (!IS_ERR(soc_regulator)) {
++ if (freq == cpu_op_tbl[0].cpu_rate && !IS_ERR(soc_regulator) && !IS_ERR(pu_regulator)) {
+ ret = regulator_set_voltage(soc_regulator, soc_volt,
+ soc_volt);
+ if (ret < 0) {
+ printk(KERN_DEBUG "COULD NOT SET SOC VOLTAGE!!!!\n");
+ return ret;
+ }
+- }
+- if (!IS_ERR(pu_regulator)) {
+ ret = regulator_set_voltage(pu_regulator, pu_volt,
+ pu_volt);
+ if (ret < 0) {
+ printk(KERN_DEBUG "COULD NOT SET PU VOLTAGE!!!!\n");
+ return ret;
+ }
++ soc_regulator_set = 1;
+ }
+ ret = regulator_set_voltage(cpu_regulator, gp_volt,
+ gp_volt);
+@@ -128,21 +128,20 @@ int set_cpu_freq(int freq)
+ printk(KERN_DEBUG "COULD NOT SET GP VOLTAGE!!!!\n");
+ return ret;
+ }
+- if (!IS_ERR(soc_regulator)) {
++ if (soc_regulator_set && !IS_ERR(soc_regulator) && !IS_ERR(pu_regulator)) {
+ ret = regulator_set_voltage(soc_regulator, soc_volt,
+ soc_volt);
+ if (ret < 0) {
+ printk(KERN_DEBUG "COULD NOT SET SOC VOLTAGE BACK!!!!\n");
+ return ret;
+ }
+- }
+- if (!IS_ERR(pu_regulator)) {
+ ret = regulator_set_voltage(pu_regulator, pu_volt,
+ pu_volt);
+ if (ret < 0) {
+ printk(KERN_DEBUG "COULD NOT SET PU VOLTAGE!!!!\n");
+ return ret;
+ }
++ soc_regulator_set = 0;
+ }
+ /* Check if the bus freq can be decreased.*/
+ bus_freq_update(cpu_clk, false);
+@@ -219,7 +218,7 @@ static int mxc_set_target(struct cpufreq_policy *policy,
+ * So update it for all CPUs.
+ */
+
+- for_each_possible_cpu(i)
++ for_each_cpu(i, policy->cpus)
+ per_cpu(cpu_data, i).loops_per_jiffy =
+ cpufreq_scale(per_cpu(cpu_data, i).loops_per_jiffy,
+ freqs.old, freqs.new);
+@@ -241,11 +240,8 @@ void mxc_cpufreq_suspend(void)
+ pre_suspend_rate = clk_get_rate(cpu_clk);
+ /*set flag and raise up cpu frequency if needed*/
+ cpu_freq_suspend_in = 1;
+- if (pre_suspend_rate != (imx_freq_table[0].frequency * 1000)) {
++ if (pre_suspend_rate != (imx_freq_table[0].frequency * 1000))
+ set_cpu_freq(imx_freq_table[0].frequency * 1000);
+- loops_per_jiffy = cpufreq_scale(loops_per_jiffy,
+- pre_suspend_rate / 1000, imx_freq_table[0].frequency);
+- }
+ cpu_freq_suspend_in = 2;
+ mutex_unlock(&set_cpufreq_lock);
+
+@@ -255,11 +251,8 @@ void mxc_cpufreq_resume(void)
+ {
+ mutex_lock(&set_cpufreq_lock);
+ cpu_freq_suspend_in = 1;
+- if (clk_get_rate(cpu_clk) != pre_suspend_rate) {
++ if (clk_get_rate(cpu_clk) != pre_suspend_rate)
+ set_cpu_freq(pre_suspend_rate);
+- loops_per_jiffy = cpufreq_scale(loops_per_jiffy,
+- imx_freq_table[0].frequency, pre_suspend_rate / 1000);
+- }
+ cpu_freq_suspend_in = 0;
+ mutex_unlock(&set_cpufreq_lock);
+ }
+@@ -269,22 +262,16 @@ void mxc_cpufreq_resume(void)
+ static int mxc_cpufreq_suspend(struct cpufreq_policy *policy)
+ {
+ pre_suspend_rate = clk_get_rate(cpu_clk);
+- if (pre_suspend_rate != (imx_freq_table[0].frequency * 1000)) {
++ if (pre_suspend_rate != (imx_freq_table[0].frequency * 1000))
+ set_cpu_freq(imx_freq_table[0].frequency * 1000);
+- loops_per_jiffy = cpufreq_scale(loops_per_jiffy,
+- pre_suspend_rate / 1000, imx_freq_table[0].frequency);
+- }
+
+ return 0;
+ }
+
+ static int mxc_cpufreq_resume(struct cpufreq_policy *policy)
+ {
+- if (clk_get_rate(cpu_clk) != pre_suspend_rate) {
++ if (clk_get_rate(cpu_clk) != pre_suspend_rate)
+ set_cpu_freq(pre_suspend_rate);
+- loops_per_jiffy = cpufreq_scale(loops_per_jiffy,
+- imx_freq_table[0].frequency, pre_suspend_rate / 1000);
+- }
+ return 0;
+ }
+ #endif
+diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/plat-mxc/devices/platform-ahci-imx.c b/arch/arm/plat-mxc/devices/platform-ahci-imx.c
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/plat-mxc/devices/platform-imx-dcp.c b/arch/arm/plat-mxc/devices/platform-imx-dcp.c
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/plat-mxc/devices/platform-imx-dma.c b/arch/arm/plat-mxc/devices/platform-imx-dma.c
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/plat-mxc/devices/platform-imx-i2c.c b/arch/arm/plat-mxc/devices/platform-imx-i2c.c
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/plat-mxc/devices/platform-imx-iim.c b/arch/arm/plat-mxc/devices/platform-imx-iim.c
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/plat-mxc/devices/platform-imx-ocotp.c b/arch/arm/plat-mxc/devices/platform-imx-ocotp.c
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/plat-mxc/devices/platform-imx-rngb.c b/arch/arm/plat-mxc/devices/platform-imx-rngb.c
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/plat-mxc/devices/platform-imx-ssi.c b/arch/arm/plat-mxc/devices/platform-imx-ssi.c
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/plat-mxc/devices/platform-imx_dvfs.c b/arch/arm/plat-mxc/devices/platform-imx_dvfs.c
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/plat-mxc/devices/platform-imx_ipuv3.c b/arch/arm/plat-mxc/devices/platform-imx_ipuv3.c
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/plat-mxc/devices/platform-imx_srtc.c b/arch/arm/plat-mxc/devices/platform-imx_srtc.c
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/plat-mxc/devices/platform-imx_tve.c b/arch/arm/plat-mxc/devices/platform-imx_tve.c
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/plat-mxc/devices/platform-imx_vpu.c b/arch/arm/plat-mxc/devices/platform-imx_vpu.c
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/plat-mxc/devices/platform-mxc_gpu.c b/arch/arm/plat-mxc/devices/platform-mxc_gpu.c
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/plat-mxc/devices/platform-mxc_pwm.c b/arch/arm/plat-mxc/devices/platform-mxc_pwm.c
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c b/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/plat-mxc/dvfs_core.c b/arch/arm/plat-mxc/dvfs_core.c
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/plat-mxc/dvfs_per.c b/arch/arm/plat-mxc/dvfs_per.c
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/plat-mxc/include/mach/ahci_sata.h b/arch/arm/plat-mxc/include/mach/ahci_sata.h
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/plat-mxc/include/mach/arc_otg.h b/arch/arm/plat-mxc/include/mach/arc_otg.h
+old mode 100755
+new mode 100644
+index f2bb01c..bdb6b25
+--- a/arch/arm/plat-mxc/include/mach/arc_otg.h
++++ b/arch/arm/plat-mxc/include/mach/arc_otg.h
+@@ -246,11 +246,6 @@ extern void __iomem *imx_otg_base;
+ #define PORTSC_PTS_SERIAL (3 << 30) /* serial */
+ #define PORTSC_STS (1 << 29) /* serial xcvr select */
+ #define PORTSC_PTW (1 << 28) /* UTMI width */
+-#define PORTSC_PORT_SPEED_FULL (0x0<<26)
+-#define PORTSC_PORT_SPEED_LOW (0x1<<26)
+-#define PORTSC_PORT_SPEED_HIGH (0x2<<26)
+-#define PORTSC_PORT_SPEED_UNDEF (0x3<<26)
+-#define PORTSC_PORT_SPEED_MASK (0x3<<26)
+ #define PORTSC_HSIC_MODE (1 << 25) /* Only for HSIC */
+ #define PORTSC_PHCD (1 << 23) /* Low Power Suspend */
+ #define PORTSC_WKDC (1 << 21) /* wakeup on discnt*/
+diff --git a/arch/arm/plat-mxc/include/mach/clock.h b/arch/arm/plat-mxc/include/mach/clock.h
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/plat-mxc/include/mach/dvfs_dptc_struct.h b/arch/arm/plat-mxc/include/mach/dvfs_dptc_struct.h
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/plat-mxc/include/mach/esdhc.h b/arch/arm/plat-mxc/include/mach/esdhc.h
+index bb15db1..294e4cd 100644
+--- a/arch/arm/plat-mxc/include/mach/esdhc.h
++++ b/arch/arm/plat-mxc/include/mach/esdhc.h
+@@ -34,6 +34,7 @@ struct esdhc_platform_data {
+ unsigned int support_18v;
+ unsigned int support_8bit;
+ unsigned int keep_power_at_suspend;
++ unsigned int caps;
+ unsigned int delay_line;
+ int (*platform_pad_change)(unsigned int index, int clock);
+ };
+diff --git a/arch/arm/plat-mxc/include/mach/fsl_usb.h b/arch/arm/plat-mxc/include/mach/fsl_usb.h
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/plat-mxc/include/mach/fsl_usb_gadget.h b/arch/arm/plat-mxc/include/mach/fsl_usb_gadget.h
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/plat-mxc/include/mach/imx_rfkill.h b/arch/arm/plat-mxc/include/mach/imx_rfkill.h
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx53.h b/arch/arm/plat-mxc/include/mach/iomux-mx53.h
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx6q.h b/arch/arm/plat-mxc/include/mach/iomux-mx6q.h
+index 9226af1..83f2881 100644
+--- a/arch/arm/plat-mxc/include/mach/iomux-mx6q.h
++++ b/arch/arm/plat-mxc/include/mach/iomux-mx6q.h
+@@ -2909,6 +2909,24 @@
+ #define _MX6Q_PAD_TEST_MODE__TCU_TEST_MODE \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
++#define _MX6Q_PAD_SD2_CMD__USDHC3_CMD \
++ IOMUX_PAD(0x06A0, 0x02B8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
++
++#define _MX6Q_PAD_SD2_CLK__USDHC3_CLK \
++ IOMUX_PAD(0x06A4, 0x02BC, 0, 0x0000, 0, 0)
++
++#define _MX6Q_PAD_SD2_DAT0__USDHC3_DAT0 \
++ IOMUX_PAD(0x06A8, 0x02C0, 0, 0x0000, 0, 0)
++
++#define _MX6Q_PAD_SD2_DAT1__USDHC3_DAT1 \
++ IOMUX_PAD(0x06AC, 0x02C4, 0, 0x0000, 0, 0)
++
++#define _MX6Q_PAD_SD2_DAT2__USDHC3_DAT2 \
++ IOMUX_PAD(0x06B0, 0x02C8, 0, 0x0000, 0, 0)
++
++#define _MX6Q_PAD_SD2_DAT3__USDHC3_DAT3 \
++ IOMUX_PAD(0x06B4, 0x02CC, 0, 0x0000, 0, 0)
++
+ #define _MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 \
+ IOMUX_PAD(0x0690, 0x02A8, 0, 0x0000, 0, 0)
+ #define _MX6Q_PAD_SD3_DAT7__UART1_TXD \
+@@ -6517,6 +6535,48 @@
+ #define MX6Q_PAD_TEST_MODE__TCU_TEST_MODE \
+ (_MX6Q_PAD_TEST_MODE__TCU_TEST_MODE | MUX_PAD_CTRL(NO_PAD_CTRL))
+
++#define MX6Q_PAD_SD2_CMD__USDHC2_CMD_50MHZ \
++ (_MX6Q_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
++#define MX6Q_PAD_SD2_CMD__USDHC2_CMD_100MHZ \
++ (_MX6Q_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
++#define MX6Q_PAD_SD2_CMD__USDHC2_CMD_200MHZ \
++ (_MX6Q_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
++
++#define MX6Q_PAD_SD2_CLK__USDHC2_CLK_50MHZ \
++ (_MX6Q_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
++#define MX6Q_PAD_SD2_CLK__USDHC2_CLK_100MHZ \
++ (_MX6Q_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
++#define MX6Q_PAD_SD2_CLK__USDHC2_CLK_200MHZ \
++ (_MX6Q_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
++
++#define MX6Q_PAD_SD2_DAT0__USDHC2_DAT0_50MHZ \
++ (_MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
++#define MX6Q_PAD_SD2_DAT0__USDHC2_DAT0_100MHZ \
++ (_MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
++#define MX6Q_PAD_SD2_DAT0__USDHC2_DAT0_200MHZ \
++ (_MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
++
++#define MX6Q_PAD_SD2_DAT1__USDHC2_DAT1_50MHZ \
++ (_MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
++#define MX6Q_PAD_SD2_DAT1__USDHC2_DAT1_100MHZ \
++ (_MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
++#define MX6Q_PAD_SD2_DAT1__USDHC2_DAT1_200MHZ \
++ (_MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
++
++#define MX6Q_PAD_SD2_DAT2__USDHC2_DAT2_50MHZ \
++ (_MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
++#define MX6Q_PAD_SD2_DAT2__USDHC2_DAT2_100MHZ \
++ (_MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
++#define MX6Q_PAD_SD2_DAT2__USDHC2_DAT2_200MHZ \
++ (_MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
++
++#define MX6Q_PAD_SD2_DAT3__USDHC2_DAT3_50MHZ \
++ (_MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
++#define MX6Q_PAD_SD2_DAT3__USDHC2_DAT3_100MHZ \
++ (_MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
++#define MX6Q_PAD_SD2_DAT3__USDHC2_DAT3_200MHZ \
++ (_MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
++
+ #define MX6Q_PAD_SD3_DAT7__USDHC3_DAT7_50MHZ \
+ (_MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+ #define MX6Q_PAD_SD3_DAT7__USDHC3_DAT7_100MHZ \
+diff --git a/arch/arm/plat-mxc/include/mach/ipu-v3.h b/arch/arm/plat-mxc/include/mach/ipu-v3.h
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/plat-mxc/include/mach/mx50.h b/arch/arm/plat-mxc/include/mach/mx50.h
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/plat-mxc/include/mach/mx53.h b/arch/arm/plat-mxc/include/mach/mx53.h
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
+old mode 100755
+new mode 100644
+index 2315909..3f58604
+--- a/arch/arm/plat-mxc/include/mach/mxc.h
++++ b/arch/arm/plat-mxc/include/mach/mxc.h
+@@ -249,7 +249,6 @@ extern unsigned int __mxc_cpu_type;
+ struct cpu_op {
+ u32 pll_reg;
+ u32 pll_rate;
+- u32 pll_lpm_rate;
+ u32 cpu_rate;
+ u32 pdr0_reg;
+ u32 pdf;
+diff --git a/arch/arm/plat-mxc/include/mach/mxc91231.h b/arch/arm/plat-mxc/include/mach/mxc91231.h
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/plat-mxc/include/mach/mxc_dvfs.h b/arch/arm/plat-mxc/include/mach/mxc_dvfs.h
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/plat-mxc/include/mach/mxc_edid.h b/arch/arm/plat-mxc/include/mach/mxc_edid.h
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/plat-mxc/include/mach/mxc_vpu.h b/arch/arm/plat-mxc/include/mach/mxc_vpu.h
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/plat-mxc/include/mach/sdram_autogating.h b/arch/arm/plat-mxc/include/mach/sdram_autogating.h
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/plat-mxc/include/mach/system.h b/arch/arm/plat-mxc/include/mach/system.h
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/plat-mxc/isp1504xc.c b/arch/arm/plat-mxc/isp1504xc.c
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/plat-mxc/pwm.c b/arch/arm/plat-mxc/pwm.c
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/plat-mxc/serialxc.c b/arch/arm/plat-mxc/serialxc.c
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/plat-mxc/usb_common.c b/arch/arm/plat-mxc/usb_common.c
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/plat-mxc/usb_wakeup.c b/arch/arm/plat-mxc/usb_wakeup.c
+old mode 100755
+new mode 100644
+diff --git a/arch/arm/plat-mxc/utmixc.c b/arch/arm/plat-mxc/utmixc.c
+old mode 100755
+new mode 100644
+diff --git a/arch/powerpc/boot/wrapper b/arch/powerpc/boot/wrapper
+old mode 100755
+new mode 100644
+diff --git a/drivers/char/fsl_otp.c b/drivers/char/fsl_otp.c
+old mode 100755
+new mode 100644
+diff --git a/drivers/char/fsl_otp.h b/drivers/char/fsl_otp.h
+old mode 100755
+new mode 100644
+diff --git a/drivers/char/regs-ocotp-v2.h b/drivers/char/regs-ocotp-v2.h
+old mode 100755
+new mode 100644
+diff --git a/drivers/crypto/caam/caamhash.c b/drivers/crypto/caam/caamhash.c
+index ee06515..cdc3f3e 100644
+--- a/drivers/crypto/caam/caamhash.c
++++ b/drivers/crypto/caam/caamhash.c
+@@ -441,13 +441,7 @@ static u32 hash_digest_key(struct caam_hash_ctx *ctx, const u8 *key_in,
+ dma_addr_t src_dma, dst_dma;
+ int ret = 0;
+
+- /*
+- * Hashing descriptor is 6 commands (including header), 2 pointers,
+- * and 2 extended lengths
+- */
+- desc = kmalloc((CAAM_CMD_SZ * 6 + CAAM_PTR_SZ * 2 +
+- CAAM_EXTLEN_SZ * 2),
+- GFP_KERNEL | GFP_DMA);
++ desc = kmalloc(CAAM_CMD_SZ * 6 + CAAM_PTR_SZ * 2, GFP_KERNEL | GFP_DMA);
+
+ init_job_desc(desc, 0);
+
+@@ -1510,8 +1504,6 @@ static int ahash_init(struct ahash_request *req)
+ state->final = ahash_final_no_ctx;
+
+ state->current_buf = 0;
+- state->buflen_0 = 0;
+- state->buflen_1 = 0;
+
+ return 0;
+ }
+diff --git a/drivers/crypto/caam/desc_constr.h b/drivers/crypto/caam/desc_constr.h
+index 0393c98..c85c1f0 100644
+--- a/drivers/crypto/caam/desc_constr.h
++++ b/drivers/crypto/caam/desc_constr.h
+@@ -9,7 +9,6 @@
+ #define IMMEDIATE (1 << 23)
+ #define CAAM_CMD_SZ sizeof(u32)
+ #define CAAM_PTR_SZ sizeof(dma_addr_t)
+-#define CAAM_EXTLEN_SZ sizeof(u32)
+ #define CAAM_DESC_BYTES_MAX (CAAM_CMD_SZ * MAX_CAAM_DESCSIZE)
+
+ #ifdef DEBUG
+diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
+old mode 100755
+new mode 100644
+diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
+old mode 100755
+new mode 100644
+diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
+old mode 100755
+new mode 100644
+diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
+old mode 100755
+new mode 100644
+diff --git a/drivers/hwmon/da9052-adc.c b/drivers/hwmon/da9052-adc.c
+old mode 100755
+new mode 100644
+diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c
+index df9fca3..4c2a62b 100644
+--- a/drivers/i2c/busses/i2c-imx.c
++++ b/drivers/i2c/busses/i2c-imx.c
+@@ -141,7 +141,7 @@ static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy)
+ break;
+ if (!for_busy && !(temp & I2SR_IBB))
+ break;
+- if (fatal_signal_pending(current)) {
++ if (signal_pending(current)) {
+ dev_dbg(&i2c_imx->adapter.dev,
+ "<%s> I2C Interrupted\n", __func__);
+ return -EINTR;
+diff --git a/drivers/input/misc/Kconfig b/drivers/input/misc/Kconfig
+old mode 100755
+new mode 100644
+diff --git a/drivers/input/misc/Makefile b/drivers/input/misc/Makefile
+old mode 100755
+new mode 100644
+diff --git a/drivers/input/misc/isl29023.c b/drivers/input/misc/isl29023.c
+old mode 100755
+new mode 100644
+diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconfig
+old mode 100755
+new mode 100644
+index 7cf975a..a2589e4
+--- a/drivers/input/touchscreen/Kconfig
++++ b/drivers/input/touchscreen/Kconfig
+@@ -199,6 +199,16 @@ config TOUCHSCREEN_ELAN
+ To compile this driver as a module, choose M here: the
+ module will be called elan-touch.
+
++config TOUCHSCREEN_EGALAX_SINGLE_TOUCH
++ bool "EETI eGalax touchscreen as single-touch"
++ default N
++ depends on TOUCHSCREEN_EGALAX
++ help
++ If you say yes here you get single-touch touchscreen support
++ on the eGalax I2C controller.
++ If you say "no", you'll get the normal multi-touch.
++
++
+ config TOUCHSCREEN_FUJITSU
+ tristate "Fujitsu serial touchscreen"
+ select SERIO
+@@ -282,6 +292,22 @@ config TOUCHSCREEN_MAX11801
+ To compile this driver as a module, choose M here: the
+ module will be called max11801_ts.
+
++config TOUCHSCREEN_FT5X06
++ tristate "Focaltech FT5X06 5 point touchscreen"
++ select I2C
++ help
++ If you say yes here you get touchscreen support through
++ FocalTech's FT5X06 controller.
++
++config TOUCHSCREEN_FT5X06_SINGLE_TOUCH
++ bool "FT5X06 touchscreen as single-touch"
++ default N
++ depends on TOUCHSCREEN_FT5X06
++ help
++ If you say yes here you get single-touch touchscreen support
++ on the FT5X06 I2C controller.
++ If you say "no", you'll get the normal 5-finger goodness.
++
+ config TOUCHSCREEN_MCS5000
+ tristate "MELFAS MCS-5000 touchscreen"
+ depends on I2C
+@@ -695,6 +721,17 @@ config TOUCHSCREEN_TSC2007
+ To compile this driver as a module, choose M here: the
+ module will be called tsc2007.
+
++config TOUCHSCREEN_TSC2004
++ tristate "TSC2004 based touchscreens"
++ depends on I2C
++ help
++ Say Y here if you have a TSC2004 based touchscreen.
++
++ If unsure, say N.
++
++ To compile this driver as a module, choose M here: the
++ module will be called tsc2004.
++
+ config TOUCHSCREEN_W90X900
+ tristate "W90P910 touchscreen driver"
+ depends on HAVE_CLK
+diff --git a/drivers/input/touchscreen/Makefile b/drivers/input/touchscreen/Makefile
+old mode 100755
+new mode 100644
+index e614512..eac3453
+--- a/drivers/input/touchscreen/Makefile
++++ b/drivers/input/touchscreen/Makefile
+@@ -49,6 +49,7 @@ obj-$(CONFIG_TOUCHSCREEN_TOUCHRIGHT) += touchright.o
+ obj-$(CONFIG_TOUCHSCREEN_TOUCHWIN) += touchwin.o
+ obj-$(CONFIG_TOUCHSCREEN_TSC2005) += tsc2005.o
+ obj-$(CONFIG_TOUCHSCREEN_TSC2007) += tsc2007.o
++obj-$(CONFIG_TOUCHSCREEN_TSC2004) += tsc2004.o
+ obj-$(CONFIG_TOUCHSCREEN_UCB1400) += ucb1400_ts.o
+ obj-$(CONFIG_TOUCHSCREEN_WACOM_W8001) += wacom_w8001.o
+ obj-$(CONFIG_TOUCHSCREEN_WM831X) += wm831x-ts.o
+@@ -64,4 +65,5 @@ obj-$(CONFIG_TOUCHSCREEN_P1003) += p1003_ts.o
+ obj-$(CONFIG_TOUCHSCREEN_TPS6507X) += tps6507x-ts.o
+ obj-$(CONFIG_TOUCHSCREEN_MAX11801) += max11801_ts.o
+ obj-$(CONFIG_TOUCHSCREEN_EGALAX) += egalax_ts.o
++obj-$(CONFIG_TOUCHSCREEN_FT5X06) += ft5x06_ts.o
+ obj-$(CONFIG_TOUCHSCREEN_ELAN) += elan_ts.o
+diff --git a/drivers/input/touchscreen/da9052_tsi_filter.c b/drivers/input/touchscreen/da9052_tsi_filter.c
+old mode 100755
+new mode 100644
+diff --git a/drivers/input/touchscreen/egalax_ts.c b/drivers/input/touchscreen/egalax_ts.c
+index fff8afe..0b6cde7 100644
+--- a/drivers/input/touchscreen/egalax_ts.c
++++ b/drivers/input/touchscreen/egalax_ts.c
+@@ -139,7 +139,7 @@ retry:
+ events[id].x = x;
+ events[id].y = y;
+
+-#ifdef FORCE_SINGLE_POINTER_SUPPORT
++#ifdef CONFIG_TOUCHSCREEN_EGALAX_SINGLE_TOUCH
+ input_report_abs(input_dev, ABS_X, x);
+ input_report_abs(input_dev, ABS_Y, y);
+ input_event(data->input_dev, EV_KEY, BTN_TOUCH, 1);
+@@ -166,7 +166,7 @@ retry:
+ dev_dbg(&client->dev, "release id:%d\n", id);
+ events[id].valid = 0;
+ events[id].status = 0;
+-#ifdef FORCE_SINGLE_POINTER_SUPPORT
++#ifdef CONFIG_TOUCHSCREEN_EGALAX_SINGLE_TOUCH
+ input_report_key(input_dev, BTN_TOUCH, 0);
+ input_report_abs(input_dev, ABS_PRESSURE, 0);
+ #else
+@@ -256,8 +256,9 @@ static int __devinit egalax_ts_probe(struct i2c_client *client,
+ __set_bit(ABS_PRESSURE, input_dev->absbit);
+ input_set_abs_params(input_dev, ABS_X, 0, 32767, 0, 0);
+ input_set_abs_params(input_dev, ABS_Y, 0, 32767, 0, 0);
++ input_set_abs_params(input_dev, ABS_PRESSURE, 0, 1, 0, 0);
+
+-#ifndef FORCE_SINGLE_POINTER_SUPPORT
++#ifndef CONFIG_TOUCHSCREEN_EGALAX_SINGLE_TOUCH
+ input_set_abs_params(input_dev, ABS_MT_POSITION_X, 0, 32767, 0, 0);
+ input_set_abs_params(input_dev, ABS_MT_POSITION_Y, 0, 32767, 0, 0);
+ input_set_abs_params(input_dev, ABS_MT_TOUCH_MAJOR, 0, 255, 0, 0);
+diff --git a/drivers/input/touchscreen/ft5x06_ts.c b/drivers/input/touchscreen/ft5x06_ts.c
+new file mode 100644
+index 0000000..89b5726
+--- /dev/null
++++ b/drivers/input/touchscreen/ft5x06_ts.c
+@@ -0,0 +1,572 @@
++/*
++ * Boundary Devices FTx06 touch screen controller.
++ *
++ * Copyright (c) by Boundary Devices <info at boundarydevices.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ */
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/i2c.h>
++#include <linux/slab.h>
++#include <linux/interrupt.h>
++#include <linux/wait.h>
++#include <linux/io.h>
++#include <mach/hardware.h>
++#include <mach/gpio.h>
++#include <linux/proc_fs.h>
++#include <linux/delay.h>
++#include <linux/input.h>
++
++#ifdef CONFIG_TOUCHSCREEN_FT5X06_SINGLE_TOUCH
++#else
++#define USE_ABS_MT
++#endif
++
++struct point {
++ int x;
++ int y;
++};
++
++struct ft5x06_ts {
++ struct i2c_client *client;
++ struct input_dev *idev;
++ wait_queue_head_t sample_waitq;
++ struct semaphore sem;
++ struct completion init_exit;
++ struct task_struct *rtask;
++ int use_count;
++ int bReady;
++ int irq;
++ unsigned gp;
++ struct proc_dir_entry *procentry;
++};
++static const char *client_name = "ft5x06";
++
++struct ft5x06_ts *gts;
++
++static char const procentryname[] = {
++ "ft5x06"
++};
++
++static int ts_startup(struct ft5x06_ts *ts);
++static void ts_shutdown(struct ft5x06_ts *ts);
++
++static int ft5x06_proc_read
++ (char *page,
++ char **start,
++ off_t off,
++ int count,
++ int *eof,
++ void *data)
++{
++ printk(KERN_ERR "%s\n", __func__);
++ return 0 ;
++}
++
++static int
++ft5x06_proc_write
++ (struct file *file,
++ const char __user *buffer,
++ unsigned long count,
++ void *data)
++{
++ printk(KERN_ERR "%s\n", __func__);
++ return count ;
++}
++
++/*-----------------------------------------------------------------------*/
++static inline void ts_evt_add(struct ft5x06_ts *ts,
++ unsigned buttons, struct point *p)
++{
++ struct input_dev *idev = ts->idev;
++ int i;
++ if (!buttons) {
++ /* send release to user space. */
++#ifdef USE_ABS_MT
++ input_event(idev, EV_ABS, ABS_MT_TOUCH_MAJOR, 0);
++ input_event(idev, EV_KEY, BTN_TOUCH, 0);
++ input_mt_sync(idev);
++#else
++ input_report_abs(idev, ABS_PRESSURE, 0);
++ input_report_key(idev, BTN_TOUCH, 0);
++ input_sync(idev);
++#endif
++ } else {
++ for (i = 0; i < buttons; i++) {
++#ifdef USE_ABS_MT
++ input_event(idev, EV_ABS, ABS_MT_POSITION_X, p[i].x);
++ input_event(idev, EV_ABS, ABS_MT_POSITION_Y, p[i].y);
++ input_event(idev, EV_ABS, ABS_MT_TOUCH_MAJOR, 1);
++ input_mt_sync(idev);
++#else
++ input_report_abs(idev, ABS_X, p[i].x);
++ input_report_abs(idev, ABS_Y, p[i].y);
++ input_report_abs(idev, ABS_PRESSURE, 1);
++ input_report_key(idev, BTN_TOUCH, 1);
++ input_sync(idev);
++#endif
++ }
++ input_event(idev, EV_KEY, BTN_TOUCH, 1);
++ }
++#ifdef USE_ABS_MT
++ input_sync(idev);
++#endif
++}
++
++static int ts_open(struct input_dev *idev)
++{
++ struct ft5x06_ts *ts = input_get_drvdata(idev);
++ return ts_startup(ts);
++}
++
++static void ts_close(struct input_dev *idev)
++{
++ struct ft5x06_ts *ts = input_get_drvdata(idev);
++ ts_shutdown(ts);
++}
++
++static inline int ts_register(struct ft5x06_ts *ts)
++{
++ struct input_dev *idev;
++ idev = input_allocate_device();
++ if (idev == NULL)
++ return -ENOMEM;
++
++ ts->idev = idev;
++ idev->name = procentryname ;
++ idev->id.product = ts->client->addr;
++ idev->open = ts_open;
++ idev->close = ts_close;
++
++ __set_bit(EV_ABS, idev->evbit);
++ __set_bit(EV_KEY, idev->evbit);
++ __set_bit(BTN_TOUCH, idev->keybit);
++
++#ifdef USE_ABS_MT
++ input_set_abs_params(idev, ABS_MT_POSITION_X, 0, 1023, 0, 0);
++ input_set_abs_params(idev, ABS_MT_POSITION_Y, 0, 0x255, 0, 0);
++ input_set_abs_params(idev, ABS_MT_TOUCH_MAJOR, 0, 1, 0, 0);
++#else
++ __set_bit(EV_SYN, idev->evbit);
++ input_set_abs_params(idev, ABS_X, 0, 1023, 0, 0);
++ input_set_abs_params(idev, ABS_Y, 0, 0x255, 0, 0);
++ input_set_abs_params(idev, ABS_PRESSURE, 0, 1, 0, 0);
++#endif
++
++ input_set_drvdata(idev, ts);
++ return input_register_device(idev);
++}
++
++static inline void ts_deregister(struct ft5x06_ts *ts)
++{
++ if (ts->idev) {
++ input_unregister_device(ts->idev);
++ input_free_device(ts->idev);
++ ts->idev = NULL;
++ }
++}
++
++#ifdef DEBUG
++static void printHex(u8 const *buf, unsigned len)
++{
++ char hex[512];
++ char *next = hex ;
++ char *end = hex+sizeof(hex);
++
++ while (len--) {
++ next += snprintf(next, end-next, "%02x", *buf++);
++ if (next >= end) {
++ hex[sizeof(hex)-1] = '\0' ;
++ break;
++ }
++ }
++ printk(KERN_ERR "%s\n", hex);
++}
++#endif
++
++static void write_reg(struct ft5x06_ts *ts, int regnum, int value)
++{
++ u8 regnval[] = {
++ regnum,
++ value
++ };
++ struct i2c_msg pkt = {
++ ts->client->addr, 0, sizeof(regnval), regnval
++ };
++ int ret = i2c_transfer(ts->client->adapter, &pkt, 1);
++ if (ret != 1)
++ printk(KERN_WARNING "%s: i2c_transfer failed\n", __func__);
++ else
++ printk(KERN_DEBUG "%s: set register 0x%02x to 0x%02x\n",
++ __func__, regnum, value);
++}
++
++static void set_mode(struct ft5x06_ts *ts, int mode)
++{
++ write_reg(ts, 0, (mode&7)<<4);
++ printk(KERN_DEBUG "%s: changed mode to 0x%02x\n", __func__, mode);
++}
++
++#define WORK_MODE 0
++#define FACTORY_MODE 4
++
++/*-----------------------------------------------------------------------*/
++
++/*
++ * This is a RT kernel thread that handles the I2c accesses
++ * The I2c access functions are expected to be able to sleep.
++ */
++static int ts_thread(void *_ts)
++{
++ int ret;
++ struct point points[5];
++ unsigned char buf[33];
++ struct ft5x06_ts *ts = _ts;
++ unsigned char startch[1] = { 0 };
++ struct i2c_msg readpkt[2] = {
++ {ts->client->addr, 0, 1, startch},
++ {ts->client->addr, I2C_M_RD, sizeof(buf), buf}
++ };
++
++ struct task_struct *tsk = current;
++
++ ts->rtask = tsk;
++
++ daemonize("ft5x06tsd");
++ /* only want to receive SIGKILL */
++ allow_signal(SIGKILL);
++
++ complete(&ts->init_exit);
++
++ do {
++ int buttons = 0 ;
++ ts->bReady = 0;
++ ret = i2c_transfer(ts->client->adapter, readpkt,
++ ARRAY_SIZE(readpkt));
++ if (ret != ARRAY_SIZE(readpkt)) {
++ printk(KERN_WARNING "%s: i2c_transfer failed\n",
++ client_name);
++ msleep(1000);
++ } else {
++ int i;
++ unsigned char *p = buf+3;
++#ifdef DEBUG
++ printHex(buf, sizeof(buf));
++#endif
++ buttons = buf[2];
++ if (buttons > 5) {
++ printk(KERN_ERR
++ "%s: invalid button count %02x\n",
++ __func__, buttons);
++ buttons = 0 ;
++ } else {
++ for (i = 0; i < buttons; i++) {
++ points[i].x = ((p[0] << 8)
++ | p[1]) & 0x7ff;
++ points[i].y = ((p[2] << 8)
++ | p[3]) & 0x7ff;
++ p += 6;
++ }
++ }
++ }
++
++ if (signal_pending(tsk))
++ break;
++#ifdef DEBUG
++ printk(KERN_ERR "%s: buttons = %d, "
++ "points[0].x = %d, "
++ "points[0].y = %d\n",
++ client_name, buttons, points[0].x, points[0].y);
++#endif
++ ts_evt_add(ts, buttons, points);
++ if (0 < buttons)
++ wait_event_interruptible_timeout(ts->sample_waitq,
++ ts->bReady, HZ/20);
++ else
++ wait_event_interruptible(ts->sample_waitq, ts->bReady);
++ if (gpio_get_value(ts->gp)) {
++ if (buttons) {
++ buttons = 0;
++ ts_evt_add(ts, buttons, points);
++ }
++ if (signal_pending(tsk))
++ break;
++ }
++ } while (1);
++
++ ts->rtask = NULL;
++ complete_and_exit(&ts->init_exit, 0);
++}
++
++/*
++ * We only detect samples ready with this interrupt
++ * handler, and even then we just schedule our task.
++ */
++static irqreturn_t ts_interrupt(int irq, void *id)
++{
++ struct ft5x06_ts *ts = id;
++ int bit = gpio_get_value(ts->gp);
++ if (bit == 0) {
++ ts->bReady = 1;
++ wmb(); /* flush bReady */
++ wake_up(&ts->sample_waitq);
++ }
++ return IRQ_HANDLED;
++}
++
++#define ID_G_THGROUP 0x80
++#define ID_G_PERIODMONITOR 0x89
++#define FT5X0X_REG_HEIGHT_B 0x8a
++#define FT5X0X_REG_MAX_FRAME 0x8b
++#define FT5X0X_REG_FEG_FRAME 0x8e
++#define FT5X0X_REG_LEFT_RIGHT_OFFSET 0x92
++#define FT5X0X_REG_UP_DOWN_OFFSET 0x93
++#define FT5X0X_REG_DISTANCE_LEFT_RIGHT 0x94
++#define FT5X0X_REG_DISTANCE_UP_DOWN 0x95
++#define FT5X0X_REG_MAX_X_HIGH 0x98
++#define FT5X0X_REG_MAX_X_LOW 0x99
++#define FT5X0X_REG_MAX_Y_HIGH 0x9a
++#define FT5X0X_REG_MAX_Y_LOW 0x9b
++#define FT5X0X_REG_K_X_HIGH 0x9c
++#define FT5X0X_REG_K_X_LOW 0x9d
++#define FT5X0X_REG_K_Y_HIGH 0x9e
++#define FT5X0X_REG_K_Y_LOW 0x9f
++
++#define ID_G_AUTO_CLB 0xa0
++#define ID_G_B_AREA_TH 0xae
++
++#ifdef DEBUG
++static void dumpRegs(struct ft5x06_ts *ts, unsigned start, unsigned end)
++{
++ u8 regbuf[512];
++ unsigned char startch[1] = { start };
++ int ret ;
++ struct i2c_msg readpkt[2] = {
++ {ts->client->addr, 0, 1, startch},
++ {ts->client->addr, I2C_M_RD, end-start+1, regbuf}
++ };
++ ret = i2c_transfer(ts->client->adapter, readpkt, ARRAY_SIZE(readpkt));
++ if (ret != ARRAY_SIZE(readpkt)) {
++ printk(KERN_WARNING "%s: i2c_transfer failed\n", client_name);
++ } else {
++ printk(KERN_ERR "registers %02x..%02x\n", start, end);
++ printHex(regbuf, end-start+1);
++ }
++}
++#endif
++
++static int ts_startup(struct ft5x06_ts *ts)
++{
++ int ret = 0;
++ if (ts == NULL)
++ return -EIO;
++
++ if (down_interruptible(&ts->sem))
++ return -EINTR;
++
++ if (ts->use_count++ != 0)
++ goto out;
++
++ if (ts->rtask)
++ panic("ft5x06tsd: rtask running?");
++
++ ret = request_irq(ts->irq, &ts_interrupt, IRQF_TRIGGER_FALLING,
++ client_name, ts);
++ if (ret) {
++ printk(KERN_ERR "%s: request_irq failed, irq:%i\n",
++ client_name, ts->irq);
++ goto out;
++ }
++
++#ifdef DEBUG
++ set_mode(ts, FACTORY_MODE);
++ dumpRegs(ts, 0x4c, 0x4C);
++ write_reg(ts, 0x4C, 0x05);
++ dumpRegs(ts, 0, 0x4C);
++#endif
++ set_mode(ts, WORK_MODE);
++#ifdef DEBUG
++ dumpRegs(ts, 0x3b, 0x3b);
++ dumpRegs(ts, 0x6a, 0x6a);
++ dumpRegs(ts, ID_G_THGROUP, ID_G_PERIODMONITOR);
++ dumpRegs(ts, FT5X0X_REG_HEIGHT_B, FT5X0X_REG_K_Y_LOW);
++ dumpRegs(ts, ID_G_AUTO_CLB, ID_G_B_AREA_TH);
++#endif
++ set_mode(ts, WORK_MODE);
++
++ init_completion(&ts->init_exit);
++ ret = kernel_thread(ts_thread, ts, CLONE_KERNEL);
++ if (ret >= 0) {
++ wait_for_completion(&ts->init_exit);
++ ret = 0;
++ } else {
++ free_irq(ts->irq, ts);
++ }
++
++ out:
++ if (ret)
++ ts->use_count--;
++ up(&ts->sem);
++ return ret;
++}
++
++/*
++ * Release touchscreen resources. Disable IRQs.
++ */
++static void ts_shutdown(struct ft5x06_ts *ts)
++{
++ if (ts) {
++ down(&ts->sem);
++ if (--ts->use_count == 0) {
++ if (ts->rtask) {
++ send_sig(SIGKILL, ts->rtask, 1);
++ wait_for_completion(&ts->init_exit);
++ }
++ free_irq(ts->irq, ts);
++ }
++ up(&ts->sem);
++ }
++}
++/*-----------------------------------------------------------------------*/
++
++/* Return 0 if detection is successful, -ENODEV otherwise */
++static int detect_ft5x06(struct i2c_client *client)
++{
++ struct i2c_adapter *adapter = client->adapter;
++ char buffer;
++ struct i2c_msg pkt = {
++ client->addr,
++ I2C_M_RD,
++ sizeof(buffer),
++ &buffer
++ };
++ if (!i2c_check_functionality(adapter, I2C_FUNC_I2C))
++ return -ENODEV;
++ if (i2c_transfer(adapter, &pkt, 1) != 1)
++ return -ENODEV;
++ return 0;
++}
++
++/* Return 0 if detection is successful, -ENODEV otherwise */
++static int ts_detect(struct i2c_client *client,
++ struct i2c_board_info *info)
++{
++ int err = detect_ft5x06(client);
++ if (!err)
++ strlcpy(info->type, "ft5x06-ts", I2C_NAME_SIZE);
++ return err;
++}
++
++static int ts_probe(struct i2c_client *client, const struct i2c_device_id *id)
++{
++ int err = 0;
++ struct ft5x06_ts *ts;
++ struct device *dev = &client->dev;
++ if (gts) {
++ printk(KERN_ERR "%s: Error gts is already allocated\n",
++ client_name);
++ return -ENOMEM;
++ }
++ if (detect_ft5x06(client) != 0) {
++ dev_err(dev, "%s: Could not detect touch screen.\n",
++ client_name);
++ return -ENODEV;
++ }
++ ts = kzalloc(sizeof(struct ft5x06_ts), GFP_KERNEL);
++ if (!ts) {
++ dev_err(dev, "Couldn't allocate memory for %s\n", client_name);
++ return -ENOMEM;
++ }
++ init_waitqueue_head(&ts->sample_waitq);
++ sema_init(&ts->sem, 1);
++ ts->client = client;
++ ts->irq = client->irq ;
++ ts->gp = irq_to_gpio(client->irq);
++ printk(KERN_INFO "%s: %s touchscreen irq=%i, gp=%i\n", __func__,
++ client_name, ts->irq, ts->gp);
++ i2c_set_clientdata(client, ts);
++ err = ts_register(ts);
++ if (err == 0) {
++ gts = ts;
++ ts->procentry = create_proc_entry(procentryname, 0, NULL);
++ if (ts->procentry) {
++ ts->procentry->read_proc = ft5x06_proc_read ;
++ ts->procentry->write_proc = ft5x06_proc_write ;
++ }
++ } else {
++ printk(KERN_WARNING "%s: ts_register failed\n", client_name);
++ ts_deregister(ts);
++ kfree(ts);
++ }
++ return err;
++}
++
++static int ts_remove(struct i2c_client *client)
++{
++ struct ft5x06_ts *ts = i2c_get_clientdata(client);
++ remove_proc_entry(procentryname, 0);
++ if (ts == gts) {
++ gts = NULL;
++ ts_deregister(ts);
++ } else {
++ printk(KERN_ERR "%s: Error ts!=gts\n", client_name);
++ }
++ kfree(ts);
++ return 0;
++}
++
++
++/*-----------------------------------------------------------------------*/
++
++static const struct i2c_device_id ts_idtable[] = {
++ { "ft5x06-ts", 0 },
++ { }
++};
++
++static struct i2c_driver ts_driver = {
++ .driver = {
++ .owner = THIS_MODULE,
++ .name = "ft5x06-ts",
++ },
++ .id_table = ts_idtable,
++ .probe = ts_probe,
++ .remove = __devexit_p(ts_remove),
++ .detect = ts_detect,
++};
++
++static int __init ts_init(void)
++{
++ int res = i2c_add_driver(&ts_driver);
++ if (res) {
++ printk(KERN_WARNING "%s: i2c_add_driver failed\n", client_name);
++ return res;
++ }
++ printk(KERN_INFO "%s: " __DATE__ "\n", client_name);
++ return 0;
++}
++
++static void __exit ts_exit(void)
++{
++ i2c_del_driver(&ts_driver);
++}
++
++MODULE_AUTHOR("Boundary Devices <info at boundarydevices.com>");
++MODULE_DESCRIPTION("I2C interface for FocalTech ft5x06 touch screen controller.");
++MODULE_LICENSE("GPL");
++
++module_init(ts_init)
++module_exit(ts_exit)
+diff --git a/drivers/input/touchscreen/max11801_ts.c b/drivers/input/touchscreen/max11801_ts.c
+old mode 100755
+new mode 100644
+diff --git a/drivers/input/touchscreen/tsc2004.c b/drivers/input/touchscreen/tsc2004.c
+new file mode 100644
+index 0000000..37af845
+--- /dev/null
++++ b/drivers/input/touchscreen/tsc2004.c
+@@ -0,0 +1,561 @@
++/*
++ * drivers/input/touchscreen/tsc2004.c
++ *
++ * Copyright (C) 2009 Texas Instruments Inc
++ * Author: Vaibhav Hiremath <hvaibhav at ti.com>
++ *
++ * Using code from:
++ * - tsc2007.c
++ *
++ * This package is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ */
++
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/input.h>
++#include <linux/interrupt.h>
++#include <linux/i2c.h>
++#include <linux/i2c/tsc2007.h>
++
++static int calibration[7];
++module_param_array(calibration, int, NULL, S_IRUGO | S_IWUSR);
++
++static void translate(u16 *px, u16 *py)
++{
++ int x, y, x1, y1;
++ if (calibration[6]) {
++ x1 = *px;
++ y1 = *py;
++
++ x = calibration[0] * x1 +
++ calibration[1] * y1 +
++ calibration[2];
++ x /= calibration[6];
++ if (x < 0)
++ x = 0;
++ y = calibration[3] * x1 +
++ calibration[4] * y1 +
++ calibration[5];
++ y /= calibration[6];
++ if (y < 0)
++ y = 0;
++ *px = x ;
++ *py = y ;
++ }
++}
++
++#define TS_POLL_DELAY 1 /* ms delay between samples */
++#define TS_POLL_PERIOD 1 /* ms delay between samples */
++
++/* Control byte 0 */
++#define TSC2004_CMD0(addr, pnd, rw) ((addr<<3)|(pnd<<1)|rw)
++/* Control byte 1 */
++#define TSC2004_CMD1(cmd, mode, rst) ((1<<7)|(cmd<<4)|(mode<<2)|(rst<<1))
++
++/* Command Bits */
++#define READ_REG 1
++#define WRITE_REG 0
++#define SWRST_TRUE 1
++#define SWRST_FALSE 0
++#define PND0_TRUE 1
++#define PND0_FALSE 0
++
++/* Converter function mapping */
++enum convertor_function {
++ MEAS_X_Y_Z1_Z2, /* Measure X,Y,z1 and Z2: 0x0 */
++ MEAS_X_Y, /* Measure X and Y only: 0x1 */
++ MEAS_X, /* Measure X only: 0x2 */
++ MEAS_Y, /* Measure Y only: 0x3 */
++ MEAS_Z1_Z2, /* Measure Z1 and Z2 only: 0x4 */
++ MEAS_AUX, /* Measure Auxillary input: 0x5 */
++ MEAS_TEMP1, /* Measure Temparature1: 0x6 */
++ MEAS_TEMP2, /* Measure Temparature2: 0x7 */
++ MEAS_AUX_CONT, /* Continuously measure Auxillary input: 0x8 */
++ X_DRV_TEST, /* X-Axis drivers tested 0x9 */
++ Y_DRV_TEST, /* Y-Axis drivers tested 0xA */
++ /*Command Reserved*/
++ SHORT_CKT_TST = 0xC, /* Short circuit test: 0xC */
++ XP_XN_DRV_STAT, /* X+,Y- drivers status: 0xD */
++ YP_YN_DRV_STAT, /* X+,Y- drivers status: 0xE */
++ YP_XN_DRV_STAT /* Y+,X- drivers status: 0xF */
++};
++
++/* Register address mapping */
++enum register_address {
++ X_REG, /* X register: 0x0 */
++ Y_REG, /* Y register: 0x1 */
++ Z1_REG, /* Z1 register: 0x2 */
++ Z2_REG, /* Z2 register: 0x3 */
++ AUX_REG, /* AUX register: 0x4 */
++ TEMP1_REG, /* Temp1 register: 0x5 */
++ TEMP2_REG, /* Temp2 register: 0x6 */
++ STAT_REG, /* Status Register: 0x7 */
++ AUX_HGH_TH_REG, /* AUX high threshold register: 0x8 */
++ AUX_LOW_TH_REG, /* AUX low threshold register: 0x9 */
++ TMP_HGH_TH_REG, /* Temp high threshold register:0xA */
++ TMP_LOW_TH_REG, /* Temp low threshold register: 0xB */
++ CFR0_REG, /* Configuration register 0: 0xC */
++ CFR1_REG, /* Configuration register 1: 0xD */
++ CFR2_REG, /* Configuration register 2: 0xE */
++ CONV_FN_SEL_STAT /* Convertor function select register: 0xF */
++};
++
++/* Supported Resolution modes */
++enum resolution_mode {
++ MODE_10BIT, /* 10 bit resolution */
++ MODE_12BIT /* 12 bit resolution */
++};
++
++/* Configuraton register bit fields */
++/* CFR0 */
++#define PEN_STS_CTRL_MODE (1<<15)
++#define ADC_STS (1<<14)
++#define RES_CTRL (1<<13)
++#define ADC_CLK_4MHZ (0<<11)
++#define ADC_CLK_2MHZ (1<<11)
++#define ADC_CLK_1MHZ (2<<11)
++#define PANEL_VLTG_STB_TIME_0US (0<<8)
++#define PANEL_VLTG_STB_TIME_100US (1<<8)
++#define PANEL_VLTG_STB_TIME_500US (2<<8)
++#define PANEL_VLTG_STB_TIME_1MS (3<<8)
++#define PANEL_VLTG_STB_TIME_5MS (4<<8)
++#define PANEL_VLTG_STB_TIME_10MS (5<<8)
++#define PANEL_VLTG_STB_TIME_50MS (6<<8)
++#define PANEL_VLTG_STB_TIME_100MS (7<<8)
++
++/* CFR2 */
++#define PINTS1 (1<<15)
++#define PINTS0 (1<<14)
++#define MEDIAN_VAL_FLTR_SIZE_1 (0<<12)
++#define MEDIAN_VAL_FLTR_SIZE_3 (1<<12)
++#define MEDIAN_VAL_FLTR_SIZE_7 (2<<12)
++#define MEDIAN_VAL_FLTR_SIZE_15 (3<<12)
++#define AVRG_VAL_FLTR_SIZE_1 (0<<10)
++#define AVRG_VAL_FLTR_SIZE_3_4 (1<<10)
++#define AVRG_VAL_FLTR_SIZE_7_8 (2<<10)
++#define AVRG_VAL_FLTR_SIZE_16 (3<<10)
++#define MAV_FLTR_EN_X (1<<4)
++#define MAV_FLTR_EN_Y (1<<3)
++#define MAV_FLTR_EN_Z (1<<2)
++
++#define MAX_12BIT ((1 << 12) - 1)
++#define MEAS_MASK 0xFFF
++
++struct ts_event {
++ u16 x;
++ u16 y;
++ u16 z1, z2;
++};
++
++struct tsc2004 {
++ struct input_dev *input;
++ char phys[32];
++ struct delayed_work work;
++
++ struct i2c_client *client;
++
++ u16 model;
++ u16 x_plate_ohms;
++
++ bool pendown;
++ int irq;
++
++ int (*get_pendown_state)(void);
++ void (*clear_penirq)(void);
++};
++
++static inline int tsc2004_read_xyz_data(struct tsc2004 *tsc, u8 cmd)
++{
++ s32 data;
++ u16 val;
++
++ data = i2c_smbus_read_word_data(tsc->client, cmd);
++ if (data < 0) {
++ dev_err(&tsc->client->dev, "i2c io (read) error: %d\n", data);
++ return data;
++ }
++
++ /*
++ * We need to swap byte order for little-endian cpus.
++ * 12 bit precision, high 4 bits should be zero
++ */
++ val = be16_to_cpu(data) & 0xfff;
++
++ dev_dbg(&tsc->client->dev, "data: 0x%x, val: 0x%x\n", data, val);
++
++ return val;
++}
++
++static inline int tsc2004_write_word_data(struct tsc2004 *tsc, u8 cmd, u16 data)
++{
++ u16 val;
++
++ val = cpu_to_be16(data);
++ return i2c_smbus_write_word_data(tsc->client, cmd, val);
++}
++
++static inline int tsc2004_write_cmd(struct tsc2004 *tsc, u8 value)
++{
++ return i2c_smbus_write_byte(tsc->client, value);
++}
++
++static int tsc2004_prepare_for_reading(struct tsc2004 *ts)
++{
++ int err;
++ int cmd, data;
++ int retries ;
++
++ /* Reset the TSC, configure for 12 bit */
++ retries = 0 ;
++ do {
++ /* Reset the TSC, configure for 12 bit */
++ cmd = TSC2004_CMD1(MEAS_X_Y_Z1_Z2, MODE_12BIT, SWRST_TRUE);
++ err = tsc2004_write_cmd(ts, cmd);
++ if (err < 0)
++ printk (KERN_ERR "%s: write_cmd %d\n", __func__, err );
++ } while ( (err < 0) && (3 < retries++) );
++
++ if (err < 0)
++ return err ;
++
++ /* Enable interrupt for PENIRQ and DAV */
++ cmd = TSC2004_CMD0(CFR2_REG, PND0_FALSE, WRITE_REG);
++ data = PINTS1 | PINTS0 | MEDIAN_VAL_FLTR_SIZE_15 |
++ AVRG_VAL_FLTR_SIZE_7_8 | MAV_FLTR_EN_X | MAV_FLTR_EN_Y |
++ MAV_FLTR_EN_Z;
++ err = tsc2004_write_word_data(ts, cmd, data);
++ if (err < 0)
++ return err;
++
++ /* Configure the TSC in TSMode 1 */
++ cmd = TSC2004_CMD0(CFR0_REG, PND0_FALSE, WRITE_REG);
++ data = PEN_STS_CTRL_MODE | ADC_CLK_2MHZ | PANEL_VLTG_STB_TIME_1MS;
++ err = tsc2004_write_word_data(ts, cmd, data);
++ if (err < 0)
++ return err;
++
++ /* Enable x, y, z1 and z2 conversion functions */
++ cmd = TSC2004_CMD1(MEAS_X_Y_Z1_Z2, MODE_12BIT, SWRST_FALSE);
++ err = tsc2004_write_cmd(ts, cmd);
++ if (err < 0)
++ return err;
++
++ return 0;
++}
++
++static void tsc2004_read_values(struct tsc2004 *tsc, struct ts_event *tc)
++{
++ int cmd;
++
++ /* Read X Measurement */
++ cmd = TSC2004_CMD0(X_REG, PND0_FALSE, READ_REG);
++ tc->x = tsc2004_read_xyz_data(tsc, cmd);
++
++ /* Read Y Measurement */
++ cmd = TSC2004_CMD0(Y_REG, PND0_FALSE, READ_REG);
++ tc->y = tsc2004_read_xyz_data(tsc, cmd);
++
++ /* Read Z1 Measurement */
++ cmd = TSC2004_CMD0(Z1_REG, PND0_FALSE, READ_REG);
++ tc->z1 = tsc2004_read_xyz_data(tsc, cmd);
++
++ /* Read Z2 Measurement */
++ cmd = TSC2004_CMD0(Z2_REG, PND0_FALSE, READ_REG);
++ tc->z2 = tsc2004_read_xyz_data(tsc, cmd);
++
++
++ tc->x &= MEAS_MASK;
++ tc->y &= MEAS_MASK;
++ tc->z1 &= MEAS_MASK;
++ tc->z2 &= MEAS_MASK;
++
++ /* Prepare for touch readings */
++ if (tsc2004_prepare_for_reading(tsc) < 0)
++ dev_dbg(&tsc->client->dev, "Failed to prepare TSC for next"
++ "reading\n");
++}
++
++static u32 tsc2004_calculate_pressure(struct tsc2004 *tsc, struct ts_event *tc)
++{
++ u32 rt = 0;
++
++ /* range filtering */
++ if (tc->x == MAX_12BIT)
++ tc->x = 0;
++
++ if (likely(tc->x && tc->z1)) {
++ /* compute touch pressure resistance using equation #1 */
++ rt = tc->z2 - tc->z1;
++ rt *= tc->x;
++ rt *= tsc->x_plate_ohms;
++ rt /= tc->z1;
++ rt = (rt + 2047) >> 12;
++ }
++
++ return rt;
++}
++
++static void tsc2004_send_up_event(struct tsc2004 *tsc)
++{
++ struct input_dev *input = tsc->input;
++
++ dev_dbg(&tsc->client->dev, "UP\n");
++
++ input_report_key(input, BTN_TOUCH, 0);
++ input_report_abs(input, ABS_PRESSURE, 0);
++ input_sync(input);
++}
++
++static void tsc2004_work(struct work_struct *work)
++{
++ struct tsc2004 *ts =
++ container_of(to_delayed_work(work), struct tsc2004, work);
++ struct ts_event tc;
++ u32 rt;
++
++ /*
++ * NOTE: We can't rely on the pressure to determine the pen down
++ * state, even though this controller has a pressure sensor.
++ * The pressure value can fluctuate for quite a while after
++ * lifting the pen and in some cases may not even settle at the
++ * expected value.
++ *
++ * The only safe way to check for the pen up condition is in the
++ * work function by reading the pen signal state (it's a GPIO
++ * and IRQ). Unfortunately such callback is not always available,
++ * in that case we have rely on the pressure anyway.
++ */
++ if (ts->get_pendown_state) {
++ if (unlikely(!ts->get_pendown_state())) {
++ tsc2004_send_up_event(ts);
++ ts->pendown = false;
++ goto out;
++ }
++
++ dev_dbg(&ts->client->dev, "pen is still down\n");
++ }
++
++ tsc2004_read_values(ts, &tc);
++
++ rt = tsc2004_calculate_pressure(ts, &tc);
++ if (rt > MAX_12BIT) {
++ /*
++ * Sample found inconsistent by debouncing or pressure is
++ * beyond the maximum. Don't report it to user space,
++ * repeat at least once more the measurement.
++ */
++ dev_dbg(&ts->client->dev, "ignored pressure %d\n", rt);
++ goto out;
++
++ }
++
++ if (rt) {
++ struct input_dev *input = ts->input;
++
++ translate(&tc.x, &tc.y);
++
++ if (!ts->pendown) {
++ dev_dbg(&ts->client->dev, "DOWN\n");
++
++ input_report_key(input, BTN_TOUCH, 1);
++ ts->pendown = true;
++ }
++
++ input_report_abs(input, ABS_X, tc.x);
++ input_report_abs(input, ABS_Y, tc.y);
++ input_report_abs(input, ABS_PRESSURE, rt);
++
++ input_sync(input);
++
++ dev_dbg(&ts->client->dev, "point(%4d,%4d), pressure (%4u)\n",
++ tc.x, tc.y, rt);
++
++ } else if (!ts->get_pendown_state && ts->pendown) {
++ /*
++ * We don't have callback to check pendown state, so we
++ * have to assume that since pressure reported is 0 the
++ * pen was lifted up.
++ */
++ tsc2004_send_up_event(ts);
++ ts->pendown = false;
++ }
++
++ out:
++ if (ts->pendown)
++ schedule_delayed_work(&ts->work,
++ msecs_to_jiffies(TS_POLL_PERIOD));
++ else
++ enable_irq(ts->irq);
++}
++
++static irqreturn_t tsc2004_irq(int irq, void *handle)
++{
++ struct tsc2004 *ts = handle;
++
++ if (!ts->get_pendown_state || likely(ts->get_pendown_state())) {
++ disable_irq_nosync(ts->irq);
++ schedule_delayed_work(&ts->work,
++ msecs_to_jiffies(TS_POLL_DELAY));
++ }
++
++ if (ts->clear_penirq)
++ ts->clear_penirq();
++
++ return IRQ_HANDLED;
++}
++
++static void tsc2004_free_irq(struct tsc2004 *ts)
++{
++ free_irq(ts->irq, ts);
++ if (cancel_delayed_work_sync(&ts->work)) {
++ /*
++ * Work was pending, therefore we need to enable
++ * IRQ here to balance the disable_irq() done in the
++ * interrupt handler.
++ */
++ enable_irq(ts->irq);
++ }
++}
++
++static int __devinit tsc2004_probe(struct i2c_client *client,
++ const struct i2c_device_id *id)
++{
++ struct tsc2004 *ts;
++ struct tsc2007_platform_data *pdata = pdata = client->dev.platform_data;
++ struct input_dev *input_dev;
++ int err;
++
++ if (!pdata) {
++ dev_err(&client->dev, "platform data is required!\n");
++ return -EINVAL;
++ }
++
++ if (!i2c_check_functionality(client->adapter,
++ I2C_FUNC_SMBUS_READ_WORD_DATA))
++ return -EIO;
++
++ ts = kzalloc(sizeof(struct tsc2004), GFP_KERNEL);
++ input_dev = input_allocate_device();
++ if (!ts || !input_dev) {
++ err = -ENOMEM;
++ goto err_free_mem;
++ }
++
++ ts->client = client;
++ ts->irq = client->irq;
++ ts->input = input_dev;
++ INIT_DELAYED_WORK(&ts->work, tsc2004_work);
++
++ ts->model = pdata->model;
++ ts->x_plate_ohms = pdata->x_plate_ohms;
++ ts->get_pendown_state = pdata->get_pendown_state;
++ ts->clear_penirq = pdata->clear_penirq;
++
++ snprintf(ts->phys, sizeof(ts->phys),
++ "%s/input0", dev_name(&client->dev));
++
++ input_dev->name = "tsc2004";
++ input_dev->phys = ts->phys;
++ input_dev->id.bustype = BUS_I2C;
++
++ input_dev->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS);
++ input_dev->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH);
++
++ input_set_abs_params(input_dev, ABS_X, 0, MAX_12BIT, 0, 0);
++ input_set_abs_params(input_dev, ABS_Y, 0, MAX_12BIT, 0, 0);
++ input_set_abs_params(input_dev, ABS_PRESSURE, 0, MAX_12BIT, 0, 0);
++
++ if (pdata->init_platform_hw)
++ pdata->init_platform_hw();
++
++ err = request_irq(ts->irq, tsc2004_irq, IRQF_TRIGGER_FALLING,
++ client->dev.driver->name, ts);
++ if (err < 0) {
++ dev_err(&client->dev, "irq %d busy?\n", ts->irq);
++ goto err_free_mem;
++ }
++
++ /* Prepare for touch readings */
++ err = tsc2004_prepare_for_reading(ts);
++ if (err < 0)
++ goto err_free_irq;
++
++ err = input_register_device(input_dev);
++ if (err)
++ goto err_free_irq;
++
++ i2c_set_clientdata(client, ts);
++
++ return 0;
++
++ err_free_irq:
++ tsc2004_free_irq(ts);
++ if (pdata->exit_platform_hw)
++ pdata->exit_platform_hw();
++ err_free_mem:
++ input_free_device(input_dev);
++ kfree(ts);
++ return err;
++}
++
++static int __devexit tsc2004_remove(struct i2c_client *client)
++{
++ struct tsc2004 *ts = i2c_get_clientdata(client);
++ struct tsc2007_platform_data *pdata = client->dev.platform_data;
++
++ tsc2004_free_irq(ts);
++
++ if (pdata->exit_platform_hw)
++ pdata->exit_platform_hw();
++
++ input_unregister_device(ts->input);
++ kfree(ts);
++
++ return 0;
++}
++
++static struct i2c_device_id tsc2004_idtable[] = {
++ { "tsc2004", 0 },
++ { }
++};
++
++MODULE_DEVICE_TABLE(i2c, tsc2004_idtable);
++
++static struct i2c_driver tsc2004_driver = {
++ .driver = {
++ .owner = THIS_MODULE,
++ .name = "tsc2004"
++ },
++ .id_table = tsc2004_idtable,
++ .probe = tsc2004_probe,
++ .remove = __devexit_p(tsc2004_remove),
++};
++
++static int __init tsc2004_init(void)
++{
++ return i2c_add_driver(&tsc2004_driver);
++}
++
++static void __exit tsc2004_exit(void)
++{
++ i2c_del_driver(&tsc2004_driver);
++}
++
++module_init(tsc2004_init);
++module_exit(tsc2004_exit);
++
++MODULE_AUTHOR("Vaibhav Hiremath <hvaibhav at ti.com>");
++MODULE_DESCRIPTION("TSC2004 TouchScreen Driver");
++MODULE_LICENSE("GPL");
+diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig
+old mode 100755
+new mode 100644
+diff --git a/drivers/leds/Makefile b/drivers/leds/Makefile
+old mode 100755
+new mode 100644
+diff --git a/drivers/media/video/mxc/capture/ov5642.c b/drivers/media/video/mxc/capture/ov5642.c
+index 492748c..245a92c 100644
+--- a/drivers/media/video/mxc/capture/ov5642.c
++++ b/drivers/media/video/mxc/capture/ov5642.c
+@@ -3228,7 +3228,6 @@ err:
+ static int ov5642_write_snapshot_para(enum ov5642_frame_rate frame_rate,
+ enum ov5642_mode mode)
+ {
+- int ret = 0;
+ bool m_60Hz = false;
+ u16 capture_frame_rate = 50;
+ u16 g_preview_frame_rate = 225;
+@@ -3256,10 +3255,7 @@ static int ov5642_write_snapshot_para(enum ov5642_frame_rate frame_rate,
+ gain = 0;
+ ov5642_read_reg(0x350b, &gain);
+
+- ret = ov5642_init_mode(frame_rate, mode);
+- if (ret < 0)
+- return ret;
+-
++ ov5642_init_mode(frame_rate, mode);
+ ret_h = ret_m = ret_l = 0;
+ ov5642_read_reg(0x380e, &ret_h);
+ ov5642_read_reg(0x380f, &ret_l);
+@@ -3335,7 +3331,7 @@ static int ov5642_write_snapshot_para(enum ov5642_frame_rate frame_rate,
+ ov5642_write_reg(0x3500, exposure_high);
+ msleep(500);
+
+- return ret ;
++ return 0;
+ }
+
+
+diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
+old mode 100755
+new mode 100644
+diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
+old mode 100755
+new mode 100644
+diff --git a/drivers/mfd/da9052-core.c b/drivers/mfd/da9052-core.c
+old mode 100755
+new mode 100644
+diff --git a/drivers/mfd/da9052-i2c.c b/drivers/mfd/da9052-i2c.c
+old mode 100755
+new mode 100644
+diff --git a/drivers/mfd/mxc-hdmi-core.c b/drivers/mfd/mxc-hdmi-core.c
+index a07db1b..3328436 100644
+--- a/drivers/mfd/mxc-hdmi-core.c
++++ b/drivers/mfd/mxc-hdmi-core.c
+@@ -41,7 +41,6 @@
+ #include <linux/mfd/mxc-hdmi-core.h>
+ #include <linux/fsl_devices.h>
+ #include <mach/hardware.h>
+-#include <linux/mfd/mxc-hdmi-core.h>
+
+ struct mxc_hdmi_data {
+ struct platform_device *pdev;
+@@ -64,111 +63,6 @@ int mxc_hdmi_disp_id;
+ static struct mxc_edid_cfg hdmi_core_edid_cfg;
+ static int hdmi_core_init;
+ static unsigned int hdmi_dma_running;
+-static struct snd_pcm_substream *hdmi_audio_stream_playback;
+-static unsigned int hdmi_cable_state;
+-static unsigned int hdmi_blank_state;
+-static spinlock_t hdmi_audio_lock, hdmi_blank_state_lock, hdmi_cable_state_lock;
+-
+-
+-unsigned int hdmi_set_cable_state(unsigned int state)
+-{
+- unsigned long flags;
+- struct snd_pcm_substream *substream = hdmi_audio_stream_playback;
+-
+- spin_lock_irqsave(&hdmi_cable_state_lock, flags);
+- hdmi_cable_state = state;
+- spin_unlock_irqrestore(&hdmi_cable_state_lock, flags);
+-
+- if (check_hdmi_state() && substream)
+- substream->ops->trigger(substream, SNDRV_PCM_TRIGGER_START);
+- return 0;
+-}
+-
+-unsigned int hdmi_set_blank_state(unsigned int state)
+-{
+- unsigned long flags;
+- struct snd_pcm_substream *substream = hdmi_audio_stream_playback;
+-
+- spin_lock_irqsave(&hdmi_blank_state_lock, flags);
+- hdmi_blank_state = state;
+- spin_unlock_irqrestore(&hdmi_blank_state_lock, flags);
+-
+- if (check_hdmi_state() && substream)
+- substream->ops->trigger(substream, SNDRV_PCM_TRIGGER_START);
+-
+- return 0;
+-}
+-
+-static void hdmi_audio_abort_stream(struct snd_pcm_substream *substream)
+-{
+- unsigned long flags;
+-
+- snd_pcm_stream_lock_irqsave(substream, flags);
+-
+- if (snd_pcm_running(substream))
+- substream->ops->trigger(substream, SNDRV_PCM_TRIGGER_STOP);
+-
+- snd_pcm_stream_unlock_irqrestore(substream, flags);
+-}
+-
+-int mxc_hdmi_abort_stream(void)
+-{
+- unsigned long flags;
+- spin_lock_irqsave(&hdmi_audio_lock, flags);
+- if (hdmi_audio_stream_playback)
+- hdmi_audio_abort_stream(hdmi_audio_stream_playback);
+- spin_unlock_irqrestore(&hdmi_audio_lock, flags);
+-
+- return 0;
+-}
+-
+-int check_hdmi_state(void)
+-{
+- unsigned long flags1, flags2;
+- unsigned int ret;
+-
+- spin_lock_irqsave(&hdmi_cable_state_lock, flags1);
+- spin_lock_irqsave(&hdmi_blank_state_lock, flags2);
+-
+- ret = hdmi_cable_state && hdmi_blank_state;
+-
+- spin_unlock_irqrestore(&hdmi_blank_state_lock, flags2);
+- spin_unlock_irqrestore(&hdmi_cable_state_lock, flags1);
+-
+- return ret;
+-}
+-
+-int mxc_hdmi_register_audio(struct snd_pcm_substream *substream)
+-{
+- unsigned long flags, flags1;
+- int ret = 0;
+-
+- snd_pcm_stream_lock_irqsave(substream, flags);
+-
+- if (substream && check_hdmi_state()) {
+- spin_lock_irqsave(&hdmi_audio_lock, flags1);
+- if (hdmi_audio_stream_playback) {
+- pr_err("%s unconsist hdmi auido stream!\n", __func__);
+- ret = -EINVAL;
+- }
+- hdmi_audio_stream_playback = substream;
+- spin_unlock_irqrestore(&hdmi_audio_lock, flags1);
+- } else
+- ret = -EINVAL;
+-
+- snd_pcm_stream_unlock_irqrestore(substream, flags);
+-
+- return ret;
+-}
+-
+-void mxc_hdmi_unregister_audio(struct snd_pcm_substream *substream)
+-{
+- unsigned long flags;
+-
+- spin_lock_irqsave(&hdmi_audio_lock, flags);
+- hdmi_audio_stream_playback = NULL;
+- spin_unlock_irqrestore(&hdmi_audio_lock, flags);
+-}
+
+ u8 hdmi_readb(unsigned int reg)
+ {
+@@ -572,7 +466,6 @@ static int mxc_hdmi_core_probe(struct platform_device *pdev)
+ struct fsl_mxc_hdmi_core_platform_data *pdata = pdev->dev.platform_data;
+ struct mxc_hdmi_data *hdmi_data;
+ struct resource *res;
+- unsigned long flags;
+ int ret = 0;
+
+ #ifdef DEBUG
+@@ -602,23 +495,6 @@ static int mxc_hdmi_core_probe(struct platform_device *pdev)
+ spin_lock_init(&irq_spinlock);
+ spin_lock_init(&edid_spinlock);
+
+-
+- spin_lock_init(&hdmi_cable_state_lock);
+- spin_lock_init(&hdmi_blank_state_lock);
+- spin_lock_init(&hdmi_audio_lock);
+-
+- spin_lock_irqsave(&hdmi_cable_state_lock, flags);
+- hdmi_cable_state = 0;
+- spin_unlock_irqrestore(&hdmi_cable_state_lock, flags);
+-
+- spin_lock_irqsave(&hdmi_blank_state_lock, flags);
+- hdmi_blank_state = 0;
+- spin_unlock_irqrestore(&hdmi_blank_state_lock, flags);
+-
+- spin_lock_irqsave(&hdmi_audio_lock, flags);
+- hdmi_audio_stream_playback = NULL;
+- spin_unlock_irqrestore(&hdmi_audio_lock, flags);
+-
+ isfr_clk = clk_get(&hdmi_data->pdev->dev, "hdmi_isfr_clk");
+ if (IS_ERR(isfr_clk)) {
+ ret = PTR_ERR(isfr_clk);
+diff --git a/drivers/mmc/core/sdio_cis.c b/drivers/mmc/core/sdio_cis.c
+index 541bdb8..3b0ca83 100644
+--- a/drivers/mmc/core/sdio_cis.c
++++ b/drivers/mmc/core/sdio_cis.c
+@@ -230,6 +230,7 @@ static int sdio_read_cis(struct mmc_card *card, struct sdio_func *func)
+ int ret;
+ struct sdio_func_tuple *this, **prev;
+ unsigned i, ptr = 0;
++ unsigned ptr_null_end;
+
+ /*
+ * Note that this works for the common CIS (function number 0) as
+@@ -258,6 +259,7 @@ static int sdio_read_cis(struct mmc_card *card, struct sdio_func *func)
+
+ BUG_ON(*prev);
+
++ ptr_null_end = (ptr | 0xff) + 1;
+ do {
+ unsigned char tpl_code, tpl_link;
+
+@@ -269,6 +271,9 @@ static int sdio_read_cis(struct mmc_card *card, struct sdio_func *func)
+ if (tpl_code == 0xff)
+ break;
+
++ if ((tpl_code == 0x00) && (ptr == ptr_null_end))
++ break; /* patch for misbehaving rtl8712 card */
++
+ /* null entries have no link field or data */
+ if (tpl_code == 0x00)
+ continue;
+@@ -282,9 +287,10 @@ static int sdio_read_cis(struct mmc_card *card, struct sdio_func *func)
+ break;
+
+ this = kmalloc(sizeof(*this) + tpl_link, GFP_KERNEL);
+- if (!this)
+- return -ENOMEM;
+-
++ if (!this) {
++ ret = -ENOMEM;
++ break;
++ }
+ for (i = 0; i < tpl_link; i++) {
+ ret = mmc_io_rw_direct(card, 0, 0,
+ ptr + i, 0, &this->data[i]);
+@@ -328,6 +334,12 @@ static int sdio_read_cis(struct mmc_card *card, struct sdio_func *func)
+ * not going to be queued for a driver.
+ */
+ kfree(this);
++ if (ret) {
++ printk(KERN_WARNING "%s: dropping invalid"
++ " CIS tuple 0x%02x (%u bytes)\n",
++ mmc_hostname(card->host),
++ tpl_code, tpl_link);
++ }
+ }
+
+ ptr += tpl_link;
+diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
+index e173686..2e3330c 100644
+--- a/drivers/mmc/host/sdhci-esdhc-imx.c
++++ b/drivers/mmc/host/sdhci-esdhc-imx.c
+@@ -849,6 +849,7 @@ static int esdhc_pltfm_init(struct sdhci_host *host, struct sdhci_pltfm_data *pd
+ host->ocr_avail_sd |= MMC_VDD_165_195;
+ if (boarddata->support_8bit)
+ host->mmc->caps |= MMC_CAP_8_BIT_DATA;
++ host->mmc->caps |= boarddata->caps;
+ if (boarddata->keep_power_at_suspend)
+ host->mmc->pm_caps |= (MMC_PM_KEEP_POWER | \
+ MMC_PM_WAKE_SDIO_IRQ);
+diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
+old mode 100755
+new mode 100644
+diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
+index 01c81fa..75c2e61 100644
+--- a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
++++ b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
+@@ -30,9 +30,6 @@
+
+ #define FEATURE_SIZE 4 /* p1, p2, p3, p4 */
+ #define NAND_CMD_SET_FEATURE 0xef
+-#define NAND_CMD_GET_FEATURE 0xee
+-#define ONFI_ASYNC_MODE_4 (1 << 4)
+-#define ONFI_ASYNC_MODE_5 (1 << 5)
+
+ struct timing_threshod timing_default_threshold = {
+ .max_data_setup_cycles = (BM_GPMI_TIMING0_DATA_SETUP >>
+@@ -311,139 +308,6 @@ inline bool is_ddr_nand(struct gpmi_nand_data *this)
+ return this->nand.onfi_version;
+ }
+
+-/*
+- * Firstly, we should know what's the GPMI-clock-period means.
+- * The GPMI-clock-period is the internal clock in the gpmi nand controller.
+- * If you set 100MHz to gpmi nand controller, the GPMI-clock-period is 10ns.
+- *
+- * Now, we begin to describe how to compute the right RDN_DELAY.
+- *
+- * 1) From the aspect of the nand chip pin:
+- * Delay = (tREA + C - tRP) [1]
+- *
+- * tREA : the maximum read access time. From the ONFI nand standards,
+- * we know that tREA is 16ns in mode 5, tREA is 20ns is mode 4.
+- * Please check it in : www.onfi.org
+- * C : a constant for adjust the delay. Choose 4 or 3.
+- * tRP : the read pulse width.
+- * Specified by the HW_GPMI_TIMING0:DATA_SETUP:
+- * tRP = (GPMI-clock-period) * DATA_SETUP
+- *
+- * 2) From the aspect of the GPMI nand controller:
+- * Delay = RDN_DELAY * 0.125 * RP [2]
+- *
+- * RP : the DLL reference period.
+- * if (GPMI-clock-period > 12ns)
+- * RP = GPMI-clock-period / 2;
+- * else
+- * RP = GPMI-clock-period;
+- *
+- * Set the HW_GPMI_CTRL1:HALF_PERIOD if GPMI-clock-period
+- * is greater 12ns.
+- *
+- * 3) since [1] equals [2], we get:
+- *
+- * (tREA + 4 - tRP) * 8
+- * RDN_DELAY = --------------------- [3]
+- * RP
+- *
+- * 4) We only support the fastest asynchronous mode of ONFI nand.
+- * For some ONFI nand, the mode 4 is the fastest mode;
+- * while for some ONFI nand, the mode 5 is the fastest mode.
+- * So we only support the mode 4 and mode 5. It is no need to
+- * support other modes.
+- */
+-static void set_edo_timing(struct gpmi_nand_data *this,
+- struct gpmi_nfc_hardware_timing *hw)
+-{
+- int mode = this->timing_mode;
+-
+- /* for GPMI_HW_GPMI_TIMING0 */
+- hw->data_setup_in_cycles = 1;
+- hw->data_hold_in_cycles = 1;
+- hw->address_setup_in_cycles = ((5 == mode) ? 1 : 0);
+-
+- /* for GPMI_HW_GPMI_TIMING1 */
+- hw->device_busy_timeout = 0x9000;
+-
+- /* for GPMI_HW_GPMI_CTRL1 */
+- hw->wrn_dly_sel = 3; /* no delay for write strobe. */
+- if (GPMI_IS_MX6Q(this)) {
+- /*
+- * for mx6q, we give a parameter table about the delay:
+- * delay | half_period
+- * + -------------------------+
+- * (mode 5) | 8 | 0 |
+- * ------ | -------------------------+
+- * (mode 4) | 0xe | 1 |
+- * + -------------------------+
+- */
+- if (mode == 5) {
+- hw->sample_delay_factor = 8;
+- hw->use_half_periods = 0;
+- } else /* mode == 4 */{
+- hw->sample_delay_factor = 0xe;
+- hw->use_half_periods = 1;
+- }
+- }
+-}
+-
+-static int enable_edo_mode(struct gpmi_nand_data *this, int mode)
+-{
+- struct resources *r = &this->resources;
+- struct nand_chip *nand = &this->nand;
+- struct mtd_info *mtd = &this->mtd;
+- uint8_t device_feature[FEATURE_SIZE];
+- int status;
+-
+- nand->select_chip(mtd, 0);
+-
+- /* [1] send SET FEATURE commond to NAND */
+- memset(device_feature, 0, sizeof(device_feature));
+- device_feature[0] = mode & 0x7;
+-
+- nand->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
+- nand->cmdfunc(mtd, NAND_CMD_SET_FEATURE, 1, -1);
+- nand->write_buf(mtd, device_feature, FEATURE_SIZE);
+- status = nand->waitfunc(mtd, nand);
+- if (status & 1) {
+- printk(KERN_ERR "fail !!\n");
+- return -EINVAL;
+- }
+-
+- memset(device_feature, 0, 4);
+- nand->cmdfunc(mtd, NAND_CMD_GET_FEATURE, 1, -1);
+- nand->read_buf(mtd, device_feature, 4);
+- if (device_feature[0] != mode) {
+- printk(KERN_ERR "failed in set feature of mode : %d\n", mode);
+- return -EINVAL;
+-
+- }
+-
+- nand->select_chip(mtd, -1);
+-
+- /* [2] about the clock, pay attention! */
+- {
+- unsigned long rate;
+- struct clk *enfc_clk;
+-
+- enfc_clk = clk_get(NULL, "enfc_clk");
+- if (IS_ERR(enfc_clk)) {
+- printk(KERN_INFO "No enfc_clk clock\n");
+- return -EINVAL;
+- }
+-
+- clk_set_parent(r->clock, enfc_clk);
+- rate = (mode == 5) ? 100000000 : 80000000;
+- clk_set_rate(enfc_clk, enfc_clk->round_rate(enfc_clk, rate));
+- clk_set_rate(r->clock, rate);
+- }
+-
+- this->flags |= ASYNC_EDO_ENABLED;
+- this->timing_mode = mode;
+- dev_info(this->dev, "enable asynchronous EDO mode %d\n", mode);
+- return 0;
+-}
+ /* To check if we need to initialize something else*/
+ int extra_init(struct gpmi_nand_data *this)
+ {
+@@ -453,24 +317,6 @@ int extra_init(struct gpmi_nand_data *this)
+ if (0)
+ return enable_ddr_toggle(this);
+ }
+-
+- /* Enable the asynchronous EDO mode, we only support the mode 4 and 5 */
+- if (is_ddr_nand(this)) {
+- struct nand_chip *nand = &this->nand;
+- int mode;
+-
+- mode = le16_to_cpu(nand->onfi_params.async_timing_mode);
+-
+- if (mode & ONFI_ASYNC_MODE_5)
+- mode = 5;
+- else if (mode & ONFI_ASYNC_MODE_4)
+- mode = 4;
+- else
+- return 0;
+-
+- return enable_edo_mode(this, mode);
+- }
+-
+ return 0;
+ }
+
+@@ -708,7 +554,6 @@ static int gpmi_nfc_compute_hardware_timing(struct gpmi_nand_data *this,
+ {
+ struct gpmi_nand_platform_data *pdata = this->pdata;
+ struct timing_threshod *nfc = &timing_default_threshold;
+- struct resources *r = &this->resources;
+ struct nand_chip *nand = &this->nand;
+ struct nand_timing target = this->timing;
+ bool improved_timing_is_available;
+@@ -748,7 +593,6 @@ static int gpmi_nfc_compute_hardware_timing(struct gpmi_nand_data *this,
+ (target.tRHOH_in_ns >= 0) ;
+
+ /* Inspect the clock. */
+- nfc->clock_frequency_in_hz = clk_get_rate(r->clock);
+ clock_frequency_in_hz = nfc->clock_frequency_in_hz;
+ clock_period_in_ns = 1000000000 / clock_frequency_in_hz;
+
+@@ -1145,8 +989,6 @@ return_results:
+ hw->address_setup_in_cycles = address_setup_in_cycles;
+ hw->use_half_periods = dll_use_half_periods;
+ hw->sample_delay_factor = sample_delay_factor;
+- hw->device_busy_timeout = 0x500; /* default busy timeout value. */
+- hw->wrn_dly_sel = 0;
+
+ /* Return success. */
+ return 0;
+@@ -1156,6 +998,7 @@ return_results:
+ void gpmi_begin(struct gpmi_nand_data *this)
+ {
+ struct resources *r = &this->resources;
++ struct timing_threshod *nfc = &timing_default_threshold;
+ unsigned char *gpmi_regs = r->gpmi_regs;
+ unsigned int clock_period_in_ns;
+ uint32_t reg;
+@@ -1177,32 +1020,26 @@ void gpmi_begin(struct gpmi_nand_data *this)
+ }
+ }
+
+- if (this->flags & ASYNC_EDO_ENABLED) {
+- if (this->flags & ASYNC_EDO_TIMING_CONFIGED)
+- return;
+- set_edo_timing(this, &hw);
+- this->flags |= ASYNC_EDO_TIMING_CONFIGED;
+- } else {
+- gpmi_nfc_compute_hardware_timing(this, &hw);
+- }
++ /* set ready/busy timeout */
++ writel(0x500 << BP_GPMI_TIMING1_BUSY_TIMEOUT,
++ gpmi_regs + HW_GPMI_TIMING1);
++
++ /* Get the timing information we need. */
++ nfc->clock_frequency_in_hz = clk_get_rate(r->clock);
++ clock_period_in_ns = 1000000000 / nfc->clock_frequency_in_hz;
+
+- /* [1] Set HW_GPMI_TIMING0 */
++ gpmi_nfc_compute_hardware_timing(this, &hw);
++
++ /* Set up all the simple timing parameters. */
+ reg = BF_GPMI_TIMING0_ADDRESS_SETUP(hw.address_setup_in_cycles) |
+ BF_GPMI_TIMING0_DATA_HOLD(hw.data_hold_in_cycles) |
+ BF_GPMI_TIMING0_DATA_SETUP(hw.data_setup_in_cycles) ;
+
+ writel(reg, gpmi_regs + HW_GPMI_TIMING0);
+
+- /* [2] Set HW_GPMI_TIMING1 */
+- writel(BF_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(hw.device_busy_timeout),
+- gpmi_regs + HW_GPMI_TIMING1);
+-
+- /* [3] The following code is to set the HW_GPMI_CTRL1. */
+- writel(BM_GPMI_CTRL1_WRN_DLY_SEL, gpmi_regs + HW_GPMI_CTRL1_CLR);
+- writel(BF_GPMI_CTRL1_WRN_DLY_SEL(hw.wrn_dly_sel),
+- gpmi_regs + HW_GPMI_CTRL1_SET);
+-
+- /* DLL_ENABLE must be set to 0 when setting RDN_DELAY or HALF_PERIOD. */
++ /*
++ * DLL_ENABLE must be set to 0 when setting RDN_DELAY or HALF_PERIOD.
++ */
+ writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_CLR);
+
+ /* Clear out the DLL control fields. */
+@@ -1213,23 +1050,30 @@ void gpmi_begin(struct gpmi_nand_data *this)
+ if (!hw.sample_delay_factor)
+ return;
+
++ /* Configure the HALF_PERIOD flag. */
+ if (hw.use_half_periods)
+ writel(BM_GPMI_CTRL1_HALF_PERIOD,
+- gpmi_regs + HW_GPMI_CTRL1_SET);
++ gpmi_regs + HW_GPMI_CTRL1_SET);
++
++ /* Set the delay factor. */
+ writel(BF_GPMI_CTRL1_RDN_DELAY(hw.sample_delay_factor),
+- gpmi_regs + HW_GPMI_CTRL1_SET);
++ gpmi_regs + HW_GPMI_CTRL1_SET);
++
++ /* Enable the DLL. */
+ writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_SET);
+
+ /*
+ * After we enable the GPMI DLL, we have to wait 64 clock cycles before
+- * we can use the GPMI. Calculate the amount of time we need to wait,
+- * in microseconds.
++ * we can use the GPMI.
++ *
++ * Calculate the amount of time we need to wait, in microseconds.
+ */
+- clock_period_in_ns = 1000000000 / clk_get_rate(r->clock);
+-
+ dll_wait_time_in_us = (clock_period_in_ns * 64) / 1000;
++
+ if (!dll_wait_time_in_us)
+ dll_wait_time_in_us = 1;
++
++ /* Wait for the DLL to settle. */
+ udelay(dll_wait_time_in_us);
+
+ err_out:
+diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
+index 21e1f65..229b2c5 100644
+--- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
++++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
+@@ -120,8 +120,6 @@ struct nand_timing {
+ int8_t tRHOH_in_ns;
+ };
+
+-#define ASYNC_EDO_ENABLED 1
+-#define ASYNC_EDO_TIMING_CONFIGED 2
+ struct gpmi_nand_data {
+ /* System Interface */
+ struct device *dev;
+@@ -183,8 +181,6 @@ struct gpmi_nand_data {
+
+ /* private */
+ void *private;
+- int flags;
+- int timing_mode;
+ };
+
+ /**
+@@ -192,27 +188,16 @@ struct gpmi_nand_data {
+ * @data_setup_in_cycles: The data setup time, in cycles.
+ * @data_hold_in_cycles: The data hold time, in cycles.
+ * @address_setup_in_cycles: The address setup time, in cycles.
+- * @device_busy_timeout: The timeout waiting for NAND Ready/Busy,
+- * this value is the number of cycles multiplied
+- * by 4096.
+ * @use_half_periods: Indicates the clock is running slowly, so the
+ * NFC DLL should use half-periods.
+ * @sample_delay_factor: The sample delay factor.
+- * @wrn_dly_sel: The delay on the GPMI write strobe.
+ */
+ struct gpmi_nfc_hardware_timing {
+- /* for GPMI_HW_GPMI_TIMING0 */
+ uint8_t data_setup_in_cycles;
+ uint8_t data_hold_in_cycles;
+ uint8_t address_setup_in_cycles;
+-
+- /* for GPMI_HW_GPMI_TIMING1 */
+- uint16_t device_busy_timeout;
+-
+- /* for GPMI_HW_GPMI_CTRL1 */
+ bool use_half_periods;
+ uint8_t sample_delay_factor;
+- uint8_t wrn_dly_sel;
+ };
+
+ /**
+diff --git a/drivers/mxc/ipu3/ipu_common.c b/drivers/mxc/ipu3/ipu_common.c
+index 5954eb6..c97d159 100644
+--- a/drivers/mxc/ipu3/ipu_common.c
++++ b/drivers/mxc/ipu3/ipu_common.c
+@@ -248,8 +248,8 @@ static int __devinit ipu_probe(struct platform_device *pdev)
+ if (plat_data->init)
+ plat_data->init(pdev->id);
+
+- ipu->irq_err = platform_get_irq(pdev, 0);
+- ipu->irq_sync = platform_get_irq(pdev, 1);
++ ipu->irq_sync = platform_get_irq(pdev, 0);
++ ipu->irq_err = platform_get_irq(pdev, 1);
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+ if (!res || ipu->irq_sync < 0 || ipu->irq_err < 0) {
+@@ -2381,13 +2381,15 @@ static irqreturn_t ipu_irq_handler(int irq, void *desc)
+ uint32_t int_ctrl;
+ const int err_reg[] = { 5, 6, 9, 10, 0 };
+ const int int_reg[] = { 1, 2, 3, 4, 11, 12, 13, 14, 15, 0 };
+-
+- spin_lock(&ipu->spin_lock);
++ unsigned long lock_flags;
++ uint32_t oneshot;
+
+ for (i = 0;; i++) {
+ if (err_reg[i] == 0)
+ break;
+
++ spin_lock_irqsave(&ipu->spin_lock, lock_flags);
++
+ int_stat = ipu_cm_read(ipu, IPU_INT_STAT(err_reg[i]));
+ int_stat &= ipu_cm_read(ipu, IPU_INT_CTRL(err_reg[i]));
+ if (int_stat) {
+@@ -2400,34 +2402,41 @@ static irqreturn_t ipu_irq_handler(int irq, void *desc)
+ ipu_cm_read(ipu, IPU_INT_CTRL(err_reg[i])) & ~int_stat;
+ ipu_cm_write(ipu, int_stat, IPU_INT_CTRL(err_reg[i]));
+ }
++
++ spin_unlock_irqrestore(&ipu->spin_lock, lock_flags);
+ }
+
+ for (i = 0;; i++) {
+ if (int_reg[i] == 0)
+ break;
+-
++ spin_lock_irqsave(&ipu->spin_lock, lock_flags);
+ int_stat = ipu_cm_read(ipu, IPU_INT_STAT(int_reg[i]));
+ int_ctrl = ipu_cm_read(ipu, IPU_INT_CTRL(int_reg[i]));
+ int_stat &= int_ctrl;
+ ipu_cm_write(ipu, int_stat, IPU_INT_STAT(int_reg[i]));
++ spin_unlock_irqrestore(&ipu->spin_lock, lock_flags);
++ oneshot = 0;
+ while ((line = ffs(int_stat)) != 0) {
+ bit = --line;
+ int_stat &= ~(1UL << line);
+ line += (int_reg[i] - 1) * 32;
++ if (ipu->irq_list[line].flags & IPU_IRQF_ONESHOT)
++ oneshot |= 1UL << bit;
+ result |=
+ ipu->irq_list[line].handler(line,
+ ipu->irq_list[line].
+ dev_id);
+- if (ipu->irq_list[line].flags & IPU_IRQF_ONESHOT) {
+- int_ctrl &= ~(1UL << bit);
+- ipu_cm_write(ipu, int_ctrl,
+- IPU_INT_CTRL(int_reg[i]));
+- }
++ }
++ if (oneshot) {
++ spin_lock_irqsave(&ipu->spin_lock, lock_flags);
++ if ((~int_ctrl) & oneshot)
++ BUG();
++ int_ctrl &= ~oneshot;
++ ipu_cm_write(ipu, int_ctrl, IPU_INT_CTRL(int_reg[i]));
++ spin_unlock_irqrestore(&ipu->spin_lock, lock_flags);
+ }
+ }
+
+- spin_unlock(&ipu->spin_lock);
+-
+ return result;
+ }
+
+diff --git a/drivers/mxc/mlb/mxc_mlb150.c b/drivers/mxc/mlb/mxc_mlb150.c
+old mode 100755
+new mode 100644
+diff --git a/drivers/mxc/thermal/cooling.c b/drivers/mxc/thermal/cooling.c
+index 0feefea..772f771 100644
+--- a/drivers/mxc/thermal/cooling.c
++++ b/drivers/mxc/thermal/cooling.c
+@@ -177,7 +177,6 @@ int anatop_thermal_cpu_hotplug(bool cpu_on)
+ sys_write(fd, (char *)"1", MAX_CPU_ONLINE_LEN);
+ cpu_mask &= ~(0x1 << cpu);
+ ret = 0;
+- sys_close(fd);
+ break;
+ }
+ sys_close(fd);
+@@ -199,7 +198,6 @@ int anatop_thermal_cpu_hotplug(bool cpu_on)
+ sys_write(fd, (char *)"0", MAX_CPU_ONLINE_LEN);
+ cpu_mask |= 0x1 << cpu;
+ ret = 0;
+- sys_close(fd);
+ break;
+ }
+ sys_close(fd);
+diff --git a/drivers/mxc/thermal/thermal.c b/drivers/mxc/thermal/thermal.c
+index 0982a7b..dc0fd9b 100644
+--- a/drivers/mxc/thermal/thermal.c
++++ b/drivers/mxc/thermal/thermal.c
+@@ -131,17 +131,22 @@
+ #define MEASURE_FREQ 3276 /* 3276 RTC clocks delay, 100ms */
+ #define KELVIN_TO_CEL(t, off) (((t) - (off)))
+ #define CEL_TO_KELVIN(t, off) (((t) + (off)))
+-#define DEFAULT_RATIO 145
+-#define DEFAULT_N40C 1563
+-#define REG_VALUE_TO_CEL(ratio, raw) ((raw_n40c - raw) * 100 / ratio - 40)
++
++#define DEFAULT_RAW_25C 1469
++#define DEFAULT_RAW_HOT 1375
++#define DEFAULT_TEMP_HOT 90
++
+ #define ANATOP_DEBUG false
+ #define THERMAL_FUSE_NAME "/sys/fsl_otp/HW_OCOTP_ANA1"
+
+ /* variables */
+ unsigned long anatop_base;
+-unsigned int ratio;
+-unsigned int raw_25c, raw_hot, hot_temp, raw_n40c, raw_125c, raw_critical;
++unsigned int raw_critical;
+ static struct clk *pll3_clk;
++unsigned raw_25c;
++unsigned long long cvt_to_celsius;
++unsigned long long cvt_to_raw;
++
+ static bool full_run = true;
+ static bool suspend_flag;
+ static unsigned int thermal_irq;
+@@ -255,6 +260,7 @@ static int anatop_dump_temperature_register(void)
+ __raw_readl(anatop_base + HW_ANADIG_ANA_MISC1));
+ return 0;
+ }
++
+ static void anatop_update_alarm(unsigned int alarm_value)
+ {
+ if (cooling_device_disable || suspend_flag)
+@@ -267,6 +273,21 @@ static void anatop_update_alarm(unsigned int alarm_value)
+
+ return;
+ }
++
++int cvt_raw_to_celius(unsigned raw)
++{
++ int change = (raw_25c - raw);
++ change = (int)((change * cvt_to_celsius) >> 32);
++ return 25 + change;
++}
++
++int cvt_celius_to_raw(int celius)
++{
++ int change = (celius - 25);
++ change = (int)((change * cvt_to_raw) >> 32);
++ return raw_25c - change;
++}
++
+ static int anatop_thermal_get_temp(struct thermal_zone_device *thermal,
+ long *temp)
+ {
+@@ -277,7 +298,7 @@ static int anatop_thermal_get_temp(struct thermal_zone_device *thermal,
+ if (!tz)
+ return -EINVAL;
+
+- if (!ratio || suspend_flag) {
++ if (!raw_25c || suspend_flag) {
+ *temp = KELVIN_TO_CEL(TEMP_ACTIVE, KELVIN_OFFSET);
+ return 0;
+ }
+@@ -320,12 +341,13 @@ static int anatop_thermal_get_temp(struct thermal_zone_device *thermal,
+
+ if (ANATOP_DEBUG)
+ anatop_dump_temperature_register();
+- /* only the temp between -40C and 125C is valid, this
++
++ /* only the temp between -25C and 125C is valid, this
+ is for save */
+- if (tmp <= raw_n40c && tmp >= raw_125c)
+- tz->temperature = REG_VALUE_TO_CEL(ratio, tmp);
+- else {
+- printk(KERN_WARNING "Invalid temperature, force it to 25C\n");
++ tz->temperature = cvt_raw_to_celius(tmp);
++ if ((tz->temperature < -25) || (tz->temperature > 125)) {
++ pr_warn("Invalid temperature %ld C, force it to 25C\n",
++ tz->temperature);
+ tz->temperature = 25;
+ }
+
+@@ -482,7 +504,7 @@ static int anatop_thermal_set_trip_temp(struct thermal_zone_device *thermal,
+ if (tz->trips.critical.flags.valid) {
+ tz->trips.critical.temperature = CEL_TO_KELVIN(
+ *temp, tz->kelvin_offset);
+- raw_critical = raw_25c - ratio * (*temp - 25) / 100;
++ raw_critical = cvt_celius_to_raw(*temp);
+ anatop_update_alarm(raw_critical);
+ }
+ break;
+@@ -826,31 +848,48 @@ __setup("no_cooling_device", anatop_thermal_cooling_device_disable);
+
+ static int anatop_thermal_counting_ratio(unsigned int fuse_data)
+ {
++ unsigned raw25c, raw_hot, hot_temp;
+ int ret = -EINVAL;
+
+ pr_info("Thermal calibration data is 0x%x\n", fuse_data);
+- if (fuse_data == 0 || fuse_data == 0xffffffff || (fuse_data & 0xff) == 0) {
+- pr_info("%s: invalid calibration data, disable cooling!!!\n", __func__);
+- cooling_device_disable = true;
+- ratio = DEFAULT_RATIO;
+- disable_irq(thermal_irq);
+- return ret;
+- }
+
+ ret = 0;
+ /* Fuse data layout:
+ * [31:20] sensor value @ 25C
+ * [19:8] sensor value of hot
+ * [7:0] hot temperature value */
+- raw_25c = fuse_data >> 20;
++ raw25c = fuse_data >> 20;
+ raw_hot = (fuse_data & 0xfff00) >> 8;
+ hot_temp = fuse_data & 0xff;
+
+- ratio = ((raw_25c - raw_hot) * 100) / (hot_temp - 25);
+- raw_n40c = raw_25c + (13 * ratio) / 20;
+- raw_125c = raw_25c - ratio;
++ if ((raw25c <= raw_hot) || (hot_temp <= 25)) {
++ pr_info("%s: invalid calibration data, disable cooling!!! raw25c=%x raw_hot=%x hot_temp=%x\n",
++ __func__, raw25c, raw_hot, hot_temp);
++ cooling_device_disable = true;
++ raw_25c = DEFAULT_RAW_25C;
++ disable_irq(thermal_irq);
++ cvt_to_celsius = (DEFAULT_TEMP_HOT - 25);
++ cvt_to_celsius <<= 32;
++ cvt_to_celsius /= DEFAULT_RAW_25C - DEFAULT_RAW_HOT;
++
++ cvt_to_raw = DEFAULT_RAW_25C - DEFAULT_RAW_HOT;
++ cvt_to_raw <<= 32;
++ cvt_to_raw /= (DEFAULT_TEMP_HOT - 25);
++ return ret;
++ }
++ ret = 0;
++ raw_25c = raw25c;
++ cvt_to_celsius = hot_temp - 25; /* hot_temp > 25 */
++ cvt_to_celsius <<= 32;
++ do_div(cvt_to_celsius, raw25c - raw_hot); /* raw25c > raw_hot */
++
++ cvt_to_raw = raw25c - raw_hot;
++ cvt_to_raw <<= 32;
++ do_div(cvt_to_raw, hot_temp - 25);
++ pr_info("%s: raw25c=%d raw_hot=%d hot_temp=%d\n", __func__, raw25c, raw_hot, hot_temp);
++
+ /* Init default critical temp to set alarm */
+- raw_critical = raw_25c - ratio * (KELVIN_TO_CEL(TEMP_CRITICAL, KELVIN_OFFSET) - 25) / 100;
++ raw_critical = cvt_celius_to_raw(KELVIN_TO_CEL(TEMP_CRITICAL, KELVIN_OFFSET));
+ clk_enable(pll3_clk);
+ anatop_update_alarm(raw_critical);
+
+@@ -877,6 +916,7 @@ static int anatop_thermal_probe(struct platform_device *pdev)
+ struct resource *res_io, *res_irq, *res_calibration;
+ void __iomem *base, *calibration_addr;
+ struct anatop_device *device;
++ unsigned fuse_data;
+
+ device = kzalloc(sizeof(*device), GFP_KERNEL);
+ if (!device) {
+@@ -913,15 +953,13 @@ static int anatop_thermal_probe(struct platform_device *pdev)
+ goto anatop_failed;
+ }
+
+- pll3_clk = clk_get(NULL, "pll3_main_clk");
+- if (IS_ERR(pll3_clk)) {
+- retval = -ENOENT;
+- goto anatop_failed;
+- }
+-
+- raw_n40c = DEFAULT_N40C;
+ /* use calibration data to get ratio */
+- anatop_thermal_counting_ratio(__raw_readl(calibration_addr));
++ fuse_data = __raw_readl(calibration_addr);
++#if 1
++ if (!fuse_data)
++ fuse_data = (0x552 << 8) | 58 | (0x58e << 20);
++#endif
++ anatop_thermal_counting_ratio(fuse_data);
+
+ res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+ if (res_irq == NULL) {
+@@ -932,6 +970,11 @@ static int anatop_thermal_probe(struct platform_device *pdev)
+ NULL);
+ thermal_irq = res_irq->start;
+
++ pll3_clk = clk_get(NULL, "pll3_main_clk");
++ if (IS_ERR(pll3_clk)) {
++ retval = -ENOENT;
++ goto anatop_failed;
++ }
+
+ anatop_thermal_add(device);
+ anatop_thermal_cpufreq_init();
+diff --git a/drivers/net/fec.c b/drivers/net/fec.c
+old mode 100755
+new mode 100644
+index 5af378f..75d57de
+--- a/drivers/net/fec.c
++++ b/drivers/net/fec.c
+@@ -122,8 +122,8 @@ MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
+ #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
+ #define FEC_ENET_TX_FRSIZE 2048
+ #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE)
+-#define TX_RING_SIZE 128 /* Must be power of two */
+-#define TX_RING_MOD_MASK 127 /* for this to work */
++#define TX_RING_SIZE 16 /* Must be power of two */
++#define TX_RING_MOD_MASK 15 /* for this to work */
+
+ #define BUFDES_SIZE ((RX_RING_SIZE + TX_RING_SIZE) * sizeof(struct bufdesc))
+
+@@ -1054,7 +1054,7 @@ static int fec_enet_mii_probe(struct net_device *ndev)
+ return 0;
+ }
+
+-static int fec_enet_mii_init(struct platform_device *pdev)
++static int fec_enet_mii_init(struct platform_device *pdev, int phy_irq)
+ {
+ static struct mii_bus *fec0_mii_bus;
+ struct net_device *ndev = platform_get_drvdata(pdev);
+@@ -1120,7 +1120,7 @@ static int fec_enet_mii_init(struct platform_device *pdev)
+ }
+
+ for (i = 0; i < PHY_MAX_ADDR; i++)
+- fep->mii_bus->irq[i] = PHY_POLL;
++ fep->mii_bus->irq[i] = phy_irq;
+
+ if (mdiobus_register(fep->mii_bus))
+ goto err_out_free_mdio_irq;
+@@ -1772,6 +1772,7 @@ fec_probe(struct platform_device *pdev)
+ struct net_device *ndev;
+ int i, irq, ret = 0;
+ struct resource *r;
++ int phy_irq = PHY_POLL;
+
+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!r)
+@@ -1804,8 +1805,11 @@ fec_probe(struct platform_device *pdev)
+ platform_set_drvdata(pdev, ndev);
+
+ pdata = pdev->dev.platform_data;
+- if (pdata)
++ if (pdata) {
+ fep->phy_interface = pdata->phy;
++ if (pdata->phy_irq)
++ phy_irq = pdata->phy_irq;
++ }
+
+ /* This device has up to three irqs on some platforms */
+ for (i = 0; i < 3; i++) {
+@@ -1833,7 +1837,7 @@ fec_probe(struct platform_device *pdev)
+ if (ret)
+ goto failed_init;
+
+- ret = fec_enet_mii_init(pdev);
++ ret = fec_enet_mii_init(pdev, phy_irq);
+ if (ret)
+ goto failed_mii_init;
+
+diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
+index 80747d2..6eafb5c 100644
+--- a/drivers/net/phy/micrel.c
++++ b/drivers/net/phy/micrel.c
+@@ -16,6 +16,7 @@
+ * ks8001, ks8737, ks8721, ks8041, ks8051 100/10 phy
+ */
+
++#include <linux/delay.h>
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/phy.h>
+@@ -48,16 +49,34 @@ static int kszphy_ack_interrupt(struct phy_device *phydev)
+ int rc;
+
+ rc = phy_read(phydev, MII_KSZPHY_INTCS);
+-
+ return (rc < 0) ? rc : 0;
+ }
+
+ static int kszphy_set_interrupt(struct phy_device *phydev)
+ {
+- int temp;
+- temp = (PHY_INTERRUPT_ENABLED == phydev->interrupts) ?
+- KSZPHY_INTCS_ALL : 0;
+- return phy_write(phydev, MII_KSZPHY_INTCS, temp);
++ int bmcr, new_bmcr;
++ bmcr = phy_read(phydev, MII_BMCR);
++ if (PHY_INTERRUPT_ENABLED == phydev->interrupts) {
++ new_bmcr = bmcr & ~BMCR_PDOWN;
++ if (bmcr != new_bmcr) {
++ unsigned intcs, temp;
++ phy_write(phydev, MII_BMCR, new_bmcr);
++ udelay(100); /* power up needs delay after */
++ /* force master mode */
++ phy_write(phydev, 0x9, 0x1f00);
++ }
++ return phy_write(phydev, MII_KSZPHY_INTCS, KSZPHY_INTCS_ALL);
++ } else {
++ phy_write(phydev, MII_KSZPHY_INTCS, 0);
++ new_bmcr = bmcr | BMCR_PDOWN;
++ if ((PHY_HALTED == phydev->state) && (bmcr != new_bmcr)) {
++ phy_write(phydev, MII_BMCR, bmcr | BMCR_ANRESTART);
++ /* let phy note link is down before poweroff */
++ udelay(10);
++ phy_write(phydev, MII_BMCR, new_bmcr);
++ }
++ return 0;
++ }
+ }
+
+ static int kszphy_config_intr(struct phy_device *phydev)
+@@ -66,8 +85,10 @@ static int kszphy_config_intr(struct phy_device *phydev)
+
+ /* set the interrupt pin active low */
+ temp = phy_read(phydev, MII_KSZPHY_CTRL);
+- temp &= ~KSZPHY_CTRL_INT_ACTIVE_HIGH;
+- phy_write(phydev, MII_KSZPHY_CTRL, temp);
++ if (temp & KSZPHY_CTRL_INT_ACTIVE_HIGH) {
++ temp &= ~KSZPHY_CTRL_INT_ACTIVE_HIGH;
++ phy_write(phydev, MII_KSZPHY_CTRL, temp);
++ }
+ rc = kszphy_set_interrupt(phydev);
+ return rc < 0 ? rc : 0;
+ }
+@@ -76,10 +97,12 @@ static int ksz9021_config_intr(struct phy_device *phydev)
+ {
+ int temp, rc;
+
+- /* set the interrupt pin active low */
+ temp = phy_read(phydev, MII_KSZPHY_CTRL);
+- temp &= ~KSZ9021_CTRL_INT_ACTIVE_HIGH;
+- phy_write(phydev, MII_KSZPHY_CTRL, temp);
++ if (temp & KSZ9021_CTRL_INT_ACTIVE_HIGH) {
++ /* set the interrupt pin active low */
++ temp &= ~KSZ9021_CTRL_INT_ACTIVE_HIGH;
++ phy_write(phydev, MII_KSZPHY_CTRL, temp);
++ }
+ rc = kszphy_set_interrupt(phydev);
+ return rc < 0 ? rc : 0;
+ }
+diff --git a/drivers/net/wireless/wl12xx/Kconfig b/drivers/net/wireless/wl12xx/Kconfig
+index 35ce7b0..1dc6a47 100644
+--- a/drivers/net/wireless/wl12xx/Kconfig
++++ b/drivers/net/wireless/wl12xx/Kconfig
+@@ -1,6 +1,7 @@
+ menuconfig WL12XX_MENU
+ tristate "TI wl12xx driver support"
+ depends on MAC80211 && EXPERIMENTAL
++ select WEXT_PRIV
+ ---help---
+ This will enable TI wl12xx driver support for the following chips:
+ wl1271, wl1273, wl1281 and wl1283.
+@@ -12,6 +13,7 @@ config WL12XX
+ depends on INET
+ select FW_LOADER
+ select CRC7
++ select WIRELESS_EXT
+ ---help---
+ This module adds support for wireless adapters based on TI wl1271 and
+ TI wl1273 chipsets. This module does *not* include support for wl1251.
+diff --git a/drivers/net/wireless/wl12xx/main.c b/drivers/net/wireless/wl12xx/main.c
+index e6497dc..f1ffec0 100644
+--- a/drivers/net/wireless/wl12xx/main.c
++++ b/drivers/net/wireless/wl12xx/main.c
+@@ -1767,6 +1767,8 @@ static void wl1271_op_remove_interface(struct ieee80211_hw *hw,
+
+ mutex_unlock(&wl->mutex);
+ cancel_work_sync(&wl->recovery_work);
++ if (wl->set_power)
++ wl->set_power(0);
+ }
+
+ void wl1271_configure_filters(struct wl1271 *wl, unsigned int filters)
+@@ -3781,9 +3783,39 @@ static ssize_t wl1271_sysfs_show_hw_pg_ver(struct device *dev,
+ static DEVICE_ATTR(hw_pg_ver, S_IRUGO | S_IWUSR,
+ wl1271_sysfs_show_hw_pg_ver, NULL);
+
++
++static int parse_mac(unsigned char *mac, unsigned char const *str_mac)
++{
++ int i = 0;
++ char *end;
++ int ret = -EINVAL;
++
++ for (;;) {
++ mac[i++] = simple_strtoul(str_mac, &end, 16);
++ if (i == 6) {
++ if (!*end || (*end == ' '))
++ ret = 0;
++ break;
++ }
++ str_mac = end + 1;
++ if ((*end != '-') && (*end != ':'))
++ break;
++ }
++ return ret;
++}
++
++static char *mac;
++module_param(mac, charp, S_IRUGO);
++MODULE_PARM_DESC(mac, "mac address override");
++
+ int wl1271_register_hw(struct wl1271 *wl)
+ {
+ int ret;
++ u8 override_mac[ETH_ALEN];
++ memset(override_mac, 0, ETH_ALEN);
++ if (mac)
++ if (parse_mac(override_mac, mac))
++ memset(override_mac, 0, ETH_ALEN);
+
+ if (wl->mac80211_registered)
+ return 0;
+@@ -3804,6 +3836,9 @@ int wl1271_register_hw(struct wl1271 *wl)
+ wl->mac_addr[5] = nvs_ptr[3];
+ }
+
++ if (is_valid_ether_addr(override_mac))
++ memcpy(wl->mac_addr, override_mac, sizeof(wl->mac_addr));
++
+ SET_IEEE80211_PERM_ADDR(wl->hw, wl->mac_addr);
+
+ ret = ieee80211_register_hw(wl->hw);
+diff --git a/drivers/net/wireless/wl12xx/sdio.c b/drivers/net/wireless/wl12xx/sdio.c
+index 536e506..5bd82f2 100644
+--- a/drivers/net/wireless/wl12xx/sdio.c
++++ b/drivers/net/wireless/wl12xx/sdio.c
+@@ -303,6 +303,7 @@ static int __devinit wl1271_probe(struct sdio_func *func,
+ /* Tell PM core that we don't need the card to be powered now */
+ pm_runtime_put_noidle(&func->dev);
+
++ wl->set_power = wlan_data->set_power;
+ wl1271_notice("initialized");
+
+ return 0;
+diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
+old mode 100755
+new mode 100644
+diff --git a/drivers/power/Makefile b/drivers/power/Makefile
+old mode 100755
+new mode 100644
+diff --git a/drivers/power/sabresd_battery.c b/drivers/power/sabresd_battery.c
+index c7318a6..516fbd8 100755
+--- a/drivers/power/sabresd_battery.c
++++ b/drivers/power/sabresd_battery.c
+@@ -884,52 +884,16 @@ static int max8903_suspend(struct platform_device *pdev,
+ pm_message_t state)
+ {
+ struct max8903_data *data = platform_get_drvdata(pdev);
+- int irq;
+- if (data) {
+- struct max8903_pdata *pdata = data->pdata;
+- if (pdata) {
+- irq = gpio_to_irq(pdata->dok);
+- enable_irq_wake(irq);
+- irq = gpio_to_irq(pdata->uok);
+- enable_irq_wake(irq);
+- cancel_delayed_work(&data->work);
+- }
+- }
++
++ cancel_delayed_work(&data->work);
+ return 0;
+ }
+
+ static int max8903_resume(struct platform_device *pdev)
+ {
+ struct max8903_data *data = platform_get_drvdata(pdev);
+- bool ta_in;
+- bool usb_in;
+- int irq;
+- if (data) {
+- struct max8903_pdata *pdata = data->pdata;
+- if (pdata) {
+- ta_in = gpio_get_value(pdata->dok) ? false : true;
+- usb_in = gpio_get_value(pdata->uok) ? false : true;
+- if (ta_in != data->ta_in) {
+- data->ta_in = ta_in;
+- pr_info("TA(DC-IN) Charger %s.\n", ta_in ?
+- "Connected" : "Disconnected");
+- max8903_charger_update_status(data);
+- power_supply_changed(&data->psy);
+- }
+- if (usb_in != data->usb_in) {
+- data->usb_in = usb_in;
+- pr_info("USB Charger %s.\n", usb_in ?
+- "Connected" : "Disconnected");
+- max8903_charger_update_status(data);
+- power_supply_changed(&data->usb);
+- }
+- irq = gpio_to_irq(pdata->dok);
+- disable_irq_wake(irq);
+- irq = gpio_to_irq(pdata->uok);
+- disable_irq_wake(irq);
+- schedule_delayed_work(&data->work, BATTERY_UPDATE_INTERVAL);
+- }
+- }
++
++ schedule_delayed_work(&data->work, BATTERY_UPDATE_INTERVAL);
+ return 0;
+
+ }
+diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
+old mode 100755
+new mode 100644
+diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
+old mode 100755
+new mode 100644
+diff --git a/drivers/regulator/da9052-regulator.c b/drivers/regulator/da9052-regulator.c
+old mode 100755
+new mode 100644
+diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
+old mode 100755
+new mode 100644
+diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
+old mode 100755
+new mode 100644
+diff --git a/drivers/rtc/rtc-da9052.c b/drivers/rtc/rtc-da9052.c
+old mode 100755
+new mode 100644
+diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
+index 8a66f3e..96df580 100644
+--- a/drivers/tty/serial/imx.c
++++ b/drivers/tty/serial/imx.c
+@@ -1212,9 +1212,12 @@ imx_set_termios(struct uart_port *port, struct ktermios *termios,
+ {
+ struct imx_port *sport = (struct imx_port *)port;
+ unsigned long flags;
+- unsigned int ucr2, old_ucr1, old_txrxen, baud, quot;
++ unsigned new_ucr2, old_ucr2;
++ unsigned new_ufcr, old_ufcr;
++ unsigned old_ubir, old_ubmr;
++ unsigned int baud, quot;
+ unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
+- unsigned int div, ufcr;
++ unsigned int div;
+ unsigned long num, denom;
+ uint64_t tdiv64;
+
+@@ -1237,26 +1240,25 @@ imx_set_termios(struct uart_port *port, struct ktermios *termios,
+ old_csize = CS8;
+ }
+
++ new_ucr2 = UCR2_SRST | UCR2_IRTS;
+ if ((termios->c_cflag & CSIZE) == CS8)
+- ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
+- else
+- ucr2 = UCR2_SRST | UCR2_IRTS;
++ new_ucr2 |= UCR2_WS;
+
+ if (termios->c_cflag & CRTSCTS) {
+ if( sport->have_rtscts ) {
+- ucr2 &= ~UCR2_IRTS;
+- ucr2 |= UCR2_CTSC;
++ new_ucr2 &= ~UCR2_IRTS;
++ new_ucr2 |= UCR2_CTSC;
+ } else {
+ termios->c_cflag &= ~CRTSCTS;
+ }
+ }
+
+ if (termios->c_cflag & CSTOPB)
+- ucr2 |= UCR2_STPB;
++ new_ucr2 |= UCR2_STPB;
+ if (termios->c_cflag & PARENB) {
+- ucr2 |= UCR2_PREN;
++ new_ucr2 |= UCR2_PREN;
+ if (termios->c_cflag & PARODD)
+- ucr2 |= UCR2_PROE;
++ new_ucr2 |= UCR2_PROE;
+ }
+
+ /*
+@@ -1269,7 +1271,7 @@ imx_set_termios(struct uart_port *port, struct ktermios *termios,
+
+ spin_lock_irqsave(&sport->port.lock, flags);
+
+- sport->port.read_status_mask = 0;
++ sport->port.read_status_mask = 0xff;
+ if (termios->c_iflag & INPCK)
+ sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
+ if (termios->c_iflag & (BRKINT | PARMRK))
+@@ -1296,22 +1298,6 @@ imx_set_termios(struct uart_port *port, struct ktermios *termios,
+ */
+ uart_update_timeout(port, termios->c_cflag, baud);
+
+- /*
+- * disable interrupts and drain transmitter
+- */
+- old_ucr1 = readl(sport->port.membase + UCR1);
+- writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
+- sport->port.membase + UCR1);
+-
+- while ( !(readl(sport->port.membase + USR2) & USR2_TXDC))
+- barrier();
+-
+- /* then, disable everything */
+- old_txrxen = readl(sport->port.membase + UCR2);
+- writel(old_txrxen & ~( UCR2_TXEN | UCR2_RXEN),
+- sport->port.membase + UCR2);
+- old_txrxen &= (UCR2_TXEN | UCR2_RXEN);
+-
+ if (USE_IRDA(sport)) {
+ /*
+ * use maximum available submodule frequency to
+@@ -1338,31 +1324,47 @@ imx_set_termios(struct uart_port *port, struct ktermios *termios,
+ num -= 1;
+ denom -= 1;
+
+- ufcr = readl(sport->port.membase + UFCR);
+- ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
++ old_ufcr = readl(sport->port.membase + UFCR);
++ new_ufcr = (old_ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
+
+- if (sport->use_dcedte)
+- ufcr |= UFCR_DCEDTE;
+-
+- writel(ufcr, sport->port.membase + UFCR);
++ old_ubir = readl(sport->port.membase + UBIR);
++ old_ubmr = readl(sport->port.membase + UBMR);
++ old_ucr2 = readl(sport->port.membase + UCR2) & ~UCR2_CTS;
++ new_ucr2 |= old_ucr2 & (UCR2_TXEN | UCR2_RXEN);
+
+- writel(num, sport->port.membase + UBIR);
+- writel(denom, sport->port.membase + UBMR);
++ if (sport->use_dcedte)
++ new_ufcr |= UFCR_DCEDTE;
++ if ((old_ufcr != new_ufcr) || (old_ucr2 != new_ucr2) ||
++ (old_ubir != num) || (old_ubmr != denom)) {
++ int i;
++ /* software reset */
++ writel(readl(sport->port.membase + UCR2) &
++ ~(UCR2_TXEN | UCR2_RXEN | UCR2_SRST | UCR2_CTS),
++ sport->port.membase + UCR2);
++ for (i = 0; i < 2000; i++) {
++ unsigned uts = readl(sport->port.membase + UTS);
++ if (!(uts & UTS_SOFTRST))
++ break;
++ }
++ writel(new_ufcr, sport->port.membase + UFCR);
++ writel(num, sport->port.membase + UBIR);
++ writel(denom, sport->port.membase + UBMR);
+
+- if (!cpu_is_mx1())
+- writel(sport->port.uartclk / div / 1000,
++ if (!cpu_is_mx1())
++ writel(sport->port.uartclk / div / 1000,
+ sport->port.membase + MX2_ONEMS);
+
+- writel(old_ucr1, sport->port.membase + UCR1);
++ /* set the parity, stop bits and data size */
++ writel(new_ucr2, sport->port.membase + UCR2);
+
+- /* set the parity, stop bits and data size */
+- writel(ucr2 | old_txrxen, sport->port.membase + UCR2);
++ if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
++ imx_enable_ms(&sport->port);
+
++ pr_info("old_ufcr=%x new_ufcr=%x, old_ucr2=%x new_ucr2=%x, old_ubir=%x num=%lx, old_ubmr=%x denom=%lx\n",
++ old_ufcr, new_ufcr, old_ucr2, new_ucr2, old_ubir, num, old_ubmr, denom);
++ pr_info("clk=%i div=%i num=%li denom=%li baud=%i\n", sport->port.uartclk, div, num+1, denom+1, baud);
++ }
+ spin_unlock_irqrestore(&sport->port.lock, flags);
+-
+- if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
+- imx_enable_ms(&sport->port);
+-
+ }
+
+ static const char *imx_type(struct uart_port *port)
+diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
+old mode 100755
+new mode 100644
+diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile
+old mode 100755
+new mode 100644
+diff --git a/drivers/usb/gadget/arcotg_udc.c b/drivers/usb/gadget/arcotg_udc.c
+old mode 100755
+new mode 100644
+diff --git a/drivers/usb/gadget/arcotg_udc.h b/drivers/usb/gadget/arcotg_udc.h
+old mode 100755
+new mode 100644
+diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
+old mode 100755
+new mode 100644
+diff --git a/drivers/usb/host/ehci-arc.c b/drivers/usb/host/ehci-arc.c
+old mode 100755
+new mode 100644
+diff --git a/drivers/usb/host/ehci-fsl.h b/drivers/usb/host/ehci-fsl.h
+old mode 100755
+new mode 100644
+diff --git a/drivers/usb/otg/Kconfig b/drivers/usb/otg/Kconfig
+old mode 100755
+new mode 100644
+diff --git a/drivers/usb/otg/Makefile b/drivers/usb/otg/Makefile
+old mode 100755
+new mode 100644
+diff --git a/drivers/usb/otg/fsl_otg.c b/drivers/usb/otg/fsl_otg.c
+old mode 100755
+new mode 100644
+diff --git a/drivers/usb/otg/fsl_otg.h b/drivers/usb/otg/fsl_otg.h
+old mode 100755
+new mode 100644
+diff --git a/drivers/usb/otg/otg_fsm.c b/drivers/usb/otg/otg_fsm.c
+old mode 100755
+new mode 100644
+diff --git a/drivers/usb/otg/otg_fsm.h b/drivers/usb/otg/otg_fsm.h
+old mode 100755
+new mode 100644
+diff --git a/drivers/video/backlight/Kconfig b/drivers/video/backlight/Kconfig
+old mode 100755
+new mode 100644
+diff --git a/drivers/video/backlight/Makefile b/drivers/video/backlight/Makefile
+old mode 100755
+new mode 100644
+diff --git a/drivers/video/mxc/mxc_ipuv3_fb.c b/drivers/video/mxc/mxc_ipuv3_fb.c
+index 745c485..d8df225 100644
+--- a/drivers/video/mxc/mxc_ipuv3_fb.c
++++ b/drivers/video/mxc/mxc_ipuv3_fb.c
+@@ -830,6 +830,8 @@ static int mxcfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
+ vtotal = var->yres + var->lower_margin + var->vsync_len +
+ var->upper_margin;
+ var->pixclock = (vtotal * htotal * 6UL) / 100UL;
++ if (!var->pixclock)
++ var->pixclock = 1000;
+ var->pixclock = KHZ2PICOS(var->pixclock);
+ dev_dbg(info->device,
+ "pixclock set for 60Hz refresh = %u ps\n",
+@@ -2229,7 +2231,7 @@ static int mxcfb_probe(struct platform_device *pdev)
+ mxcfbi->ipu_ch_nf_irq = IPU_IRQ_DC_SYNC_NFACK;
+ mxcfbi->ipu_alp_ch_irq = -1;
+ mxcfbi->ipu_ch = MEM_DC_SYNC;
+- mxcfbi->cur_blank = mxcfbi->next_blank = FB_BLANK_POWERDOWN;
++ mxcfbi->cur_blank = mxcfbi->next_blank = FB_BLANK_UNBLANK;
+
+ ret = mxcfb_register(fbi);
+ if (ret < 0)
+diff --git a/drivers/video/mxc/mxcfb.c b/drivers/video/mxc/mxcfb.c
+index 4dffee5..a3f6476 100644
+--- a/drivers/video/mxc/mxcfb.c
++++ b/drivers/video/mxc/mxcfb.c
+@@ -346,6 +346,8 @@ static int mxcfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
+ vtotal = var->yres + var->lower_margin + var->vsync_len +
+ var->upper_margin;
+ var->pixclock = (vtotal * htotal * 6UL) / 100UL;
++ if (!var->pixclock)
++ var->pixclock = 1000;
+ var->pixclock = KHZ2PICOS(var->pixclock);
+ dev_dbg(info->device,
+ "pixclock set for 60Hz refresh = %u ps\n",
+diff --git a/drivers/video/mxc/mxcfb_claa_wvga.c b/drivers/video/mxc/mxcfb_claa_wvga.c
+index 3dbad0d..4f15ba4 100644
+--- a/drivers/video/mxc/mxcfb_claa_wvga.c
++++ b/drivers/video/mxc/mxcfb_claa_wvga.c
+@@ -117,7 +117,7 @@ static struct notifier_block nb = {
+ static int __devinit lcd_probe(struct platform_device *pdev)
+ {
+ int i;
+- struct mxc_lcd_platform_data *plat = pdev->dev.platform_data;
++ struct fsl_mxc_lcd_platform_data *plat = pdev->dev.platform_data;
+
+ if (plat) {
+ if (plat->reset)
+diff --git a/drivers/video/mxc_hdmi.c b/drivers/video/mxc_hdmi.c
+index a45c347..d5f3b5d 100644
+--- a/drivers/video/mxc_hdmi.c
++++ b/drivers/video/mxc_hdmi.c
+@@ -1070,7 +1070,7 @@ static int hdmi_phy_configure(struct mxc_hdmi *hdmi, unsigned char pRep,
+ while (val == 0) {
+ udelay(1000);
+ if (msec-- == 0) {
+- dev_dbg(&hdmi->pdev->dev, "PHY PLL not locked\n");
++ dev_err(&hdmi->pdev->dev, "PHY PLL not locked\n");
+ return false;
+ }
+ val = hdmi_readb(HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
+@@ -1394,6 +1394,28 @@ static int mxc_hdmi_read_edid(struct mxc_hdmi *hdmi)
+ return HDMI_EDID_SUCCESS;
+ }
+
++static void mxc_hdmi_enable_pins(struct mxc_hdmi *hdmi)
++{
++ struct fsl_mxc_hdmi_platform_data *plat = hdmi->pdev->dev.platform_data;
++
++ dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
++
++ /* Enable pins to HDMI */
++ if (plat->enable_pins)
++ plat->enable_pins();
++}
++
++static void mxc_hdmi_disable_pins(struct mxc_hdmi *hdmi)
++{
++ struct fsl_mxc_hdmi_platform_data *plat = hdmi->pdev->dev.platform_data;
++
++ dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
++
++ /* Disable pins to HDMI */
++ if (plat->disable_pins)
++ plat->disable_pins();
++}
++
+ static void mxc_hdmi_phy_disable(struct mxc_hdmi *hdmi)
+ {
+ dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
+@@ -1633,8 +1655,6 @@ static void mxc_hdmi_set_mode(struct mxc_hdmi *hdmi)
+ if (fb_mode_is_equal(&hdmi->previous_non_vga_mode, mode)) {
+ dev_dbg(&hdmi->pdev->dev,
+ "%s: Video mode same as previous\n", __func__);
+- /* update fbi mode in case modelist is updated */
+- hdmi->fbi->mode = (struct fb_videomode *)mode;
+ mxc_hdmi_phy_init(hdmi);
+ } else {
+ dev_dbg(&hdmi->pdev->dev, "%s: New video mode\n", __func__);
+@@ -1747,13 +1767,10 @@ static void hotplug_worker(struct work_struct *work)
+ #ifdef CONFIG_MXC_HDMI_CEC
+ mxc_hdmi_cec_handle(0x80);
+ #endif
+- hdmi_set_cable_state(1);
+
+ } else if (!(phy_int_pol & HDMI_PHY_HPD)) {
+ /* Plugout event */
+ dev_dbg(&hdmi->pdev->dev, "EVENT=plugout\n");
+- hdmi_set_cable_state(0);
+- mxc_hdmi_abort_stream();
+ mxc_hdmi_cable_disconnected(hdmi);
+
+ /* Make HPD intr active high to capture plugin event */
+@@ -2042,13 +2059,10 @@ static int mxc_hdmi_fb_event(struct notifier_block *nb,
+
+ if (hdmi->fb_reg && hdmi->cable_plugin)
+ mxc_hdmi_setup(hdmi, val);
+- hdmi_set_blank_state(1);
+
+ } else if (*((int *)event->data) != hdmi->blank) {
+ dev_dbg(&hdmi->pdev->dev,
+ "event=FB_EVENT_BLANK - BLANK\n");
+- hdmi_set_blank_state(0);
+- mxc_hdmi_abort_stream();
+
+ mxc_hdmi_phy_disable(hdmi);
+
+@@ -2275,6 +2289,8 @@ static void mxc_hdmi_disp_deinit(struct mxc_dispdrv_handle *disp)
+
+ fb_unregister_client(&hdmi->nb);
+
++ mxc_hdmi_disable_pins(hdmi);
++
+ clk_disable(hdmi->hdmi_isfr_clk);
+ clk_put(hdmi->hdmi_isfr_clk);
+ clk_disable(hdmi->hdmi_iahb_clk);
+diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
+old mode 100755
+new mode 100644
+diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
+old mode 100755
+new mode 100644
+diff --git a/include/linux/fec.h b/include/linux/fec.h
+index 8f69cb5..7a08261 100644
+--- a/include/linux/fec.h
++++ b/include/linux/fec.h
+@@ -21,6 +21,7 @@ struct fec_platform_data {
+ int (*power_hibernate) (struct phy_device *);
+ phy_interface_t phy;
+ unsigned char mac[ETH_ALEN];
++ int phy_irq;
+ };
+
+ #endif
+diff --git a/include/linux/mfd/da9052/da9052.h b/include/linux/mfd/da9052/da9052.h
+old mode 100755
+new mode 100644
+diff --git a/include/linux/mfd/da9052/tsi_filter.h b/include/linux/mfd/da9052/tsi_filter.h
+old mode 100755
+new mode 100644
+diff --git a/include/linux/mfd/mxc-hdmi-core.h b/include/linux/mfd/mxc-hdmi-core.h
+index 26fa47d..8ddea5a 100644
+--- a/include/linux/mfd/mxc-hdmi-core.h
++++ b/include/linux/mfd/mxc-hdmi-core.h
+@@ -21,11 +21,6 @@
+
+ #include <mach/mxc_edid.h>
+
+-#include <sound/core.h>
+-#include <sound/pcm.h>
+-#include <sound/pcm_params.h>
+-#include <sound/soc.h>
+-
+ #define IRQ_DISABLE_SUCCEED 0
+ #define IRQ_DISABLE_FAIL 1
+
+@@ -55,11 +50,5 @@ extern int mxc_hdmi_disp_id;
+ void hdmi_set_registered(int registered);
+ int hdmi_get_registered(void);
+ unsigned int hdmi_SDMA_check(void);
+-int mxc_hdmi_abort_stream(void);
+-int mxc_hdmi_register_audio(struct snd_pcm_substream *substream);
+-void mxc_hdmi_unregister_audio(struct snd_pcm_substream *substream);
+-unsigned int hdmi_set_cable_state(unsigned int state);
+-unsigned int hdmi_set_blank_state(unsigned int state);
+-int check_hdmi_state(void);
+
+ #endif
+diff --git a/localversion b/localversion
+new file mode 100644
+index 0000000..94b3434
+--- /dev/null
++++ b/localversion
+@@ -0,0 +1 @@
++-1968-gd3f7f36
+diff --git a/sound/soc/codecs/mxc_spdif.c b/sound/soc/codecs/mxc_spdif.c
+index c80eed6..883aa4d 100644
+--- a/sound/soc/codecs/mxc_spdif.c
++++ b/sound/soc/codecs/mxc_spdif.c
+@@ -571,7 +571,6 @@ static int mxc_spdif_playback_start(struct snd_pcm_substream *substream,
+ if (!plat_data->spdif_tx)
+ return -EINVAL;
+
+- spdif_priv->tx_active = true;
+ regval = __raw_readl(spdif_base_addr + SPDIF_REG_SCR);
+ regval &= 0xfc33e3;
+ regval &= ~SCR_LOW_POWER;
+@@ -716,11 +715,9 @@ static int mxc_spdif_capture_start(struct snd_pcm_substream *substream,
+ struct mxc_spdif_platform_data *plat_data = spdif_priv->plat_data;
+ unsigned long regval;
+
+- if (!plat_data->spdif_rx)
++ if (!plat_data->spdif_rx || !spdif_priv->rx_active)
+ return -EINVAL;
+
+- spdif_priv->rx_active = true;
+-
+ regval = __raw_readl(spdif_base_addr + SPDIF_REG_SCR);
+ /*
+ * initial and reset SPDIF configuration:
+diff --git a/sound/soc/codecs/wm8962.c b/sound/soc/codecs/wm8962.c
+index b145311..8558be5 100644
+--- a/sound/soc/codecs/wm8962.c
++++ b/sound/soc/codecs/wm8962.c
+@@ -5,7 +5,6 @@
+ *
+ * Author: Mark Brown <broonie at opensource.wolfsonmicro.com>
+ *
+- * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+@@ -4020,7 +4019,7 @@ static int wm8962_probe(struct snd_soc_codec *codec)
+ dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
+ goto err_get;
+ }
+- msleep(100);
++
+ ret = snd_soc_read(codec, WM8962_SOFTWARE_RESET);
+ if (ret < 0) {
+ dev_err(codec->dev, "Failed to read ID register\n");
+diff --git a/sound/soc/imx/Kconfig b/sound/soc/imx/Kconfig
+index 72d8550..e4b57c7 100644
+--- a/sound/soc/imx/Kconfig
++++ b/sound/soc/imx/Kconfig
+@@ -70,12 +70,12 @@ config SND_SOC_IMX_WM8958
+ a WM8958 codec.
+
+ config SND_SOC_IMX_WM8962
+- tristate "SoC Audio support for IMX boards with WM8962"
++ tristate "SoC Audio support for IMX boards with WM8958"
+ select SND_MXC_SOC_MX2
+ select SND_SOC_WM8962
+ help
+ Say Y if you want to add support for SoC audio on an i.MX board with
+- a WM8962 codec.
++ a WM8958 codec.
+
+ config SND_SOC_IMX_CS42888
+ tristate "SoC Audio support for i.MX boards with cs42888"
+diff --git a/sound/soc/imx/imx-hdmi-dma.c b/sound/soc/imx/imx-hdmi-dma.c
+index 74d4555..f0afcf1 100644
+--- a/sound/soc/imx/imx-hdmi-dma.c
++++ b/sound/soc/imx/imx-hdmi-dma.c
+@@ -597,27 +597,9 @@ static void hdmi_sdma_isr(void *data)
+ if (runtime->access == SNDRV_PCM_ACCESS_MMAP_INTERLEAVED) {
+ appl_bytes = frames_to_bytes(runtime,
+ runtime->control->appl_ptr);
+-
+- if (rtd->appl_bytes > appl_bytes) {
+- if (appl_bytes > rtd->buffer_bytes)
+- rtd->appl_bytes =
+- appl_bytes - rtd->buffer_bytes;
+- else
+- rtd->appl_bytes = 0;
+- } else {
+- if ((appl_bytes - rtd->appl_bytes) >
+- rtd->buffer_bytes)
+- rtd->appl_bytes =
+- appl_bytes - rtd->buffer_bytes;
+-
+- }
+-
+ offset = rtd->appl_bytes % rtd->buffer_bytes;
+ space_to_end = rtd->buffer_bytes - offset;
+ count = appl_bytes - rtd->appl_bytes;
+- if (count > rtd->buffer_bytes)
+- count = rtd->buffer_bytes;
+-
+ rtd->appl_bytes = appl_bytes;
+
+ if (count <= space_to_end) {
+@@ -663,25 +645,9 @@ static irqreturn_t hdmi_dma_isr(int irq, void *dev_id)
+ if (runtime->access == SNDRV_PCM_ACCESS_MMAP_INTERLEAVED) {
+ appl_bytes = frames_to_bytes(runtime,
+ runtime->control->appl_ptr);
+- if (rtd->appl_bytes > appl_bytes) {
+- if (appl_bytes > rtd->buffer_bytes)
+- rtd->appl_bytes =
+- appl_bytes - rtd->buffer_bytes;
+- else
+- rtd->appl_bytes = 0;
+- } else {
+- if ((appl_bytes - rtd->appl_bytes) >
+- rtd->buffer_bytes)
+- rtd->appl_bytes =
+- appl_bytes - rtd->buffer_bytes;
+-
+- }
+-
+ offset = rtd->appl_bytes % rtd->buffer_bytes;
+ space_to_end = rtd->buffer_bytes - offset;
+ count = appl_bytes - rtd->appl_bytes;
+- if (count > rtd->buffer_bytes)
+- count = rtd->buffer_bytes;
+ rtd->appl_bytes = appl_bytes;
+
+ if (count <= space_to_end) {
+@@ -1100,8 +1066,6 @@ static int hdmi_dma_hw_params(struct snd_pcm_substream *substream,
+ /* Init par for mmap optimizate */
+ init_table(rtd->channels);
+
+- rtd->appl_bytes = 0;
+-
+ return 0;
+ }
+
+@@ -1109,56 +1073,17 @@ static int hdmi_dma_trigger(struct snd_pcm_substream *substream, int cmd)
+ {
+ struct snd_pcm_runtime *runtime = substream->runtime;
+ struct imx_hdmi_dma_runtime_data *rtd = runtime->private_data;
+- unsigned long offset, count, space_to_end, appl_bytes;
+
+ switch (cmd) {
+ case SNDRV_PCM_TRIGGER_START:
+ case SNDRV_PCM_TRIGGER_RESUME:
+ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+- if (!check_hdmi_state())
+- return 0;
+ rtd->frame_idx = 0;
+ if (runtime->access == SNDRV_PCM_ACCESS_MMAP_INTERLEAVED) {
+- appl_bytes = frames_to_bytes(runtime,
++ rtd->appl_bytes = frames_to_bytes(runtime,
+ runtime->control->appl_ptr);
+- /* If resume, the rtd->appl_bytes may stil
+- * keep the old value but the control->
+- * appl_ptr is clear. Reset it if this
+- * misalignment happens*/
+- if (rtd->appl_bytes > appl_bytes) {
+- if (appl_bytes > rtd->buffer_bytes)
+- rtd->appl_bytes =
+- appl_bytes - rtd->buffer_bytes;
+- else
+- rtd->appl_bytes = 0;
+- } else {
+- if ((appl_bytes - rtd->appl_bytes) >
+- rtd->buffer_bytes)
+- rtd->appl_bytes =
+- appl_bytes - rtd->buffer_bytes;
+
+- }
+-
+- offset = rtd->appl_bytes % rtd->buffer_bytes;
+- space_to_end = rtd->buffer_bytes - offset;
+- count = appl_bytes - rtd->appl_bytes;
+-
+- if (count > rtd->buffer_bytes) {
+- pr_err("Error Count,ring buffer size[%ld], count[%ld]!\n",
+- rtd->buffer_bytes, count);
+- return -EINVAL;
+- }
+-
+- rtd->appl_bytes = appl_bytes;
+-
+- if (count <= space_to_end) {
+- hdmi_dma_mmap_copy(substream, offset, count);
+- } else {
+- hdmi_dma_mmap_copy(substream,
+- offset, space_to_end);
+- hdmi_dma_mmap_copy(substream,
+- 0, count - space_to_end);
+- }
++ hdmi_dma_mmap_copy(substream, 0, rtd->appl_bytes);
+
+ }
+ dumpregs();
+@@ -1270,12 +1195,6 @@ static int hdmi_dma_open(struct snd_pcm_substream *substream)
+ (int)clk_get_rate(hdmi_dma_priv->isfr_clk),
+ (int)clk_get_rate(hdmi_dma_priv->iahb_clk));
+
+- ret = mxc_hdmi_register_audio(substream);
+- if (ret < 0) {
+- pr_err("ERROR: HDMI is not ready!\n");
+- return ret;
+- }
+-
+ hdmi_fifo_reset();
+
+ ret = snd_pcm_hw_constraint_integer(substream->runtime,
+@@ -1296,7 +1215,6 @@ static int hdmi_dma_close(struct snd_pcm_substream *substream)
+ struct imx_hdmi_dma_runtime_data *rtd = runtime->private_data;
+
+ hdmi_dma_irq_disable(rtd);
+- mxc_hdmi_unregister_audio(substream);
+
+ clk_disable(rtd->iahb_clk);
+ clk_disable(rtd->isfr_clk);
+diff --git a/sound/soc/imx/imx-si4763.c b/sound/soc/imx/imx-si4763.c
+index 1dd50e7..3bf7f03 100644
+--- a/sound/soc/imx/imx-si4763.c
++++ b/sound/soc/imx/imx-si4763.c
+@@ -94,7 +94,7 @@ static int imx_3stack_si4763_hw_params(struct snd_pcm_substream *substream,
+ /* set the SSI system clock as input (unused) */
+ snd_soc_dai_set_sysclk(cpu_dai, IMX_SSP_SYS_CLK, 0, SND_SOC_CLOCK_IN);
+
+- snd_soc_dai_set_clkdiv(cpu_dai, IMX_SSI_TX_DIV_PM, 4);
++ snd_soc_dai_set_clkdiv(cpu_dai, IMX_SSI_TX_DIV_PM, 9);
+ snd_soc_dai_set_clkdiv(cpu_dai, IMX_SSI_TX_DIV_2, 1);
+ snd_soc_dai_set_clkdiv(cpu_dai, IMX_SSI_TX_DIV_PSR, 0);
+ return 0;
+diff --git a/sound/soc/imx/imx-wm8962.c b/sound/soc/imx/imx-wm8962.c
+index b13f68f..8da589f 100644
+--- a/sound/soc/imx/imx-wm8962.c
++++ b/sound/soc/imx/imx-wm8962.c
+@@ -111,9 +111,6 @@ static int imx_hifi_hw_params(struct snd_pcm_substream *substream,
+ channels == 1 ? 0xfffffffe : 0xfffffffc,
+ 2, 32);
+
+- dai_format = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_IF |
+- SND_SOC_DAIFMT_CBM_CFM;
+-
+ /* set cpu DAI configuration */
+ ret = snd_soc_dai_set_fmt(cpu_dai, dai_format);
+ if (ret < 0)
+diff --git a/tools/perf/util/include/linux/compiler.h b/tools/perf/util/include/linux/compiler.h
+index 547628e..791f9dd 100644
+--- a/tools/perf/util/include/linux/compiler.h
++++ b/tools/perf/util/include/linux/compiler.h
+@@ -5,9 +5,7 @@
+ #define __always_inline inline
+ #endif
+ #define __user
+-#ifndef __attribute_const__
+ #define __attribute_const__
+-#endif
+
+ #define __used __attribute__((__unused__))
+
diff --git a/recipes-kernel/linux/linux-imx_3.0.35.bb b/recipes-kernel/linux/linux-imx_3.0.35.bb
index 4aa5f08..a3f876e 100644
--- a/recipes-kernel/linux/linux-imx_3.0.35.bb
+++ b/recipes-kernel/linux/linux-imx_3.0.35.bb
@@ -13,3 +13,6 @@ LOCALVERSION = "-12.09.01+yocto"
# iMX6Q SabreLITE changes done by Boundary Devices
SRC_URI_append_imx6qsabrelite = " file://sync-boundary-changes.patch"
+
+# iMX6Q Nitrogen6 configuration support
+SRC_URI_append_imx6qnitrogen6w = " file://support_for_nitrogen6_configuration.patch"
--
1.8.0
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