[linux-yocto] [kernel-cache][PATCH] qemuriscv64: Initial support for 64-bit QEMU RISC-V

[Bruce Ashfield]

On 2019-01-11 6:40 p.m., Alistair Francis wrote:
> On Wed, Jan 9, 2019 at 9:34 AM Bruce Ashfield
> <bruce.ashfield at windriver.com> wrote:
>>
>> On 2019-01-09 12:21 p.m., Alistair Francis wrote:
>>> On Wed, Jan 9, 2019 at 9:18 AM Bruce Ashfield
>>> <bruce.ashfield at windriver.com> wrote:
>>>>
>>>> On 2019-01-09 12:16 p.m., Alistair Francis wrote:
>>>>> On Wed, Jan 9, 2019 at 8:34 AM Bruce Ashfield
>>>>> <bruce.ashfield at windriver.com> wrote:
>>>>>>
>>>>>> Looks fine to me. This is on the 4.19 and master branches
>>>>>> of the kernel-cache.
>>>>>
>>>>> Thanks Bruce!
>>>>>
>>>>>>
>>>>>> I'll send SRCREV bumps for those kernel versions shortly.
>>>>>
>>>>> Do you mind if I do it? I have a patch ready now to bump the SHA and
>>>>> add qemuriscv64 as a supported machine.
>>>>
>>>> I have it queued with a number of other changes, so it needs to
>>>> come along with that SRCREV bump.
>>>
>>> Ah, no worries then.
>>>
>>>>
>>>>>
>>>>> Otherwise if you do can you add qemuriscv64 as compatible.
>>>>>
>>>>
>>>> I'd have to test it first before I could add that. What would be
>>>> the steps to do that ? Is everything else in oe-core ?
>>>
>>> We would also need to add the qemuriscv64 machine in order to build it.
>>>
>>> The only thing we are missing after that is the bootloader, which
>>> isn't in oe-core. We are working on a improved boot flow for RISC-V so
>>> the current boot loader will probably never go into oe-core.
>>
>> Gotcha.
>>
>> I'm just tidying up the other changes. I do expect to have them
>> out today. So the wait won't be too long!
> 
> Any update on the SRCREV changes?

I just sent them a few minutes ago!

Bruce

> 
> Alistair
> 
>>
>> Bruce
>>
>>>
>>> Alistair
>>>
>>>>
>>>> Bruce
>>>>
>>>>> Alistair
>>>>>
>>>>>>
>>>>>> Cheers,
>>>>>>
>>>>>> Bruce
>>>>>>
>>>>>> On 2019-01-07 7:54 p.m., Alistair Francis wrote:
>>>>>>> Signed-off-by: Alistair Francis <alistair.francis at wdc.com>
>>>>>>> ---
>>>>>>>      arch/riscv/riscv.cfg                     |  8 ++++++
>>>>>>>      arch/riscv/riscv.scc                     |  4 +++
>>>>>>>      bsp/qemuriscv64/qemuriscv64-standard.scc |  8 ++++++
>>>>>>>      bsp/qemuriscv64/qemuriscv64.cfg          | 34 ++++++++++++++++++++++++
>>>>>>>      bsp/qemuriscv64/qemuriscv64.scc          |  1 +
>>>>>>>      5 files changed, 55 insertions(+)
>>>>>>>      create mode 100644 arch/riscv/riscv.cfg
>>>>>>>      create mode 100644 arch/riscv/riscv.scc
>>>>>>>      create mode 100644 bsp/qemuriscv64/qemuriscv64-standard.scc
>>>>>>>      create mode 100644 bsp/qemuriscv64/qemuriscv64.cfg
>>>>>>>      create mode 100644 bsp/qemuriscv64/qemuriscv64.scc
>>>>>>>
>>>>>>> diff --git a/arch/riscv/riscv.cfg b/arch/riscv/riscv.cfg
>>>>>>> new file mode 100644
>>>>>>> index 00000000..e19a967e
>>>>>>> --- /dev/null
>>>>>>> +++ b/arch/riscv/riscv.cfg
>>>>>>> @@ -0,0 +1,8 @@
>>>>>>> +
>>>>>>> +CONFIG_RISCV=y
>>>>>>> +CONFIG_RISCV_ISA_C=y
>>>>>>> +CONFIG_RISCV_ISA_A=y
>>>>>>> +
>>>>>>> +CONFIG_RISCV_TIMER=y
>>>>>>> +
>>>>>>> +CONFIG_MMU=y
>>>>>>> diff --git a/arch/riscv/riscv.scc b/arch/riscv/riscv.scc
>>>>>>> new file mode 100644
>>>>>>> index 00000000..a792680a
>>>>>>> --- /dev/null
>>>>>>> +++ b/arch/riscv/riscv.scc
>>>>>>> @@ -0,0 +1,4 @@
>>>>>>> +if [ "$KARCH" = "riscv" ]; then
>>>>>>> +     kconf hardware riscv.cfg
>>>>>>> +     include cfg/timer/hz_100.scc
>>>>>>> +fi
>>>>>>> diff --git a/bsp/qemuriscv64/qemuriscv64-standard.scc b/bsp/qemuriscv64/qemuriscv64-standard.scc
>>>>>>> new file mode 100644
>>>>>>> index 00000000..1725c4fa
>>>>>>> --- /dev/null
>>>>>>> +++ b/bsp/qemuriscv64/qemuriscv64-standard.scc
>>>>>>> @@ -0,0 +1,8 @@
>>>>>>> +define KMACHINE qemuriscv64
>>>>>>> +define KTYPE standard
>>>>>>> +define KARCH riscv64
>>>>>>> +
>>>>>>> +include ktypes/standard/standard.scc
>>>>>>> +
>>>>>>> +include cfg/virtio.scc
>>>>>>> +include qemuriscv64.scc
>>>>>>> diff --git a/bsp/qemuriscv64/qemuriscv64.cfg b/bsp/qemuriscv64/qemuriscv64.cfg
>>>>>>> new file mode 100644
>>>>>>> index 00000000..3e51db56
>>>>>>> --- /dev/null
>>>>>>> +++ b/bsp/qemuriscv64/qemuriscv64.cfg
>>>>>>> @@ -0,0 +1,34 @@
>>>>>>> +#
>>>>>>> +# RISC-V 64-bit
>>>>>>> +#
>>>>>>> +CONFIG_ARCH_RV64I=y
>>>>>>> +CONFIG_64BIT=y
>>>>>>> +
>>>>>>> +#
>>>>>>> +# Platform type
>>>>>>> +#
>>>>>>> +CONFIG_MAXPHYSMEM_128GB=y
>>>>>>> +CONFIG_SMP=y
>>>>>>> +CONFIG_NR_CPUS=8
>>>>>>> +CONFIG_TUNE_GENERIC=y
>>>>>>> +
>>>>>>> +#
>>>>>>> +# Bus support
>>>>>>> +#
>>>>>>> +CONFIG_PCI=y
>>>>>>> +CONFIG_PCI_ECAM=y
>>>>>>> +CONFIG_PCI_HOST_COMMON=y
>>>>>>> +CONFIG_PCI_HOST_GENERIC=y
>>>>>>> +CONFIG_PCIEPORTBUS=y
>>>>>>> +
>>>>>>> +#
>>>>>>> +# Non-8250 serial port support
>>>>>>> +#
>>>>>>> +CONFIG_HVC_DRIVER=y
>>>>>>> +CONFIG_HVC_RISCV_SBI=y
>>>>>>> +CONFIG_VIRTIO_CONSOLE=y
>>>>>>> +
>>>>>>> +#
>>>>>>> +# IRQ chip support
>>>>>>> +#
>>>>>>> +CONFIG_SIFIVE_PLIC=y
>>>>>>> diff --git a/bsp/qemuriscv64/qemuriscv64.scc b/bsp/qemuriscv64/qemuriscv64.scc
>>>>>>> new file mode 100644
>>>>>>> index 00000000..527a2878
>>>>>>> --- /dev/null
>>>>>>> +++ b/bsp/qemuriscv64/qemuriscv64.scc
>>>>>>> @@ -0,0 +1 @@
>>>>>>> +kconf hardware qemuriscv64.cfg
>>>>>>>
>>>>>>
>>>>
>>