[linux-yocto] [PATCH 5/6] valleyisland-io: gpio-baytrail: setup IOAPIC interrupt on non-ACPI system

[boon.leong.ong at intel.com]

From: Ong Boon Leong <boon.leong.ong at intel.com>

BayTrail GPIO NORTH, SOUTH and SUS clusters use IRQ48,
49 and 50 respectively. On non-ACPI system, we need
to setup IOAPIC RTE for device that use interrupt
beyond IRQ23.

This commit is only applicable for v3.8 GPIO driver and not after.
For v3.10 onwards, only ACPI enumeration will be supported in
in drivers/pinctrl/pinctrl-baytrail.c.

Signed-off-by: Ong Boon Leong <boon.leong.ong at intel.com>
---
 ...-baytrail-setup-IOAPIC-interrupt-for-GPIO.patch |   84 ++++++++++++++++++++
 1 file changed, 84 insertions(+)
 create mode 100644 meta/cfg/kernel-cache/features/valleyisland-io/0024-gpio-baytrail-setup-IOAPIC-interrupt-for-GPIO.patch

diff --git a/meta/cfg/kernel-cache/features/valleyisland-io/0024-gpio-baytrail-setup-IOAPIC-interrupt-for-GPIO.patch b/meta/cfg/kernel-cache/features/valleyisland-io/0024-gpio-baytrail-setup-IOAPIC-interrupt-for-GPIO.patch
new file mode 100644
index 0000000..04740a5
--- /dev/null
+++ b/meta/cfg/kernel-cache/features/valleyisland-io/0024-gpio-baytrail-setup-IOAPIC-interrupt-for-GPIO.patch
@@ -0,0 +1,84 @@
+From 4fb056de66954240a84aecfa865d407303ec5b5a Mon Sep 17 00:00:00 2001
+From: "Chew, Kean Ho" <kean.ho.chew at intel.com>
+Date: Tue, 11 Feb 2014 11:25:45 -0500
+Subject: [PATCH 5/5] gpio-baytrail: setup IOAPIC interrupt for GPIO clusters
+ on non-ACPI system
+
+BayTrail GPIO NORTH, SOUTH and SUS clusters use IRQ48,
+49 and 50 respectively. On non-ACPI system, we need
+to setup IOAPIC RTE for device that use interrupt
+beyond IRQ23.
+
+Signed-off-by: Chew, Kean Ho <kean.ho.chew at intel.com>
+Signed-off-by: Chew, Chiau Ee <chiau.ee.chew at intel.com>
+---
+ drivers/gpio/gpio-baytrail.c | 37 +++++++++++++++++++++++++++++++++++++
+ 1 file changed, 37 insertions(+)
+
+diff --git a/drivers/gpio/gpio-baytrail.c b/drivers/gpio/gpio-baytrail.c
+index ecd53ea..5612c68 100644
+--- a/drivers/gpio/gpio-baytrail.c
++++ b/drivers/gpio/gpio-baytrail.c
+@@ -431,6 +431,36 @@ static const struct irq_domain_ops byt_gpio_irq_ops = {
+ 	.map = byt_gpio_irq_map,
+ };
+ 
++#ifdef CONFIG_GPIO_BAYTRAIL_DEV
++static int byt_gpio_irq_enable(unsigned hwirq, struct platform_device *pdev)
++{
++	struct io_apic_irq_attr irq_attr;
++	struct device *dev = &pdev->dev;
++	/*
++	 *  Since PCI BIOS is not able to provide IRQ mapping to
++	 *  IRQ24 and onward, we need register to ioapic directly
++	 *  and hardcode pci->irq= hwirq
++	 */
++	irq_attr.ioapic = mp_find_ioapic(hwirq);
++	if (irq_attr.ioapic < 0) {
++		dev_err(&pdev->dev,
++			"Unable to locate IOAPIC for IRQ=%d\n", hwirq);
++		return irq_attr.ioapic;
++	}
++	irq_attr.ioapic_pin = hwirq;
++	irq_attr.trigger = 1;	/* level */
++	irq_attr.polarity = 1;	/* active low */
++	io_apic_set_pci_routing(dev, hwirq, &irq_attr);
++	return 0;
++
++}
++#else
++static int byt_gpio_irq_enable(unsigned hwirq, struct platform_device *pdev)
++{
++	return 0;
++}
++#endif
++
+ static int byt_gpio_probe(struct platform_device *pdev)
+ {
+ 	struct byt_gpio *vg;
+@@ -512,6 +542,11 @@ static int byt_gpio_probe(struct platform_device *pdev)
+ 	if (irq_rc && irq_rc->start) {
+ 		hwirq = irq_rc->start;
+ 		gc->to_irq = byt_gpio_to_irq;
++		ret = byt_gpio_irq_enable(hwirq, pdev);
++		if (ret) {
++			dev_err(&pdev->dev, "failed to add GPIO to APIC\n");
++			return ret;
++		}
+ 
+ 		vg->domain = irq_domain_add_linear(NULL, gc->ngpio,
+ 						   &byt_gpio_irq_ops, vg);
+@@ -523,8 +558,10 @@ static int byt_gpio_probe(struct platform_device *pdev)
+ 		irq_set_handler_data(hwirq, vg);
+ 		irq_set_chained_handler(hwirq, byt_gpio_irq_handler);
+ 
++#ifndef CONFIG_GPIO_BAYTRAIL_DEV
+ 		/* Register interrupt handlers for gpio signaled acpi events */
+ 		acpi_gpiochip_request_interrupts(gc);
++#endif
+ 	}
+ 
+ 	pm_runtime_enable(dev);
+-- 
+1.8.4.2
+
-- 
1.7.10.4