[linux-yocto] [PATCH 2/6] valleyisland-io: gpio-baytrail: add function mux checking in gpio pin request

[boon.leong.ong at intel.com]

From: Ong Boon Leong <boon.leong.ong at intel.com>

The requested GPIO pin must has the function mux bits set
to GPIO function by BIOS in advance. Else, the gpio pin
request would fail. This is to ensure that we do not expose
any GPIO pins which shall be used for other purposes,
for eg: wakeup pin, I/O interfaces for LPSS, etc.

This commit is only applicable for v3.8 GPIO driver and not after.
For v3.10 onwards, as of the date of this commit, the content of this
commit is making its way to upstream. So, please search for upstream commit
in drivers/pinctrl/pinctrl-baytrail.c in the future.

Signed-off-by: Ong Boon Leong <boon.leong.ong at intel.com>
---
 ...il-add-function-mux-checking-in-gpio-pin-.patch |   68 ++++++++++++++++++++
 1 file changed, 68 insertions(+)
 create mode 100644 meta/cfg/kernel-cache/features/valleyisland-io/0021-gpio-baytrail-add-function-mux-checking-in-gpio-pin-.patch

diff --git a/meta/cfg/kernel-cache/features/valleyisland-io/0021-gpio-baytrail-add-function-mux-checking-in-gpio-pin-.patch b/meta/cfg/kernel-cache/features/valleyisland-io/0021-gpio-baytrail-add-function-mux-checking-in-gpio-pin-.patch
new file mode 100644
index 0000000..6adb0d0
--- /dev/null
+++ b/meta/cfg/kernel-cache/features/valleyisland-io/0021-gpio-baytrail-add-function-mux-checking-in-gpio-pin-.patch
@@ -0,0 +1,68 @@
+From fabe6aea713998cf051877e942e95f14feb75d65 Mon Sep 17 00:00:00 2001
+From: "Chew, Kean Ho" <kean.ho.chew at intel.com>
+Date: Wed, 12 Feb 2014 03:59:23 -0500
+Subject: [PATCH 2/5] gpio-baytrail: add function mux checking in gpio pin
+ request
+
+The requested GPIO pin must has the function mux bits set
+to GPIO function by BIOS in advance. Else, the gpio pin
+request would fail. This is to ensure that we do not expose
+any GPIO pins which shall be used for other purposes,
+for eg: wakeup pin, I/O interfaces for LPSS, etc.
+
+Signed-off-by: Chew, Kean Ho <kean.ho.chew at intel.com>
+Signed-off-by: Chew, Chiau Ee <chiau.ee.chew at intel.com>
+---
+ drivers/gpio/gpio-baytrail.c | 33 ++++++++++++++-------------------
+ 1 file changed, 14 insertions(+), 19 deletions(-)
+
+diff --git a/drivers/gpio/gpio-baytrail.c b/drivers/gpio/gpio-baytrail.c
+index fc7ef5a..cf3aeee 100644
+--- a/drivers/gpio/gpio-baytrail.c
++++ b/drivers/gpio/gpio-baytrail.c
+@@ -155,28 +155,23 @@ static int byt_gpio_request(struct gpio_chip *chip, unsigned offset)
+ 	void __iomem *reg = byt_gpio_reg(chip, offset, BYT_CONF0_REG);
+ 	u32 value;
+ 
++	value =	readl(reg) & BYT_PIN_MUX;
++	if ((!strcmp(chip->label, "byt_gpio.2") ||
++		!strcmp(chip->label, "INT33B2:02")) &&
++			 offset >= 11 && offset <= 21) {
++		if (value != 1)
++			goto not_gpio;
++	} else {
++		if (value)
++			goto not_gpio;
++	}
+ 	pm_runtime_get(&vg->pdev->dev);
+ 
+-	value = readl(reg) & BYT_PIN_MUX;
+-
+-/* Policy about what should be done when requesting a gpio is unclear.
+- * In most cases PIN MUX 000 means gpio function, with the exception of SUS
+- * core pins 11-21 where gpio is mux 001.
+- *
+- * Some pins are set by bios to a non-gpio mux, but still marked as gpio
+- * resource in acpi tables, and they work just as they should when not touching
+- * the pin muxing. (For example mmc card detect switch)
+- *
+- * option 1, check pin mux is "gpio", else fail (FIXME gpio SUS pins 11-21):
+- *	if (value)
+- *		return -EINVAL;
+- *
+- * option 2, force pin mux to gpio mode (FIXME gpio SUS pins 11-21):
+- *	writel(value & ~BYT_PIN_MUX, reg);
+- *
+- * option 3: don't touch the pinmuxing at all, let BIOS handle it
+- */
+ 	return 0;
++
++not_gpio:
++	dev_err(&vg->pdev->dev, "GPIO %d is not a GPIO pin.\n", (int)offset);
++	return -EINVAL;
+ }
+ 
+ static void byt_gpio_free(struct gpio_chip *chip, unsigned offset)
+-- 
+1.8.4.2
+
-- 
1.7.10.4