[linux-yocto] [PATCHv2 2/2] meta: valleyisland-io: move PCI mode related configurations into separate scc file

[rebecca.swee.fun.chang at intel.com]

From: "Chang, Rebecca Swee Fun" <rebecca.swee.fun.chang at intel.com>

Valley Island LPSS I/O device supports PCI and ACPI mode enumeration.
PCI mode configurations are moved into separate scc file for
enumeration mode switching. Mode switching is done in kernel recipe.

Signed-off-by: Chang, Rebecca Swee Fun <rebecca.swee.fun.chang at intel.com>
---
 .../features/valleyisland-io/valleyisland-io-pci.cfg           |    8 ++++++++
 .../features/valleyisland-io/valleyisland-io-pci.scc           |    4 ++++
 2 files changed, 12 insertions(+)
 create mode 100644 meta/cfg/kernel-cache/features/valleyisland-io/valleyisland-io-pci.cfg
 create mode 100644 meta/cfg/kernel-cache/features/valleyisland-io/valleyisland-io-pci.scc

diff --git a/meta/cfg/kernel-cache/features/valleyisland-io/valleyisland-io-pci.cfg b/meta/cfg/kernel-cache/features/valleyisland-io/valleyisland-io-pci.cfg
new file mode 100644
index 0000000..c6a78c5
--- /dev/null
+++ b/meta/cfg/kernel-cache/features/valleyisland-io/valleyisland-io-pci.cfg
@@ -0,0 +1,8 @@
+# By default, enable PCI mode enumeration
+# for Valley Island LPSS Devices
+CONFIG_BYT_LPSS_BRD=y
+CONFIG_GPIO_BYT_DEVICE=y
+CONFIG_I2C_DESIGNWARE_PCI=y
+CONFIG_SPI_PXA2XX_PCI=y
+CONFIG_DW_DMAC_PCI=y
+CONFIG_PWM_LPSS_PCI=y
diff --git a/meta/cfg/kernel-cache/features/valleyisland-io/valleyisland-io-pci.scc b/meta/cfg/kernel-cache/features/valleyisland-io/valleyisland-io-pci.scc
new file mode 100644
index 0000000..50c0e3d
--- /dev/null
+++ b/meta/cfg/kernel-cache/features/valleyisland-io/valleyisland-io-pci.scc
@@ -0,0 +1,4 @@
+define KFEATURE_DESCRIPTION "Enable PCI mode Valley Island LPSS I/O Devices"
+define KFEATURE_COMPATIBILITY arch
+
+kconf hardware valleyisland-io-pci.cfg
-- 
1.7.10.4