[linux-yocto] [PATCH 14/87] arch/arm/mach-axxia/axxia.c: Chip select control for SPI devices.

[Bruce Ashfield]

On 13-05-27 12:55 PM, Paul Butler wrote:
> Signed-off-by: Paul Butler <paul.butler at windriver.com>

Why is this separate from the patch that introduces mach-axxia ?

Bruce

> ---
>   arch/arm/mach-axxia/axxia.c | 51 ++++++++++++++++++++++++++++++++++-----------
>   1 file changed, 39 insertions(+), 12 deletions(-)
>
> diff --git a/arch/arm/mach-axxia/axxia.c b/arch/arm/mach-axxia/axxia.c
> index 623957e..777f998 100644
> --- a/arch/arm/mach-axxia/axxia.c
> +++ b/arch/arm/mach-axxia/axxia.c
> @@ -48,6 +48,7 @@
>   #include <mach/timers.h>
>   #include "axxia.h"
>   #include "pci.h"
> +#include "i2c.h"
>
>   static const char *axxia_dt_match[] __initconst = {
>   	"lsi,axm5516",		/* AXM5516 */
> @@ -157,19 +158,41 @@ static struct of_dev_auxdata axxia_auxdata_lookup[] __initdata = {
>   	{}
>   };
>
> -struct pl022_config_chip spi_eeprom = {
> -	.iface = SSP_INTERFACE_MOTOROLA_SPI,
> -	.clk_freq = {
> -		.cpsdvsr = 0,   /* value from 2 to 254 (even only!) */
> -		.scr     = 0,	/* value from 0 to 255 */
> -	},
> -	.com_mode = POLLING_TRANSFER,
> +static inline void
> +spidev_chip_select(u32 control, unsigned n)
> +{
> +	if (control == SSP_CHIP_SELECT)
> +		writel(~(1<<n) & 0x1F, ssp_base+0x30);
> +	else
> +		writel(0x1F, ssp_base+0x30);
> +}
> +
> +static void spi_cs_eeprom0(u32 control) { spidev_chip_select(control, 0); }
> +static void spi_cs_eeprom1(u32 control) { spidev_chip_select(control, 1); }
> +static void spi_cs_eeprom2(u32 control) { spidev_chip_select(control, 2); }
> +
> +struct pl022_config_chip spi_eeprom0 = {
> +	.iface      = SSP_INTERFACE_MOTOROLA_SPI,
> +	.com_mode   = POLLING_TRANSFER,
> +	.cs_control = spi_cs_eeprom0
> +};
> +
> +struct pl022_config_chip spi_eeprom1 = {
> +	.iface      = SSP_INTERFACE_MOTOROLA_SPI,
> +	.com_mode   = POLLING_TRANSFER,
> +	.cs_control = spi_cs_eeprom1
> +};
> +
> +struct pl022_config_chip spi_eeprom2 = {
> +	.iface      = SSP_INTERFACE_MOTOROLA_SPI,
> +	.com_mode   = POLLING_TRANSFER,
> +	.cs_control = spi_cs_eeprom2
>   };
>
>   static struct spi_board_info spi_devs[] __initdata = {
>   	{
>   		.modalias               = "spidev",
> -		.controller_data        = &spi_eeprom,
> +		.controller_data        = &spi_eeprom0,
>   		.bus_num                = 0,
>   		.chip_select            = 0,
>   		.max_speed_hz           = 12000000,
> @@ -177,7 +200,7 @@ static struct spi_board_info spi_devs[] __initdata = {
>   	},
>   	{
>   		.modalias               = "spidev",
> -		.controller_data        = &spi_eeprom,
> +		.controller_data        = &spi_eeprom1,
>   		.bus_num                = 0,
>   		.chip_select            = 1,
>   		.max_speed_hz           = 12000000,
> @@ -185,7 +208,7 @@ static struct spi_board_info spi_devs[] __initdata = {
>   	},
>   	{
>   		.modalias               = "spidev",
> -		.controller_data        = &spi_eeprom,
> +		.controller_data        = &spi_eeprom2,
>   		.bus_num                = 0,
>   		.chip_select            = 2,
>   		.max_speed_hz           = 12000000,
> @@ -208,11 +231,15 @@ void __init axxia_dt_init(void)
>   	ssp_base =
>   		of_iomap(of_find_compatible_node(NULL, NULL, "arm,pl022"), 0);
>   	if (!WARN_ON(ssp_base == NULL)) {
> -		printk(KERN_INFO "SSPCSR = %08x\n", readl(ssp_base+0x30));
> -		writel((0x1F << 8) | (0<<5) | (0x1F<<0), ssp_base+0x30);
> +		/* Use legacy mode, bits 0..4 control nCS[0..4] pins */
> +		writel(0x1F, ssp_base+0x30);
>   	}
>
>   	axxia_pcie_init();
> +
> +#ifdef CONFIG_I2C
> +	axxia_register_i2c_busses();
> +#endif
>   }
>
>   static void axxia_restart(char str, const char *cmd)
>