[linux-yocto] [PATCH 55/87] lsi/nand: add acp3400 nand flash controller support
Paul Butler
butler.paul at gmail.com
Mon May 27 09:56:26 PDT 2013
From: Jiang Lu <lu.jiang at windriver.com>
Extracted from lsi.patch in lsi_acp_linux_6.8.1.18 tarball.
[Jiang: The main modifications include:
* Introduce lsi_nand_{read_byte, errstat, init_size} in order
not to modify the nand_base.c
* add return to lsi_nand_write_page_hwecc() to fix
compile warnings
* change file name to lsi_acp_nand.c]
Signed-off-by: Jiang Lu <lu.jiang at windriver.com>
---
drivers/mtd/nand/Kconfig | 7 +
drivers/mtd/nand/Makefile | 1 +
drivers/mtd/nand/lsi_acp_nand.c | 3789 +++++++++++++++++++++++++++++++++++++++
drivers/mtd/nand/nand_ids.c | 1 +
4 files changed, 3798 insertions(+)
create mode 100644 drivers/mtd/nand/lsi_acp_nand.c
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 0e43a3f..102ad83 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -527,4 +527,11 @@ config MTD_NAND_FSMC
Enables support for NAND Flash chips on the ST Microelectronics
Flexible Static Memory Controller (FSMC)
+config MTD_NAND_EP501X
+ tristate "Driver for Eureka EP501/EP501G1/EP501G3 Controllers"
+ depends on MTD_NAND
+ help
+ Enables NAND flash support for the Eureka EP501, EP501G1
+ and EP501G3 controllers.
+
endif # MTD_NAND
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index d4b4d87..01a11f8 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -51,5 +51,6 @@ obj-$(CONFIG_MTD_NAND_MPC5121_NFC) += mpc5121_nfc.o
obj-$(CONFIG_MTD_NAND_RICOH) += r852.o
obj-$(CONFIG_MTD_NAND_JZ4740) += jz4740_nand.o
obj-$(CONFIG_MTD_NAND_GPMI_NAND) += gpmi-nand/
+obj-$(CONFIG_MTD_NAND_EP501X) += lsi_acp_nand.o
nand-objs := nand_base.o nand_bbt.o
diff --git a/drivers/mtd/nand/lsi_acp_nand.c b/drivers/mtd/nand/lsi_acp_nand.c
new file mode 100644
index 0000000..94b8e3c
--- /dev/null
+++ b/drivers/mtd/nand/lsi_acp_nand.c
@@ -0,0 +1,3789 @@
+/*
+ * drivers/lsi/acp/nand.c
+ *
+ * NAND Controller Driver for LSI's ACP
+ *
+ * Copyright (C) 2009 LSI Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/spinlock.h>
+#include <linux/delay.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
+#include <linux/of.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <asm/cacheflush.h>
+
+/* -- DEBUG --------------------------------------------------------- */
+
+#include <asm/lsi/debug.h>
+
+/* -- LOGIO --------------------------------------------------------- */
+
+#undef LOGIO
+/*#define LOGIO*/
+#ifdef LOGIO
+int enable_logio;
+static inline unsigned long _READL(const char *, int, unsigned long);
+static inline unsigned long
+_READL(const char *file, int line, unsigned long address)
+{
+ unsigned long value;
+
+ value = readl(address);
+
+ if (0 != enable_logio)
+ printk(KERN_INFO "%s:%d - Read 0x%08lx from 0x%08lx\n",
+ file, line, value, address);
+
+ return value;
+}
+#define READL(address) _READL(__FILE__, __LINE__, (address))
+static inline void _WRITEL(const char *, int, unsigned long, unsigned long);
+static inline void
+_WRITEL(const char *file, int line, unsigned long value, unsigned long address)
+{
+ writel(value, address);
+
+ if (0 != enable_logio)
+ printk(KERN_ERR "%s:%d - Wrote 0x%08lx to 0x%08lx\n",
+ file, line, value, address);
+
+ return;
+}
+#define WRITEL(value, address) _WRITEL(__FILE__, __LINE__, (value), (address))
+#else /* LOGIO */
+#define READL(address) readl((address))
+#define WRITEL(value, address) writel((value), (address))
+#endif /* LOGIO */
+
+/*
+ ----------------------------------------------------------------------
+*/
+
+#define NAND_DATA_REG 0x00000000
+#define NAND_CMD_REG 0x00008000
+#define NAND_INDEX_REG 0x00008004
+#define NAND_STATUS1_REG 0x00008008
+#define NAND_STATUS2_REG 0x0000800C
+#define NAND_ID0_REG 0x00008010
+#define NAND_ID1_REG 0x00008014
+#define NAND_ID2_REG 0x00008018
+#define NAND_ID3_REG 0x0000801C
+#define NAND_ID4_REG 0x00008020
+#define NAND_ID5_REG 0x00008024
+#define NAND_ID6_REG 0x00008028
+#define NAND_ID7_REG 0x0000802C
+#define NAND_INTR_EN_REG 0x00008030
+#define NAND_INTR_STATUS_REG 0x00008034
+#define NAND_INTR_REG 0x00008038
+#define NAND_ECC_ADDR_LOG_REG 0x0000803C
+#define NAND_ECC_VAL_REG 0x00008040
+#define NAND_ECC_INJECT_REG 0x00008044
+#define NAND_EXT_INDEX_REG 0x00008048
+#define NAND_TIMING1_REG 0x0000804C
+#define NAND_TIMING2_REG 0x00008050
+#define NAND_CONFIG_REG 0x00008054
+#define NAND_PECC_REG 0x00008058
+
+#define EP501_NAND_DATA_REG 0x0000
+#define EP501_NAND_CMD_REG 0x8000
+#define EP501_NAND_INDEX_REG 0x8004
+#define EP501_NAND_STATUS0_REG 0x8008
+#define EP501_NAND_STATUS1_REG 0x800C
+#define EP501_NAND_ID0_REG 0x8010
+#define EP501_NAND_ID1_REG 0x8014
+#define EP501_NAND_ID2_REG 0x8018
+#define EP501_NAND_ID3_REG 0x801C
+#define EP501_NAND_ID4_REG 0x8020
+#define EP501_NAND_ID5_REG 0x8024
+#define EP501_NAND_ID6_REG 0x8028
+#define EP501_NAND_ID7_REG 0x802C
+#define EP501_NAND_INTR_EN_REG 0x8030
+#define EP501_NAND_INTR_STATUS_REG 0x8034
+#define EP501_NAND_INTR_REG 0x8038
+#define EP501_NAND_ECC_ADDR_LOG_REG 0x803C
+#define EP501_NAND_ECC_VAL_REG 0x8040
+#define EP501_NAND_ECC_INJECT_REG 0x8044
+#define EP501_NAND_EXT_INDEX_REG 0x8048
+#define EP501_NAND_TIMING0_REG 0x804C
+#define EP501_NAND_TIMING1_REG 0x8050
+#define EP501_NAND_CONFIG_REG 0x8054
+#define EP501_NAND_PECC_REG 0x8058
+
+#define EP501G1_NAND_DATA_REG 0x0000
+#define EP501G1_NAND_CMD_REG 0x8000
+#define EP501G1_NAND_INDEX_REG 0x8004
+#define EP501G1_NAND_STATUS0_REG 0x8008
+#define EP501G1_NAND_ID0_REG 0x8010
+#define EP501G1_NAND_ID2_REG 0x8018
+#define EP501G1_NAND_ID4_REG 0x8020
+#define EP501G1_NAND_ID6_REG 0x8028
+#define EP501G1_NAND_INTR_EN_REG 0x8030
+#define EP501G1_NAND_INTR_STATUS_REG 0x8034
+#define EP501G1_NAND_INTR_REG 0x8038
+#define EP501G1_NAND_EXT_INDEX_REG 0x8048
+#define EP501G1_NAND_TIMING0_REG 0x804C
+#define EP501G1_NAND_TIMING1_REG 0x8050
+#define EP501G1_NAND_CONFIG_REG 0x8054
+#define EP501G1_NAND_1BIT_ECC0_STATUS 0x8058
+#define EP501G1_NAND_1BIT_ECC1_STATUS 0x805c
+#define EP501G1_NAND_1BIT_ECC2_STATUS 0x8060
+#define EP501G1_NAND_1BIT_ECC3_STATUS 0x8064
+#define EP501G1_NAND_1BIT_ECC4_STATUS 0x8068
+#define EP501G1_NAND_1BIT_ECC5_STATUS 0x806c
+#define EP501G1_NAND_1BIT_ECC6_STATUS 0x8070
+#define EP501G1_NAND_1BIT_ECC7_STATUS 0x8074
+#define EP501G1_NAND_BCH_STATUS 0x807c
+#define EP501G1_NAND_SYN_R12_S0 0x8080
+#define EP501G1_NAND_SYN_R34_S0 0x8084
+#define EP501G1_NAND_SYN_R56_S0 0x8088
+#define EP501G1_NAND_SYN_R78_S0 0x808c
+#define EP501G1_NAND_SYN_R12_S1 0x8090
+#define EP501G1_NAND_SYN_R34_S1 0x8094
+#define EP501G1_NAND_SYN_R56_S1 0x8098
+#define EP501G1_NAND_SYN_R78_S1 0x809c
+#define EP501G1_NAND_SYN_R12_S2 0x80a0
+#define EP501G1_NAND_SYN_R34_S2 0x80a4
+#define EP501G1_NAND_SYN_R56_S2 0x80a8
+#define EP501G1_NAND_SYN_R78_S2 0x80ac
+#define EP501G1_NAND_SYN_R12_S3 0x80b0
+#define EP501G1_NAND_SYN_R34_S3 0x80b4
+#define EP501G1_NAND_SYN_R56_S3 0x80b8
+#define EP501G1_NAND_SYN_R78_S3 0x80bc
+#define EP501G1_NAND_SYN_R12_S4 0x80c0
+#define EP501G1_NAND_SYN_R34_S4 0x80c4
+#define EP501G1_NAND_SYN_R56_S4 0x80c8
+#define EP501G1_NAND_SYN_R78_S4 0x80cc
+#define EP501G1_NAND_SYN_R12_S5 0x80d0
+#define EP501G1_NAND_SYN_R34_S5 0x80d4
+#define EP501G1_NAND_SYN_R56_S5 0x80d8
+#define EP501G1_NAND_SYN_R78_S5 0x80dc
+#define EP501G1_NAND_SYN_R12_S6 0x80e0
+#define EP501G1_NAND_SYN_R34_S6 0x80e4
+#define EP501G1_NAND_SYN_R56_S6 0x80e8
+#define EP501G1_NAND_SYN_R78_S6 0x80ec
+#define EP501G1_NAND_SYN_R12_S7 0x80f0
+#define EP501G1_NAND_SYN_R34_S7 0x80f4
+#define EP501G1_NAND_SYN_R56_S7 0x80f8
+#define EP501G1_NAND_SYN_R78_S7 0x80fc
+
+#define EP501G3_NAND_DATA_REG 0x0000
+#define EP501G3_NAND_CMD_REG 0x8000
+#define EP501G3_NAND_INDEX_REG 0x8004
+#define EP501G3_NAND_STATUS0_REG 0x8008
+#define EP501G3_NAND_ID0_REG 0x8010
+#define EP501G3_NAND_ID2_REG 0x8018
+#define EP501G3_NAND_ID4_REG 0x8020
+#define EP501G3_NAND_ID6_REG 0x8028
+#define EP501G3_NAND_INTR_EN_REG 0x8030
+#define EP501G3_NAND_INTR_STATUS_REG 0x8034
+#define EP501G3_NAND_INTR_REG 0x8038
+#define EP501G3_NAND_EXT_INDEX_REG 0x8048
+#define EP501G3_NAND_TIMING0_REG 0x804C
+#define EP501G3_NAND_TIMING1_REG 0x8050
+#define EP501G3_NAND_CONFIG_REG 0x8054
+#define EP501G3_NAND_TIMING2_REG 0x805c
+#define EP501G3_NAND_BCH_STATUS 0x807c
+#define EP501G3_NAND_SYN_R12_S0 0x8080
+#define EP501G3_NAND_SYN_R34_S0 0x8084
+#define EP501G3_NAND_SYN_R56_S0 0x8088
+#define EP501G3_NAND_SYN_R78_S0 0x808c
+#define EP501G3_NAND_SYN_R12_S1 0x8090
+#define EP501G3_NAND_SYN_R34_S1 0x8094
+#define EP501G3_NAND_SYN_R56_S1 0x8098
+#define EP501G3_NAND_SYN_R78_S1 0x809c
+#define EP501G3_NAND_SYN_R12_S2 0x80a0
+#define EP501G3_NAND_SYN_R34_S2 0x80a4
+#define EP501G3_NAND_SYN_R56_S2 0x80a8
+#define EP501G3_NAND_SYN_R78_S2 0x80ac
+#define EP501G3_NAND_SYN_R12_S3 0x80b0
+#define EP501G3_NAND_SYN_R34_S3 0x80b4
+#define EP501G3_NAND_SYN_R56_S3 0x80b8
+#define EP501G3_NAND_SYN_R78_S3 0x80bc
+#define EP501G3_NAND_SYN_R12_S4 0x80c0
+#define EP501G3_NAND_SYN_R34_S4 0x80c4
+#define EP501G3_NAND_SYN_R56_S4 0x80c8
+#define EP501G3_NAND_SYN_R78_S4 0x80cc
+#define EP501G3_NAND_SYN_R12_S5 0x80d0
+#define EP501G3_NAND_SYN_R34_S5 0x80d4
+#define EP501G3_NAND_SYN_R56_S5 0x80d8
+#define EP501G3_NAND_SYN_R78_S5 0x80dc
+#define EP501G3_NAND_SYN_R12_S6 0x80e0
+#define EP501G3_NAND_SYN_R34_S6 0x80e4
+#define EP501G3_NAND_SYN_R56_S6 0x80e8
+#define EP501G3_NAND_SYN_R78_S6 0x80ec
+#define EP501G3_NAND_SYN_R12_S7 0x80f0
+#define EP501G3_NAND_SYN_R34_S7 0x80f4
+#define EP501G3_NAND_SYN_R56_S7 0x80f8
+#define EP501G3_NAND_SYN_R78_S7 0x80fc
+#define EP501G3_NAND_SYN_R12_S8 0x8100
+#define EP501G3_NAND_SYN_R34_S8 0x8104
+#define EP501G3_NAND_SYN_R56_S8 0x8108
+#define EP501G3_NAND_SYN_R78_S8 0x810c
+#define EP501G3_NAND_SYN_R12_S9 0x8110
+#define EP501G3_NAND_SYN_R34_S9 0x8114
+#define EP501G3_NAND_SYN_R56_S9 0x8118
+#define EP501G3_NAND_SYN_R78_S9 0x811c
+#define EP501G3_NAND_SYN_R12_S10 0x8120
+#define EP501G3_NAND_SYN_R34_S10 0x8124
+#define EP501G3_NAND_SYN_R56_S10 0x8128
+#define EP501G3_NAND_SYN_R78_S10 0x812c
+#define EP501G3_NAND_SYN_R12_S11 0x8130
+#define EP501G3_NAND_SYN_R34_S11 0x8134
+#define EP501G3_NAND_SYN_R56_S11 0x8138
+#define EP501G3_NAND_SYN_R78_S11 0x813c
+#define EP501G3_NAND_SYN_R12_S12 0x8140
+#define EP501G3_NAND_SYN_R34_S12 0x8144
+#define EP501G3_NAND_SYN_R56_S12 0x8148
+#define EP501G3_NAND_SYN_R78_S12 0x814c
+#define EP501G3_NAND_SYN_R12_S13 0x8150
+#define EP501G3_NAND_SYN_R34_S13 0x8154
+#define EP501G3_NAND_SYN_R56_S13 0x8158
+#define EP501G3_NAND_SYN_R78_S13 0x815c
+#define EP501G3_NAND_SYN_R12_S14 0x8160
+#define EP501G3_NAND_SYN_R34_S14 0x8164
+#define EP501G3_NAND_SYN_R56_S14 0x8168
+#define EP501G3_NAND_SYN_R78_S14 0x816c
+#define EP501G3_NAND_SYN_R12_S15 0x8170
+#define EP501G3_NAND_SYN_R34_S15 0x8174
+#define EP501G3_NAND_SYN_R56_S15 0x8178
+#define EP501G3_NAND_SYN_R78_S15 0x817c
+
+/*
+ ==============================================================================
+ ==============================================================================
+ Some Oddities...
+
+ -1-
+ Reading EP501 registers while the device is calculating ECC will
+ hang the AHB. As the only way to know that an ECC calculation is in
+ progress is to read the "extra bits" added to the interrupt status
+ register, this can cause problems. To get around this, the
+ PECC_BUSY signal from the controller is also available in a general
+ purpose system register. 0x149.0.0xc/0x0020_0040_0000_c00c, bit 24.
+ So, before reading the interrupt status register (or any other
+ register for that matter) make sure the bit mentioned above is
+ clear. See BZ21212.
+
+ -2-
+ Extra bits have been added to the interrupt status register. See
+ BZ21196. From that defect...
+
+ == Bit 0
+ This bit is set when un-correctable ECC is detected. This bit can be
+ cleared by writing "0" to this register. Writing "1" has no
+ effect. An interrupt is generated if this bit and the enable bit
+ (bit 0) in the Interrupt Enable Register are "1". This bit is not
+ set if ECC is disabled.
+
+ == Bit 1
+ This bit is set when correctable ECC is detected. This bit can be
+ cleared by writing "0" to this register. Writing "1" has no
+ effect. An interrupt is generated if this bit and the enable bit
+ (bit 1) in the Interrupt Enable Register are "1". This bit is not
+ set if ECC is disabled.
+
+ == Bit 2
+ This bit is set when a rising edge is detected on the non gated
+ READY/BUSY# input from the NAND Flash. This bit can be cleared by
+ writing a "0" to this register. Writing a "1" has no effect. An
+ interrupt is generated if this bit and the enable bit (bit 2) in the
+ Interrupt Enable Register are "1".
+
+ == Bit 3
+ This bit is set when a falling edge is detected on the non gated
+ READY/BUSY# input from the NAND Flash. This bit can be cleared by
+ writing a "0" to this register. Writing a "1" has no effect. An
+ interrupt is generated if this bit and the enable bit (bit 3) in the
+ Interrupt Enable Register are "1".
+
+ == Bit 4
+ This bit is set when a falling edge is detected on the PECC_BUSY
+ signal which indicates when the NAND controller has taken control of
+ the NAND Flash for ECC byte access. This bit can be cleared by
+ writing a "0" to this register. Writing a "1" has no effect. An
+ interrupt is generated if this bit and the enable bit (bit 4) in the
+ Interrupt Enable Register are "1".
+
+ == Bit 5
+ This bit is read only and is the synchronized level on the non gated
+ READY/BUSY# input from the NAND Flash. This bit can be used to poll
+ the status of this signal and is not used to generate an interrupt.
+
+ == Bit 6
+ This bit is read only and indicates the level on the PECC_BUSY
+ signal which indicates when the NAND controller has taken control of
+ the NAND Flash for ECC byte access. This bit can be used to poll the
+ level of this signal and is not used to generate an interrupt.
+
+ ==============================================================================
+ ==============================================================================
+*/
+
+static void *gpreg_base;
+
+#define LSI_NAND_PECC_BUSY_REGISTER (gpreg_base + 0x00c)
+
+#ifdef CONFIG_ACP_X1V1
+#define LSI_NAND_PECC_BUSY_MASK (1 << 25)
+#else
+#define LSI_NAND_PECC_BUSY_MASK (1 << 28)
+#endif
+
+#define MAX_READ_BUF 16
+/*
+ ----------------------------------------------------------------------
+ MTD structures
+*/
+
+static struct mtd_info lsi_nand_mtd = { 0 };
+static struct nand_chip lsi_nand_chip = { 0 };
+
+static struct lsi_nand_private {
+ int cur; /* -1 means there is no meaningful data in buffer */
+ uint8_t buf[MAX_READ_BUF];
+} lsi_nand_private;
+
+#define NAND_CMD_START_ECC_READ 0x23
+
+#define NAND_CMD_CE_OFF_501 0xEE
+#define NAND_CMD_CE_OFF_501G1 0xEE
+#define NAND_CMD_CE_OFF_501G3 0xFE
+static int nand_cmd_ce_off;
+
+typedef union {
+ unsigned long raw;
+
+ struct {
+#ifdef CONFIG_ACP
+ unsigned long th:8;
+ unsigned long trp:8;
+ unsigned long twp:8;
+ unsigned long ts:8;
+#else
+ unsigned long ts:8;
+ unsigned long twp:8;
+ unsigned long trp:8;
+ unsigned long th:8;
+#endif
+ } __packed bits;
+} nand_timing_control_register_0_t;
+
+typedef union {
+ unsigned long raw;
+
+ struct {
+#ifdef CONFIG_ACP
+ unsigned long twb:8;
+ unsigned long trr:8;
+ unsigned long trh:8;
+ unsigned long twh:8;
+#else
+ unsigned long twh:8;
+ unsigned long trh:8;
+ unsigned long trr:8;
+ unsigned long twb:8;
+#endif
+ } __packed bits;
+} __packed nand_timing_control_register_1_t;
+
+typedef union {
+ unsigned long raw;
+
+ struct {
+#ifdef CONFIG_ACP
+ unsigned long:8;
+ unsigned long trhw:8;
+ unsigned long twhr:8;
+ unsigned long tccs:8;
+#else
+ unsigned long tccs:8;
+ unsigned long twhr:8;
+ unsigned long trhw:8;
+ unsigned long:8;
+#endif
+ } __packed bits;
+} __packed nand_timing_control_register_2_t;
+
+typedef enum {
+ LSI_NAND_NONE, LSI_NAND_EP501, LSI_NAND_EP501G1, LSI_NAND_EP501G3
+} lsi_nand_type_t;
+
+static lsi_nand_type_t lsi_nand_type;
+
+typedef struct page_wise_ecc_status_st {
+ unsigned err_bit:3;
+ unsigned column:9;
+ unsigned status:2;
+ unsigned rsvd:18;
+} page_wise_ecc_status_t;
+
+/*
+ =============================================================================
+ =============================================================================
+ Concerning ECC
+
+ The EP501 only supports 1 bit ECC mode. The EP501G1 supports both 1
+ bit and 4 bit modes. The EP501G3 supports 4 bit, 8 bit, and 12 bit.
+ The NAND part normally used on ACP boards has 2K pages (supported by
+ all three controllers) with 64 bytes of OOB. For a 2K page, 1 bit
+ ECC uses 12 bytes, 4 bit ECC uses 32 bytes, 8 bit ECC uses 64 bytes
+ and 12 bit ECC uses 80 bytes. In order to to keep the bad block
+ markers (first two bytes) and leave some OOB available for file
+ systems etc., this driver only supports 1 bit ECC or 4 bit ECC.
+
+ For now, the EP501 version will use 1 bit ECC (only option), the
+ EP501G1 version will use 4 bit (for compabitility with the EP501G3)
+ and teh EP501G3 versions will use 4 bit (due to the amount of OOB
+ required and for compatibility with the EP501G1).
+
+ EP501
+
+ The driver has not been tested with small page (512 byte) devices.
+ The only usable option is 2K. So, the OOB should be 64 bytes. The
+ first 2 bytes are reserved for marking bad blocks. The last 12
+ bytes are reserved for ECC. All other bytes are free. See
+ lsi_ep501_2k_ecclayout below.
+
+ EP501G1
+
+ This driver has been tested with 2K and 4K page sizes using 1 bit
+ and 4 bit ECC.
+ =============================================================================
+ =============================================================================
+*/
+
+static struct nand_ecclayout lsi_2k_1bit_ecclayout = {
+ .eccbytes = 12,
+ .eccpos = {
+ 52, 53, 54, 55, 56, 57,
+ 58, 59, 60, 61, 62, 63},
+ .oobfree = {{2, 50} }
+};
+
+/*
+static struct nand_ecclayout lsi_4k_1bit_ecclayout = {
+ .eccbytes = 24,
+ .eccpos = {
+ 52, 53, 54, 55, 56, 57,
+ 58, 59, 60, 61, 62, 63},
+ .oobfree = {{2, 50}}
+};
+*/
+
+static struct nand_ecclayout lsi_2k_4bit_ecclayout = {
+ .eccbytes = 32,
+ .eccpos = {
+ 32, 33, 34, 35, 36, 37, 38, 39,
+ 40, 41, 42, 43, 44, 45, 46, 47,
+ 48, 49, 50, 51, 52, 53, 54, 55,
+ 56, 57, 58, 59, 60, 61, 62, 63 },
+ .oobfree = {{2, 30} }
+};
+
+static struct nand_ecclayout lsi_4k_4bit_ecclayout = {
+ .eccbytes = 64,
+ .eccpos = {
+ 64, 65, 66, 67, 68, 69, 70, 71,
+ 72, 73, 74, 75, 76, 77, 78, 79,
+ 80, 81, 82, 83, 84, 85, 86, 87,
+ 88, 89, 90, 91, 92, 93, 94, 95,
+ 96, 97, 98, 99, 100, 101, 102, 103,
+ 104, 105, 106, 107, 108, 109, 110, 111,
+ 112, 113, 114, 115, 116, 117, 118, 119,
+ 120, 121, 122, 123, 124, 125, 126, 127
+ },
+ .oobfree = {{2, 63} }
+};
+
+#ifdef NOT_USED
+
+static struct nand_ecclayout lsi_8k_4bit_ecclayout = {
+ .eccbytes = 128,
+ .eccpos = {
+ 128, 129, 130, 131, 132, 133, 134, 135,
+ 136, 137, 138, 139, 140, 141, 142, 143,
+ 144, 145, 146, 147, 148, 149, 150, 151,
+ 152, 153, 154, 155, 156, 157, 158, 159,
+ 160, 161, 162, 163, 164, 165, 166, 167,
+ 168, 169, 170, 171, 172, 173, 174, 175,
+ 176, 177, 178, 179, 180, 181, 182, 183,
+ 184, 185, 186, 187, 188, 189, 190, 191,
+ 192, 193, 194, 195, 196, 197, 198, 199,
+ 200, 201, 202, 203, 204, 205, 206, 207,
+ 208, 209, 210, 211, 212, 213, 214, 215,
+ 216, 217, 218, 219, 220, 221, 222, 223,
+ 224, 225, 226, 227, 228, 229, 230, 231,
+ 232, 233, 234, 235, 236, 237, 238, 239,
+ 240, 241, 242, 243, 244, 245, 246, 247,
+ 248, 249, 250, 251, 252, 253, 254, 255
+ },
+ .oobfree = {{2, 126} }
+};
+
+#endif
+
+/*
+ -----------------------------------------------------------------------------
+ lsi_nand_hwcontrol
+*/
+
+static void
+lsi_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
+ struct nand_chip *chip = mtd->priv;
+
+ if (cmd != NAND_CMD_NONE)
+ WRITEL(cmd, (chip->IO_ADDR_W + NAND_CMD_REG));
+
+ return;
+}
+
+/*
+ ------------------------------------------------------------------------------
+ lsi_nand_device_ready
+
+ The READ/BUSY# input from the NAND device(s) (ORed if there are more
+ than one) is availble as an extra bit in the interrupt status
+ register. Note that this register shouldn't be read unless the
+ controller is not in the middle of calculating ECC (see "Some
+ Oddities..." above).
+*/
+
+static int
+lsi_nand_device_ready(struct mtd_info *mtd)
+{
+ struct nand_chip *chip = mtd->priv;
+ unsigned long interrupt_status;
+
+ /* Get the status. */
+ interrupt_status = READL(chip->IO_ADDR_R + NAND_INTR_STATUS_REG);
+
+ return interrupt_status & NAND_STATUS_TRUE_READY;
+}
+
+/**
+ * lsi_nand_command - [DEFAULT] Send command to NAND large page device
+ * @mtd: MTD device structure
+ * @command: the command to be sent
+ * @column: the column address for this command, -1 if none
+ * @page_addr: the page address for this command, -1 if none
+ *
+ * Send command to NAND device. This is the version for the new large page
+ * devices We dont have the separate regions as we have in the small page
+ * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
+ */
+static void
+lsi_nand_command(struct mtd_info *mtd, unsigned int command,
+ int column, int page_addr)
+{
+ register struct nand_chip *chip = mtd->priv;
+ unsigned int status = 0;
+ struct lsi_nand_private *priv = &lsi_nand_private;
+
+ DEBUG_PRINT("command=0x%x\n", command);
+ command &= 0xff;
+
+ /* Emulate NAND_CMD_READOOB */
+ if (command == NAND_CMD_READOOB) {
+ column += mtd->writesize;
+ command = NAND_CMD_READ0;
+ }
+
+ /* return if unhandled command is issued */
+ if (command != NAND_CMD_READ0 &&
+ command != NAND_CMD_SEQIN &&
+ command != NAND_CMD_ERASE1 &&
+ command != NAND_CMD_STATUS &&
+ command != NAND_CMD_READID &&
+ command != NAND_CMD_RESET &&
+ command != NAND_CMD_START_ECC_READ &&
+ command != NAND_CMD_PAGEPROG &&
+ command != NAND_CMD_ERASE2) {
+ printk(KERN_ERR
+ "lsi_nand_command(): WARN: Unhandled command 0x%x "
+ "issued for page=0x%x, column=0x%x.\n",
+ command, page_addr, column);
+ return;
+ }
+
+ priv->cur = -1;
+ /* Command latch cycle */
+ chip->cmd_ctrl(mtd, command,
+ NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
+
+ if (column != -1 || page_addr != -1) {
+ unsigned long index = 0;
+ unsigned long extended_index = 0;
+
+ /* column number */
+ /*
+ Since the ACP uses 8 bit device access, only that
+ mode is supported.
+ */
+
+ if (LSI_NAND_EP501 == lsi_nand_type) {
+ /* column number */
+ if (column != -1)
+ index = column & 0xfff;
+
+ /* page and block number */
+ if (page_addr != -1)
+ index += ((page_addr & 0x7ffff) << 12);
+ } else {
+ /* column number */
+ if (-1 != column) {
+ switch (mtd->writesize) {
+ case 512:
+ index |= (column & 0x1ff);
+ break;
+ case 2048:
+ index |= (column & 0xfff);
+ break;
+ case 4096:
+ index |= (column & 0x1fff);
+ break;
+ default:
+ break;
+ }
+ }
+
+ /* page_addr and block number */
+ if (-1 != page_addr) {
+ switch (mtd->writesize) {
+ case 512:
+ index |= (page_addr & 0x7fffff) << 9;
+ break;
+ case 2048:
+ index |= (page_addr & 0xfffff) << 12;
+ extended_index |=
+ (page_addr & 0xfff00000);
+ break;
+ case 4096:
+ index |= (page_addr & 0x7ffff) << 13;
+ extended_index |=
+ (page_addr & 0xfff80000);
+ break;
+ default:
+ break;
+ }
+ }
+ }
+
+ /* write index reg */
+ WRITEL(index, chip->IO_ADDR_W + NAND_INDEX_REG);
+
+ /* write ext index reg */
+ WRITEL(extended_index, chip->IO_ADDR_W + NAND_EXT_INDEX_REG);
+
+ mb();
+ }
+
+ /* for read command, send 0xe0 so data is populated */
+ if (command == NAND_CMD_READ0) {
+ chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
+ NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
+ do {
+ udelay(chip->chip_delay);
+ status = READL((void *)LSI_NAND_PECC_BUSY_REGISTER);
+ } while (0 != (status & LSI_NAND_PECC_BUSY_MASK));
+
+ /* wait until CHIP_BUSY goes low */
+ do {
+ udelay(chip->chip_delay);
+ status = chip->dev_ready(mtd);
+ } while (!status);
+ } else if (command == NAND_CMD_STATUS) {
+ udelay(chip->chip_delay);
+ priv->cur = 0;
+ priv->buf[0] = readb(chip->IO_ADDR_R + NAND_STATUS1_REG);
+ } else if (command == NAND_CMD_READID) {
+ priv->cur = 0;
+ priv->buf[0] = readb(chip->IO_ADDR_R + NAND_ID0_REG);
+ priv->buf[1] = readb(chip->IO_ADDR_R + NAND_ID2_REG);
+ priv->buf[2] = readb(chip->IO_ADDR_R + NAND_ID4_REG);
+ priv->buf[3] = readb(chip->IO_ADDR_R + NAND_ID6_REG);
+ }
+
+ return;
+}
+
+/**
+ * lsi_nand_read_buf - [DEFAULT] read chip data into buffer
+ * @mtd: MTD device structure
+ * @buf: buffer to store date
+ * @len: number of bytes to read
+ *
+ * Default read function for 8bit buswith
+ */
+static void lsi_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+{
+ int i = 0;
+ struct nand_chip *chip = (struct nand_chip *) mtd->priv;
+ uint32_t *p = (uint32_t *)buf;
+
+#if defined(LOGIO)
+ if (0 != enable_logio)
+ printk("KERN_NOTICE Reading NAND Buffer (len=%d)...\n", len);
+#endif
+
+ for (i = 0; i < (len >> 2); i++)
+ p[i] = readl(chip->IO_ADDR_R);
+
+ return;
+}
+
+/**
+ * lsi_nand_write_buf - [DEFAULT] write buffer to chip
+ * @mtd: MTD device structure
+ * @buf: data buffer
+ * @len: number of bytes to write
+ *
+ * Default write function for 8bit buswith
+ */
+static void
+lsi_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
+{
+ int i = 0;
+ struct nand_chip *chip = mtd->priv;
+ uint32_t *p = (uint32_t *)buf;
+
+#if defined(LOGIO)
+ if (0 != enable_logio)
+ printk(KERN_NOTICE "Writing NAND Buffer (len=%d)...\n", len);
+#endif
+
+ for (i = 0; i < (len >> 2); i++)
+ writel(p[i], chip->IO_ADDR_W);
+
+ return;
+}
+
+/**
+ * lsi_nand_verify_buf - [DEFAULT] Verify chip data against buffer
+ * @mtd: MTD device structure
+ * @buf: buffer containing the data to compare
+ * @len: number of bytes to compare
+ *
+ * Default verify function for 8bit buswith
+ */
+static int lsi_nand_verify_buf(struct mtd_info *mtd,
+ const uint8_t *buf, int len)
+{
+ int i;
+ struct nand_chip *chip = mtd->priv;
+ uint32_t *p = (uint32_t *)buf;
+
+ for (i = 0; i < (len >> 2); i++) {
+ udelay(chip->chip_delay);
+ if (p[i] != readl((uint32_t *)chip->IO_ADDR_R))
+ return -EFAULT;
+ }
+
+ return 0;
+}
+
+static int lsi_nand_read_status(struct mtd_info *mtd)
+{
+ struct nand_chip *chip = mtd->priv;
+
+ chip->cmd_ctrl(mtd, NAND_CMD_STATUS, 0);
+
+ return READL(chip->IO_ADDR_R + NAND_STATUS1_REG) & 0xff;
+}
+
+
+/**
+ * lsi_nand_wait - [DEFAULT] wait until the command is done
+ * @mtd: MTD device structure
+ * @chip: NAND chip structure
+ *
+ * Wait for command done. This applies to erase and program only
+ * Erase can take up to 400ms and program up to 20ms according to
+ * general NAND and SmartMedia specs
+ */
+static int lsi_nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
+{
+ unsigned long status = 0;
+ loff_t offset = 0;
+
+ /*
+ When reading or writing, wait for the
+ controller's PECC_BUSY signal to clear.
+ */
+#ifdef NOT_USED
+ if (FL_READING == chip->state || FL_WRITING == chip->state) {
+ for (;;) {
+ status = READL((void *)LSI_NAND_PECC_BUSY_REGISTER);
+
+ if (0 == (status & LSI_NAND_PECC_BUSY_MASK))
+ break;
+
+ udelay(chip->chip_delay);
+ }
+ }
+#else
+ for (;;) {
+ status = READL((void *)LSI_NAND_PECC_BUSY_REGISTER);
+
+ if (0 == (status & LSI_NAND_PECC_BUSY_MASK))
+ break;
+
+ udelay(chip->chip_delay);
+ }
+#endif
+
+ /*
+ In all cases, wait for the NAND device to be "ready".
+
+ N.B. The FL_READING case is handled in lsi_nand_command().
+ */
+
+ if (FL_WRITING == chip->state || FL_ERASING == chip->state) {
+ for (;;) {
+ if (chip->dev_ready(mtd))
+ break;
+
+ udelay(chip->chip_delay);
+ }
+ }
+
+ /*
+ Then get the status.
+ */
+
+ for (;;) {
+ status = lsi_nand_read_status(mtd);
+
+ if (0 != (status & NAND_STATUS_READY))
+ break;
+
+ udelay(chip->chip_delay);
+ }
+
+ if (status & NAND_STATUS_FAIL) {
+ offset = (READL(chip->IO_ADDR_R + NAND_INDEX_REG) /
+ mtd->writesize) * mtd->writesize;
+ printk(KERN_ERR
+ "lsi_nand_wait(): Action %d failed for "
+ "Offset: 0x%llx, status 0x%lx\n",
+ chip->state, offset, status);
+ }
+
+ return status;
+}
+
+/*
+ lsi_nand_ecc_hwctl
+*/
+
+void
+lsi_nand_ecc_hwctl(struct mtd_info *mtd, int mode)
+{
+ /* nothing to do to enable ECC */
+ return;
+}
+
+/**
+ * lsi_nand_ecc_calculate
+ */
+
+int
+lsi_nand_ecc_calculate(struct mtd_info *mtd, const uint8_t *dat,
+ uint8_t *ecc_code)
+{
+ struct nand_chip *chip = mtd->priv;
+
+ /* start ECC calculation */
+ if (chip->state == FL_READING)
+ chip->cmdfunc(mtd, NAND_CMD_START_ECC_READ, -1, -1);
+ else if (chip->state == FL_WRITING)
+ chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
+
+ /* wait for PECC_BUSY to go down */
+ return chip->waitfunc(mtd, chip);
+}
+
+/**
+ * lsi_nand_ecc_correct
+ */
+
+int
+lsi_nand_ecc_correct(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
+ uint8_t *calc_ecc)
+{
+ /* nothing to do to correct ECC */
+ return 0;
+}
+
+/*
+ ------------------------------------------------------------------------------
+ report_ecc_errors_ep501
+*/
+
+static int
+report_ecc_errors_ep501(struct mtd_info *mtd, struct nand_chip *chip,
+ uint8_t *buffer, int page)
+{
+ int rc = 0;
+ unsigned long ecc_status;
+ page_wise_ecc_status_t *ecc_status_reg =
+ (page_wise_ecc_status_t *)&ecc_status;
+ int column;
+ int i;
+
+ for (i = 0; i < (mtd->writesize >> 9); i++) {
+ ecc_status = READL(chip->IO_ADDR_R + EP501_NAND_PECC_REG);
+ column = (i << 9) + ecc_status_reg->column;
+
+ if (1 == ecc_status_reg->status) {
+ printk(KERN_NOTICE
+ "Single ECC Error: "
+ "Page=0x%x Column=0x%x Bit=0x%x\n",
+ page, column, ecc_status_reg->err_bit);
+
+ if (column < mtd->writesize) {
+ buffer[column] ^=
+ (1 << ecc_status_reg->err_bit);
+ ++mtd->ecc_stats.corrected;
+ } else {
+ printk(KERN_ERR
+ "Single ECC Error Not Corrected: "
+ "Column 0x%x not in "
+ "Page Size 0x%x\n",
+ column, mtd->writesize);
+ rc = -1;
+ }
+ } else if ((ecc_status & 0x3000) == 2) {
+ printk(KERN_ERR
+ "Uncorrectable ECC Error: "
+ "Page=0x%x Column=0x%x\n",
+ page, column);
+ rc = -1;
+ }
+ }
+
+ return rc;
+}
+
+int i_to_a[8192] = {
+ -1, 0, 1, 7953, 2, 7715, 7954, 3551, 3, 3313, 7716, 5441,
+ 7955, 1529, 3552, 7477, 4, 7239, 3314, 1441, 7717, 7102, 5442,
+ 1291, 7956, 7545, 1530, 3075, 3553, 5203, 7478, 2784, 5, 2546,
+ 7240, 5080, 3315, 4596, 1442, 4965, 7718, 466, 7103, 7307,
+ 5443, 2837, 1292, 822, 7957, 801, 7546, 7001, 1531, 1203,
+ 3076, 4294, 3554, 1053, 5204, 3033, 7479, 6073, 2785, 6864, 6,
+ 6626, 2547, 7658, 7241, 2691, 5081, 5835, 3316, 2893, 4597,
+ 815, 1443, 2795, 4966, 2905, 7719, 3058, 467, 563, 7104, 6763,
+ 7308, 1956, 5444, 4056, 2838, 838, 1293, 6335, 823, 965, 7958,
+ 3626, 802, 2308, 7547, 4842, 7002, 7279, 1532, 4727, 1204,
+ 2462, 3077, 8003, 4295, 4358, 3555, 584, 1054, 7877, 5205,
+ 2629, 3034, 2599, 7480, 4992, 6074, 228, 2786, 7069, 6865,
+ 6970, 7, 6732, 6627, 4178, 2548, 7845, 7659, 6831, 7242, 5051,
+ 2692, 4754, 5082, 8181, 5836, 5864, 3317, 1826, 2894, 346,
+ 4598, 7639, 816, 4352, 1444, 2361, 2796, 4313, 4967, 5263,
+ 2906, 2391, 7720, 6584, 3059, 3388, 468, 2070, 564, 7693,
+ 7105, 7041, 6764, 1387, 7309, 6882, 1957, 4604, 5445, 4120,
+ 4057, 1433, 2839, 883, 839, 7765, 1294, 7442, 6336, 4489, 824,
+ 2224, 966, 260, 7959, 5281, 3627, 6388, 803, 7420, 2309, 2970,
+ 7548, 5597, 4843, 4681, 7003, 4373, 7280, 2453, 1533, 2667,
+ 4728, 213, 1205, 7320, 2463, 2557, 3078, 34, 8004, 2655, 4296,
+ 577, 4359, 4017, 3556, 727, 585, 4795, 1055, 3138, 7878, 6097,
+ 5206, 440, 2630, 3818, 3035, 600, 2600, 7645, 7481, 4303,
+ 4993, 2820, 6075, 325, 229, 7021, 2787, 1718, 7070, 8147,
+ 6866, 2746, 6971, 6525, 8, 6287, 6733, 3363, 6628, 2882, 4179,
+ 2508, 2549, 6263, 7846, 1480, 7660, 7909, 6832, 4562, 7243,
+ 6013, 5052, 4065, 2693, 2582, 4755, 2138, 5083, 6783, 8182,
+ 6197, 5837, 5184, 5865, 87, 3318, 7602, 1827, 489, 2895, 4557,
+ 347, 7177, 4599, 5859, 7640, 2448, 817, 7472, 4353, 2900,
+ 1445, 7407, 2362, 5907, 2797, 2639, 4314, 362, 4968, 3697,
+ 5264, 202, 2907, 3580, 2392, 1752, 7721, 6899, 6585, 5043,
+ 3060, 6150, 3389, 1846, 469, 2732, 2071, 6180, 565, 1726,
+ 7694, 7182, 7106, 2215, 7042, 5823, 6765, 5568, 1388, 4135,
+ 7310, 3237, 6883, 5359, 1958, 4443, 4605, 1761, 5446, 3779,
+ 4121, 136, 4058, 1688, 1434, 339, 2840, 3670, 884, 7987, 840,
+ 2417, 7766, 352, 1295, 4024, 7443, 2429, 6337, 8166, 4490,
+ 7494, 825, 2319, 2225, 2611, 967, 2330, 261, 7082, 7960, 4389,
+ 5282, 6494, 3628, 3940, 6389, 7145, 804, 6593, 7421, 1411,
+ 2310, 4211, 2971, 7607, 7549, 5626, 5598, 1695, 4844, 283,
+ 4682, 7943, 7004, 6125, 4374, 4813, 7281, 4516, 2454, 7979,
+ 1534, 2153, 2668, 3174, 4729, 5507, 214, 5025, 1206, 4956,
+ 7321, 2123, 2464, 4075, 2558, 3323, 3079, 1335, 35, 1588,
+ 8005, 108, 2656, 6609, 4297, 4114, 578, 795, 4360, 1329, 4018,
+ 7401, 3557, 22, 728, 6678, 586, 1995, 4796, 1986, 1056, 3018,
+ 3139, 7204, 7879, 4251, 6098, 494, 5207, 4225, 441, 3882,
+ 2631, 1195, 3819, 6271, 3036, 7527, 601, 6242, 2601, 5487,
+ 7646, 645, 7482, 1544, 4304, 6346, 4994, 3150, 2821, 1857,
+ 6076, 7455, 326, 2351, 230, 6456, 7022, 1832, 2788, 4366,
+ 1719, 4244, 7071, 550, 8148, 6644, 6867, 3187, 2747, 6803,
+ 6972, 1149, 6526, 6444, 9, 6206, 6288, 2811, 6734, 5427, 3364,
+ 911, 6629, 4158, 2883, 2949, 4180, 6565, 2509, 3585, 2550,
+ 1949, 6264, 4128, 7847, 4006, 1481, 989, 7661, 6406, 7910,
+ 5343, 6833, 7568, 4563, 312, 7244, 1160, 6014, 1306, 5053,
+ 6108, 4066, 1215, 2694, 1619, 2583, 2680, 4756, 1108, 2139,
+ 2912, 5084, 1594, 6784, 3402, 8183, 6279, 6198, 6218, 5838,
+ 3764, 5185, 7217, 5866, 2113, 88, 6037, 3319, 7397, 7603,
+ 7975, 1828, 6440, 490, 641, 2896, 1748, 4558, 83, 348, 7078,
+ 7178, 1757, 4600, 256, 5860, 2387, 7641, 6521, 2449, 4013,
+ 818, 6860, 7473, 2780, 4354, 6966, 2901, 961, 1446, 407, 7408,
+ 7924, 2363, 5326, 5908, 5249, 2798, 2340, 2640, 7289, 4315,
+ 6004, 363, 2397, 4969, 41, 3698, 3987, 5265, 3644, 203, 8057,
+ 2908, 6033, 3581, 308, 2393, 953, 1753, 957, 7722, 2263, 6900,
+ 4151, 6586, 6256, 5044, 3306, 3061, 6907, 6151, 666, 3390,
+ 3005, 1847, 3702, 470, 7369, 2733, 143, 2072, 1402, 6181,
+ 3973, 566, 1497, 1727, 6355, 7695, 1173, 7183, 3991, 7107,
+ 7741, 2216, 1321, 7043, 5295, 5824, 4278, 6766, 155, 5569,
+ 5887, 1389, 4575, 4136, 4973, 7311, 1341, 3238, 5388, 6884,
+ 1457, 5360, 5166, 1959, 7705, 4444, 6689, 4606, 7115, 1762,
+ 45, 5447, 7163, 3780, 617, 4122, 2381, 137, 1091, 4059, 5817,
+ 1689, 3876, 1435, 557, 340, 207, 2841, 538, 3671, 1097, 885,
+ 1350, 7988, 7854, 841, 6371, 2418, 2295, 7767, 4908, 353,
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+ 4743, 6374, 5543, 3801, 1659, 5415, 5494, 7799, 4818, 2421,
+ 7869, 1813, 3979, 5410, 6698, 292, 5873, 2298, 5753, 1273,
+ 4098, 4697, 4861, 4496, 8074, 7770, 5715, 4689, 3656, 4877,
+ 6318, 1282, 980, 4911, 1367, 7623, 4331, 6703, 864, 5760,
+ 4379, 356, 7488, 6603, 6638, 4288, 2593, 7759, 7015, 8064,
+ 7228, 2173, 5371, 6212, 8051, 5160, 3831, 1299, 1314, 7580,
+ 3534, 5073, 3381, 482, 3167, 3510, 162, 3262, 5468, 1278,
+ 7755, 2008, 288, 4028, 5917, 478, 476, 2006, 3260, 480, 7578,
+ 1918, 5556, 5919, 942, 8022, 4770, 4030, 6549, 7447, 432,
+ 6551, 4779, 3106, 8121, 4032, 3614, 2939, 689, 4772, 510,
+ 4103, 3446, 8024, 4849, 2433, 1863, 944, 7060, 6812, 736,
+ 5921, 1359, 8135, 4654, 5558, 5527, 3370, 4828, 1920, 5739,
+ 6341, 6673, 3169, 6489, 131, 5038, 484, 3358, 4790, 6383,
+ 3383, 4173, 2303, 7653, 5075, 7948, 8170, 6656, 3536, 7375,
+ 7359, 2237, 7582, 6044, 1910, 612, 1316, 4146, 7919, 7970,
+ 1301, 2806, 4494, 1271, 290, 1811, 7797, 3799, 2010, 5983,
+ 5158, 2171, 7757, 6601, 5758, 7621, 1280, 4687, 7498, 2827,
+ 5470, 2020, 3223, 6920, 3264, 1026, 5272, 7154, 164, 3494,
+ 917, 6747, 3512, 5963, 829, 2771, 1361, 1014, 2165, 683, 5923,
+ 2857, 3088, 6773, 738, 7192, 4501, 417, 6814, 5631, 2323,
+ 1142, 7062, 2739, 2203, 4467, 946, 1878, 6300, 1797, 1865,
+ 631, 3714, 5642, 2435, 7591, 2229, 784, 5741, 517, 3116, 2873,
+ 1922, 5802, 2925, 2863, 4830, 7336, 8079, 1117, 3372, 7554,
+ 2615, 3156, 5529, 1636, 5661, 6513, 5560, 6755, 3840, 3287,
+ 4656, 4634, 6740, 1465, 8137, 8044, 971, 3681, 3616, 5005,
+ 2472, 7888, 4034, 6982, 6719, 3961, 8123, 6088, 4702, 652,
+ 3108, 1700, 2334, 1613, 4781, 149, 6933, 5729, 6553, 95, 4721,
+ 460, 434, 7035, 3664, 5853, 7449, 4950, 265, 3468, 4851, 7091,
+ 760, 3278, 8026, 4898, 1888, 5929, 3448, 5460, 4866, 3726,
+ 4105, 5603, 7086, 5000, 512, 1009, 1806, 6484, 4774, 3529,
+ 3651, 2718, 691, 6470, 5433, 1472, 2941, 4426, 7964, 4764,
+ 5847, 5636, 6794, 55, 4855, 8099, 6229, 5173, 4455, 768, 5970,
+ 6850, 5219, 6461, 4393, 2184, 3999, 1395, 2575, 276, 7095,
+ 7632, 6052, 773, 6951, 3742, 390, 1576, 1732, 2498, 5286,
+ 2061, 7677, 6819, 675, 4538, 269, 5516, 3128, 3293, 5227,
+ 3861, 701, 1036, 7780, 235, 6498, 6248, 3932, 7837, 3905,
+ 4259, 3472, 7134, 3253, 4460, 3422, 1779, 5191, 1570, 6360,
+ 4624, 3632, 6137, 5110, 422, 3349, 2705, 8030, 5306, 2273,
+ 4190, 3215, 1422, 893, 3564, 3333, 1837, 3944, 1236, 5936,
+ 4581, 6960, 7562, 4902, 1167, 4437, 5178, 5481, 4510, 6329,
+ 5197, 571, 5257, 6393, 2482, 1418, 4506, 3857, 1775, 764,
+ 3738, 5130, 3846, 7536, 6397, 3922, 3415, 4090, 7027, 7149,
+ 607, 4649, 5551, 2713, 455, 3282, 1792, 2647, 6234, 2287,
+ 2486, 7223, 5748, 1502, 5946, 808, 4674, 6173, 7197, 76, 3869,
+ 3452, 1130, 4327, 5367, 1655, 4094, 3519, 7386, 2524, 7460,
+ 6597, 3490, 4169, 4142, 506, 5523, 5464, 938, 5456, 6466,
+ 6084, 7031, 7332, 4630, 7188, 627, 7425, 5693, 4406, 743,
+ 3689, 1045, 1892, 3756, 4403, 4640, 4643, 3926, 6170, 1652,
+ 4166, 6081, 1415, 7533, 4646, 2284, 5107, 3212, 5933, 5478,
+ 7674, 5224, 3929, 3419, 5844, 4452, 3996, 6948, 2314, 3232,
+ 3692, 6778, 3182, 7522, 4109, 6120, 4987, 4051, 1048, 7540,
+ 1713, 29, 7437, 2356, 4215, 119, 1895, 4979, 3892, 4615, 5607,
+ 7251, 6028, 6855, 3759, 6401, 6711, 6366, 7700, 1492, 2975,
+ 7827, 7428, 3093, 753, 7790, 4870, 6991, 1245, 4662, 5696,
+ 5134, 5241, 1936, 7271, 331, 7611, 3042, 4409, 3594, 2047,
+ 4923, 3730, 1262, 7296, 5975, 746, 3850, 3770, 524, 1178,
+ 7814, 7553, 1116, 7335, 2862, 5801, 2872, 516, 783, 8043,
+ 1464, 4633, 3286, 6754, 6512, 1635, 3155, 5630, 416, 7191,
+ 6772, 2856, 682, 1013, 2770, 7590, 5641, 630, 1796, 1877,
+ 4466, 2738, 1141, 5602, 3725, 5459, 5928, 4897, 3277, 7090,
+ 3467, 4425, 1471, 6469, 2717, 3528, 6483, 1008, 4999, 1699,
+ 651, 6087, 3960, 6981, 7887, 5004, 3680, 4949, 5852, 7034,
+ 459, 94, 5728, 148, 1612, 4848, 3445, 509, 688, 3613, 8120,
+ 4778, 431, 5738, 4827, 5526, 4653, 1358, 735, 7059, 1862, 287,
+ 7754, 5467, 161, 3166, 3380, 3533, 1313, 6548, 4769, 941,
+ 5555, 7577, 3259, 475, 5916, 4686, 7620, 6600, 2170, 5982,
+ 3798, 1810, 1270, 5962, 6746, 3493, 7153, 1025, 6919, 2019,
+ 2826, 7947, 7652, 4172, 6382, 3357, 5037, 6488, 6672, 2805,
+ 7969, 4145, 611, 6043, 2236, 7374, 6655, 7008, 1377, 3522,
+ 1019, 6164, 5235, 695, 3916, 6618, 6891, 7389, 1506, 924,
+ 2098, 5791, 1549, 6129, 3437, 2527, 5575, 1070, 4545, 6474,
+ 6429, 5778, 8104, 7463, 5950, 1255, 1785, 6186, 6665, 4378,
+ 863, 4330, 1366, 979, 6317, 3655, 5714, 3830, 8050, 5370,
+ 7227, 7014, 2592, 6637, 7487, 4817, 5493, 1658, 5542, 4742,
+ 7263, 2722, 2028, 8073, 4860, 4097, 5752, 5872, 6697, 3978,
+ 7868, 7285, 304, 79, 2776, 2676, 7213, 2945, 5339, 1903, 4714,
+ 3872, 2291, 5883, 6685, 662, 6351, 4520, 5617, 3455, 5893,
+ 6541, 2988, 4430, 6021, 2995, 60, 1133, 2490, 872, 3428, 2077,
+ 3201, 2458, 224, 811, 834, 7303, 3029, 5437, 3071, 3814, 8143,
+ 4677, 2651, 1383, 4485, 4750, 4309, 7983, 2607, 6176, 5355,
+ 2444, 198, 1476, 6193, 2347, 6799, 7200, 6238, 2119, 791,
+ 1407, 4809, 1538, 2147, 3773, 7596, 721, 6578, 3620, 2540,
+ 1517, 5395, 527, 8034, 3501, 7735, 401, 1154, 2157, 181, 1181,
+ 7049, 4269, 7684, 5009, 4340, 2245, 3747, 7817, 5310, 717,
+ 4265, 6156, 68, 2672, 6537, 7299, 2440, 6160, 1066, 975, 4738,
+ 3609, 3162, 5978, 3353, 5797, 2852, 4893, 6977, 3178, 3888,
+ 749, 2043, 72, 502, 3685, 5103, 3345, 6956, 3853, 2709, 6790,
+ 2571, 671, 3901, 4733, 2535, 2050, 5647, 2249, 1081, 4038,
+ 5652, 5997, 5148, 4926, 5114, 7996, 593, 2410, 6449, 5511,
+ 8094, 3733, 5301, 3751, 1125, 6986, 6115, 3462, 778, 1265,
+ 426, 5709, 3911, 3066, 5334, 218, 857, 7614, 3719, 7821, 5687,
+ 2476, 2055, 8158, 2621, 3045, 3636, 1555, 377, 851, 6531,
+ 5029, 447, 4412, 1667, 5314, 1675, 7892, 8111, 370, 6057,
+ 3597, 6141, 3408, 1929, 6912, 4478, 1210, 906, 5244, 636,
+ 4273, 3301, 8127, 1086, 4941, 3245, 1939, 3337, 171, 2087,
+ 4200, 3192, 4960, 3546, 7274, 5830, 7688, 6826, 6092, 2965,
+ 7172, 2503, 334, 1841, 5020, 7140, 1852, 1981, 7325, 383,
+ 1248, 1870, 5013, 710, 6723, 2254, 5672, 1642, 4665, 897, 930,
+ 6421, 2957, 6872, 2127, 4231, 5699, 2759, 4344, 7935, 3965,
+ 7506, 999, 1737, 5137, 3568, 5090, 1967, 3707, 8015, 2468,
+ 6929, 756, 1802, 2161, 2199, 3112, 5657, 127, 7355, 7793,
+ 3219, 5069, 2002, 3102, 6808, 4079, 5406, 4873, 4284, 185,
+ 7124, 1704, 5060, 5900, 1581, 6994, 1426, 5768, 3478, 3395,
+ 5381, 2562, 1561, 2978, 6305, 1185, 7347, 4706, 4043, 3953,
+ 5535, 7830, 2277, 2104, 6064, 2036, 2752, 3327, 5213, 7431,
+ 2518, 7053, 1629, 656, 5785, 2404, 395, 3096, 4194, 1600,
+ 5809, 3010, 5589, 3083, 2920, 6714, 1883, 3505, 2934, 4785,
+ 5153, 536, 1348, 6369, 4906, 7161, 2379, 5815, 555, 1339,
+ 1455, 7703, 7113, 7739, 5293, 153, 4573, 7367, 1400, 1495,
+ 1171, 2261, 6254, 6905, 3003, 39, 3642, 6031, 951, 405, 5324,
+ 2338, 6002, 254, 6519, 6858, 6964, 7395, 6438, 1746, 7076,
+ 1592, 6277, 3762, 2111, 1158, 6106, 1617, 1106, 1947, 4004,
+ 6404, 7566, 6204, 5425, 4156, 6563, 8009, 5583, 3895, 4472,
+ 1521, 7901, 6557, 5119, 6942, 7808, 4618, 5940, 7862, 4803,
+ 1606, 6649, 112, 1229, 5610, 7747, 5399, 8087, 99, 1222, 4527,
+ 2189, 7254, 4585, 6842, 6504, 7727, 2371, 2660, 3051, 4218,
+ 2208, 531, 249, 6937, 4931, 4936, 5667, 122, 3948, 1512, 3604,
+ 5992, 8153, 6613, 3825, 1898, 3809, 8038, 4420, 5733, 5957,
+ 4322, 4398, 4982, 1240, 6224, 3123, 2268, 5125, 4301, 323,
+ 1716, 2744, 725, 3136, 438, 598, 2665, 7318, 32, 575, 5279,
+ 7418, 5595, 4371, 4118, 881, 7440, 2222, 6582, 2068, 7039,
+ 6880, 1824, 7637, 2359, 5261, 6730, 7843, 5049, 8179, 582,
+ 2627, 4990, 7067, 3624, 4840, 4725, 8001, 3056, 6761, 4054,
+ 6333, 6624, 2689, 2891, 2793, 799, 1201, 1051, 6071, 2544,
+ 4594, 464, 2835, 7237, 7100, 7543, 5201, 8189, 7713, 3311,
+ 1527, 4364, 548, 3185, 1147, 1542, 3148, 7453, 6454, 4223,
+ 1193, 7525, 5485, 20, 1993, 3016, 4249, 1333, 106, 4112, 1327,
+ 2151, 5505, 4954, 4073, 5624, 281, 6123, 4514, 4387, 3938,
+ 6591, 4209, 4022, 8164, 2317, 2328, 3777, 1686, 3668, 2415,
+ 2213, 5566, 3235, 4441, 6897, 6148, 2730, 1724, 7405, 2637,
+ 3695, 3578, 7600, 4555, 5857, 7470, 6011, 2580, 6781, 5182,
+ 6285, 2880, 6261, 7907, 3561, 2702, 5194, 7559, 3412, 1772,
+ 5745, 452, 6847, 52, 1573, 273, 1033, 4535, 1567, 4256, 26,
+ 7519, 6363, 4612, 1933, 7787, 521, 4920, 7383, 3866, 4627,
+ 5520, 1649, 1042, 4449, 3209, 732, 8117, 3256, 3377, 6916,
+ 3795, 2233, 5034, 6509, 2869, 4463, 679, 6480, 3274, 5725,
+ 7884, 6682, 7210, 3425, 2985, 4482, 3026, 788, 195, 2095,
+ 5232, 1782, 4542, 2589, 6314, 6694, 7260, 590, 1078, 3908,
+ 1122, 374, 5684, 1926, 1672, 7732, 6575, 4262, 7681, 2849,
+ 1063, 2568, 499, 1999, 2196, 3475, 7121, 6061, 7344, 5806,
+ 1626, 2084, 3298, 7137, 6823, 6418, 707, 1964, 7932, 4800,
+ 7898, 6501, 8084, 3601, 246, 3120, 4417, 2376, 2931, 6251,
+ 5290, 6435, 5321, 5422, 6103, 1990, 3145, 3935, 5502, 6145,
+ 1683, 2877, 4552, 7415, 3133, 7840, 2065, 2686, 4837, 7710,
+ 4591, 1060, 5681, 704, 7341, 5318, 243, 4834, 1680, 4532,
+ 1769, 1039, 7784, 3271, 3792, 6311, 3023, 3022, 3791, 7783,
+ 1768, 1679, 242, 7340, 5680, 3789, 240, 238, 239, 5679, 241,
+ 1767, 3790, 3143, 1681, 3131, 4835, 7896, 244, 2929, 5319,
+ 2194, 7342, 3296, 705, 1076, 5682, 6573, 1061, 7208, 3024,
+ 5230, 6312, 8115, 3793, 2867, 3272, 7517, 7785, 3864, 1040,
+ 2700, 1770, 50, 4533, 7883, 3273, 678, 2868, 5033, 3794, 3376,
+ 8116, 7259, 6313, 4541, 5231, 194, 3025, 2984, 7209, 4255,
+ 4534, 272, 51, 451, 1771, 7558, 2701, 3208, 1041, 5519, 3865,
+ 4919, 7786, 4611, 7518, 6102, 5320, 5289, 2930, 4416, 245,
+ 8083, 7897, 4590, 4836, 2064, 3132, 4551, 1682, 5501, 3144,
+ 498, 1062, 7680, 6574, 1671, 5683, 1121, 1077, 7931, 706,
+ 6822, 3297, 1625, 7343, 7120, 2195, 5211, 1627, 393, 5807,
+ 1559, 7345, 5533, 6062, 5404, 7122, 1579, 3476, 6927, 2197,
+ 7353, 2000, 4229, 7933, 1735, 1965, 381, 708, 1640, 6419,
+ 3544, 6824, 2501, 7138, 904, 3299, 3243, 2085, 445, 1673,
+ 6055, 1927, 855, 5685, 2619, 375, 8092, 1123, 776, 3909, 2533,
+ 1079, 5146, 591, 3886, 500, 6954, 2569, 6535, 1064, 3160,
+ 2850, 179, 7682, 3745, 4263, 2145, 6576, 5393, 7733, 2635,
+ 4553, 2578, 2878, 8162, 1684, 5564, 6146, 104, 5503, 279,
+ 3936, 546, 3146, 1191, 1991, 1199, 4592, 7098, 7711, 2625,
+ 4838, 6759, 2687, 879, 2066, 7635, 7841, 321, 3134, 7316,
+ 7416, 3823, 4418, 4396, 3121, 3049, 247, 5665, 3602, 1227,
+ 8085, 2187, 6502, 5581, 7899, 7806, 4801, 6275, 6104, 4002,
+ 5423, 3640, 5322, 6517, 6436, 1453, 5291, 1398, 6252, 2918,
+ 2932, 1346, 2377, 3040, 4921, 5973, 522, 7825, 7788, 4660,
+ 1934, 117, 4613, 6853, 6364, 3230, 7520, 4049, 27, 7531, 3210,
+ 5222, 4450, 5691, 1043, 4638, 1650, 3488, 5521, 6464, 4628,
+ 4672, 3867, 5365, 7384, 605, 453, 6232, 5746, 2480, 1773,
+ 3844, 3413, 1234, 7560, 5176, 5195, 6135, 2703, 4188, 3562,
+ 6246, 4257, 4458, 1568, 2059, 4536, 3291, 1034, 2182, 274,
+ 771, 1574, 4762, 53, 5171, 6848, 2605, 196, 6797, 789, 222,
+ 3027, 8141, 4483, 5615, 2986, 58, 3426, 302, 7211, 4712, 6683,
+ 5491, 7261, 4858, 6695, 861, 6315, 8048, 2590, 3435, 4543,
+ 8102, 1783, 1375, 5233, 6889, 2096, 7650, 5035, 7967, 2234,
+ 7618, 3796, 6744, 6917, 7752, 3378, 4767, 3257, 3443, 8118,
+ 4825, 733, 649, 7885, 5850, 5726, 3723, 3275, 1469, 6481, 414,
+ 680, 5639, 4464, 1114, 2870, 1462, 6510, 7486, 2591, 7226,
+ 8049, 5713, 6316, 1365, 862, 7867, 6696, 5751, 4859, 2027,
+ 7262, 5541, 5492, 1548, 2097, 1505, 6890, 3915, 5234, 1018,
+ 1376, 6664, 1784, 5949, 8103, 6428, 4544, 5574, 3436, 4308,
+ 4484, 2650, 8142, 3070, 3028, 833, 223, 4808, 790, 6237, 6798,
+ 6192, 197, 5354, 2606, 6350, 6684, 2290, 4713, 5338, 7212,
+ 2775, 303, 3200, 3427, 2489, 59, 6020, 2987, 5892, 5616, 4998,
+ 6482, 2716, 1470, 3466, 3276, 5927, 3724, 1611, 5727, 458,
+ 5851, 3679, 7886, 3959, 650, 3154, 6511, 3285, 1463, 782,
+ 2871, 2861, 1115, 1140, 4465, 1795, 5640, 2769, 681, 6771,
+ 415, 2825, 6918, 7152, 6745, 1269, 3797, 2169, 7619, 6654,
+ 2235, 610, 7968, 6671, 5036, 6381, 7651, 1861, 734, 4652,
+ 4826, 430, 8119, 687, 3444, 5915, 3258, 5554, 4768, 1312,
+ 3379, 160, 7753, 6080, 1651, 3925, 4639, 3755, 1044, 742,
+ 5692, 6947, 4451, 3418, 5223, 5477, 3211, 2283, 7532, 7459,
+ 7385, 4093, 5366, 1129, 3868, 7196, 4673, 626, 4629, 7030,
+ 6465, 937, 5522, 4141, 3489, 330, 1935, 5133, 4661, 6990,
+ 7789, 3092, 7826, 7813, 523, 3849, 5974, 1261, 4922, 3593,
+ 3041, 2355, 28, 7539, 4050, 6119, 7521, 6777, 3231, 1491,
+ 6365, 6400, 6854, 7250, 4614, 4978, 118, 234, 1035, 3860,
+ 3292, 5515, 4537, 6818, 2060, 4623, 1569, 1778, 4459, 7133,
+ 4258, 7836, 6247, 6460, 6849, 767, 5172, 8098, 54, 5635, 4763,
+ 2497, 1575, 3741, 772, 7631, 275, 1394, 2183, 7026, 3414,
+ 6396, 3845, 3737, 1774, 4505, 2481, 5945, 5747, 2485, 6233,
+ 1791, 454, 5550, 606, 1836, 3563, 1421, 4189, 5305, 2704, 421,
+ 6136, 5256, 5196, 4509, 5177, 1166, 7561, 4580, 1235, 2792,
+ 2688, 6332, 6760, 8000, 4839, 7066, 2626, 1526, 7712, 5200,
+ 7099, 2834, 4593, 6070, 1200, 4370, 7417, 574, 7317, 597,
+ 3135, 2743, 322, 8178, 7842, 5260, 7636, 6879, 2067, 2221,
+ 880, 1723, 6147, 4440, 5565, 2414, 1685, 2327, 8163, 7906,
+ 2879, 5181, 2579, 7469, 4554, 3577, 2636, 4248, 1992, 5484,
+ 1192, 6453, 3147, 1146, 547, 4208, 3937, 4513, 280, 4072,
+ 5504, 1326, 105, 7075, 6437, 6963, 6518, 6001, 5323, 950,
+ 3641, 6562, 5424, 7565, 4003, 1105, 6105, 2110, 6276, 554,
+ 2378, 4905, 1347, 5152, 2933, 1882, 2919, 3002, 6253, 1170,
+ 1399, 4572, 5292, 7112, 1454, 8152, 3603, 3947, 5666, 4930,
+ 248, 2207, 3050, 5124, 3122, 1239, 4397, 5956, 4419, 3808,
+ 3824, 6648, 4802, 5939, 7807, 5118, 7900, 4471, 5582, 2370,
+ 6503, 4584, 2188, 1221, 8086, 7746, 1228, 6871, 6420, 896,
+ 1641, 2253, 709, 1869, 382, 8014, 1966, 3567, 1736, 7505,
+ 7934, 2758, 4230, 3191, 2086, 3336, 3244, 1085, 3300, 635,
+ 905, 1980, 7139, 1840, 2502, 2964, 6825, 5829, 3545, 2751,
+ 6063, 2276, 5534, 4042, 7346, 6304, 1560, 5588, 5808, 4193,
+ 394, 5784, 1628, 2517, 5212, 6807, 2001, 3218, 7354, 5656,
+ 2198, 1801, 6928, 5380, 3477, 1425, 1580, 5059, 7123, 4283,
+ 5405, 6976, 2851, 3352, 3161, 4737, 1065, 2439, 6536, 3900,
+ 2570, 2708, 6955, 5102, 501, 2042, 3887, 1153, 7734, 8033,
+ 5394, 2539, 6577, 7595, 2146, 67, 4264, 5309, 3746, 4339,
+ 7683, 7048, 180, 6530, 376, 3635, 2620, 2054, 5686, 3718, 856,
+ 4477, 1928, 6140, 6056, 8110, 1674, 1666, 446, 6448, 592,
+ 5113, 5147, 5651, 1080, 5646, 2534, 5333, 3910, 425, 777,
+ 6114, 1124, 5300, 8093
+};
+
+int a_to_i[8192] = {
+ 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 1455,
+ 2910, 5820, 2263, 4526, 1779, 3558, 7116, 4663, 449, 898,
+ 1796, 3592, 7184, 7567, 7857, 6349, 5173, 3525, 7050, 4795,
+ 217, 434, 868, 1736, 3472, 6944, 5103, 625, 1250, 2500, 5000,
+ 703, 1406, 2812, 5624, 3679, 7358, 7379, 7177, 7613, 7893,
+ 6149, 5541, 3813, 7626, 7739, 6617, 5661, 2453, 4906, 1019,
+ 2038, 4076, 8152, 6687, 4497, 1677, 3354, 6708, 4551, 1569,
+ 3138, 6276, 5287, 3297, 6594, 5675, 2553, 5106, 587, 1174,
+ 2348, 4696, 287, 574, 1148, 2296, 4592, 1615, 3230, 6460,
+ 6103, 2561, 5122, 3499, 6998, 4867, 937, 1874, 3748, 7496,
+ 7999, 7121, 4621, 437, 874, 1748, 3496, 6992, 4879, 945, 1890,
+ 3780, 7560, 7871, 6353, 5133, 3509, 7018, 4987, 857, 1714,
+ 3428, 6856, 4159, 1489, 2978, 5956, 2855, 5710, 2355, 4710,
+ 355, 710, 1420, 2840, 5680, 2511, 5022, 659, 1318, 2636, 5272,
+ 3231, 6462, 6099, 2569, 5138, 3467, 6934, 4995, 681, 1362,
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+ 2994, 5988, 2919, 5838, 2099, 4198, 1379, 2758, 5516, 3767,
+ 7534, 8051, 6985, 4925, 981, 1962, 3924, 7848, 6399, 5201,
+ 3341, 6682, 4507, 1689, 3378, 6756, 4455, 1889, 3778, 7556,
+ 7847, 6369, 5229, 3445, 6890, 4219, 1369, 2738, 5476, 3943,
+ 7886, 6195, 5577, 3645, 7290, 7515, 7961, 7069, 4757, 133,
+ 266, 532, 1064, 2128, 4256, 1263, 2526, 5052, 727, 1454, 2908,
+ 5816, 2271, 4542, 1747, 3494, 6988, 4919, 961, 1922, 3844,
+ 7688, 6591, 5841, 2061, 4122, 1435, 2870, 5740, 2423, 4846,
+ 115, 230, 460, 920, 1840, 3680, 7360, 7215, 7665, 7757, 6453,
+ 6085, 2597, 5194, 3387, 6774, 4419, 1833, 3666, 7332, 7399,
+ 7265, 7533, 8053, 6981, 4901, 997, 1994, 3988, 7976, 7167,
+ 4689, 269, 538, 1076, 2152, 4304, 1039, 2078, 4156, 1495,
+ 2990, 5980, 2839, 5678, 2547, 5094, 611, 1222, 2444, 4888,
+ 927, 1854, 3708, 7416, 7263, 7441, 8077, 6837, 4293, 1061,
+ 2122, 4244, 1159, 2318, 4636, 407, 814, 1628, 3256, 6512,
+ 5967, 2865, 5730, 2411, 4822, 3, 6, 12, 24, 48, 96, 192, 384,
+ 768, 1536, 3072, 6144, 5551, 3825, 7650, 7787, 6521, 5981,
+ 2837, 5674, 2555, 5110, 579, 1158, 2316, 4632, 415, 830, 1660,
+ 3320, 6640, 5711, 2353, 4706, 363, 726, 1452, 2904, 5808,
+ 2255, 4510, 1683, 3366, 6732, 4407, 1985, 3970, 7940, 7079,
+ 4833, 109, 218, 436, 872, 1744, 3488, 6976, 4911, 1009, 2018,
+ 4036, 8072, 6847, 4305, 1037, 2074, 4148, 1479, 2958, 5916,
+ 2967, 5934, 3059, 6118, 2659, 5318, 3107, 6214, 5411, 4073,
+ 8146, 6667, 4537, 1757, 3514, 7028, 4935, 801, 1602, 3204,
+ 6408, 6079, 2769, 5538, 3819, 7638, 7683, 6569, 5885, 2133,
+ 4266, 1275, 2550, 5100, 631, 1262, 2524, 5048, 735, 1470,
+ 2940, 5880, 2143, 4286, 1235, 2470, 4940, 823, 1646, 3292,
+ 6584, 5855, 2065, 4130, 1515, 3030, 6060, 2807, 5614, 3699,
+ 7398, 7267, 7529, 8061, 6997, 4869, 933, 1866, 3732, 7464,
+ 8191, 6737, 4365, 1973, 3946, 7892, 6151, 5537, 3821, 7642,
+ 7707, 6553, 5789, 2197, 4394, 2043, 4086, 8172, 6775, 4417,
+ 1837, 3674, 7348, 7367, 7201, 7661, 7797, 6469, 5925, 3045,
+ 6090, 2619, 5238, 3395, 6790, 4259, 1257, 2514, 5028, 743,
+ 1486, 2972, 5944, 3039, 6078, 2771, 5542, 3811, 7622, 7715,
+ 6633, 5757, 2389, 4778, 251, 502, 1004, 2008, 4016, 8032,
+ 7023, 4977, 845, 1690, 3380, 6760, 4479, 1873, 3746, 7492,
+ 7975, 7137, 4717, 373, 746, 1492, 2984, 5968, 2831, 5662,
+ 2451, 4902, 995, 1990, 3980, 7960, 7071, 4753, 141, 282, 564,
+ 1128, 2256, 4512, 1775, 3550, 7100, 4823, 0
+};
+
+static int err_loc_ply[100][100];
+
+static int
+fix_section(unsigned long offset, void *data, int *syndromes_in)
+{
+ int i, j, elp_sum;
+ int syndromes[9];
+ int Matrix_a[11];
+ int Matrix_b[11];
+ int Matrix_c[12];
+ int Element[7];
+ int alpha;
+ int temp_index;
+ int data_location, rev_location;
+ int result_byte, result_bit;
+ int err_location[20];
+ int err_count;
+ int d_flg;
+ int block_length, data_length;
+
+ /* correct 4 bits in 512 bytes */
+ data_length = 4096;
+ block_length = 8191;
+
+ /*
+ If there are no errors, just return.
+ */
+
+ j = 0;
+
+ for (i = 0; i < 8; ++i) {
+ if (0 != syndromes_in[i]) {
+ j = 1;
+ break;
+ }
+ }
+
+ if (0 == j)
+ return 0;
+
+ /*
+ Decode.
+ */
+
+ memcpy((void *)syndromes, (void *)syndromes_in, sizeof(int) * 9);
+ d_flg = 0;
+
+ /* initialise table entries */
+ for (i = 0; i < 8; i++)
+ syndromes[i] = i_to_a[syndromes[i]];
+
+ Matrix_c[0] = 0;
+ Matrix_c[1] = syndromes[0];
+ err_loc_ply[0][0] = 1;
+ err_loc_ply[1][0] = 1;
+ for (i = 1; i < 8; i++) {
+ err_loc_ply[0][i] = 0;
+ err_loc_ply[1][i] = 0;
+ }
+ Matrix_a[0] = 0;
+ Matrix_a[1] = 0;
+ Matrix_b[0] = -1;
+ Matrix_b[1] = 0;
+ alpha = -1;
+
+ do {
+ /* skip even loops */
+ alpha += 2;
+ if (Matrix_c[alpha] != -1) {
+ temp_index = alpha - 2;
+ if (temp_index < 0)
+ temp_index = 0;
+ while ((Matrix_c[temp_index] == -1) && (temp_index > 0))
+ temp_index = temp_index - 2;
+ if (temp_index < 0)
+ temp_index = 0;
+
+ if (temp_index > 0) {
+ j = temp_index;
+ do {
+ j = j - 2;
+ if (j < 0)
+ j = 0;
+ if ((Matrix_c[j] != -1) &&
+ (Matrix_b[temp_index] < Matrix_b[j]))
+ temp_index = j;
+ } while (j > 0);
+ }
+
+ if (Matrix_a[alpha] > Matrix_a[temp_index] +
+ alpha - temp_index)
+ Matrix_a[alpha + 2] = Matrix_a[alpha];
+ else
+ Matrix_a[alpha + 2] = Matrix_a[temp_index] +
+ alpha - temp_index;
+
+ for (i = 0; i < 8; ++i)
+ err_loc_ply[alpha + 2][i] = 0;
+
+ for (i = 0; i <= Matrix_a[temp_index]; i++) {
+ if (err_loc_ply[temp_index][i] != 0)
+ err_loc_ply[alpha + 2][i + \
+ alpha - temp_index] =
+ a_to_i[(Matrix_c[alpha] + \
+ block_length - \
+ Matrix_c[temp_index] + \
+ i_to_a[err_loc_ply[temp_index] \
+ [i]]) % block_length];
+ }
+
+ for (i = 0; i <= Matrix_a[alpha]; i++)
+ err_loc_ply[alpha + 2][i] ^=
+ err_loc_ply[alpha][i];
+ } else {
+ Matrix_a[alpha + 2] = Matrix_a[alpha];
+
+ for (i = 0; i <= Matrix_a[alpha]; i++)
+ err_loc_ply[alpha + 2][i] =
+ err_loc_ply[alpha][i];
+ }
+
+ Matrix_b[alpha + 2] = alpha+1 - Matrix_a[alpha + 2];
+
+ /* Form (alpha+2)th discrepancy. */
+ if (alpha < 8) {
+ if (syndromes[alpha + 1] != -1)
+ Matrix_c[alpha + 2] =
+ a_to_i[syndromes[alpha + 1]];
+ else
+ Matrix_c[alpha + 2] = 0;
+
+ for (i = 1; i <= Matrix_a[alpha + 2]; i++) {
+ if ((syndromes[alpha + 1 - i] != -1) &&
+ (err_loc_ply[alpha + 2][i] != 0))
+ Matrix_c[alpha + 2] ^=
+ a_to_i[(syndromes[alpha + 1 - i]
+ + i_to_a[err_loc_ply[alpha + 2]\
+ [i]]) % block_length];
+ }
+ Matrix_c[alpha + 2] = i_to_a[Matrix_c[alpha + 2]];
+ }
+ } while ((alpha < 7) && (Matrix_a[alpha + 2] <= 4));
+
+ alpha = alpha+2;
+ Matrix_a[7] = Matrix_a[alpha];
+ if (Matrix_a[7] <= 4) {
+ for (i = 1; i <= Matrix_a[7]; i++)
+ Element[i] = i_to_a[err_loc_ply[alpha][i]];
+
+ err_count = 0 ;
+ for (i = 1; i <= block_length; i++) {
+ elp_sum = 1 ;
+ for (j = 1; j <= Matrix_a[7]; j++)
+ if (Element[j] != -1) {
+ Element[j] = (Element[j] + j) %
+ block_length ;
+ elp_sum ^= a_to_i[Element[j]] ;
+ }
+
+ if (!elp_sum) {
+ err_location[err_count] = block_length - i ;
+ err_count++ ;
+ }
+ }
+
+ if (err_count == Matrix_a[7])
+ d_flg = 1 ;
+ }
+
+ if (d_flg == 0) {
+ return -1;
+ } else {
+ for (i = 0; i < err_count; i++) {
+ if (err_location[i] >= 52)
+ data_location = err_location[i] - 52;
+ else
+ data_location = err_location[i] + data_length;
+
+ if (data_location <= 4095) {
+ rev_location = 4095 - data_location;
+ result_bit = rev_location % 8;
+ result_byte = (rev_location - result_bit) / 8;
+
+ printk(KERN_NOTICE
+ "Corrected ECC Error: "
+ "offset 0x%lx byte 0x%x bit %d\n",
+ offset, result_byte, result_bit);
+
+ result_byte =
+ (result_byte & 0xfffffffc) |
+ ((result_byte & 0x3) ^ 0x3);
+ *((unsigned char *)(data +
+ result_byte)) ^=
+ (1 << result_bit);
+ } else {
+ rev_location = 4147 - data_location;
+ result_bit = rev_location % 8;
+ result_byte = (rev_location - result_bit) / 8;
+ printk(KERN_ERR
+ "BCH byte = %d, bit = %d\n",
+ result_byte, result_bit);
+ }
+ }
+
+ if (0 != err_count)
+ return 1;
+ else
+ return 0;
+ }
+}
+
+/*
+ ------------------------------------------------------------------------------
+ report_ecc_errors_ep501g1
+*/
+
+static int
+report_ecc_errors_ep501g1(struct mtd_info *mtd, struct nand_chip *chip,
+ uint8_t *buffer, int page)
+{
+ unsigned long bch_status;
+ int rc = 0;
+ int i;
+ int is_blank = 1;
+ uint8_t *data = buffer;
+ int section;
+ int syndrome;
+ unsigned long syndromes[8][8];
+
+ /* If there are no errors, return. */
+ bch_status = READL(chip->IO_ADDR_R + EP501G1_NAND_BCH_STATUS);
+
+ if (0 == bch_status)
+ goto report_ecc_errors_ep501g1_end;
+
+ switch (mtd->writesize) {
+ case 512:
+ bch_status &= 0x1;
+ break;
+ case 2048:
+ bch_status &= 0xf;
+ break;
+ case 4096:
+ bch_status &= 0xff;
+ break;
+ default:
+ printk(KERN_ERR "Unexpected Page Size!\n");
+ rc = -1;
+ goto report_ecc_errors_ep501g1_end;
+ break;
+ }
+
+ /* Ignore fully erased blocks. */
+ if (NULL != data) {
+ for (i = 0; i < mtd->writesize; ++i) {
+ if (0xff != *data++) {
+ is_blank = 0;
+ break;
+ }
+ }
+ }
+
+ if (0 != is_blank)
+ goto report_ecc_errors_ep501g1_end;
+
+ /* Read the syndrome registers and split them into syndromes. */
+ for (section = 0; section < 8; ++section) {
+ unsigned long address;
+ unsigned long value;
+
+ address = EP501G1_NAND_SYN_R12_S0 + (section * 0x10);
+
+ for (syndrome = 0; syndrome < 8; syndrome += 2) {
+ value = READL(chip->IO_ADDR_R + address +
+ (syndrome * 2));
+ syndromes[section][syndrome] =
+ (value & 0x1fff);
+ syndromes[section][syndrome + 1] =
+ ((value & 0x1fff0000) >> 16);
+ }
+ }
+
+#ifdef NOT_USED
+ /* Debug output (BCH status register and syndromes). */
+ printk(KERN_INFO "BCH Status Register: 0x%02lx\n", bch_status);
+
+ for (section = 0; section < 8; ++section) {
+ printk(KERN_INFO "Syndromes, Section %d: ", section);
+
+ for (syndrome = 0; syndrome < 8; ++syndrome) {
+ printk(KERN_INFO "0x%04lx ",
+ syndromes[section][syndrome]);
+ }
+
+ printk(KERN_INFO "\n");
+ }
+#endif
+
+ for (i = 0; i < 4; ++i) {
+ if ((1 << i) == (bch_status & (1 << i))) {
+ rc = fix_section(((page * mtd->writesize) + (512 * i)),
+ (void *)(buffer + (512 * i)),
+ (int *)&syndromes[i]);
+
+ if (-1 == rc)
+ printk(KERN_ERR
+ "Uncorrectable ECC Error: Page %d\n",
+ page);
+ }
+ }
+
+ report_ecc_errors_ep501g1_end:
+
+ return rc;
+}
+
+/*
+ ------------------------------------------------------------------------------
+ report_ecc_errors_ep501g3
+*/
+
+static int
+report_ecc_errors_ep501g3(struct mtd_info *mtd, struct nand_chip *chip,
+ uint8_t *buffer, int page)
+{
+ unsigned long bch_status;
+ int rc = 0;
+ unsigned long value;
+ int i;
+ int is_blank = 1;
+ uint8_t *data = buffer;
+ int section;
+ int syndrome;
+ unsigned long syndromes[8][8];
+
+ /* Verify 4-bit mode in the EP501G3 case. */
+ value = (READL(chip->IO_ADDR_R + EP501_NAND_CONFIG_REG) & 0x1800) >> 11;
+
+ if (1 != value) {
+ printk("Only 4-Bit ECC is supported.\n");
+ rc = -1;
+ goto report_ecc_errors_ep501g3_end;
+ }
+
+ /* If there are no errors, return. */
+ bch_status = READL(chip->IO_ADDR_R + EP501G1_NAND_BCH_STATUS);
+
+ if (0 == bch_status)
+ goto report_ecc_errors_ep501g3_end;
+
+ switch (mtd->writesize) {
+ case 512:
+ bch_status &= 0x1;
+ break;
+ case 2048:
+ bch_status &= 0xf;
+ break;
+ case 4096:
+ bch_status &= 0xff;
+ break;
+ default:
+ printk(KERN_ERR "Unexpected Page Size!\n");
+ rc = -1;
+ goto report_ecc_errors_ep501g3_end;
+ break;
+ }
+
+ /* Ignore fully erased blocks. */
+ if (NULL != data) {
+ for (i = 0; i < mtd->writesize; ++i) {
+ if (0xff != *data++) {
+ is_blank = 0;
+ break;
+ }
+ }
+ }
+
+ if (0 != is_blank)
+ goto report_ecc_errors_ep501g3_end;
+
+ /* Read the syndrome registers and split them into syndromes. */
+ for (section = 0; section < 8; ++section) {
+ unsigned long address;
+ unsigned long value;
+
+ address = EP501G1_NAND_SYN_R12_S0 + (section * 0x10);
+
+ for (syndrome = 0; syndrome < ((mtd->writesize / 512) * 2);
+ syndrome += 2, address += 4) {
+ value = READL(chip->IO_ADDR_R + address);
+ syndromes[section][syndrome] =
+ (value & 0x1fff);
+ syndromes[section][syndrome + 1] =
+ ((value & 0x1fff0000) >> 16);
+ }
+ }
+
+#ifdef NOT_USED
+ /* Debug output (BCH status register and syndromes). */
+ printk(KERN_INFO "BCH Status Register: 0x%02lx\n", bch_status);
+
+ for (section = 0; section < 8; ++section) {
+ printk(KERN_INFO "Syndromes, Section %d: ", section);
+
+ for (syndrome = 0; syndrome < 8; ++syndrome)
+ printk(KERN_INFO "0x%04lx ",
+
+ printk(KERN_INFO "\n");
+ }
+#endif
+
+ for (i = 0; i < 4; ++i) {
+ if ((1 << i) == (bch_status & (1 << i))) {
+ rc = fix_section(((page * mtd->writesize) + (512 * i)),
+ (void *)(buffer + (512 * i)),
+ (int *)&syndromes[i]);
+
+ if (-1 == rc)
+ printk(KERN_ERR
+ "Uncorrectable ECC Error: Page %d\n",
+ page);
+ }
+ }
+
+ report_ecc_errors_ep501g3_end:
+
+ return rc;
+}
+
+/*
+ ------------------------------------------------------------------------------
+ report_ecc_errors
+*/
+
+static int
+report_ecc_errors(struct mtd_info *mtd, struct nand_chip *chip,
+ uint8_t *buffer, int page)
+{
+ int rc = 0;
+
+ switch (lsi_nand_type) {
+ case LSI_NAND_EP501:
+ rc = report_ecc_errors_ep501(mtd, chip, buffer, page);
+ break;
+ case LSI_NAND_EP501G1:
+ rc = report_ecc_errors_ep501g1(mtd, chip, buffer, page);
+ break;
+ case LSI_NAND_EP501G3:
+ rc = report_ecc_errors_ep501g3(mtd, chip, buffer, page);
+ break;
+ default:
+ rc = -1;
+ break;
+ }
+
+ return rc;
+}
+
+
+/**
+ * nand_read_page_hwecc - hardware ecc based page read function
+ * @mtd: mtd info structure
+ * @chip: nand chip info structure
+ * @buf: buffer to store read data
+ *
+ * Not for syndrome calculating ecc controllers which need a special oob layout
+ */
+
+static int
+lsi_nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
+ uint8_t *buf, int page)
+{
+ int rc;
+ /*int page = 0;*/
+
+ /* Read the current page number and save it. */
+ /*page = READL(chip->IO_ADDR_R + NAND_INDEX_REG) >> 12;*/
+
+ /* read the page */
+ chip->read_buf(mtd, buf, mtd->writesize);
+
+ /* read oob data */
+ chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
+
+ /* start ECC calculations */
+ chip->ecc.calculate(mtd, NULL, NULL);
+
+ /* Read the ECC Status and see if there were any errors */
+ rc = report_ecc_errors(mtd, chip, buf, page);
+
+ /* cmd to controller to turn off CE */
+ chip->cmd_ctrl(mtd, nand_cmd_ce_off, 0);
+ return rc;
+}
+
+/**
+ * lsi_nand_write_page_hwecc - hardware ecc based page write function
+ * @mtd: mtd info structure
+ * @chip: nand chip info structure
+ * @buf: data buffer
+ */
+static int
+lsi_nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
+ const uint8_t *buf)
+{
+ /* write the page data */
+ chip->write_buf(mtd, buf, mtd->writesize);
+
+ /*
+ * Write the oob data. Last 12 bytes are used by HW ECC.
+ * Do not touch them.
+ */
+ chip->write_buf(mtd, chip->oob_poi, mtd->oobsize - chip->ecc.bytes);
+ return 0;
+}
+
+/**
+ * lsi_nand_write_page - [REPLACEABLE] write one page
+ * @mtd: MTD device structure
+ * @chip: NAND chip descriptor
+ * @buf: the data to write
+ * @page: page number to write
+ * @cached: cached programming
+ * @raw: use _raw version of write_page
+ */
+
+static int
+lsi_nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
+ const uint8_t *buf, int page, int cached, int raw)
+{
+ int status;
+
+ chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
+
+ if (unlikely(raw))
+ chip->ecc.write_page_raw(mtd, chip, buf);
+ else
+ chip->ecc.write_page(mtd, chip, buf);
+
+ /* calculate ECC */
+ status = chip->ecc.calculate(mtd, NULL, NULL);
+
+ /* cmd to controller to turn off CE */
+ chip->cmd_ctrl(mtd, nand_cmd_ce_off, 0);
+
+ /*
+ * See if operation failed and additional status checks are
+ * available
+ */
+ if (status & NAND_STATUS_FAIL) {
+ printk(KERN_ERR "ERROR: Page write failed for page 0x%x\n",
+ page);
+
+ if (chip->errstat)
+ status = chip->errstat(mtd, chip, FL_WRITING, status,
+ page);
+
+ return -EIO;
+ }
+
+#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
+ /* Send command to read back the data */
+ chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
+
+ if (chip->verify_buf(mtd, buf, mtd->writesize))
+ return -EIO;
+#endif
+
+ return 0;
+}
+
+
+/**
+ * lsi_nand_read_oob_std - [REPLACABLE] the most common OOB data read function
+ * @mtd: mtd info structure
+ * @chip: nand chip info structure
+ * @page: page number to read
+ * @sndcmd: flag whether to issue read command or not
+ */
+
+static int
+lsi_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
+ int page, int sndcmd)
+{
+ int rc;
+
+ /* send command to read oob */
+ chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
+
+ /* read oob data */
+ chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
+
+ /* start ECC calculations */
+ chip->ecc.calculate(mtd, NULL, NULL);
+
+ /* Read the ECC Status and see if there were any errors */
+ rc = report_ecc_errors(mtd, chip, NULL, page);
+
+ /* cmd to controller to turn off CE */
+ chip->cmd_ctrl(mtd, nand_cmd_ce_off, 0);
+
+ return sndcmd;
+}
+
+/**
+ * lsi_nand_write_oob_std - [REPLACABLE] the most common OOB data write
+ * function
+ * @mtd: mtd info structure
+ * @chip: nand chip info structure
+ * @page: page number to write
+ */
+
+static int
+lsi_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip, int page)
+{
+ /* start OOB write */
+ chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
+
+ /*
+ * Write the oob data. Last 12 bytes are used by HW ECC.
+ * Do not touch them.
+ */
+ chip->write_buf(mtd, chip->oob_poi, mtd->oobsize - chip->ecc.bytes);
+
+ /* calculate ECC */
+ chip->ecc.calculate(mtd, NULL, NULL);
+
+ /* cmd to controller to turn off CE */
+ chip->cmd_ctrl(mtd, nand_cmd_ce_off, 0);
+
+ return (chip->dev_ready(mtd) & NAND_STATUS_FAIL) ? -EIO : 0;
+}
+
+/*
+ ======================================================================
+ ======================================================================
+ Public
+ ======================================================================
+ ======================================================================
+*/
+
+/*
+ ------------------------------------------------------------------------------
+ lsi_nand_set_config
+*/
+
+int
+lsi_nand_set_config(struct mtd_info *mtd, struct nand_chip *chip)
+{
+ unsigned long config = 0;
+ unsigned long mbits;
+
+ mbits = ((chip->chipsize >> 20) * 8);
+
+ if (LSI_NAND_EP501 == lsi_nand_type) {
+ /* The EP501 only supports 512 and 2k page sizes. */
+ if (512 != mtd->writesize &&
+ 2048 != mtd->writesize)
+ return -1;
+
+ while (64 < mbits) {
+ ++config; /* 0b000=64Mbit, 0b001=128Mbit, etc. */
+ mbits >>= 1;
+ }
+
+ if (512 < mtd->writesize)
+ config |= 0x100; /* large block */
+
+ config |= 0x200; /* not write protected */
+ chip->ecc.layout = &lsi_2k_1bit_ecclayout;
+ chip->ecc.size = mtd->writesize;
+ chip->ecc.bytes = chip->ecc.layout->eccbytes;
+ } else if (LSI_NAND_EP501G1 == lsi_nand_type) {
+ /* The EP501G1 only supports 512, 2k, and 4k page sizes, */
+ if (512 != mtd->writesize &&
+ 2048 != mtd->writesize &&
+ 4096 != mtd->writesize)
+ return -1;
+
+ /* and device sizes as follows. */
+ if (512 == mtd->writesize) {
+ switch (mbits) {
+ case 64:
+ break;
+ case 128:
+ config |= 1;
+ break;
+ case 256:
+ config |= 2;
+ break;
+ case 512:
+ config |= 3;
+ break;
+ case 1024:
+ config |= 4;
+ break;
+ case 2048:
+ config |= 5;
+ break;
+ case 4096:
+ config |= 6;
+ break;
+ case 8192:
+ config |= 7;
+ break;
+ default:
+ return -1;
+ break;
+ }
+ } else {
+ switch (mbits) {
+ case 512:
+ config |= 3;
+ break;
+ case 1024:
+ config |= 4;
+ break;
+ case 2048:
+ config |= 5;
+ break;
+ case 4096:
+ config |= 6;
+ break;
+ case 8192:
+ config |= 7;
+ break;
+ case 16384:
+ break;
+ case 32768:
+ config |= 1;
+ break;
+ case 65536:
+ config |= 2;
+ break;
+ default:
+ return -1;
+ break;
+ }
+ }
+
+ switch (mtd->writesize) {
+ case 512:
+ break;
+ case 2048:
+ config |= 0x1 << 8;
+ chip->ecc.layout = &lsi_2k_4bit_ecclayout;
+ break;
+ case 4096:
+ config |= 0x2 << 8;
+ chip->ecc.layout = &lsi_4k_4bit_ecclayout;
+ break;
+ default:
+ return -1;
+ break;
+ }
+
+ config |= 1 << 10; /* not write protected */
+
+ config |= 1 << 11; /* 4 bit ECC */
+
+ if (512 < mtd->writesize)
+ config |= 1 << 12; /* 3 cycle row address */
+
+ chip->ecc.size = mtd->writesize;
+
+ if (mtd->oobsize == 224)
+ chip->ecc.bytes = 224 - chip->ecc.layout->eccbytes;
+ else
+ chip->ecc.bytes = chip->ecc.layout->eccbytes;
+
+ } else if (LSI_NAND_EP501G3 == lsi_nand_type) {
+ /* The EP501G3 only supports 2k, 4k, and 8k page sizes, */
+ if (2048 != mtd->writesize &&
+ 4096 != mtd->writesize &&
+ 8192 != mtd->writesize)
+ return -1;
+
+ /* and device sizes as follows. */
+ switch (mbits) {
+ case 512:
+ config |= 3;
+ break;
+ case 1024:
+ config |= 4;
+ break;
+ case 2048:
+ config |= 5;
+ break;
+ case 4096:
+ config |= 6;
+ break;
+ case 8192:
+ config |= 7;
+ break;
+ case 16384:
+ break;
+ case 32768:
+ config |= 1;
+ break;
+ case 65536:
+ config |= 2;
+ break;
+ default:
+ printk(KERN_ERR "Invalid Device Size: 0x%lx\n", mbits);
+ return -1;
+ break;
+ }
+
+ switch (mtd->writesize) {
+ case 2048:
+ config |= 0x1 << 8;
+ chip->ecc.layout = &lsi_2k_4bit_ecclayout;
+ break;
+ case 4096:
+ config |= 0x2 << 8;
+ chip->ecc.layout = &lsi_4k_4bit_ecclayout;
+ break;
+#ifdef NOT_USED
+ case 8192:
+ config |= 0x3 << 8;
+ chip->ecc.layout = &lsi_8k_4bit_ecclayout;
+ break;
+#endif
+ default:
+ return -1;
+ break;
+ }
+
+ config |= 1 << 10; /* not write protected */
+ config |= 1 << 13; /* 3 cycle row address */
+
+ /*
+ 2K/4bit - 32 bytes (8192)
+ 2K/8bit - 64 bytes (16384)
+ 2K/12bit - 80 bytes (24576)
+ ...
+ 8K/12bit - 320 bytes (98304)
+ */
+
+ if (mtd->oobsize < chip->ecc.layout->eccbytes) {
+ printk(KERN_ERR
+ "ECC requires %d bytes, only %d are available.\n",
+ chip->ecc.layout->eccbytes, mtd->oobsize);
+ return -1;
+ }
+
+ config |= 1 << 11; /* 4 bit ECC */
+ mtd->oobavail = mtd->oobsize - chip->ecc.layout->eccbytes;
+ mtd->oobavail -= (mtd->oobavail % 4);
+ config |= (chip->ecc.layout->eccbytes / 4) << 16;
+ chip->ecc.size = mtd->writesize;
+ chip->ecc.bytes = chip->ecc.layout->eccbytes;
+ } else {
+ return -1;
+ }
+
+ WRITEL(config, chip->IO_ADDR_W + EP501_NAND_CONFIG_REG);
+
+ return 0;
+}
+
+static uint8_t
+lsi_nand_read_byte(struct mtd_info *mtd)
+{
+ struct lsi_nand_private *priv = &lsi_nand_private;
+ struct nand_chip *chip = mtd->priv;
+
+ if (priv->cur >= 0) {
+ WARN_ON(priv->cur >= MAX_READ_BUF);
+ return priv->buf[priv->cur++];
+ } else
+ return readb(chip->IO_ADDR_R);
+}
+
+static int lsi_nand_errstat
+ (struct mtd_info *mtd, struct nand_chip *chip,
+ int state, int status, int page) {
+ /* if erase failed for a block, mark it as bad block */
+ if ((FL_ERASING == chip->state) && (status & NAND_STATUS_FAIL))
+ mtd_block_markbad(mtd, page << chip->page_shift);
+
+ return status;
+}
+
+static int
+lsi_nand_init_size(struct mtd_info *mtd, struct nand_chip *chip, u8 *id_data)
+{
+ int busw, extid;
+
+ /* The 3rd id byte holds MLC / multichip data */
+ chip->cellinfo = readb(chip->IO_ADDR_R + NAND_ID4_REG);
+ /* The 4th id byte is the important one */
+ extid = readb(chip->IO_ADDR_R + NAND_ID6_REG);
+
+ /* Add workaournd for Micron MT29Fxxxxxx NAND flash */
+ if (id_data[0] == NAND_MFR_MICRON && id_data[1] == 0x48) {
+ /* Calc pagesize */
+ mtd->writesize = 1024 << (extid & 0x03);
+ extid >>= 2;
+ /*Calc oobsize */
+ mtd->oobsize = ((extid & 0x03) == 0x03) ? 218 : 224;
+ extid >>= 3;
+ /* Calc blocksize. Blocksize is multiples of 256KiB */
+ mtd->erasesize = (256 * 1024) << (extid & 0x03);
+ busw = 0;
+ } else {
+ /* Calc pagesize */
+ mtd->writesize = 1024 << (extid & 0x03);
+ extid >>= 2;
+ /* Calc oobsize */
+ mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
+ extid >>= 2;
+ /* Calc blocksize. Blocksize is multiples of 64KiB */
+ mtd->erasesize = (64 * 1024) << (extid & 0x03);
+ extid >>= 2;
+ /* Get buswidth information */
+ busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
+ }
+
+ lsi_nand_set_config(mtd, chip);
+
+ return busw;
+}
+
+/*
+ ----------------------------------------------------------------------
+ lsi_nand_init
+*/
+
+#define NAND_BASE 0x002000440000ULL
+#define NAND_SIZE 0x20000
+#define GPREG_BASE 0x00200040c000ULL
+#define GPREG_SIZE 0x1000
+
+static int __init
+lsi_nand_init(void)
+{
+ void *nand_base;
+ struct device_node *np = NULL;
+ struct mtd_part_parser_data ppdata;
+ static const char *part_probe_types[]
+ = { "cmdlinepart", "ofpart", NULL };
+
+ memset(&ppdata, 0, sizeof(ppdata));
+
+ np = of_find_node_by_type(np, "nand");
+
+ while (np && !of_device_is_compatible(np, "acp-nand"))
+ np = of_find_node_by_type(np, "nand");
+
+ if (np) {
+ const u32 *reg;
+ int reglen;
+ u64 nand_address;
+ unsigned long nand_length;
+ u64 gpreg_address;
+ unsigned long gpreg_length;
+ const u32 *enabled;
+
+ enabled = of_get_property(np, "enabled", NULL);
+
+ if (NULL == enabled) {
+ printk("ACP NAND Controller Isn't Enabled.\n");
+ return -1;
+ }
+
+ reg = of_get_property(np, "reg", ®len);
+
+ if (reg && (16 == reglen)) {
+ nand_address = of_translate_address(np, reg);
+ nand_length = reg[1];
+ reg += 2;
+ gpreg_address = of_translate_address(np, reg);
+ gpreg_length = reg[1];
+ printk(KERN_INFO "nand_address=0x%08llx nand_length=0x%lx\n"
+ "gpreg_address=0x%08llx gpreg_length=0x%lx\n",
+ nand_address, nand_length,
+ gpreg_address, gpreg_length);
+ nand_base = ioremap(nand_address, nand_length);
+ gpreg_base = ioremap(gpreg_address, gpreg_length);
+ } else {
+ return -1;
+ }
+
+ ppdata.of_node = np;
+ } else {
+ printk(KERN_INFO "ACP NAND: Using Static Addresses.\n");
+ nand_base = ioremap(0x002000440000ULL, 0x20000);
+ gpreg_base = ioremap(0x00200040c000ULL, 0x1000);
+ }
+
+ /*
+ Determine the version of the controller.
+
+ As there is not version register, see if bits 5:3 of the
+ configuration register are writable. There are in the EP501
+ case and aren't in the EP501G1 case.
+ */
+
+ {
+ unsigned long cr;
+ unsigned long cr_save;
+
+ cr = cr_save = READL((void *)(nand_base + NAND_CONFIG_REG));
+ cr = 0x2038;
+ WRITEL(cr, (void *)(nand_base + EP501_NAND_CONFIG_REG));
+ cr = READL((void *)nand_base + EP501_NAND_CONFIG_REG);
+ WRITEL(cr_save, (void *)(nand_base + EP501_NAND_CONFIG_REG));
+
+ if (0 == (cr & 0x2038))
+ lsi_nand_type = LSI_NAND_EP501G1;
+ else if (0x38 == (cr & 0x2038))
+ lsi_nand_type = LSI_NAND_EP501;
+ else if (0x2000 == (cr & 0x2038))
+ lsi_nand_type = LSI_NAND_EP501G3;
+ else
+ lsi_nand_type = LSI_NAND_NONE;
+ }
+
+ switch (lsi_nand_type) {
+ case LSI_NAND_EP501:
+ printk(KERN_INFO "EP501 NAND Controller.\n");
+ nand_cmd_ce_off = NAND_CMD_CE_OFF_501;
+ break;
+ case LSI_NAND_EP501G1:
+ printk(KERN_INFO "EP501G1 NAND Controller.\n");
+ nand_cmd_ce_off = NAND_CMD_CE_OFF_501G1;
+ break;
+ case LSI_NAND_EP501G3:
+ printk(KERN_INFO "EP501G3 NAND Controller.\n");
+ nand_cmd_ce_off = NAND_CMD_CE_OFF_501G3;
+ break;
+ default:
+ printk(KERN_INFO "Unknown NAND Controller!\n");
+ return -1;
+ break;
+ }
+
+ /* Initialize structures */
+ memset(&lsi_nand_mtd, 0, sizeof(struct mtd_info));
+ memset(&lsi_nand_chip, 0, sizeof(struct nand_chip));
+
+ /* Link the private data with the MTD structure */
+ lsi_nand_mtd.priv = &lsi_nand_chip;
+ lsi_nand_mtd.owner = THIS_MODULE;
+ lsi_nand_mtd.name = "acp-nand";
+
+ /* init chip callbacks */
+ lsi_nand_chip.IO_ADDR_R = (void *) nand_base;
+ lsi_nand_chip.IO_ADDR_W = (void *) nand_base;
+ lsi_nand_chip.write_buf = lsi_nand_write_buf;
+ lsi_nand_chip.read_buf = lsi_nand_read_buf;
+ lsi_nand_chip.verify_buf = lsi_nand_verify_buf;
+ lsi_nand_chip.write_page = lsi_nand_write_page;
+ lsi_nand_chip.cmd_ctrl = lsi_nand_hwcontrol;
+ lsi_nand_chip.dev_ready = lsi_nand_device_ready;
+ lsi_nand_chip.cmdfunc = lsi_nand_command;
+ lsi_nand_chip.waitfunc = lsi_nand_wait;
+ lsi_nand_chip.chip_delay = 10;
+ lsi_nand_chip.bbt_options = NAND_BBT_USE_FLASH;
+ lsi_nand_chip.read_byte = lsi_nand_read_byte;
+ lsi_nand_chip.errstat = lsi_nand_errstat;
+ lsi_nand_chip.init_size = lsi_nand_init_size;
+
+ /* initialize ECC */
+ lsi_nand_chip.ecc.mode = NAND_ECC_HW;
+ lsi_nand_chip.ecc.steps = 1;
+ lsi_nand_chip.ecc.total = 12;
+ lsi_nand_chip.ecc.hwctl = lsi_nand_ecc_hwctl;
+ lsi_nand_chip.ecc.calculate = lsi_nand_ecc_calculate;
+ lsi_nand_chip.ecc.correct = lsi_nand_ecc_correct;
+ lsi_nand_chip.ecc.read_page = lsi_nand_read_page_hwecc;
+ lsi_nand_chip.ecc.write_page = lsi_nand_write_page_hwecc;
+ lsi_nand_chip.ecc.read_page_raw = lsi_nand_read_page_hwecc;
+ lsi_nand_chip.ecc.write_page_raw = lsi_nand_write_page_hwecc;
+ lsi_nand_chip.ecc.read_oob = lsi_nand_read_oob;
+ lsi_nand_chip.ecc.write_oob = lsi_nand_write_oob;
+
+ printk(KERN_ERR "Enabling NAND ECC...\n");
+ /* clear any existing ECC status */
+ WRITEL(0x0, lsi_nand_chip.IO_ADDR_W + NAND_INTR_STATUS_REG);
+ /* enable ECC */
+ WRITEL(0x0, lsi_nand_chip.IO_ADDR_W + NAND_INTR_EN_REG);
+
+ /*
+ ======================================================================
+ Timing Control
+
+ This may need to be changed, based on the devices used. Each field is
+ described below.
+ */
+
+ /*
+ TCR0 - NAND Timing Control Register 0
+ */
+
+ {
+ nand_timing_control_register_0_t tcr0;
+
+ /* TH [31:24] - CLE, CE & ALE hold Time */
+ tcr0.bits.th = 0x08;
+
+ /* TRP [23:16] - Read Pulse Width */
+ tcr0.bits.trp = 0x0c;
+
+ /* TWP [15:8] - Write Pulse Width */
+ tcr0.bits.twp = 0x0c;
+
+ /* TS [7:0] - Setup Time for CLE, CE & ALE */
+ tcr0.bits.ts = 0x05;
+
+ WRITEL(tcr0.raw,
+ (lsi_nand_chip.IO_ADDR_W + NAND_TIMING1_REG));
+ }
+
+ /*
+ TCR1 - NAND Timing Control Register 1
+ */
+
+ {
+ nand_timing_control_register_1_t tcr1;
+
+ /* TWB [31:24] - WE Rising Edge to RY/BY Falling Edge */
+ tcr1.bits.twb = 0x1e;
+
+ /* TRR [23:16] - RY/BY Rising Edge To Read Falling Edge */
+ tcr1.bits.trr = 0x07;
+
+ /* TRH [15:8] - Read Pulse High Time */
+ tcr1.bits.trh = 0x03;
+
+ /* TWH [7:0] - Write Pulse High Time */
+ tcr1.bits.twh = 0x03;
+
+ WRITEL(tcr1.raw,
+ (lsi_nand_chip.IO_ADDR_W + NAND_TIMING2_REG));
+ }
+
+ /*
+ TCR2 - NAND Timing Control Register 2 (EP501G3 Only)
+ */
+
+ {
+ nand_timing_control_register_2_t tcr2;
+
+ tcr2.bits.tccs = 0x10;
+ tcr2.bits.twhr = 0x10;
+ tcr2.bits.trhw = 0x14;
+ WRITEL(tcr2.raw,
+ (lsi_nand_chip.IO_ADDR_W + EP501G3_NAND_TIMING2_REG));
+ }
+
+ printk(KERN_ERR "Searching for NAND flash...\n");
+ /* Scan to find existence of the device */
+ if (nand_scan(&lsi_nand_mtd, 1)) {
+ printk(KERN_ERR "nand_scan failure...\n");
+ return -ENXIO;
+ }
+
+ /* Register the partitions */
+
+ mtd_device_parse_register(&lsi_nand_mtd, part_probe_types, &ppdata,
+ NULL, 0);
+
+ /* Return happy */
+ return 0;
+}
+
+module_init(lsi_nand_init);
+
+/*
+ ----------------------------------------------------------------------
+ lsi_nand_exit
+*/
+
+static void __exit
+lsi_nand_exit(void)
+{
+ /* Release resources, unregister device */
+ nand_release(&lsi_nand_mtd);
+}
+
+module_exit(lsi_nand_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Jay Jayatheerthan <jay.jayatheerthan at lsi.com>");
+MODULE_DESCRIPTION("MTD map driver for LSI's ACP board");
diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c
index af4fe8c..db2dce9 100644
--- a/drivers/mtd/nand/nand_ids.c
+++ b/drivers/mtd/nand/nand_ids.c
@@ -115,6 +115,7 @@ struct nand_flash_dev nand_flash_ids[] = {
{"NAND 2GiB 3,3V 8-bit", 0xD5, 0, 2048, 0, LP_OPTIONS},
{"NAND 2GiB 1,8V 16-bit", 0xB5, 0, 2048, 0, LP_OPTIONS16},
{"NAND 2GiB 3,3V 16-bit", 0xC5, 0, 2048, 0, LP_OPTIONS16},
+ {"NAND 2GiB 3,3V 16-bit", 0x48, 0, 2048, 0, LP_OPTIONS},
/* 32 Gigabit */
{"NAND 4GiB 1,8V 8-bit", 0xA7, 0, 4096, 0, LP_OPTIONS},
--
1.8.3
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