[linux-yocto] [PATCH 24/87] arm/dts: add dts for LSI AXM5516 simulation and emulation/asic.

Paul Butler butler.paul at gmail.com
Mon May 27 09:55:55 PDT 2013


From: John Jacques <john.jacques at lsi.com>

Device tree source files for LSI AXM5516 simulation and emulation/asic.

Signed-off-by: John Jacques <john.jacques at lsi.com>
---
 arch/arm/boot/dts/axm55xx.dts    | 290 +++++++++++++++++++++++++
 arch/arm/boot/dts/axm55xxsim.dts | 447 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 737 insertions(+)
 create mode 100644 arch/arm/boot/dts/axm55xx.dts
 create mode 100644 arch/arm/boot/dts/axm55xxsim.dts

diff --git a/arch/arm/boot/dts/axm55xx.dts b/arch/arm/boot/dts/axm55xx.dts
new file mode 100644
index 0000000..3359cb4
--- /dev/null
+++ b/arch/arm/boot/dts/axm55xx.dts
@@ -0,0 +1,290 @@
+/*
+ * arch/arm/boot/dts/axm5500-sim.dts
+ *
+ * Copyright (C) 2012 LSI
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+/dts-v1/;
+
+/ {
+	model = "AXM5516";
+	compatible = "arm", "lsi,axm5516";
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	chosen { };
+
+	aliases {
+		serial0 = &axxia_serial0;
+		timer   = &axxia_timers;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu at 0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <0>;
+		};
+	};
+
+	memory at 00000000 {
+		device_type = "memory";
+		reg = <0 0x00000000 0 0x40000000>;
+	};
+
+	gic: interrupt-controller at 2001001000 {
+		compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
+		#interrupt-cells = <3>;
+		#address-cells = <0>;
+		interrupt-controller;
+		reg = <0x20 0x01001000 0 0x1000>,
+		      <0x20 0x01002000 0 0x100>;
+	};
+
+	timer {
+		compatible = "arm,armv7-timer";
+		interrupts = <1 13 0xf08>,
+			     <1 14 0xf08>;
+	};
+
+
+	gpdma at 2020140000 {
+		compatible = "lsi,dma32";
+		reg = <0x20 0x20140000 0x00 0x1000>;
+		interrupts = <0 60 4>, /* busy */
+			     <0 61 4>; /* error */
+
+		channel0 {
+			interrupts = <0 62 4>;
+		};
+
+		channel1 {
+			interrupts = <0 63 4>;
+		};
+	};
+
+	gpdma at 2020141000 {
+		status = "disabled";
+		compatible = "lsi,dma32";
+		reg = <0x20 0x20141000 0x00 0x1000>;
+		interrupts = <0 64 4>, /* busy */
+			     <0 65 4>; /* error */
+
+		channel0 {
+			interrupts = <0 66 4>;
+		};
+
+		channel1 {
+			interrupts = <0 67 4>;
+		};
+	};
+
+	gpreg at 2010094000  {
+		compatible = "lsi,gpreg";
+		reg = <0x20 0x10094000 0 0x1000>;
+	};
+
+	ethernet at 201100000000 {
+		compatible = "smsc,lan91c111";
+		device_type = "network";
+		reg = <0x20 0x11000000 0 0x10000>;
+		interrupts = <0 1 4>;
+		phy-mode = "mii";
+		reg-io-width = <4>;
+		smsc,irq-active-high;
+		smsc,irq-push-pull;
+	};
+
+        amba {
+		compatible = "arm,amba-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		mmci at 020101E0000 {
+			compatible = "arm,pl180", "arm,primecell";
+			reg = <0x20 0x101E0000 0x00 0x1000>;
+			interrupts = <0 222 4>,
+				     <0 223 4>;
+		};
+
+		axxia_serial0: uart at 2010080000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x20 0x10080000 0x00 0x1000>;
+			interrupts = <0 56 4>;
+		};
+
+		axxia_timers: timer at 2010091000 {
+			compatible = "arm,sp804", "arm,primecell";
+			reg = <0x20 0x10091000 0 0x1000>;
+			interrupts = <0 47 4>,
+				     <0 48 4>,
+				     <0 49 4>,
+				     <0 50 4>,
+				     <0 51 4>,
+				     <0 52 4>,
+				     <0 53 4>,
+				     <0 54 4>;
+		};
+
+		gpio at 2010092000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0x20 0x10092000 0 0x1000>;
+			interrupts = <0 10 4>,
+				     <0 11 4>,
+				     <0 12 4>,
+				     <0 13 4>,
+				     <0 14 4>,
+				     <0 15 4>,
+				     <0 16 4>,
+				     <0 17 4>;
+		};
+
+		gpio at 2010093000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0x20 0x10093000 0x00 0x1000>;
+			interrupts = <0 18 4>;
+		};
+
+		ssp at 2010088000 {
+			compatible = "arm,pl022", "arm,primecell";
+			reg = <0x20 0x10088000 0x00 0x1000>;
+			interrupts = <0 42 4>;
+		};
+
+	};
+
+    PCIE0: pciex at 0xf0120000 {
+                compatible = "lsi,plb-pciex";
+                device_type = "pci";
+                enabled = <0>;
+                plx = <0>;
+                primary;
+                port = <0>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                /* config space access MPAGE7 registers*/
+                reg = < 0x30 0x38000000 0x0 0x01000000
+                0x20 0x20120000 0x0 0x00008000 >;
+                bus-range = <0 0x0f>;
+                /* Outbound ranges */
+                /* < <3-cell PCI addr> <2-cell CPU (PLB) addr> <2-cell size> > *
+/
+                ranges = <0x03000000 0x00000000 0xa0000000
+                          0x30 0x00000000
+                          0x00 0x10000000>;
+                /* Inbound ranges */
+                /* < <3-cell PCI addr> <2-cell CPU addr> <2-cell size> > */
+                dma-ranges = <0x03000000 0x00000000 0xa0000000
+                              0x00 0x00000000
+                              0x00 0x10000000>;
+                    interrupt-parent = <&gic>;
+                interrupts = <29 2>;
+                interrupt-map-mask = <0000 0 0 7>;
+                interrupt-map = <
+                        /* <3-cell dev> <irq#> <prnt> <2-cell prnt IRQ/sense> */
+                        0000 0 0 1 &gic 29 2
+                        0000 0 0 2 &gic 29 2
+                        0000 0 0 3 &gic 29 2
+                        0000 0 0 4 &gic 29 2
+                >;
+        };
+
+        PCIE1: pciex at 0xf0128000 {
+                compatible = "lsi,plb-pciex";
+                device_type = "pci";
+                enabled = <0>;
+                plx = <0>;
+                primary;
+                port = <1>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                /* config space access MPAGE7 registers*/
+                reg = <0x30 0x78000000 0x0 0x01000000
+                       0x20 0x20128000 0x0 0x00008000 >;
+                bus-range = <0 0x0f>;
+                /* Outbound ranges */
+                /* < <3-cell PCI addr> <2-cell CPU (PLB) addr> <2-cell size> > */
+                ranges = <0x03000000 0x00000000 0xa0000000
+                          0x30 0x40000000
+                          0x00 0x10000000>;
+                /* Inbound ranges */
+                /* < <3-cell PCI addr> <2-cell CPU addr> <2-cell size> > */
+                dma-ranges = <0x03000000 0x00000000 0xb0000000
+                             0x00 0x00000000
+                              0x00 0x10000000>;
+                interrupt-parent = <&gic>;
+                interrupts = <72 2>;
+                interrupt-map-mask = <0000 0 0 7>;
+                interrupt-map = <
+                        /* <3-cell dev> <irq#> <prnt> <2-cell prnt IRQ/sense> */
+                        0000 0 0 1 &gic 72 2
+                        0000 0 0 2 &gic 72 2
+                        0000 0 0 3 &gic 72 2
+                        0000 0 0 4 &gic 72 2
+                >;
+        };
+
+        PCIE2: pciex at 0xf0130000 {
+                compatible = "lsi,plb-pciex";
+                device_type = "pci";
+                enabled = <0>;
+                plx = <0>;
+                primary;
+                port = <2>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                /* config space access MPAGE7 registers*/
+                reg = <0x30 0xb8000000 0x0 0x01000000
+                       0x20 0x20130000 0x0 0x00008000 >;
+                bus-range = <0 0x0f>;
+                /* Outbound ranges */
+                /* < <3-cell PCI addr> <2-cell CPU (PLB) addr> <2-cell size> > */
+                ranges = <0x03000000 0x00000000 0xa0000000
+                          0x30 0x80000000
+                          0x00 0x10000000>;
+                /* Inbound ranges */
+                /* < <3-cell PCI addr> <2-cell CPU addr> <2-cell size> > */
+                dma-ranges = <0x03000000 0x00000000 0xc0000000
+                              0x00 0x00000000
+                              0x00 0x10000000>;
+
+                interrupt-parent = <&gic>;
+                interrupts = <73 2>;
+                interrupt-map-mask = <0000 0 0 7>;
+                interrupt-map = <
+                        /* <3-cell dev> <irq#> <prnt> <2-cell prnt IRQ/sense> */
+                        0000 0 0 1 &gic 73 2
+                        0000 0 0 2 &gic 73 2
+                        0000 0 0 3 &gic 73 2
+                        0000 0 0 4 &gic 73 2
+                >;
+        };
+};
+
+/*
+  Local Variables:
+  mode: C
+  End:
+*/
diff --git a/arch/arm/boot/dts/axm55xxsim.dts b/arch/arm/boot/dts/axm55xxsim.dts
new file mode 100644
index 0000000..2147ceb
--- /dev/null
+++ b/arch/arm/boot/dts/axm55xxsim.dts
@@ -0,0 +1,447 @@
+/*
+ * arch/arm/boot/dts/axm-sim.dts
+ *
+ * Copyright (C) 2012 LSI
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+/dts-v1/;
+
+/ {
+	model = "AXM5516";
+	compatible = "arm", "lsi,axm5516";
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	chosen { };
+
+	aliases {
+		serial0 = &axxia_serial0;
+		serial1 = &axxia_serial1;
+		serial2 = &axxia_serial2;
+		serial3 = &axxia_serial3;
+		timer   = &axxia_timers;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu at 0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <0>;
+		};
+
+		cpu at 1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <1>;
+		};
+
+		cpu at 2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <2>;
+		};
+
+		cpu at 3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <3>;
+		};
+
+		cpu at 4 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <4>;
+		};
+
+		cpu at 5 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <5>;
+		};
+
+		cpu at 6 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <6>;
+		};
+
+		cpu at 7 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <7>;
+		};
+
+		cpu at 8 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <8>;
+		};
+
+		cpu at 9 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <9>;
+		};
+
+		cpu at 10 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <10>;
+		};
+
+		cpu at 11 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <11>;
+		};
+
+		cpu at 12 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <12>;
+		};
+
+		cpu at 13 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <13>;
+		};
+
+		cpu at 14 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <14>;
+		};
+
+		cpu at 15 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <15>;
+		};
+	};
+
+	memory at 00000000 {
+		device_type = "memory";
+		reg = <0 0x00000000 0 0x40000000>;
+	};
+
+	gic: interrupt-controller at 2001001000 {
+		compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
+		#interrupt-cells = <3>;
+		#address-cells = <0>;
+		interrupt-controller;
+		reg = <0x20 0x01001000 0 0x1000>,  /* gic dist base */
+		      <0x20 0x01002000 0 0x100>,   /* gic cpu base */
+		      <0x20 0x10030000 0 0x100>,   /* axm IPI mask reg base */
+		      <0x20 0x10040000 0 0x20000>; /* axm IPI send reg base */
+	};
+
+	timer {
+		compatible = "arm,armv7-timer";
+		interrupts = <1 13 0xf08>,
+			     <1 14 0xf08>;
+	};
+
+
+	gpdma at 2020140000 {
+		compatible = "lsi,dma32";
+		reg = <0x20 0x20140000 0x00 0x1000>;
+		interrupts = <0 60 4>, /* busy */
+			     <0 61 4>; /* error */
+
+		channel0 {
+			interrupts = <0 62 4>;
+		};
+
+		channel1 {
+			interrupts = <0 63 4>;
+		};
+	};
+
+	gpdma at 2020141000 {
+		status = "disabled";
+		compatible = "lsi,dma32";
+		reg = <0x20 0x20141000 0x00 0x1000>;
+		interrupts = <0 64 4>, /* busy */
+			     <0 65 4>; /* error */
+
+		channel0 {
+			interrupts = <0 66 4>;
+		};
+
+		channel1 {
+			interrupts = <0 67 4>;
+		};
+	};
+
+	gpreg at 2010094000  {
+		compatible = "lsi,gpreg";
+		reg = <0x20 0x10094000 0 0x1000>;
+	};
+
+	ethernet at 201100000000 {
+		compatible = "smsc,lan91c111";
+		device_type = "network";
+		reg = <0x20 0x11000000 0 0x10000>;
+		interrupts = <0 1 4>;
+		phy-mode = "mii";
+		reg-io-width = <4>;
+		smsc,irq-active-high;
+		smsc,irq-push-pull;
+	};
+
+        amba {
+		compatible = "arm,amba-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		mmci at 020101E0000 {
+			compatible = "arm,pl180", "arm,primecell";
+			reg = <0x20 0x101E0000 0x00 0x1000>;
+			interrupts = <0 222 4>,
+				     <0 223 4>;
+		};
+
+		axxia_serial0: uart at 2010080000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x20 0x10080000 0x00 0x1000>;
+			interrupts = <0 56 4>;
+		};
+
+		axxia_serial1: uart at 2010081000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x20 0x10081000 0x00 0x1000>;
+			interrupts = <0 57 4>;
+		};
+
+		axxia_serial2: uart at 2010082000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x20 0x10082000 0x00 0x1000>;
+			interrupts = <0 58 4>;
+		};
+
+		axxia_serial3: uart at 2010083000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x20 0x10083000 0x00 0x1000>;
+			interrupts = <0 59 4>;
+		};
+
+		axxia_timers: timer at 2010091000 {
+			compatible = "arm,sp804", "arm,primecell";
+			reg = <0x20 0x10091000 0 0x1000>;
+			interrupts = <0 47 4>,
+				     <0 48 4>,
+				     <0 49 4>,
+				     <0 50 4>,
+				     <0 51 4>,
+				     <0 52 4>,
+				     <0 53 4>,
+				     <0 54 4>;
+		};
+
+		gpio at 2010092000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0x20 0x10092000 0 0x1000>;
+			interrupts = <0 10 4>,
+				     <0 11 4>,
+				     <0 12 4>,
+				     <0 13 4>,
+				     <0 14 4>,
+				     <0 15 4>,
+				     <0 16 4>,
+				     <0 17 4>;
+		};
+
+		gpio at 2010093000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0x20 0x10093000 0x00 0x1000>;
+			interrupts = <0 18 4>;
+		};
+
+		ssp at 2010088000 {
+			compatible = "arm,pl022", "arm,primecell";
+			reg = <0x20 0x10088000 0x00 0x1000>;
+			interrupts = <0 42 4>;
+		};
+
+	};
+
+    PCIE0: pciex at 0xf0120000 {
+                compatible = "lsi,plb-pciex";
+                device_type = "pci";
+                enabled = <0>;
+                plx = <0>;
+                primary;
+                port = <0>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                /* config space access MPAGE7 registers*/
+                reg = < 0x30 0x38000000 0x0 0x01000000
+                0x20 0x20120000 0x0 0x00008000 >;
+                bus-range = <0 0x0f>;
+                /* Outbound ranges */
+                /* < <3-cell PCI addr> <2-cell CPU (PLB) addr> <2-cell size> > *
+/
+                ranges = <0x03000000 0x00000000 0xa0000000
+                          0x30 0x00000000
+                          0x00 0x10000000>;
+                /* Inbound ranges */
+                /* < <3-cell PCI addr> <2-cell CPU addr> <2-cell size> > */
+                dma-ranges = <0x03000000 0x00000000 0xa0000000
+                              0x00 0x00000000
+                              0x00 0x10000000>;
+                    interrupt-parent = <&gic>;
+                interrupts = <29 2>;
+                interrupt-map-mask = <0000 0 0 7>;
+                interrupt-map = <
+                        /* <3-cell dev> <irq#> <prnt> <2-cell prnt IRQ/sense> */
+                        0000 0 0 1 &gic 29 2
+                        0000 0 0 2 &gic 29 2
+                        0000 0 0 3 &gic 29 2
+                        0000 0 0 4 &gic 29 2
+                >;
+        };
+
+        PCIE1: pciex at 0xf0128000 {
+                compatible = "lsi,plb-pciex";
+                device_type = "pci";
+                enabled = <0>;
+                plx = <0>;
+                primary;
+                port = <1>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                /* config space access MPAGE7 registers*/
+                reg = <0x30 0x78000000 0x0 0x01000000
+                       0x20 0x20128000 0x0 0x00008000 >;
+                bus-range = <0 0x0f>;
+                /* Outbound ranges */
+                /* < <3-cell PCI addr> <2-cell CPU (PLB) addr> <2-cell size> > */
+                ranges = <0x03000000 0x00000000 0xa0000000
+                          0x30 0x40000000
+                          0x00 0x10000000>;
+                /* Inbound ranges */
+                /* < <3-cell PCI addr> <2-cell CPU addr> <2-cell size> > */
+                dma-ranges = <0x03000000 0x00000000 0xb0000000
+                             0x00 0x00000000
+                              0x00 0x10000000>;
+                interrupt-parent = <&gic>;
+                interrupts = <72 2>;
+                interrupt-map-mask = <0000 0 0 7>;
+                interrupt-map = <
+                        /* <3-cell dev> <irq#> <prnt> <2-cell prnt IRQ/sense> */
+                        0000 0 0 1 &gic 72 2
+                        0000 0 0 2 &gic 72 2
+                        0000 0 0 3 &gic 72 2
+                        0000 0 0 4 &gic 72 2
+                >;
+        };
+
+        PCIE2: pciex at 0xf0130000 {
+                compatible = "lsi,plb-pciex";
+                device_type = "pci";
+                enabled = <0>;
+                plx = <0>;
+                primary;
+                port = <2>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                /* config space access MPAGE7 registers*/
+                reg = <0x30 0xb8000000 0x0 0x01000000
+                       0x20 0x20130000 0x0 0x00008000 >;
+                bus-range = <0 0x0f>;
+                /* Outbound ranges */
+                /* < <3-cell PCI addr> <2-cell CPU (PLB) addr> <2-cell size> > */
+                ranges = <0x03000000 0x00000000 0xa0000000
+                          0x30 0x80000000
+                          0x00 0x10000000>;
+                /* Inbound ranges */
+                /* < <3-cell PCI addr> <2-cell CPU addr> <2-cell size> > */
+                dma-ranges = <0x03000000 0x00000000 0xc0000000
+                              0x00 0x00000000
+                              0x00 0x10000000>;
+
+                interrupt-parent = <&gic>;
+                interrupts = <73 2>;
+                interrupt-map-mask = <0000 0 0 7>;
+                interrupt-map = <
+                        /* <3-cell dev> <irq#> <prnt> <2-cell prnt IRQ/sense> */
+                        0000 0 0 1 &gic 73 2
+                        0000 0 0 2 &gic 73 2
+                        0000 0 0 3 &gic 73 2
+                        0000 0 0 4 &gic 73 2
+                >;
+        };
+
+        I2C0: i2c at 0x02010084000 {
+                compatible = "lsi,api2c";
+                device_type = "i2c";
+                enabled = <0>;
+                port = <0>;
+                /* bus_name = "auto"; */
+                /* bus = <2>; */
+                reg = <0x20 0x10084000 0x00 0x1000>;
+		interrupts = <0 19 4>;
+        };
+
+        I2C1: i2c at 0x02010085000 {
+                compatible = "lsi,api2c";
+                device_type = "i2c";
+                enabled = <0>;
+                port = <1>;
+                /* bus_name = "auto"; */
+                /* bus = <3>; */
+                reg = <0x20 0x10085000 0x00 0x1000>;
+		interrupts = <0 20 4>;
+        };
+
+        I2C2: i2c at 0x02010086000 {
+                compatible = "lsi,api2c";
+                device_type = "i2c";
+                enabled = <0>;
+                port = <2>;
+                /* bus_name = "auto"; */
+                /* bus = <4>; */
+                reg = <0x20 0x10086000 0x00 0x1000>;
+		interrupts = <0 21 4>;
+        };
+
+        SMB: i2c at 0x02010087000 {
+                compatible = "lsi,api2c";
+                device_type = "i2c";
+                enabled = <0>;
+                port = <3>;
+                bus_name = "smb";
+                /* bus = <5>; */
+                reg = <0x20 0x10087000 0x00 0x1000>;
+		interrupts = <0 22 4>;
+        };
+};
+
+/*
+  Local Variables:
+  mode: C
+  End:
+*/
-- 
1.8.3




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