[linux-yocto] [PATCH 47/70] powerpc/44x: Fix/Initialize PID to kernel PID before the TLB search
butler.paul at gmail.com
Mon Jun 10 18:46:10 PDT 2013
From: Wei Yang <Wei.Yang at windriver.com>
commit f13bfcc6961a5c9f511c401292db522edcd0b061 upstream
Initialize the PID register with kernel pid (0) before we start
setting the TLB mapping for KEXEC. Also set the MMUCR[TID] to kernel
This was spotted while testing the kexec on ISS for 47x. ISS doesn't
return a successful tlbsx for a kernel address with PID set to a user PID.
Though the hardware/qemu/simics work fine.
This patch is harmless and initializes the PID to 0 (kernel PID) which
is usually the case during a normal kernel boot. This would fix the kexec
on ISS for 440. I have tested this patch on sequoia board.
Signed-off-by: Suzuki K Poulose <suzuki at in.ibm.com>
Cc: Josh Boyer <jwboyer at gmail.com>
Signed-off-by: Josh Boyer <jwboyer at gmail.com>
Integrated-by: Wei Yang <Wei.Yang at windriver.com>
arch/powerpc/kernel/misc_32.S | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S
index c85fe05..0dfc0d5 100644
@@ -770,8 +770,12 @@ relocate_new_kernel:
- /* Load our MSR_IS and TID to MMUCR for TLB search */
- mfspr r3,SPRN_PID
+ * Load the PID with kernel PID (0).
+ * Also load our MSR_IS and TID to MMUCR for TLB search.
+ li r3, 0
+ mtspr SPRN_PID, r3
andi. r4,r4,MSR_IS at l
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